CN113165121A

CN113165121A - Method for manufacturing semiconductor device and laminate

Info

Publication number: CN113165121A
Application number: CN202080006808.4A
Authority: CN
Inventors: 文田祐介; 田久真也; 爱泽和人; 长谷川裕也
Original assignee: Lintec Corp
Current assignee: Lintec Corp
Priority date: 2019-03-26
Filing date: 2020-03-11
Publication date: 2021-07-23
Anticipated expiration: 2040-03-11
Also published as: KR20210142584A; WO2020195808A1; TW202101551A; CN113165121B; JPWO2020195808A1

Abstract

The invention provides a method for manufacturing a semiconductor device and a laminate. Even when the distance between adjacent singulated chips is small, cracks and chips are less likely to occur in the manufacturing process. A method for manufacturing a semiconductor device having a rectangular planar shape, wherein an adhesive sheet is attached to a surface of a wafer including a plurality of rectangular planned singulation regions arranged in a matrix along a short side direction of the planned singulation regions, a back surface of the wafer to which the adhesive sheet is attached is ground, and the chips are divided along planned dividing lines defining the planned singulation regions.

Description

Method for manufacturing semiconductor device and laminate

Technical Field

The present invention relates to a method for manufacturing a semiconductor device, and a laminate used in the method for manufacturing the semiconductor device.

Background

As a process for manufacturing a semiconductor device such as a semiconductor chip having a semiconductor circuit formed on a silicon substrate, a method called DBG (Dicing Before Grinding) is known. DBG is a method as follows: grooves having a depth corresponding to the finished thickness are formed in streets (streets) between the wafers, and the back surface of the wafer is ground so that the grooves formed in the past are exposed from the back surface of the wafer, thereby dividing the wafer into individual semiconductor chips.

For the purpose of increasing the number of chips obtained from one wafer, a method called SDBG (step Dicing Before Grinding) has also been proposed. SDBG refers to the following processing method: a converging point of laser light having a wavelength which is transparent to a wafer is positioned inside the wafer, the wafer is irradiated with the laser light along a planned dividing line, a modified layer based on multiphoton absorption is formed inside the wafer, the back surface side of the wafer is ground to thin the wafer, and the wafer is divided into individual semiconductor chips with the modified layer as a dividing starting point.

When a processing method is used in which the gap between chips in a wafer after division is made very small as in the case of SDBG, a chip or a crack may occur in a singulated semiconductor chip. For this reason, for example, patent document 1 proposes providing a notch prevention layer made of a metal film or the like at each intersection of planned dividing lines on the wafer surface.

Documents of the prior art

Patent document

Patent document 1: japanese patent laid-open publication No. 2018-6653

Disclosure of Invention

Problems to be solved by the invention

However, the demand for miniaturization of chip size is increasing, and the problem of cracks and chipping of the semiconductor chip becomes remarkable with the miniaturization of the semiconductor chip. According to the study of the present inventors, the following was found: when a method of reducing the gap formed by dicing as much as possible using a DBG, or a method of making the interval between adjacent chips substantially zero at the time of dividing the wafer like SDBG, is used, the problem of cracking or chipping due to the contact between adjacent chips becomes more significant when the chip size is reduced. Therefore, a new and useful method for manufacturing a semiconductor device is desired, which can more effectively prevent chipping and cracking of a chip.

In view of the above problems, an object of the present invention is to provide a method for manufacturing a semiconductor device, in which cracks and chipping are less likely to occur in chips in a manufacturing process even when a distance between adjacent singulated chips is small, and a laminate suitable for the manufacturing method.

Means for solving the problems

The present inventors have conducted extensive studies to solve the above problems, and as a result, have found that the above problems can be solved by appropriately setting the direction of application of an adhesive sheet to be applied to the circuit layer formation surface of a wafer based on a region to be singulated of the wafer, and have completed the present invention.

Namely, the present invention provides the following [1] to [6 ].

[1] A method for manufacturing a semiconductor device having a rectangular planar shape,

adhering an adhesive sheet to a surface of a wafer including a plurality of rectangular regions to be singulated arranged in a matrix along a short side direction of the regions to be singulated,

the back surface of the wafer to which the adhesive sheet is attached is ground, and the wafer is divided along lines to be divided which define the areas to be singulated.

[2] The method for manufacturing a semiconductor device according to the above [1], wherein,

forming a modified portion serving as a starting point of division in the wafer at a planar position corresponding to the planned dividing line after the adhesive sheet is attached to the front surface of the wafer,

and grinding the back surface of the wafer on which the adhesive sheet is adhered, and dividing the wafer along the lines to be divided.

[3] The method of manufacturing a semiconductor device according to the above [1] or [2], wherein an aspect ratio of the region to be singulated expressed by a length in a longitudinal direction/a length in a short side direction is 1.05 or more.

[4] The method for manufacturing a semiconductor device according to any one of the above [1] to [3], wherein the length of the region to be singulated in the longitudinal direction is 5 to 50mm, and the length thereof in the short-side direction is 2 to 20 mm.

[5] The method for manufacturing a semiconductor device according to any one of the above [1] to [4], wherein a transfer sheet is attached to the back surface of the wafer after grinding,

after the transfer sheet is attached, the adhesive sheet is separated from the wafer.

[6] A laminate, wherein the laminate comprises:

a wafer including a plurality of rectangular singulated predetermined regions arranged in a matrix; and

and an adhesive sheet that is attached to the surface of the wafer in a state in which tension is applied in the short side direction of the planned singulation region.

ADVANTAGEOUS EFFECTS OF INVENTION

According to the present invention, it is possible to provide a method for manufacturing a semiconductor device in which cracks and chipping are less likely to occur in chips in a manufacturing process even when the distance between adjacent singulated chips is small, and a laminate suitable for the manufacturing method.

Drawings

Fig. 1 is a schematic cross-sectional view of a wafer on which a circuit layer is formed, a laminate in which an adhesive sheet is attached to the circuit layer of the wafer, and a semiconductor chip as a semiconductor device obtained by processing the wafer using the laminate.

Fig. 2 is an explanatory diagram showing a relationship between a bonding direction of the adhesive sheet to the wafer and a region to be singulated on the wafer.

Fig. 3 is a schematic cross-sectional view showing a manufacturing process of the laminate.

Fig. 4 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device.

Fig. 5 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device.

Fig. 6 is a schematic plan view showing a wafer used in the method for manufacturing a semiconductor device according to the embodiment of the present invention in comparison with a wafer used in the method for manufacturing a semiconductor device according to a comparative example.

Detailed Description

Hereinafter, embodiments of the present invention (hereinafter, may be referred to as "the present embodiment") will be described.

[ wafer, laminate, and semiconductor device ]

The semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present embodiment includes a wafer portion and a circuit portion formed on a surface thereof, and has a rectangular planar shape. In this specification, the term "semiconductor device" refers to all devices used for a processor, a memory, a sensor, and the like, which can function by utilizing semiconductor characteristics. Specifically, a wafer including integrated circuits, a thinned wafer including integrated circuits, a chip including integrated circuits, a thinned chip including integrated circuits, an electronic component including these chips, and an electronic device including the electronic component can be exemplified. But also the chip before packaging.

The semiconductor device is obtained by singulating a wafer having a circuit layer provided on a surface thereof.

In addition, in a step of processing a wafer provided with a circuit layer into a semiconductor device, a laminate is used in which an adhesive sheet is bonded to a circuit layer forming surface of the wafer.

Hereinafter, a wafer, a stacked body, and a semiconductor device according to embodiments of the present invention will be described with reference to the drawings.

Fig. 1 is a schematic cross-sectional view of a wafer having a circuit layer formed thereon, a laminate having an adhesive sheet bonded to the surface of the wafer having the circuit layer formed thereon, and a semiconductor chip as a semiconductor device obtained by processing the wafer.

As shown in fig. 1(a), first, a wafer W having a circuit layer C formed on the surface thereof is prepared by a semiconductor forming process including photolithography.

Next, as shown in fig. 1(B), the adhesive sheet 1 is bonded to the surface of the wafer W on which the circuit layer C is formed, to obtain a laminate 10.

Further, as shown in fig. 1(C), the wafer W is cut along the planned dividing lines defining the planned dividing areas while grinding the back surface of the wafer W as necessary, thereby forming a singulated wafer WI. In this way, the wafer W having the circuit layer C is singulated into a plurality of pieces to obtain semiconductor chips CP as semiconductor devices. The singulation target region will be described in detail later.

< wafer >

The wafer W is produced by cutting a high-purity silicon single crystal into a disk shape. The diameter of the wafer W is not limited to this, and is, for example, 12 inches.

The circuit layer C is a layer including a semiconductor circuit formed on the surface of the wafer W by a semiconductor manufacturing process.

The semiconductor process includes a step of forming a thin film of silicon oxide, aluminum, or the like, which is a raw material of a circuit, on a silicon wafer by sputtering, plating, CVD, or the like, and then forming a semiconductor circuit by photolithography.

The photolithography method has: a step of covering the thin film formed on the silicon wafer with a resist film; irradiating the resist film with UV light through a mask having a circuit pattern formed thereon; developing and selectively removing uncured portions of the resist film; a step of etching and removing the thin film exposed by the development; implanting impurities such as phosphorus and boron into the silicon substrate exposed by the etching to impart semiconductor characteristics; a step of activating impurity ions by heat treatment using a flash lamp, laser irradiation, or the like; and a step of removing the resist film.

< semiconductor device >

For example, the wafer W is divided into a plurality of semiconductor chips each having a size of about 12mm × 6mm in a plan view. In the case of dicing into such sizes, about 1000 semiconductor chips were obtained from a wafer having a diameter of 12 inches.

As described above, the semiconductor chip as a semiconductor device includes the wafer portion derived from the wafer W and the circuit portion derived from the circuit layer C formed on the surface thereof.

The semiconductor chip obtained by the method for manufacturing a semiconductor device of the present embodiment has a rectangular planar shape. Therefore, various functions can be provided to the semiconductor chip, or the upper and lower sides of the semiconductor chip can be easily grasped.

< layered product >

The laminate 10 has an adhesive sheet 1 adhered to the surface of the wafer W on which the circuit layer C is formed.

(adhesive sheet)

The adhesive sheet 1 is a laminate including a base material layer and an adhesive layer laminated on the base material layer, and typically includes a base material layer, a cushion layer provided on at least one surface side of the base material layer, and an adhesive layer provided on the other surface side of the base material layer. The pressure-sensitive adhesive sheet 1 may include other structural layers than these, and for example, a primer layer may be formed on the surface of the substrate on the pressure-sensitive adhesive layer side, or a release sheet for protecting the pressure-sensitive adhesive layer until use may be laminated on the surface of the pressure-sensitive adhesive layer. The substrate may be a single layer or a plurality of layers. The same applies to the buffer layer and the adhesive layer. The adhesive sheet 1 is attached to the wafer W such that the adhesive layer of the adhesive sheet 1 is in contact with the circuit layer C of the wafer W, and the adhesive sheet 1 functions as a protective film for protecting the circuit layer C of the wafer W.

(substrate layer)

The material of the base material layer is not particularly limited, and is suitable for a processing member of an electronic component because dust generation is less than that of paper or nonwoven fabric, and is preferably a resin film from the viewpoint of easy availability. By providing the pressure-sensitive adhesive sheet with a base material layer, the shape stability of the pressure-sensitive adhesive sheet can be improved, or toughness can be imparted to the pressure-sensitive adhesive sheet. Even when the circuit layer C of the wafer W has large irregularities, the surface opposite to the surface to which the adhesive sheet is attached can be easily kept smooth.

The substrate layer may be a substrate layer composed of a single-layer film formed of one resin film or a substrate layer composed of a multilayer film in which a plurality of resin films are laminated.

The thickness of the base layer is preferably 5 to 250 μm, more preferably 10 to 200 μm, and still more preferably 25 to 150 μm, from the viewpoint of imparting an appropriate elastic force to the adhesive sheet and from the viewpoint of workability in winding the adhesive sheet.

Examples of the resin film that can be used for the base layer include polyolefin-based films, halogenated vinyl polymer-based films, acrylic resin-based films, rubber-based films, cellulose-based films, polyester-based films, polycarbonate-based films, polystyrene-based films, polyphenylene sulfide-based films, cycloolefin polymer-based films, and films formed from a cured product of an energy ray curable composition containing a polyurethane resin.

The polyester film used for the base layer may be a film made of a copolymer of polyester, or a resin mixed film made of a mixture of the polyester and a relatively small amount of another resin. Among these polyester films, polyethylene terephthalate films are preferred from the viewpoint of easy availability and high thickness accuracy.

(adhesive layer)

The adhesive layer provided on the base material layer or the intermediate layer protects the circuit layer C by reliably fixing the adhesive sheet to the circuit layer C of the wafer W.

The adhesive layer comprises an adhesive. Examples of the adhesive include acrylic adhesives, rubber adhesives, urethane adhesives, silicone adhesives, polyvinyl ether adhesives, and olefin adhesives. These binders may be used alone or in combination of two or more.

The thickness of the adhesive layer can be adjusted as appropriate depending on the size of the unevenness of the circuit layer to be protected, and is preferably 5 to 200 μm, more preferably 7 to 150 μm, and still more preferably 10 to 100 μm.

(intermediate layer)

The intermediate layer is not particularly limited, and is preferably formed from a resin composition containing a urethane (meth) acrylate and a thiol group-containing compound, from the viewpoint of obtaining good uneven absorbency.

The thickness of the intermediate layer can be appropriately adjusted depending on the size of the surface roughness of the semiconductor to be protected, and is preferably 50 to 400 μm, more preferably 70 to 300 μm, and even more preferably 80 to 250 μm, from the viewpoint of absorbing relatively large roughness.

(bonding direction of adhesive sheet)

Fig. 2 is an explanatory diagram showing a relationship between a bonding direction of the adhesive sheet 1 to the wafer W and the planned singulation region R on the wafer W.

As shown in fig. 2(a), a V notch Wv indicating a reference direction of processing or working on the wafer W and a semiconductor circuit provided in each of the planned singulation regions R defined by the planned dividing lines E are formed on the front surface of the wafer W. The semiconductor circuit is formed with reference to the direction indicated by the V notch Wv. The adhesive sheet described later is also bonded with reference to the direction indicated by the V notch Wv.

Here, the planned singulation region R is rectangular in plan view. The lines E defining the areas R to be singulated are imaginary lines, and the individual circuits need only be formed so as not to straddle the lines E, and it is not necessary to physically form the lines E defining the areas R to be singulated on the front surface of the wafer W or the circuit layer C. However, in order to easily recognize the region to be singulated R or to smoothly divide the wafer W, a processing groove or the like to be the line to divide E may be formed in advance by photolithography.

By making the region R to be singulated rectangular, the shape of the finally obtained semiconductor chip also becomes rectangular.

In the example shown in fig. 2 a, each circuit of the circuit layer C is formed so that the short side direction d2 of each planned singulation region R coincides with the direction d3 (hereinafter, also referred to as the vertical direction) shown by the V notch Wv. Thus, the longitudinal direction d1 of the planned singulation region coincides with a direction (hereinafter, also referred to as a transverse direction) orthogonal to the direction d3 indicated by the V notch Wv.

The length of the region R to be singulated in the longitudinal direction is preferably 5 to 50mm, more preferably 7 to 40mm, and still more preferably 10 to 30mm, from the viewpoint of easily suppressing chipping and cracking of the semiconductor chip in the manufacturing process and easily providing various functions to the semiconductor chip.

The length of the planned singulation region R in the short side direction is preferably 2 to 20mm, more preferably 3 to 18mm, and even more preferably 4 to 15mm, from the viewpoint of improving the ease of handling and facilitating the addition of the minimum necessary functions to the semiconductor chip.

The aspect ratio of the planned singulation region R, which is represented by the ratio of the length in the longitudinal direction to the length in the short direction (the length in the longitudinal direction/the length in the short direction), is preferably 1.05 or more, more preferably 1.10 or more, further preferably 1.15 or more, and further preferably 10 or less, more preferably 7.0 or less, and further preferably 5.0 or less, from the viewpoint of appropriately maintaining the balance between the suppression of chipping and cracking of the semiconductor chip and the imparting of the function to the semiconductor chip in the manufacturing process.

In this embodiment, as described later, since the wafer W is divided by the SDBG when manufacturing the semiconductor device, the distance between the adjacent chips is substantially zero. Therefore, the lengths in the longitudinal direction and the lateral direction of the singulation predetermined region R coincide with the lengths in the longitudinal direction and the lateral direction of the semiconductor chip.

Note that the semiconductor circuit may not be provided outside the area to be singulated R, and a semiconductor circuit not used may be provided outside the area to be singulated as a dummy circuit.

As shown in fig. 2(B), the adhesive sheet 1 has a length and a width capable of covering the entire surface of the wafer W. When a wafer W having a diameter of 12 inches is used, for example, a long adhesive sheet having a width of 400mm can be used as the adhesive sheet 1. In fig. 2(B), the wafer W covered with the adhesive sheet 1 and the regions R to be singulated thereof are indicated by thin lines for easy understanding. When a pressure-sensitive adhesive sheet having light transmittance is used as the pressure-sensitive adhesive sheet 1, the shape and the alignment direction of the regions R to be singulated can be confirmed through the pressure-sensitive adhesive sheet 1.

When the adhesive sheet 1 is to be bonded, the wafer W is set on the bonding apparatus with reference to the direction d3 indicated by the V notch Wv. At this time, the wafer W is set so that the sticking direction d4 of the adhesive sheet 1 of the sticking apparatus is along the direction d3 indicated by the V notch Wv. Thus, in the present embodiment, the short side direction d2 of the singulation predetermined region R is along the direction d3 shown by the V notch Wv.

After the adhesive sheet 1 is attached to the circuit layer C of the wafer W, the adhesive sheet 1 extending from the wafer W is cut and removed as necessary. As described later, when the adhesive sheet 1 is attached by a method of applying tension so as to eliminate the flexure of the adhesive sheet 1, or the like, the adhesive sheet 1 is attached to the circuit layer C in a state where tension is applied along the attaching direction d4 of the adhesive sheet 1. Thereby, the laminated body 10 is formed in a state where tension is applied in a direction along the short side direction d2 of the planned singulation region R.

Here, the bonding direction d4 of the adhesive sheet is set to be along the direction d3 indicated by the V-notch Wv (i.e., the short side direction d2 of the planned singulation region R in this example), but as shown in fig. 2B, the bonding direction d4 of the adhesive sheet 1 may be set to be within a certain angle θ with respect to the direction d3 indicated by the V-notch Wv. Here, θ is preferably within a range of ± 45 °, more preferably ± 40 °, and further preferably ± 35 ° with respect to the direction d3 indicated by the V notch Wv.

[ method for producing laminate ]

Fig. 3 is a schematic cross-sectional view showing a step of producing a laminate. Fig. 3(a) is a view showing a state where the wafer W having the circuit layer C formed thereon is placed on the support body 100, fig. 3(B) is a view showing a state where the adhesive sheet 1 is attached to the circuit layer C of the wafer W, and fig. 3(C) is a view showing a state where the adhesive sheet 1 is attached to the circuit layer C of the wafer W.

As shown in fig. 3(a), after the wafer W having the circuit layer C formed thereon is placed on the support 100 so that the back surface of the wafer W is in contact with the support 100, as shown in fig. 3(B), the adhesive sheet 1 is attached to the circuit layer C of the wafer W. In this example, one end of the adhesive sheet 1 is wound around a winding member or held by a holding member to hold the adhesive sheet 1 in a state of being lifted from the wafer W, and the adhesive sheet 1 is attached to the surface of the wafer W on which the circuit layer C is formed while the adhesive sheet 1 is sequentially pressed by the pressing body 101 from the other end.

At this time, in order to eliminate the slack of the adhesive sheet 1 as much as possible, a constant tension is applied in the longitudinal direction of the adhesive sheet 1 (i.e., the direction in which the adhesive sheet 1 is attached), or a pressing force of a pressing body is applied in the longitudinal direction of the adhesive sheet 1, so that the adhesive sheet 1 is attached to the wafer W with the tension applied in the attaching direction d 4. The adhesive sheet 1 is attached to the circuit layer C of the wafer W in a state where almost no tension is applied in the width direction of the adhesive sheet 1.

After the adhesive sheet 1 is attached to the circuit layer C, the adhesive sheet 1 extending from the wafer W is cut and removed as necessary. As shown in fig. 3(C), a laminate 10 in which the adhesive sheet 1 is bonded to the circuit layer C of the wafer W is produced.

The material constituting the support 100 is not particularly limited, and a metal material such as stainless steel is used, for example.

[ method for manufacturing semiconductor device ]

An example of the method for manufacturing a semiconductor device according to the present embodiment includes the steps of: the laminated body having the adhesive sheet attached to the circuit layer of the wafer is processed, the wafer is divided, the back surface of the wafer is ground, a transfer sheet is attached to the surface of the divided wafer opposite to the circuit layer forming surface (i.e., the back surface of the wafer), and after the adhesive sheet is removed, the wafer is cut together with the transfer sheet and singulated. Hereinafter, each step will be described in order. The transfer sheet is a sheet that is attached to the back surface of a wafer, and after the wafer is separated from the adhesive sheet, the wafer is transferred to the front surface thereof and held.

Fig. 4 and 5 are schematic cross-sectional views showing a manufacturing process of a semiconductor device.

Fig. 4(a) is a view showing a state in which the laminate 10 is mounted on a support 200 different from the support 100. As shown in fig. 4(a), the laminate 10 is placed on the support 200 so that the adhesive sheet 1 contacts the support 200. As the support 200, for example, a support made of the same material as the support 100 or a porous plate made of ceramic can be used.

Fig. 4(B) is a diagram showing a state where the wafer W is irradiated with the laser light from the back side. As shown in fig. 4(B), the laser beam 103 is irradiated from the rear surface side to the wafer W while the laser beam 103 and the wafer W are relatively moved along the planned dividing line E defining the planned singulation region R, by using the condenser 102, and determining the position of the laser beam 103 such that the focal point of the laser beam 103 having a wavelength that is transparent to the wafer W is located inside the wafer W. Thus, the reformed portion M is formed inside the wafer W at the planar position corresponding to the line to divide E. The modifying portion M is a portion where the wafer W is modified by laser irradiation, and serves as a starting point for cleaving the wafer W.

Fig. 4(C) is a view showing a state where the back surface side of the wafer W is ground. As shown in fig. 4(C), the back surface of the wafer W is ground by using the grinder 104 until a desired thickness is achieved. By this process, the wafer W is thinned and lightened. At the same time, the wafer W is cut along the planned dividing lines E defining the planned singulation region R, with the modified portion M as a starting point. The modified portion M formed in the wafer W is removed by grinding.

In the SDBG, when the wafer is divided at the time of grinding, only a crack due to stealth dicing (reference numeral P of fig. 4 (C)) exists between adjacent chips, and the distance between the chips is substantially zero. Therefore, the chips are displaced by a slight stress or impact, and the chips are likely to be brought into contact with each other, pressed, rubbed, or collided, and thus cracks are likely to occur. Further, when an adhesive sheet such as a protective sheet for back grinding is stuck, since the sheet is stuck by applying tension in the sticking direction, stress tends to remain in the laminate after the adhesive sheet is stuck. Therefore, it is presumed that by grinding the back surface of the wafer, the stress in the laminate is released while the wafer W is cut into individual chips from the reformed portion M, and the chips are easily moved in the sticking direction of the adhesive sheet, and as a result, the chips come into contact with each other, press, rub, or collide with each other, and cracks are caused.

In the method of manufacturing a semiconductor device according to the present embodiment, the reason why chipping and cracking of the chip are suppressed is not limited to this, but one of the reasons may be considered as follows. That is, by attaching the adhesive sheet along the short side direction of the chip while making the length in the longitudinal direction of the chip different from the length in the transverse direction, the number of cutting lines between the chips in the attaching direction of the adhesive sheet is increased as compared with the case where the adhesive sheet is attached along the long side direction of the chip. It is thus presumed that the amount of movement of the chips in the bonding direction is dispersed by more chips, and that contact, pressing, friction, collision, and the like between the chips are reduced, which leads to suppression of cracks and chipping.

In the present embodiment, the modified portion is removed by grinding, but for example, in an application where thinning of the wafer is not required, or in a case where the wafer is originally thick, at least a part of the modified portion may be left on the wafer even after grinding.

Fig. 5(a) shows a step of separating the laminated body 11, which is obtained by grinding and dividing the wafer W, from the support body 200. Fig. 5(B) shows a step of attaching the laminate 11 obtained by grinding and dividing the wafer W to the transfer sheet held by the ring frame 300. Fig. 5(C) shows a step of separating the adhesive sheet 1 from the laminate 11 bonded to the transfer sheet 303. Fig. 5(D) shows an expanding step of separating the respective chips together with the transfer sheet 303.

As shown in fig. 5(a), the laminated body 11, which is separated from the support body 200 and from which the wafer W is ground and divided, is bonded to a film-like adhesive 301 of a transfer sheet 303 including a film-like adhesive 301 and a support sheet 302, which is held around the ring frame 300, as shown in fig. 5 (B). Next, as shown in fig. 5C, the adhesive sheet 1 is separated from the laminate 11 obtained by grinding and dividing the wafer W, and further, as shown in fig. 5D, the film-like adhesive 301 is also cut together with the chips (the cut film-like adhesive is denoted by reference numeral 301 a) by stretching the support sheet 302, and the chips are separated into individual chips with a gap G therebetween.

As the transfer sheet 303, for example, a transfer sheet may be used in which a film-like adhesive 301 having a curing property is provided on a support sheet 302 including a base material made of the same material as the base material layer of the psa sheet 1 via a psa layer as needed.

According to the above manufacturing method, the semiconductor device can be manufactured with high yield while suppressing the occurrence of chipping and cracking of the chip in the manufacturing process.

In the present embodiment, the wafer is divided by SDBG, but the present invention is not limited thereto, and for example, the wafer may be divided by DBG. When the DBG is used, when the distance between chips formed by dicing is small, the effect of preventing chipping and cracking of the chips is easily exhibited. When the DBG is used, the wafer is half-cut from the front surface of the wafer on which the circuit layer is formed, the adhesive sheet is attached to the circuit-formed surface of the wafer, and the back surface of the wafer is ground.

Examples

Next, specific examples of the present invention will be described, but the present invention is not limited to these examples.

[ examples and comparative examples ]

The chips of examples 1 to 3 and comparative examples 1 to 4 were produced by the following procedure. In examples 1 to 3 and comparative examples 1 to 4, mirror wafers in which circuit layers were not formed were used in order to match the experimental conditions as much as possible and to facilitate the experiment.

< example 1>

A mirror wafer of single crystal silicon having a diameter of 12 inches was prepared, and an adhesive sheet was attached to one surface (hereinafter referred to as a first surface) of the wafer along a direction indicated by a vertex of the V notch (hereinafter referred to as a vertical direction) with reference to the V notch provided in the mirror wafer. As the pressure-sensitive adhesive sheet, a back surface polishing tape "E-3135 KN" manufactured by Lintec Kabushiki Kaisha was used. The pressure-sensitive adhesive sheet was adhered using an adhering device ("RAD-3510F/12" manufactured by Lindceko corporation) under conditions of a pressing amount of 15 μm, a protruding amount of 150 μm, an adhering speed of 5mm/s, an adhering stress of 0.35MPa, and an adhering temperature of 23 ℃.

Next, SDBG was performed so that the length in the vertical direction was 6mm and the length in the direction perpendicular to the vertical direction (hereinafter, referred to as the horizontal direction) was 12 mm. Specifically, a stealth dicing laser saw "DFL 7361" manufactured by DISCO corporation is irradiated with laser light from the surface (hereinafter, referred to as a second surface) side of the wafer opposite to the first surface, and a modified layer is formed inside the wafer so that 980 singulation regions having a size of 6mm in the vertical direction × 12mm in the horizontal direction are arranged in a matrix.

Further, the other surface (hereinafter referred to as the second surface) of the wafer was ground using a back grinding apparatus ("DPG 8760" manufactured by dysco) until the thickness of the wafer became 30 μm, thereby removing the modified layer inside the wafer and cutting the wafer along the planned dividing lines defining the planned dividing regions.

Subsequently, the second surface of the singulated wafer was attached to a dicing tape ("D-175" manufactured by Lingdeko corporation) provided on a tape mounter "RAD-2700" manufactured by Lingdeko corporation, and the adhesive sheet was removed. Next, using an IR camera provided in the stealth dicing laser saw, the presence or absence of cracks was observed from the first surface side, and the number of chips with cracks was counted.

The number of chips having cracks was 1 in 980, and the crack generation rate was 0.10%.

< example 2>

A wafer was processed by SDBG under the same conditions as in example 1 except that the wafer having the adhesive sheet attached to the first surface thereof was made 4mm long in the vertical direction and 12mm long in the horizontal direction along the vertical direction in the same procedure as in example 1, and was singulated into 1471 chips.

As a result of observation in the same manner as in example 1, 1 of 1471 chips with cracks was observed, and the crack occurrence rate was 0.07%.

< example 3>

The wafer was processed by SDBG under the same conditions as in example 1, except that the wafer having the adhesive sheet attached to the first surface thereof was made 8mm long in the vertical direction and 12mm long in the horizontal direction along the vertical direction in the same procedure as in example 1, and was singulated into 735 chips.

The observation was carried out in the same manner as in example 1, and as a result, 1 of 735 chips in which cracks were generated had a crack generation rate of 0.13%.

< comparative example 1>

A wafer was processed by SDBG under the same conditions as in example 1, except that the wafer having the adhesive sheet attached to the first surface thereof was 12mm long in the vertical direction and 6mm long in the horizontal direction along the vertical direction in the same procedure as in example 1, and was singulated into 980 chips.

Fig. 6 is a schematic plan view showing an example of the present invention in comparison with a comparative example. As shown in fig. 6(a), in the wafers W1 of examples 1 and 2, the sticking direction d4 of the adhesive sheet 1 and the short side direction d2 of the planned singulation region R were aligned with the direction d3 indicated by the V notch Wv. On the other hand, as shown in fig. 6(B), in the wafer W2 of comparative example 1, the bonding direction d4 of the adhesive sheet and the longitudinal direction d1 of the planned singulation region R are aligned with the direction d3 indicated by the V notch.

As a result of observation in the same manner as in example 1, 11 chips out of 980 with cracks formed, and the crack growth rate was 1.12%.

< comparative example 2>

A wafer having a psa sheet attached to its first surface was processed by SDBG under the same conditions as in example 1, except that the wafer had a longitudinal length of 12mm and a lateral length of 4mm as in example 1, and was singulated into 1471 chips.

The observation was carried out in the same manner as in example 1, and the number of chips with cracks was 14 out of 1471, and the crack growth rate was 0.95%.

< comparative example 3>

The SDBG process was performed on the wafer under the same conditions as in example 1 except that the wafer having the adhesive sheet attached to the first surface thereof had a length of 12mm in the vertical direction and a length of 12mm in the horizontal direction as in example 1, and the wafer was singulated into 490 chips.

The observation was carried out in the same manner as in example 1, and the number of chips with cracks was 6 out of 490, and the crack growth rate was 1.22%.

< comparative example 4>

The wafer was subjected to SDBG-based processing under the same conditions as in example 1 except that the wafer having the adhesive sheet attached to the first surface thereof was 12mm in the longitudinal direction and 8mm in the lateral direction as in example 1, and was singulated into 735 chips.

The observation was carried out in the same manner as in example 1, and the number of cracked chips was 9 out of 735, and the crack growth rate was 1.22%.

The results of examples 1 to 3 and comparative examples 1 to 4 are shown in Table 1.

[ Table 1]

As is clear from the results in table 1, in examples 1 to 3 in which the bonding direction of the adhesive sheet was aligned with the short side direction of the chip, the number of chips with cracks was small, and the crack occurrence rate was also a very small value.

In contrast, in comparative examples 1, 2, and 4 in which the bonding direction of the adhesive sheet was aligned with the longitudinal direction of the chip, the number of chips with cracks was increased. In particular, it is found that the values of the crack generation rates of comparative examples 1 and 2 are increased by 10 times or more as compared with examples 1 and 2, and that comparative example 4 is also increased by about 10 times as compared with example 3.

In comparative example 3 in which the chip shape was square and the length of 1 side was equal to the length of the long side of the chips in examples 1 to 3, the number of chips with cracks was also increased, and the crack occurrence rate was increased to 10 times or more and to around 10 times of example 3 as compared with examples 1 and 2, respectively.

Industrial applicability

The method for manufacturing a semiconductor device according to the present invention is not likely to cause chipping or cracking of chips even when a processing method such as SDBG is used to divide a wafer so that the distance between chips becomes very small, and can be suitably applied to manufacturing semiconductor chips used in processors, memories, sensors, and the like. The laminate of the present invention can be suitably used in the method for manufacturing a semiconductor device.

Description of the reference numerals

1: adhesive sheet

10: laminated body

11: laminate obtained by grinding and dividing wafer portion

100. 200: support body

101: pressing body

102: light collector

103: laser

104: grinding machine

300: ring frame

301: film-like adhesive

301 a: cut film-like adhesive

302: support sheet

303: transfer sheet

C: circuit layer

And (3) CP: semiconductor chip (semiconductor device)

d 1: longitudinal direction of the long side

d 2: short side direction

d 3: direction shown by V notch

d 4: pasting direction (tension direction)

E: dividing predetermined line

G: gap

M: modified part

P: crack (crack)

R: singulating predetermined areas

Wv: v-notch

W: wafer

WI: singulated wafer

Claims

1. A method for manufacturing a semiconductor device having a rectangular planar shape,

2. The method for manufacturing a semiconductor device according to claim 1,

3. The method for manufacturing a semiconductor device according to claim 1 or 2,

the aspect ratio of the planned singulation region, which is represented by the length in the longitudinal direction/the length in the short-side direction, is 1.05 or more.

4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3,

the length of the single slice preset area in the long side direction is 5-50 mm, and the length of the single slice preset area in the short side direction is 2-20 mm.

5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4,

sticking a transfer printing sheet on the back of the ground wafer,

6. A laminate, wherein the laminate comprises: