CN113165121B - Method for manufacturing semiconductor device and laminate - Google Patents

Method for manufacturing semiconductor device and laminate Download PDF

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Publication number
CN113165121B
CN113165121B CN202080006808.4A CN202080006808A CN113165121B CN 113165121 B CN113165121 B CN 113165121B CN 202080006808 A CN202080006808 A CN 202080006808A CN 113165121 B CN113165121 B CN 113165121B
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Prior art keywords
wafer
adhesive sheet
semiconductor device
chips
manufacturing
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CN113165121A (en
Inventor
文田祐介
田久真也
爱泽和人
长谷川裕也
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Lintec Corp
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Lintec Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/50—Working by transmitting the laser beam through or within the workpiece
    • B23K26/53—Working by transmitting the laser beam through or within the workpiece for modifying or reforming the material inside the workpiece, e.g. for producing break initiation cracks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Optics & Photonics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Oil, Petroleum & Natural Gas (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Mechanical Engineering (AREA)
  • Dicing (AREA)

Abstract

The invention provides a method for manufacturing a semiconductor device and a laminate. Even when the distance between adjacent singulated chips is small, cracks and chips are less likely to occur in the manufacturing process. A method for manufacturing a semiconductor device having a rectangular planar shape, wherein an adhesive sheet is stuck on a surface of a wafer including a plurality of rectangular singulation areas arranged in a matrix, the wafer is ground on a back surface of the wafer stuck with the adhesive sheet along a short side direction of the singulation areas, and the chips are divided along a dividing line defining the singulation areas.

Description

Method for manufacturing semiconductor device and laminate
Technical Field
The present invention relates to a method for manufacturing a semiconductor device, and a laminate used in the method for manufacturing a semiconductor device.
Background
As a process for manufacturing a semiconductor device such as a semiconductor chip in which a semiconductor circuit is formed on a silicon substrate, a method called DBG (Dicing Before Grinding: dicing followed by grinding) is known. DBG is the following method: grooves having a depth corresponding to the finished thickness are formed in streets (streets) of the wafer, and the back surface of the wafer is ground so that the grooves formed before are exposed from the back surface of the wafer to divide the wafer into individual semiconductor chips.
For the purpose of increasing the number of chips obtained from one wafer, a method called SDBG (Stealth Dicing Before Grinding: stealth dicing before grinding) has also been proposed. SDBG refers to the following processing method: a laser beam is irradiated to a wafer along a dividing line by positioning a light-condensing point of the laser beam having a wavelength having transparency with respect to the wafer inside the wafer, a modified layer by multiphoton absorption is formed inside the wafer, and then the wafer is thinned by grinding the back surface side of the wafer, and the wafer is divided into individual semiconductor chips by taking the modified layer as a dividing start point.
As in the case of the SDBG, if a processing method is used in which the gap between the chips in the divided wafer is extremely small, chipping or cracking may occur in the singulated semiconductor chips. For this reason, for example, patent document 1 proposes providing a notch preventing layer made of a metal film or the like at each intersection of lines to be divided on the wafer surface.
Prior art literature
Patent literature
Patent document 1: japanese patent laid-open publication No. 2018-6653
Disclosure of Invention
Problems to be solved by the invention
However, the demand for miniaturization of the chip size is increasing, and with miniaturization of the semiconductor chip, the problem of cracking and chipping of the semiconductor chip becomes remarkable. According to the study of the present inventors, the following situation was revealed: in the case of using a method of minimizing the gap formed by dicing by using DBG, or a method of making the interval between adjacent chips substantially zero at the dicing timing of a wafer as in the case of SDBG, if the chip size is reduced, the problem of cracks or chipping due to contact between adjacent chips becomes more remarkable. Accordingly, a new and useful method for manufacturing a semiconductor device is demanded which can more effectively prevent chipping and cracking of a chip.
In view of the above, an object of the present invention is to provide a method for manufacturing a semiconductor device, and a laminate suitable for the method, in which cracks and chips are less likely to occur in a manufacturing process even when the distance between adjacent singulated chips is small.
Means for solving the problems
The present inventors have made intensive studies to solve the above problems, and as a result, have found that the above problems can be solved by appropriately setting the adhering direction of an adhesive sheet to be adhered to a circuit layer forming surface of a wafer based on a predetermined area for singulation of the wafer, and have completed the present invention.
That is, the present invention provides the following [1] to [6].
[1] A method for manufacturing a semiconductor device having a rectangular planar shape, wherein,
an adhesive sheet is adhered to the surface of a wafer including a plurality of rectangular singulation areas arranged in a matrix along the short side direction of the singulation areas,
the back surface of the wafer to which the adhesive sheet is attached is ground, and the wafer is divided along a dividing line defining the dividing predetermined region.
[2] The method for manufacturing a semiconductor device according to the above [1], wherein,
after the adhesive sheet is adhered to the surface of the wafer, a modified portion is formed as a start point of division inside the wafer at a planar position corresponding to the division scheduled line,
and grinding the back surface of the wafer to which the adhesive sheet is attached, and dividing the wafer along the dividing line.
[3] The method for manufacturing a semiconductor device according to the above [1] or [2], wherein the aspect ratio of the region to be singulated, expressed by the length in the long side direction/the length in the short side direction, is 1.05 or more.
[4] The method for manufacturing a semiconductor device according to any one of [1] to [3], wherein the length in the longitudinal direction of the region to be singulated is 5 to 50mm and the length in the short direction is 2 to 20mm.
[5] The method for manufacturing a semiconductor device according to any one of the above [1] to [4], wherein a transfer sheet is attached to the back surface of the wafer after grinding,
after the transfer sheet is attached, the adhesive sheet is separated from the wafer.
[6] A laminate, wherein the laminate comprises:
a wafer including a plurality of rectangular singulated predetermined regions arranged in a matrix; and
and an adhesive sheet which is adhered to the surface of the wafer in a state where tension is applied along the short side direction of the region to be singulated.
ADVANTAGEOUS EFFECTS OF INVENTION
According to the present invention, it is possible to provide a method for manufacturing a semiconductor device, and a laminate suitable for the method, in which cracks and chipping are less likely to occur in chips in a manufacturing process even when the distance between adjacent singulated chips is small.
Drawings
Fig. 1 is a schematic cross-sectional view of a wafer on which a circuit layer is formed, a laminate in which an adhesive sheet is attached to the circuit layer of the wafer, and a semiconductor chip as a semiconductor device obtained by processing the wafer using the laminate.
Fig. 2 is an explanatory diagram showing a relationship between a bonding direction of an adhesive sheet to a wafer and a predetermined area for singulation on the wafer.
Fig. 3 is a schematic cross-sectional view showing a process for producing a laminate.
Fig. 4 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device.
Fig. 5 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device.
Fig. 6 is a schematic plan view showing a wafer used in the method for manufacturing a semiconductor device according to the embodiment of the present invention in comparison with a wafer used in the method for manufacturing a semiconductor device according to the comparative example.
Detailed Description
Hereinafter, an embodiment of the present invention (hereinafter, sometimes referred to as "the present embodiment") will be described.
[ wafer, laminate, and semiconductor device ]
The semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present embodiment includes a wafer portion and a circuit portion formed on a surface thereof, and has a rectangular planar shape. In the present specification, the term "semiconductor device" refers to all devices that are used by a processor, a memory, a sensor, and the like and can function by utilizing semiconductor characteristics. Specifically, examples of the wafer including an integrated circuit, the thinned wafer including an integrated circuit, the chip including an integrated circuit, the thinned chip including an integrated circuit, the electronic component including these chips, and the electronic device including the electronic component are given. Also included are the chips prior to packaging.
The semiconductor device is obtained by singulating a wafer provided with a circuit layer on a surface.
In the step of processing a wafer provided with a circuit layer into a semiconductor device, a laminate having an adhesive sheet adhered to a circuit layer formation surface of the wafer is used.
Hereinafter, a wafer, a stacked body, and a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.
Fig. 1 is a schematic cross-sectional view of a wafer on which a circuit layer is formed, a laminate in which an adhesive sheet is attached to a surface of the wafer on which the circuit layer is formed, and a semiconductor chip as a semiconductor device obtained by processing the wafer.
As shown in fig. 1 (a), first, a wafer W having a circuit layer C formed on the surface thereof is prepared by a semiconductor formation process including photolithography.
Next, as shown in fig. 1 (B), an adhesive sheet 1 is attached to the surface of the wafer W on which the circuit layer C is formed, to obtain a laminate 10.
Further, as shown in fig. 1 (C), the back surface of the wafer W is ground as needed, and the wafer W is divided along a dividing line defining a dividing predetermined region, thereby forming a singulated wafer WI. In this way, the wafer W having the circuit layer C is singulated into a plurality of pieces, and the semiconductor chip CP as the semiconductor device is obtained. The singulation of the predetermined areas will be described in detail later.
< wafer >
The wafer W is produced by cutting high-purity single crystal silicon into a disk shape. The diameter of the wafer W is not limited thereto, and is, for example, 12 inches.
The circuit layer C is a layer including a semiconductor circuit formed on the surface of the wafer W by a semiconductor manufacturing process.
The semiconductor process includes a step of forming a semiconductor circuit by photolithography after forming a thin film of silicon oxide, aluminum, or the like, which is a material of the circuit, on a silicon wafer by sputtering, plating, CVD, or the like.
The photolithography method comprises: covering the thin film formed on the silicon wafer with a resist film; a step of irradiating the resist film with UV light through a mask having a circuit pattern formed thereon; developing and selectively removing an uncured portion of the resist film; etching and removing the thin film exposed by the development; a step of implanting impurities such as phosphorus and boron into the silicon substrate exposed by etching to impart semiconductor characteristics; a step of activating impurity ions by heat treatment using a flash lamp, laser irradiation, or the like; and a step of peeling the resist film.
< semiconductor device >
As an example, the wafer W is divided into a plurality of semiconductor chips each having a size of about 12mm×6mm in plan view. When divided into these dimensions, approximately 1000 semiconductor chips were obtained from a wafer having a diameter of 12 inches.
As described above, the semiconductor chip as the semiconductor device includes the wafer portion derived from the wafer W and the circuit portion derived from the circuit layer C formed on the surface thereof.
The semiconductor chip obtained by the method of manufacturing a semiconductor device according to the present embodiment has a rectangular planar shape. Accordingly, various functions can be provided to the semiconductor chip, or the upper and lower sides of the semiconductor chip can be easily grasped.
< laminate >
The laminate 10 has an adhesive sheet 1 adhered to the surface of a wafer W on which a circuit layer C is formed.
(adhesive sheet)
The adhesive sheet 1 is a laminate including a base layer and an adhesive layer laminated on the base layer, and typically includes a base layer, a buffer layer provided on at least one surface side of the base layer, and an adhesive layer provided on the other surface side of the base layer. The pressure-sensitive adhesive sheet 1 may include other structural layers than those, and for example, a primer layer may be formed on the surface of the base material on the pressure-sensitive adhesive layer side, or a release sheet for protecting the pressure-sensitive adhesive layer until use may be laminated on the surface of the pressure-sensitive adhesive layer. The substrate may be a single layer or a plurality of layers. The same applies to the buffer layer and the adhesive layer. The adhesive sheet 1 is attached to the wafer W such that the adhesive layer of the adhesive sheet 1 contacts the circuit layer C of the wafer W, and the adhesive sheet 1 functions as a protective film for protecting the circuit layer C of the wafer W.
(substrate layer)
The material of the base material layer is not particularly limited, and is preferably a resin film from the viewpoint of easy availability because it is suitable for a processing member of an electronic component because it generates less dust and dirt than paper or nonwoven fabric. By providing the adhesive sheet with a base layer, the shape stability of the adhesive sheet can be improved or toughness can be imparted to the adhesive sheet. Even when the irregularities of the circuit layer C of the wafer W are large, the surface opposite to the surface to which the adhesive sheet is adhered is easily kept smooth.
The base material layer may be a base material layer formed of a single layer film formed of one resin film, or may be a base material layer formed of a multilayer film formed by laminating a plurality of resin films.
The thickness of the base layer is preferably 5 to 250 μm, more preferably 10 to 200 μm, and even more preferably 25 to 150 μm from the viewpoint of imparting an appropriate elastic force to the adhesive sheet and from the viewpoint of handling properties at the time of winding the adhesive sheet.
Examples of the resin film that can be used for the base layer include polyolefin films, vinyl halide polymer films, acrylic resin films, rubber films, cellulose films, polyester films, polycarbonate films, polystyrene films, polyphenylene sulfide films, cycloolefin polymer films, and films composed of a cured product of an energy ray-curable composition containing a polyurethane resin.
The polyester film used for the base layer may be a film made of a copolymer of polyester or a resin blend film made of a mixture of the above polyester and a relatively small amount of other resin. Among these polyester films, polyethylene terephthalate films are preferred from the viewpoints of easy availability and high thickness accuracy.
(adhesive layer)
The adhesive layer provided on the base material layer or the intermediate layer protects the circuit layer C by reliably fixing the adhesive sheet to the circuit layer C of the wafer W.
The adhesive layer comprises an adhesive. Examples of the adhesive include an acrylic adhesive, a rubber adhesive, a urethane adhesive, a silicone adhesive, a polyvinyl ether adhesive, and an olefin adhesive. These binders may be used singly or in combination.
The thickness of the pressure-sensitive adhesive layer can be appropriately adjusted according to the size of the irregularities of the circuit layer to be protected, and is preferably 5 to 200. Mu.m, more preferably 7 to 150. Mu.m, and still more preferably 10 to 100. Mu.m.
(intermediate layer)
The intermediate layer is not particularly limited, and is preferably formed of a resin composition containing urethane (meth) acrylate and a thiol group-containing compound from the viewpoint of obtaining good uneven absorbability.
The thickness of the intermediate layer may be appropriately adjusted according to the size of the irregularities on the semiconductor surface to be protected, and is preferably 50 to 400 μm, more preferably 70 to 300 μm, and even more preferably 80 to 250 μm from the viewpoint of being able to absorb relatively large irregularities.
(direction of adhering the adhesive sheet)
Fig. 2 is an explanatory diagram showing a relationship between the direction in which the adhesive sheet 1 is attached to the wafer W and the region R to be singulated on the wafer W.
As shown in fig. 2 (a), V-notch Wv indicating a reference direction of processing and working of the wafer W and semiconductor circuits provided in the individual predetermined areas R defined by the dividing lines E are formed on the surface of the wafer W. The semiconductor circuit is formed with reference to the direction shown by V notch Wv. The adhesive sheet to be described later is also bonded with reference to the direction indicated by V notch Wv.
Here, the region R to be singulated is rectangular in plan view. The dividing line E defining the region R is virtual, and it is not necessary to physically form the dividing line E defining the region R on the surface of the wafer W and the circuit layer C as long as the circuits are formed so as not to cross the dividing line E. However, in order to easily identify the region R to be singulated or to smoothly divide the wafer W, a processing groove or the like to be the line E to be divided may be formed in advance by photolithography.
By setting the singulation target area R to be rectangular, the shape of the finally obtained semiconductor chip is also rectangular.
In the example shown in fig. 2 a, each circuit of the circuit layer C is formed so that the short-side direction d2 of each region R to be singulated coincides with the direction d3 (hereinafter also referred to as the longitudinal direction) shown by the V-notch Wv. Thus, the longitudinal direction d1 of the region to be singulated coincides with the direction (hereinafter also referred to as the lateral direction) orthogonal to the direction d3 shown by the V-notch Wv.
The length of the region R to be singulated in the longitudinal direction is preferably 5 to 50mm, more preferably 7 to 40mm, and even more preferably 10 to 30mm, from the viewpoint of easily suppressing chipping and cracking of the semiconductor chip during the manufacturing process and easily imparting various functions to the semiconductor chip.
The length of the region R to be singulated in the short side direction is preferably 2 to 20mm, more preferably 3 to 18mm, and even more preferably 4 to 15mm, from the viewpoint of improving the ease of handling or providing a desired minimum function to the semiconductor chip.
The aspect ratio of the length in the longitudinal direction to the length in the short direction (length in the longitudinal direction/length in the short direction) of the region R to be singulated is preferably 1.05 or more, more preferably 1.10 or more, still more preferably 1.15 or more, and is preferably 10 or less, more preferably 7.0 or less, still more preferably 5.0 or less, from the viewpoint of properly maintaining the balance between the notch and crack suppression property of the semiconductor chip in the manufacturing process and the function imparting property of the semiconductor chip.
In the present embodiment, as described later, the wafer W is divided by the SDBG at the time of manufacturing the semiconductor device, and therefore, the distance between adjacent chips is substantially zero. Therefore, the lengths of the singulation target area R in the longitudinal and lateral directions coincide with the lengths of the semiconductor chips in the longitudinal and lateral directions.
The semiconductor circuit may not be provided outside the region R to be singulated, or may be provided outside the region to be singulated as a dummy circuit.
As shown in fig. 2 (B), the adhesive sheet 1 has a length and a width capable of covering the entire surface of the wafer W. In the case of using a wafer W having a diameter of 12 inches, for example, a long adhesive sheet having a width of 400mm may be used as the adhesive sheet 1. In fig. 2 (B), for ease of understanding, the wafer W covered with the adhesive sheet 1 and the region R to be singulated are shown with thin lines. If a pressure-sensitive adhesive sheet having light transmittance is used as the pressure-sensitive adhesive sheet 1, the shape and arrangement direction of the regions R to be singulated can be confirmed through the pressure-sensitive adhesive sheet 1.
When the adhesive sheet 1 is attached, the wafer W is set on the attaching device with reference to the direction d3 indicated by the V-notch Wv. At this time, the wafer W is set so that the adhering direction d4 of the adhesive sheet 1 of the adhering device is along the direction d3 indicated by the V-notch Wv. Thus, in the present embodiment, the short-side direction d2 of the region R to be singulated is along the direction d3 indicated by the V notch Wv.
After the adhesive sheet 1 is attached to the circuit layer C of the wafer W, the adhesive sheet 1 extending from the wafer W is cut and removed as necessary. As will be described later, when the adhesive sheet 1 is attached by a method or the like in which the adhesive sheet 1 is attached while applying tension so as to eliminate the deflection of the adhesive sheet 1, the adhesive sheet 1 is attached to the circuit layer C in a state in which tension is applied in the attaching direction d4 of the adhesive sheet 1. Thereby, the laminated body 10 is formed in a state where tension is applied in the direction along the short-side direction d2 of the region R to be singulated.
Here, the adhering direction d4 of the adhesive sheet is set to be along the direction d3 indicated by the V-notch Wv (i.e., the short-side direction d2 of the region R to be singulated in this example), but as shown in fig. 2 (B), the adhering direction d4 of the adhesive sheet 1 may be set to be within a certain angle θ with respect to the direction d3 indicated by the V-notch Wv. Here, θ is preferably within a range of ±45°, more preferably ±40°, and even more preferably ±35° with respect to the direction d3 shown by the V-notch Wv.
[ method for producing laminate ]
Fig. 3 is a schematic cross-sectional view showing a process for producing a laminate. Fig. 3 (a) is a view showing a case where the wafer W on which the circuit layer C is formed is placed on the support 100, fig. 3 (B) is a view showing a case where the adhesive sheet 1 is attached to the circuit layer C of the wafer W, and fig. 3 (C) is a view showing a case where the adhesive sheet 1 is attached to the circuit layer C of the wafer W.
As shown in fig. 3 (a), after the wafer W is placed on the support 100 so that the back surface of the wafer W on which the circuit layer C is formed contacts the support 100, the adhesive sheet 1 is attached to the circuit layer C of the wafer W as shown in fig. 3 (B). In this example, the adhesive sheet 1 is held in a state of being lifted from the wafer W by winding the adhesive sheet 1 by a winding member or by gripping one end of the adhesive sheet 1 by a gripping member, and the adhesive sheet 1 is adhered to the formation surface of the circuit layer C of the wafer W while the adhesive sheet 1 is sequentially pressed from the other end by the pressing body 101.
At this time, in order to eliminate the slack of the adhesive sheet 1 as much as possible, a constant tension is applied in the longitudinal direction of the adhesive sheet 1 (i.e., the adhering direction of the adhesive sheet 1), or a pressing force of a pressing body is applied in the longitudinal direction of the adhesive sheet 1, so that the adhesive sheet 1 is adhered to the wafer W in a state where a tension is applied in the adhering direction d 4. The adhesive sheet 1 is adhered to the circuit layer C of the wafer W in a state where little tension is applied in the width direction of the adhesive sheet 1.
After the adhesive sheet 1 is attached to the circuit layer C, the adhesive sheet 1 extending from the wafer W is cut and removed as necessary. As shown in fig. 3 (C), a laminate 10 having the adhesive sheet 1 adhered to the circuit layer C of the wafer W is produced.
The material constituting the support 100 is not particularly limited, and a metal material such as stainless steel is used.
[ method for manufacturing semiconductor device ]
An example of the method for manufacturing a semiconductor device according to the present embodiment includes the steps of: the laminate having the adhesive sheet adhered to the circuit layer of the wafer is processed, the wafer is divided, the back surface of the wafer is ground, the transfer sheet is adhered to the surface of the divided wafer opposite to the circuit layer forming surface (i.e., the back surface of the wafer), and after the adhesive sheet is removed, the wafer is cut together with the transfer sheet to be singulated. The respective steps will be described in order below. The transfer sheet is a sheet for holding a wafer by being attached to the back surface of the wafer and transferring the wafer to the front surface of the wafer after the wafer is separated from the adhesive sheet.
Fig. 4 and 5 are schematic cross-sectional views showing a manufacturing process of the semiconductor device.
Fig. 4 (a) is a diagram showing a state in which the laminated body 10 is mounted on a support 200 different from the support 100. As shown in fig. 4 (a), the laminate 10 is placed on the support 200 so that the adhesive sheet 1 contacts the support 200. As the support 200, for example, a support made of the same material as the support 100 or a porous plate made of ceramic may be used.
Fig. 4 (B) is a diagram showing a case where the wafer W is irradiated with laser light from the back surface side. As shown in fig. 4 (B), the condenser 102 is used to position the laser beam 103 so that the converging point of the laser beam 103 having a wavelength that is transparent to the wafer W is located inside the wafer W, and the laser beam 103 is irradiated from the back side to the wafer W while relatively moving the laser beam 103 and the wafer W along the dividing line E defining the dividing region R. Thereby, the modified portion M is formed inside the wafer W at the planar position corresponding to the line to divide E. The modification section M is a portion to be modified by irradiation of laser light, and serves as a starting point for cutting the wafer W.
Fig. 4 (C) is a diagram showing a case of grinding the back surface side of the wafer W. As shown in fig. 4 (C), the back surface of the wafer W is ground by the grinder 104 until a desired thickness is reached. By this process, the wafer W is thinned and lightened. At the same time, the wafer W is cut along the line E defining the region R for dividing, starting from the modified portion M. The modified portion M formed in the wafer W is removed by grinding.
In SDBG, when a wafer is divided at the time of grinding, there is only a crack (reference sign P of fig. 4 (C)) based on stealth dicing between adjacent chips, and the distance between the chips is substantially zero. Therefore, the chips are displaced by a minute stress or impact, and the chips are likely to be in contact with each other, pressed, rubbed, or bumped, and thus a crack is likely to be generated. In addition, when an adhesive sheet such as a protective sheet for back grinding is attached, since tension is applied in the attaching direction thereof to attach, a laminate after the adhesive sheet is attached is liable to remain in stress. Therefore, it is supposed that the wafer W is cut from the modified portion M as a starting point by grinding the back surface of the wafer, and at the same time, the stress in the laminate is released, and the chips are easily moved in the adhesion direction of the adhesive sheet, and as a result, the chips are brought into contact with each other, pressed, rubbed, or collided with each other, and cracks are initiated.
In the method for manufacturing a semiconductor device according to the present embodiment, the reasons why chipping and cracking of a chip are suppressed are not limited thereto, but the following reasons can be considered as one. That is, by making the length in the longitudinal direction of the chip different from the length in the lateral direction, and attaching the adhesive sheet along the short side direction of the chip, the number of cutting lines between chips in the attaching direction of the adhesive sheet increases as compared with the case of attaching the adhesive sheet along the long side direction of the chip. From this, it is assumed that the movement amount of the chips in the bonding direction is dispersed by more chips, and the contact, pressing, friction, collision, and the like between the chips are reduced, which involves suppression of cracks and chips.
In the present embodiment, the modified portion is removed by grinding, but for example, in the case where the wafer is originally thick, for example, in the application where thinning of the wafer is not required, at least a part of the modified portion may be left on the wafer after grinding.
Fig. 5 (a) shows a step of separating the laminate 11, which is obtained by grinding and dividing the wafer W, from the support 200. Fig. 5 (B) shows a step of adhering the laminate 11, which is obtained by grinding and dividing the wafer W, to a transfer sheet held by the ring frame 300. Fig. 5 (C) shows a step of separating the pressure-sensitive adhesive sheet 1 from the laminate 11 attached to the transfer sheet 303. Fig. 5 (D) shows an expanding step of separating each chip from the transfer sheet 303.
As shown in fig. 5 (a), the laminate 11, which is separated from the support 200 and from which the wafer W is ground and divided, is attached to a film-like adhesive 301 of a transfer sheet 303 including a film-like adhesive 301 and a support sheet 302, which is held around by a ring frame 300, as shown in fig. 5 (B). Next, as shown in fig. 5 (C), the adhesive sheet 1 is separated from the laminate 11 after grinding and dividing the wafer W, and further, as shown in fig. 5 (D), the film-like adhesive 301 is cut together with the chips (the cut film-like adhesive is denoted by reference numeral 301 a) by stretching the support sheet 302, whereby the chips are separated into individual chips with a gap G therebetween.
As the transfer sheet 303, for example, a transfer sheet in which a film-like adhesive 301 having curability is provided on a support sheet 302 including a base material made of the same material as that of the base material layer of the adhesive sheet 1 via an adhesive layer as needed can be used.
According to the above manufacturing method, the occurrence of chipping and cracking of the chip can be suppressed in the manufacturing process, and the semiconductor device can be manufactured with high yield.
In the present embodiment, the wafer is divided by the SDBG, but the present invention is not limited to this, and for example, the wafer may be divided by the DBG. In the case of using DBG, when the distance between chips formed by dicing is small, the effect of preventing chipping and cracking of the chips is easily exhibited. In the case of using DBG, the wafer is half-cut from the front surface of the wafer on which the circuit layer is formed, and then an adhesive sheet is attached to the circuit formation surface of the wafer, and then the back surface of the wafer is ground.
Examples
Specific examples of the present invention will be described below, but the present invention is not limited to these examples.
Examples and comparative examples
The chips of examples 1 to 3 and comparative examples 1 to 4 were prepared by the following procedure. In examples 1 to 3 and comparative examples 1 to 4, mirror wafers in which all the circuit layers were not formed were used in order to make the experimental conditions as uniform as possible and to facilitate the experiment.
Example 1]
A mirror wafer of single crystal silicon having a diameter of 12 inches was prepared, and an adhesive sheet was attached to one surface (hereinafter referred to as the first surface) of the wafer along the direction indicated by the apex of the V-notch (hereinafter referred to as the longitudinal direction) with reference to the V-notch provided in the mirror wafer. As the pressure-sensitive adhesive sheet, a back surface polishing tape "E-3135KN" manufactured by LINTEC Co., ltd was used. The adhesive sheet was applied using an application device (RAD-3510F/12, manufactured by Lindeke Co., ltd.) under conditions of 15 μm in press-in amount, 150 μm in projecting amount, 5mm/s in application speed, 0.35MPa in application stress, and 23 ℃.
Then, SDBG was implemented such that the length in the longitudinal direction was 6mm and the length in the direction orthogonal to the longitudinal direction (hereinafter referred to as the transverse direction) was 12 mm. Specifically, a modified layer is formed in the wafer by laser irradiation from the surface (hereinafter referred to as the second surface) side of the wafer opposite to the first surface by a stealth dicing laser saw "DFL7361" manufactured by Disclina (DISCO) corporation, in such a manner that 980 pieces of predetermined areas for singulation having a size of 6mm in the vertical direction and 12mm in the horizontal direction are arranged in a matrix.
Further, the other surface (hereinafter referred to as the second surface) of the wafer was ground using a back grinding device (DPG 8760, manufactured by dix corporation) until the thickness of the wafer became 30 μm, thereby removing the modified layer in the wafer, and the wafer was cut along a line to divide the predetermined areas.
Then, the second surface of the singulated wafer was stuck to a dicing tape ("D-175" manufactured by Wande Co., ltd.) provided on a tape mounter "RAD-2700" manufactured by Lende Co., ltd, and the adhesive sheet was removed. Next, using an IR camera provided in the invisible dicing laser saw, the number of chips on which cracks were generated was counted, as to whether or not cracks were generated, as seen from the first surface side.
The number of chips with cracks was 1 out of 980, and the crack generation rate was 0.10%.
Example 2]
The wafer was singulated so as to obtain 1471 chips by performing SDBG-based processing under the same conditions as in example 1 except that the wafer was 4mm long in the longitudinal direction and 12mm long in the lateral direction with respect to the wafer with the adhesive sheet attached to the first surface in the longitudinal direction in the same manner as in example 1.
As a result of observation in the same manner as in example 1, 1 out of 1471 chips having cracks, the crack generation rate was 0.07%.
Example 3]
The wafer was singulated so as to obtain 735 chips by performing SDBG-based processing under the same conditions as in example 1, except that the wafer was 8mm long in the longitudinal direction and 12mm long in the lateral direction with respect to the wafer with the adhesive sheet adhered to the first surface in the longitudinal direction in the same manner as in example 1.
As a result of observation in the same manner as in example 1, 1 out of 735 chips having cracks, the crack generation rate was 0.13%.
Comparative example 1]
The wafer was singulated so as to become 980 chips by performing SDBG-based processing under the same conditions as in example 1, except that the length in the longitudinal direction was 12mm and the length in the lateral direction was 6mm with respect to the wafer to which the adhesive sheet was attached on the first surface in the longitudinal direction in the same manner as in example 1.
Fig. 6 is a schematic plan view showing an example of the present invention in comparison with a comparative example. As shown in fig. 6 (a), in the wafer W1 of examples 1 and 2, the bonding direction d4 of the adhesive sheet 1 and the short-side direction d2 of the region R to be singulated are aligned with the direction d3 shown by V notch Wv. On the other hand, as shown in fig. 6 (B), in the wafer W2 of comparative example 1, the bonding direction d4 of the adhesive sheet and the longitudinal direction d1 of the region R to be singulated are made to coincide with the direction d3 shown by the V notch.
As a result of observation in the same manner as in example 1, the number of chips having cracks was 11 out of 980, and the crack generation rate was 1.12%.
Comparative example 2]
The wafer was subjected to SDBG-based processing under the same conditions as in example 1 except that the length in the longitudinal direction was 12mm and the length in the lateral direction was 4mm with respect to the wafer to which the adhesive sheet was attached on the first surface as in example 1, and singulated into 1471 chips.
As a result of observation in the same manner as in example 1, 14 chips out of 1471 were cracked, and the crack generation rate was 0.95%.
Comparative example 3]
The wafer was subjected to SDBG processing under the same conditions as in example 1 except that the length in the longitudinal direction was 12mm and the length in the lateral direction was 12mm with respect to the wafer to which the adhesive sheet was attached on the first surface as in example 1, and singulated into 490 chips.
As a result of observation in the same manner as in example 1, 6 chips out of 490 chips having cracks were produced, and the crack production rate was 1.22%.
Comparative example 4]
The wafer was subjected to SDBG-based processing under the same conditions as in example 1 except that the length in the longitudinal direction was 12mm and the length in the lateral direction was 8mm with respect to the wafer to which the adhesive sheet was attached on the first surface as in example 1, and singulated into 735 chips.
As a result of observation in the same manner as in example 1, 9 chips out of 735 chips having cracks were produced, and the crack production rate was 1.22%.
The results of examples 1 to 3 and comparative examples 1 to 4 are shown in Table 1.
TABLE 1
As is clear from the results in table 1, in examples 1 to 3 in which the bonding direction of the adhesive sheet was aligned with the short side direction of the chip, the number of chips in which cracks were generated was small, and the crack generation rate also showed a very small value.
In contrast, in comparative examples 1, 2, and 4 in which the bonding direction of the adhesive sheet was aligned with the longitudinal direction of the chip, the number of chips in which cracks were generated was increased. In particular, it was found that the crack generation rates of comparative examples 1 and 2 increased by 10 times or more as compared with examples 1 and 2, and that comparative example 4 also increased by about 10 times as compared with example 3.
In comparative example 3, in which the chip shape was square and the length of 1 side was equal to the length of the long side of the chips of examples 1 to 3, the number of chips having cracks was increased, and the crack generation rate was increased by 10 times or more and by about 10 times as much as that of examples 1 and 2, respectively.
Industrial applicability
The method for manufacturing a semiconductor device of the present invention is not likely to cause chipping and cracking of chips even when a processing method such as SDBG is used in which a wafer is divided so that a distance between chips becomes extremely small, and can be suitably applied to manufacturing semiconductor chips used for processors, memories, sensors, and the like. The laminate of the present invention can be suitably used in the method for manufacturing a semiconductor device.
Description of the reference numerals
1: pressure-sensitive adhesive sheet
10: laminate body
11: laminate having ground and divided wafer portions
100. 200: support body
101: pressing body
102: condenser
103: laser light
104: grinding machine
300: ring frame
301: film-like adhesive
301a: cut film-like adhesive
302: support sheet
303: transfer sheet
C: circuit layer
CP: semiconductor chip (semiconductor device)
d1: in the long side direction
d2: in the short direction
d3: direction indicated by V notch
d4: pasting direction (tension direction)
E: dividing predetermined line
G: gap of
M: modification part
P: crack and crack
R: singulating predetermined regions
Wv: v-notch
W: wafer with a plurality of wafers
WI: singulated wafers

Claims (5)

1. A method for manufacturing a semiconductor device having a rectangular planar shape, wherein,
an adhesive sheet is adhered to the surface of a disc-shaped wafer including a plurality of rectangular singulation areas arranged in a matrix along the short side direction of the singulation areas,
the aspect ratio of the predetermined region to be singulated, expressed as the length in the long side direction/the length in the short side direction, is 1.05 or more and 7.0 or less,
the back surface of the wafer to which the adhesive sheet is attached is ground, and the wafer is divided along a dividing line defining the dividing predetermined region.
2. The method for manufacturing a semiconductor device according to claim 1, wherein,
after the adhesive sheet is adhered to the surface of the wafer, a modified portion is formed as a start point of division inside the wafer at a planar position corresponding to the division scheduled line,
and grinding the back surface of the wafer to which the adhesive sheet is attached, and dividing the wafer along the dividing line.
3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein,
the aspect ratio of the predetermined region to be singulated, expressed as the length in the long side direction/the length in the short side direction, is 1.05 or more and 5.0 or less.
4. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein,
the length of the single-chip preset area in the long side direction is 5-50 mm, and the length of the single-chip preset area in the short side direction is 2-20 mm.
5. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein,
a transfer sheet is stuck on the back surface of the ground wafer,
after the transfer sheet is attached, the adhesive sheet is separated from the wafer.
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