WO2020169027A1 - 显示驱动电路、显示模组、显示屏的驱动方法及电子设备 - Google Patents

显示驱动电路、显示模组、显示屏的驱动方法及电子设备 Download PDF

Info

Publication number
WO2020169027A1
WO2020169027A1 PCT/CN2020/075721 CN2020075721W WO2020169027A1 WO 2020169027 A1 WO2020169027 A1 WO 2020169027A1 CN 2020075721 W CN2020075721 W CN 2020075721W WO 2020169027 A1 WO2020169027 A1 WO 2020169027A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
clock signal
display
clock
goa
Prior art date
Application number
PCT/CN2020/075721
Other languages
English (en)
French (fr)
Inventor
韦育伦
刘俊彦
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201910844205.0A external-priority patent/CN111613181B/zh
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP20759437.5A priority Critical patent/EP3920172A4/en
Priority to US17/433,201 priority patent/US11508311B2/en
Publication of WO2020169027A1 publication Critical patent/WO2020169027A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3666—Control of matrices with row and column drivers using an active matrix with the matrix divided into sections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0828—Several active elements per pixel in active matrix panels forming a digital to analog [D/A] conversion circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0221—Addressing of scan or signal lines with use of split matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0238—Improving the black level

Definitions

  • This application relates to the field of terminal technology, and in particular to a display driving circuit, a display module, a driving method of a display screen, and electronic equipment.
  • the plurality of display driving circuits may include one main display driving circuit and at least one auxiliary display driving circuit.
  • the main display driving circuit sends the internally generated clock signal to the auxiliary display driving circuit, and the auxiliary display driving circuit performs time synchronization based on the received clock signal, so as to realize synchronization between the multiple display driving circuits.
  • this synchronization method is only used for synchronizing vertical synchronization (V-Sync) and horizontal synchronization (H-Sync) signals between multiple display driving circuits.
  • V-Sync vertical synchronization
  • H-Sync horizontal synchronization
  • the vertical synchronization signal is used for synchronization between frames of the scanned image
  • the horizontal synchronization signal is used for synchronization between the line-to-line of the scanned image.
  • the clock signal in the row scanning each row of pixels is generated based on the internal clock signal of each display driving circuit, and clock synchronization is not performed. Due to the error of the internal clock frequency of different display driving circuits, the display performance of the display screen will be affected.
  • the present application provides a display driving circuit, a display module, a driving method of a display screen, and electronic equipment, which can improve the display performance of the display screen.
  • an electronic device including: a display screen, including a first display area and a second display area; a main controller, including a first clock output terminal, the first clock output terminal is used to separately A display driving circuit and a second display driving circuit send a first clock signal; the first display driving circuit includes a first clock receiving end, and the first clock receiving end is used to receive the first clock signal; The first display driving circuit also includes a first gate drive array GOA clock signal output terminal, the first GOA clock signal output terminal is used to output a first GOA clock signal to the display screen, and the first GOA clock signal is used for Control the GOA of the first display area to turn on or off, wherein the first GOA clock signal is generated based on the first clock signal; the second display driving circuit includes a second clock receiving end, the The second clock receiving terminal is used to receive the first clock signal; the second display driving circuit further includes a second GOA clock signal output terminal, and the second GOA clock signal output terminal is used to output the first clock signal to the display screen.
  • each of the plurality of display driving circuits in the electronic device may receive the first clock signal sent by the main controller, and generate the GOA clock signal based on the first clock signal, so that a plurality of The GOA clock signals output by the display drive circuit to the display screen are all generated based on the same clock signal, which can reduce the error between the frequencies of the GOA clock signals between different display drive circuits and improve the display performance of the display screen.
  • the first display driving circuit further includes a first vertical synchronization signal output terminal for outputting a first vertical synchronization signal to the display screen, wherein the first vertical synchronization signal A vertical synchronization signal is generated based on the first clock signal, and the first vertical synchronization signal is used for frame synchronization of the first display area;
  • the second display driving circuit also includes a second vertical synchronization signal output Terminal, used to output a second vertical synchronization signal to the display screen, where the second vertical synchronization clock signal is generated based on the first clock signal, and the second vertical synchronization signal is used to perform the first
  • the first vertical synchronization signal and the second vertical synchronization signal are signals with the same phase.
  • each of the plurality of display driving circuits in the electronic device can receive the first clock signal sent by the main controller, and generate a vertical synchronization signal based on the first clock signal, so that a plurality of The vertical synchronization signal output by the display drive circuit to the display screen is generated based on the same signal, so the frequency error of the vertical synchronization signal between different display drive circuits can be reduced, and the difference between the vertical synchronization signal and the GOA clock signal can be reduced.
  • the timing error between time improves the display performance of the display.
  • the first display driving circuit further includes a first horizontal synchronization signal output terminal for outputting a first horizontal synchronization signal to the display screen, wherein the first horizontal synchronization signal A horizontal synchronization signal is generated based on the first clock signal, and the first horizontal synchronization signal is used for line synchronization of the first display area;
  • the second display driving circuit also includes a second horizontal synchronization signal output Terminal, used to output a second horizontal synchronization signal to the display screen, where the second horizontal synchronization signal is generated based on the first clock signal, and the second horizontal synchronization signal is used to perform the second Line synchronization of the display area.
  • each of the multiple display drive circuits in the electronic device receives the first clock signal sent by the main controller, and generates a horizontal synchronization signal based on the first clock signal, so that multiple displays
  • the horizontal synchronization signal output by the driving circuit to the display screen is generated based on the same clock signal. Therefore, the frequency error of the horizontal synchronization signal between different display driving circuits can be reduced, and the difference between the horizontal synchronization signal and the GOA clock signal can be reduced.
  • the timing error between time improves the display performance of the display.
  • the first display driving circuit further includes a first light-emitting EM signal output terminal for outputting a first EM signal to the display screen, and the first EM signal For controlling the pixel circuit in the first display area to emit or not emit light, wherein the first EM signal is generated based on the first clock signal; and/or, the second display driving circuit further includes The second EM signal output terminal is used to output a second EM signal to the display screen, and the second EM signal is used to control the pixel circuit in the second display area to emit or not emit light, wherein the second The EM signal is generated based on the first clock signal.
  • each of the multiple display drive circuits in the electronic device receives the first clock signal sent by the main controller, and generates an EM signal based on the first clock signal, so that multiple display drive circuits
  • the EM signal output by the circuit to the display screen is generated based on the same clock signal, so the frequency error of the EM signal between different display driving circuits can be reduced, and the timing error between the EM signal and the GOA clock signal can be reduced, Improved the display performance of the display.
  • the first display drive circuit includes a video processing module, and the video processing module is configured to process video data input by the main controller to generate The video source signal sent by the display screen, the reference clock of the digital circuit in the video processing module is the third clock signal generated by the internal clock generation module of the first display drive circuit, and the analog circuit in the video processing module The reference clock is the first clock signal.
  • the display drive circuit uses the first clock signal sent by the main controller as the reference clock of the analog circuit in the display drive circuit, and at the same time uses the internally generated third clock signal as the digital circuit in the display drive circuit.
  • the reference clock can reduce the frequency error between the clock signals of multiple display driving circuits, and can reduce the problems of timing convergence and electromagnetic interference.
  • a first buffer is provided in the video processing module, and the first buffer is provided between the digital circuit and the analog circuit in the video processing module.
  • a display drive circuit in a second aspect, includes: a first clock receiving terminal for receiving a first clock signal sent by a main controller; a first gate drive array GOA clock signal output terminal, so The first GOA clock signal output terminal is used to output a first GOA clock signal to the display screen, the first GOA clock signal is used to control the GOA of the display screen to turn on or off, wherein the first GOA clock The signal is generated based on the first clock signal.
  • the display driving circuit of the second aspect is based on the same inventive concept as the electronic device of the first aspect. Therefore, the beneficial technical effects that can be achieved by the technical solution of the second aspect can be referred to the description of the first aspect and will not be repeated.
  • the display driving circuit further includes a first vertical synchronization signal output terminal for outputting a first vertical synchronization signal to the display screen, wherein the first vertical synchronization signal The synchronization signal is generated based on the first clock signal, and the first vertical synchronization signal is used for frame synchronization of the display screen.
  • the display driving circuit further includes a first horizontal synchronization signal output terminal for outputting a first horizontal synchronization signal to the display screen, wherein the first horizontal synchronization signal The synchronization signal is generated based on the first clock signal, and the first horizontal synchronization signal is used for line synchronization of the display screen.
  • the first display driving circuit further includes a first light-emitting EM signal output terminal for outputting a first EM signal to the display screen, and the first EM signal A pixel circuit for controlling the display screen to emit light or not, wherein the first EM signal is generated based on the first clock signal.
  • the display drive circuit includes a video processing module, and the video processing module is configured to process the video data input by the main controller to generate the video data input to the display screen.
  • the reference clock of the digital circuit in the video processing module is the third clock signal generated by the internal clock generation module of the display drive circuit, and the reference clock of the analog circuit in the video processing module is Mentioned first clock signal.
  • a first buffer is provided in the video processing module, and the first buffer is provided between the digital circuit and the analog circuit in the video processing module.
  • a method for driving a display screen includes a first display area and a second display area.
  • the method includes: a main controller sends a first display drive circuit and a second display drive circuit to the first display drive circuit.
  • the first display drive circuit sends a first clock signal;
  • the first display drive circuit outputs a first gate drive array GOA clock signal to the display screen, and the first GOA clock signal is used to control the GOA of the first display area to turn on or off, Wherein, the first GOA clock signal is generated based on the first clock signal;
  • the second display driving circuit outputs a second GOA clock signal to the display screen, and the second GOA clock signal is used to control the The GOA of the second display area is turned on or off, wherein the second GOA clock signal is generated based on the first clock signal.
  • the driving method of the display screen of the third aspect is based on the same inventive concept as the electronic device of the first aspect. Therefore, the beneficial technical effects that can be achieved by the technical solution of the third aspect can be referred to the description of the first aspect. Repeat.
  • the method further includes: the first display driving circuit outputting a first vertical synchronization signal to the display screen, wherein the first vertical synchronization signal is based on Generated by the first clock signal, the first vertical synchronization signal is used for frame synchronization of the first display area;
  • the second display driving circuit outputs a second vertical synchronization signal to the display screen, wherein the second vertical synchronization clock signal is generated based on the first clock signal, and the second vertical synchronization signal is used to perform In the frame synchronization of the second display area, the first vertical synchronization signal and the second vertical synchronization signal are signals with the same phase.
  • the first display driving circuit further includes a first horizontal synchronization signal output terminal for outputting a first horizontal synchronization signal to the display screen, wherein the first horizontal synchronization signal A horizontal synchronization signal is generated based on the first clock signal, and the first horizontal synchronization signal is used for line synchronization of the first display area;
  • the second display driving circuit also includes a second horizontal synchronization signal output Terminal, used to output a second horizontal synchronization signal to the display screen, where the second horizontal synchronization signal is generated based on the first clock signal, and the second horizontal synchronization signal is used to perform the second Line synchronization of the display area.
  • the first display drive circuit further includes a first light-emitting EM signal output terminal for outputting a first EM signal to the display screen, and the first EM signal For controlling the pixel circuit in the first display area to emit light or not, wherein the first EM signal is generated based on the first clock signal;
  • the second display driving circuit further includes a second EM signal The output terminal is used to output a second EM signal to the display screen, the second EM signal is used to control the pixel circuit in the second display area to emit light or not, where the second EM signal is based on The first clock signal is generated.
  • the first display drive circuit includes a video processing module, and the video processing module is configured to process video data input by the main controller to generate The video source signal sent by the display screen, the reference clock of the digital circuit in the video processing module is the third clock signal generated by the internal clock generation module of the first display drive circuit, and the analog circuit in the video processing module The reference clock is the first clock signal.
  • a first buffer is provided in the video processing module, and the first buffer is provided between the digital circuit and the analog circuit in the video processing module.
  • a display module including: a display screen, including a first display area and a second display area; a first display driving circuit, including a first clock receiving terminal, the first clock receiving terminal is used for Receiving the first clock signal sent by the main controller; the first display drive circuit further includes a first gate drive array GOA clock signal output terminal, the first GOA clock signal output terminal is used to output the first The GOA clock signal, the first GOA clock signal is used to control the GOA of the first display area to turn on or off, wherein the first GOA clock signal is generated based on the first clock signal; the second display driver The circuit includes a second clock receiving terminal, the second clock receiving terminal is used to receive the first clock signal; the second display driving circuit also includes a second GOA clock signal output terminal, the second GOA clock signal The output terminal is used to output a second GOA clock signal to the display screen, the second GOA clock signal is used to control the GOA of the second display area to turn on or off, and the second GOA clock signal is based on
  • the display module of the fourth aspect is based on the same inventive concept as the electronic device of the first aspect. Therefore, the beneficial technical effects that can be obtained by the technical solution of the fourth aspect can be referred to the description of the first aspect, and will not be repeated.
  • the first display driving circuit further includes a first vertical synchronization signal output terminal for outputting a first vertical synchronization signal to the display screen, wherein the first vertical synchronization signal The vertical synchronization signal is generated based on the first clock signal, and the first vertical synchronization signal is used for frame synchronization of the first display area;
  • the second display driving circuit further includes a second vertical synchronization signal output terminal , For outputting a second vertical synchronization signal to the display screen, where the second vertical synchronization clock signal is generated based on the first clock signal, and the second vertical synchronization signal is used for performing the second
  • the frame synchronization of the display area, the first vertical synchronization signal and the second vertical synchronization signal are signals with the same phase.
  • the first display driving circuit further includes a first horizontal synchronization signal output terminal for outputting a first horizontal synchronization signal to the display screen, wherein the first The horizontal synchronization signal is generated based on the first clock signal, and the first horizontal synchronization signal is used for line synchronization of the first display area;
  • the second display driving circuit further includes a second horizontal synchronization signal output terminal , For outputting a second horizontal synchronization signal to the display screen, where the second horizontal synchronization signal is generated based on the first clock signal, and the second horizontal synchronization signal is used for performing the second display The line synchronization of the area.
  • the first display driving circuit further includes a first light-emitting EM signal output terminal for outputting a first EM signal to the display screen, and the first EM signal is used for For controlling the pixel circuit in the first display area to emit or not emit light, wherein the first EM signal is generated based on the first clock signal;
  • the second display driving circuit further includes a second EM signal output The second EM signal output terminal is used to output a second EM signal to the display screen, and the second EM signal is used to control the pixel circuit in the second display area to emit light or not, wherein the The second EM signal is generated based on the first clock signal.
  • the first display drive circuit includes a video processing module, and the video processing module is configured to process video data input by the main controller to generate a
  • the video source signal sent by the screen, the reference clock of the digital circuit in the video processing module is the third clock signal generated by the internal clock generation module of the first display drive circuit, and the reference of the analog circuit in the video processing module
  • the clock is the first clock signal.
  • a first buffer is provided in the video processing module, and the first buffer is provided between a digital circuit and an analog circuit in the video processing module.
  • the present application provides a circuit system including a processor.
  • the processor is used to read and execute the computer program stored in the memory to execute the method in the third aspect or any possible implementation manner thereof, or execute the method in the fourth aspect or any possible implementation manner thereof.
  • the circuit further includes a memory, and the memory and the processor are connected to the memory through a circuit or a wire.
  • the circuit system further includes a communication interface.
  • the present application provides a computer-readable storage medium having computer instructions stored in the computer-readable storage medium, and when the computer instructions run on a computer, the computer executes the third aspect or any possible implementation manner thereof Method in.
  • the present application provides a computer program product.
  • the computer program product includes computer program code.
  • the computer program code runs on a computer, the computer executes the third aspect or any of its possible implementations. method.
  • FIG. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application. .
  • FIG. 2 is a schematic diagram of a process of processing video data by a multiple display driving circuit system according to an embodiment of the present application.
  • FIG. 3 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present application.
  • FIG. 4 is a schematic circuit diagram of a pixel circuit in a reset phase of an embodiment of the present application.
  • FIG. 5 is a schematic circuit diagram of the data voltage Vdata writing phase of the pixel circuit according to an embodiment of the present application.
  • FIG. 6 is a schematic circuit diagram of a pixel circuit in a light-emitting phase according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a gate driver on array (GOA) according to an embodiment of the present application.
  • GOA gate driver on array
  • FIG. 8 is a timing diagram of GOA according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of an electronic device according to another embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a display driving circuit according to an embodiment of the present application. .
  • FIG. 12 is a schematic structural diagram of a digital circuit of a video processing module in a display driving circuit of an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of an analog circuit of a video processing module in a display driving circuit of an embodiment of the present application.
  • Fig. 14 is a schematic structural diagram of a video processing module according to an embodiment of the present application.
  • the embodiments of the present application provide a display driving circuit, a driving method of a multiple display driving circuit system, and an electronic device, which can improve the display performance of a display screen.
  • the display driving circuit may be installed in the electronic device.
  • the electronic device in the embodiment of the present application may include any electronic device including a display screen, such as a user equipment, a mobile terminal, a mobile phone, and a tablet computer (pad), which is not limited in the embodiment of the present application.
  • a display screen such as a user equipment, a mobile terminal, a mobile phone, and a tablet computer (pad), which is not limited in the embodiment of the present application.
  • the electronic device in the embodiment of the present application includes a multi-display driving system, and the multi-display driving system includes a plurality of display driving circuits.
  • the multi-display driving system including two display driving circuits is taken as an example for description. Those skilled in the art can understand that the present application can also be applied to a multi-display driving circuit system including more than two display driving circuits.
  • FIG. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
  • the electronic device 100 is a multi-display driving circuit system. As shown in FIG. 1, the electronic device 100 includes a main controller 110, a first display driving circuit 120, a second display driving circuit 130 and a display screen 140. For ease of description, the definitions of terms involved in FIG. 1 are described below.
  • the main controller 110 is used to output the to-be-processed video data, clock synchronization signal, signaling, etc. to the display driving circuit (120, 130).
  • the main controller may include, but is not limited to, various types of processors such as a system on chip (SOC), an application processor (AP), or a general-purpose processor.
  • the video source signal is used to output to the display screen 130 to drive the display screen 130 to display images.
  • the display driving circuit 120 can also perform emission (EM) control and management, gate driver on array (GOA) control and management, and power supply voltage management on the display screen 130, and output emission (EM) to the display screen.
  • EM emission
  • GOA gate driver on array
  • EM emission
  • Signal light-emitting layer positive voltage (emission layer VDD, ELVDD) signal, light-emitting layer negative voltage (emission layer VSS, ELVSS) signal, GOA clock signal, etc.
  • the video source signal may also be referred to as a source signal.
  • multiple display driving circuits may be connected through an interface to facilitate clock synchronization or interaction.
  • the display driver circuit may also be referred to as a display driver integrated circuit (DDIC).
  • DDIC display driver integrated circuit
  • the display screen 140 is used for receiving video source signals from the display driving circuit 120 and the display driving circuit 130 respectively, and displaying images.
  • the display screen may include a folding display screen or a non-folding display screen.
  • the display screen 140 may be implemented by a flexible screen or a hard display screen.
  • the flexible screen may include, for example, an organic light-emitting diode (OLED) display screen and other structures, which are not limited in the embodiment of the present application.
  • OLED organic light-emitting diode
  • FIG. 2 is a schematic diagram of the flow of video data at the multi-display driving circuit system according to an embodiment of the present application.
  • the display screen 140 may be divided into a first display area 11 and a second display area 12.
  • the first display area 11 corresponds to the first display driving circuit 120
  • the second display area 12 and the second display driving circuit 130 correspond.
  • Different display driving circuits (120, 130) are used to drive different display areas.
  • the main controller 110 may divide the video data into a plurality of sub video data according to a plurality of display areas, and respectively send the sub video data to different display driving circuits. After each of the multiple display drive circuits processes the corresponding sub video data, multiple sub video source signals are obtained.
  • the plurality of display driving circuits may respectively send the plurality of sub video source signals to the display screen to drive different display areas of the display screen to display images.
  • the pixel circuit is the smallest circuit unit in the display screen.
  • a pixel circuit is equivalent to a sub-pixel (or sub-pixel) in the display screen, and the display screen includes multiple rows of sub-pixels.
  • the sub-pixels in the display screen are scanned line by line and emit light. Therefore, when a frame of image is displayed, after the first row of sub-pixels emit light, they need to remain illuminated until the last row of sub-pixels emit light. Realize the display of one frame of image.
  • GOA is used to control the on or off of each row of GOA in the display screen to control the input of the strobe signal for each row of pixel circuits.
  • FIG. 3 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present application.
  • the pixel circuit 50 may include a capacitor Cst, a light emitting device L, and a plurality of transistors (M1, M2, M3, M4, M5, M6, M7).
  • the transistor M1 is called the first reset transistor
  • the transistor M7 is called the second reset transistor
  • the transistor M4 is called the driving transistor
  • the transistor M6 is called the first light emission control transistor
  • the transistor M5 is called the second light emission control transistor.
  • this is only an example of a pixel circuit.
  • the pixel circuit can also adopt other designs, such as a 2T1C circuit including only 2 transistors and 1 capacitor, a 4T1C circuit including 4 transistors and 1 capacitor, including 5T2C circuits with 5 transistors and 2 capacitors, etc., the design of these pixel circuits can control the on and off of a transistor connected in series with the light-emitting device through the EM signal, so as to realize the control of the light-emitting device of the light-emitting device.
  • the application embodiment does not limit this.
  • the above-mentioned light-emitting device L may be an organic light emitting diode (OLED).
  • the display is an OLED display.
  • the light emitting device L may be a micro light emitting diode (mirco light emitting diode, mirco LED).
  • the display is a mirco LED display.
  • the working process of the pixel circuit 50 includes three stages shown in FIGS. 4-6, the first stage 1, the second stage 2, and the third stage 3.
  • the cut-off transistors are distinguished by adding an “ ⁇ ” mark.
  • the first reset transistor M1 and the second reset transistor M7 are turned on.
  • the initial voltage Vint is transmitted to the gate of the driving transistor M4 through the first reset transistor M1, thereby resetting the gate of the driving transistor M4.
  • the initial voltage Vint is transmitted to the anode (anode, a) of the OLED through the second reset transistor M7 to reset the anode a of the OLED.
  • the voltage Va of the anode a of the OLED and the voltage Vg4 of the gate g of the driving transistor M4 are Vint.
  • the voltages of the gate g of the driving transistor M4 and the anode a of the OLED can be reset to the initial voltage Vint, thereby avoiding the last image frame remaining on the gate g of the driving transistor M4 and the anode of the OLED
  • the voltage of a affects the next image frame. Therefore, the above-mentioned first stage 1 can be called the reset stage.
  • the transistor M2 and the transistor M3 are turned on.
  • the gate g of the driving transistor M4 is coupled to the drain (drain, d), and the driving transistor M4 is in a diode-on state.
  • the data voltage Vdata is written to the source s of the driving transistor M4 through the turned-on transistor M2. Therefore, the above-mentioned second stage 2 can be referred to as the data voltage Vdata writing stage of the pixel circuit.
  • the second emission control transistor M5 and the first emission control transistor M6 are turned on, and the current path between the high power supply voltage ELVDD and the low power supply voltage ELVSS is turned on.
  • the driving current I generated by the driving transistor M4 is transmitted to the OLED through the aforementioned current path to drive the OLED to emit light.
  • the above-mentioned third stage 3 can be called the light-emitting stage. From the description of the third stage 3, it can be seen that the EM signal can control the light-emitting state or the non-light-emitting state in the pixel circuit.
  • FIG. 7 is a schematic diagram of the GOA structure of an embodiment of the present application.
  • FIG. 8 is a timing diagram of a GOA circuit according to an embodiment of the present application.
  • the GOA includes a GCK clock input terminal and a GCB clock input terminal for receiving the GCK clock signal and the GCB clock signal.
  • the GCK clock signal and the GCB clock signal are a pair of mutually inverted clock signals.
  • the GOA management module in the display drive circuit can input the GCK clock signal and the GCB clock signal to the display screen.
  • GOA also includes a GN-1 signal input terminal, which is used to receive the strobe signal of the pixel circuit of the upper row of the display screen.
  • the GOA also includes a GN signal output terminal for outputting the strobe signal of the pixel circuit in the row corresponding to the GOA.
  • the G1 signal, G2 signal, ..., GN-1 signal, and GN signal in FIG. 8 respectively represent the strobe signals of the pixel circuits from the first row to the Nth row in the display screen. That is, the GN signal and the GN-1 signal are equivalent to the gate signals GN and GN-1 in Figs. 3-6.
  • the STV signal represents the start signal. Under the control of the GCK clock signal and the GCB clock signal, after the STV signal is activated, the strobe signals G1 and G2 sequentially control the pixel circuits of each row to start refreshing. The GCK controls the strobe signal to sequentially refresh each row of pixel circuits until all the display areas in the display screen are scanned.
  • multiple display drive circuits in the multiple display drive system need to be clocked in synchronization.
  • multiple display drive circuits can be divided into one main display drive circuit and at least one auxiliary display drive circuit.
  • the main display driving circuit outputs a clock synchronization signal to the auxiliary display driving circuit, and the auxiliary display driving circuit performs clock synchronization of the internal circuit of the auxiliary display driving circuit according to the clock synchronization signal received from the main display driving circuit.
  • the aforementioned clock synchronization signal may include a vertical synchronization (V-Sync) signal and a horizontal synchronization (H-Sync) signal.
  • the vertical synchronization signal is used to synchronize the frames of the scanned image
  • the horizontal synchronization signal is used to synchronize the lines of the scanned image.
  • the clock signal in the row scanning each row of pixels is generated by the internal reference clock of each display driving circuit, and the internal clock frequency of different display driving circuits has errors, which will affect the display performance of the display screen. For example, due to differences in the working environment (for example, temperature, humidity, etc.) and the device itself, the internal clock frequencies of different display drive circuits cannot be exactly the same
  • the gate driver on array (GOA) clock signal is generated based on the internal reference clock signal of the display driving circuit, so the frequency of the GOA clock signal of different display driving circuits has errors.
  • the GOA clock signal is used to control the opening or closing of the GOA of the display screen.
  • the GOA clock signal and the horizontal synchronization signal are generated based on different reference clock signals.
  • the GOA on time of the display area driven by the auxiliary display driving circuit will decrease, resulting in The charging time of the pixel circuit in the row is insufficient, thereby affecting the performance of the display screen.
  • the GOA clock signal may include the GCK signal and the GCB signal in the example of FIG. 7 or FIG. 8.
  • each display driving circuit in the plurality of display driving circuits receives the first clock signal sent by the main controller, and generates the GOA clock signal based on the first clock signal.
  • the GOA output from the plurality of display driving circuits is The clock signals are all generated based on the first clock signal, so the frequency error between the GOA clock signals output by the multiple display driving circuits is reduced, so that the GOA clock signals between the multiple display driving circuits can be effectively clocked to improve Improve the display performance of the display.
  • FIG. 9 is a schematic diagram of an electronic device according to an embodiment of the present application. As shown in FIG. 9, the electronic device includes a main controller 110, a display driving circuit 120, a display driving circuit 130, and a display screen 140. The functions of the aforementioned modules are described below.
  • Display screen 140 includes a first display area 11 and a second display area 12.
  • the main controller 110 includes a first clock output terminal, and the first clock output terminal is used to send a first clock signal to the first display driving circuit and the second display driving circuit respectively.
  • the first clock output terminal may be the MIPI TX interface of the master controller.
  • the interface can output a higher frequency and higher stability clock frequency, such as a frequency of tens to hundreds of megahertz.
  • the first display driving circuit 120 includes a first clock receiving terminal, the first clock receiving terminal is used to receive the first clock signal; the first display driving circuit 120 also includes a first gate drive array GOA clock signal output Terminal, the first GOA clock signal output terminal is used to output a first GOA clock signal to the display screen, and the first GOA clock signal is used to control the GOA of the first display area to be turned on or off, wherein The first GOA clock signal is generated based on the first clock signal.
  • the second display driving circuit 130 includes a second clock receiving terminal, the second clock receiving terminal is used to receive the first clock signal; the second display driving circuit 130 also includes a second GOA clock signal output terminal, so The second GOA clock signal output terminal is used to output a second GOA clock signal to the display screen, and the second GOA clock signal is used to control the GOA of the second display area to be turned on or off, wherein the second The GOA clock signal is generated based on the first clock signal.
  • the first GOA clock signal may be a GCK signal corresponding to the first display area
  • the second GOA clock signal may be a GCK signal corresponding to the second display area
  • the first GOA clock signal may be a GCB signal corresponding to the first display area
  • the second GOA clock signal may be a clock signal GCB signal corresponding to the second display area.
  • the GCK signal and the GCB signal are a pair of mutually inverted clock signals.
  • the first GOA clock signal and the second GOA clock signal may be signals with the same phase.
  • the first GOA clock signal is generated based on the first clock signal, which may mean that the first GOA clock signal uses the first clock signal as a reference clock signal.
  • the first clock signal may be divided or multiplied to obtain a second clock signal, and the first GOA clock signal may be generated based on the second clock signal.
  • the situation of the second GOA clock signal or other clock signals is similar, and for the sake of brevity, details are not repeated here.
  • each of the plurality of display driving circuits in the electronic device may receive the first clock signal sent by the main controller, and generate the GOA clock signal based on the first clock signal, so that a plurality of The GOA clock signals output by the display drive circuit to the display screen are all generated based on the same clock signal, which can reduce the error between the frequencies of the GOA clock signals between different display drive circuits and improve the display performance of the display screen.
  • the first display driving circuit 120 includes a first GCK signal output terminal and a first GCB signal output terminal, which are used to output the first GCK signal and the first GCB signal, respectively.
  • the second display driving circuit 130 includes a second GCK signal output terminal and a second GCB signal output terminal.
  • the phase of the first GCK signal and the second GCK signal may be the same.
  • the phases of the first GCB signal and the second GCB signal may be the same.
  • the first GCK signal, the second GCK signal, the first GCB signal, and the second GCB signal are all generated based on the first clock signal.
  • the first GOA clock signal output terminal in FIG. 9 includes the first GCK signal output terminal and/or the first GCB output terminal
  • the second GOA clock signal output terminal includes the first GCK signal output terminal. Two GCK signal output terminals and/or the second GCB signal output terminal.
  • each of the plurality of display driving circuits may also generate a vertical synchronization signal (that is, a V-sync signal) based on the first clock signal sent by the main controller, and the vertical synchronization signal is used For the synchronization between the frames of the scanned image.
  • a vertical synchronization signal that is, a V-sync signal
  • the duration of each time frame may be 16.67 ms (milliseconds), that is, the refresh rate of the display screen is 60 Hz (Hertz). Then the frequency of V-sync is 60 Hz.
  • the first display driving circuit further includes a first vertical synchronization signal output terminal (or referred to as a first V-sync signal output terminal), and the first vertical synchronization signal output terminal Used to output the first vertical synchronization signal (or called the first V-sync signal).
  • a first vertical synchronization signal output terminal or referred to as a first V-sync signal output terminal
  • the first vertical synchronization signal output terminal Used to output the first vertical synchronization signal (or called the first V-sync signal).
  • the first vertical synchronization signal is generated based on the first clock signal, and the first vertical synchronization signal is used to perform frame synchronization of the first display area; and the second display driving circuit further includes a Two vertical synchronization signal output terminals (also referred to as a second V-sync signal output terminal), the second vertical synchronization signal terminal is used to output a second vertical synchronization signal (also referred to as a second V-sync signal).
  • the second vertical synchronization clock signal is generated based on the first clock signal, and the second vertical synchronization signal is used for frame synchronization of the second display area.
  • the first vertical synchronization signal and the second vertical synchronization signal are signals with the same phase.
  • each of the plurality of display driving circuits in the electronic device can receive the first clock signal sent by the main controller, and generate a vertical synchronization signal based on the first clock signal, so that a plurality of The vertical synchronization signal output by the display drive circuit to the display screen is generated based on the same signal, so the frequency error of the vertical synchronization signal between different display drive circuits can be reduced, and the difference between the vertical synchronization signal and the GOA clock signal can be reduced.
  • the timing error between time improves the display performance of the display.
  • each display driving circuit of the plurality of display driving circuits may also generate a horizontal synchronization signal based on the first clock signal sent by the main controller, and the horizontal synchronization signal is used to scan lines and lines of the image. Synchronization between.
  • the duration of each time frame may be 16.67 ms (milliseconds), that is, the refresh rate of the display screen is 60 Hz.
  • the frequency of V-sync is 60 Hz.
  • the frequency of the horizontal synchronization signal is the refresh rate multiplied by the number of lines. For example, if the display screen has 2000 pixels, the frequency of H-sync is 120kHz (kilohertz).
  • the first display driving circuit further includes a first horizontal synchronization signal output terminal (or referred to as a first H-sync output terminal), and the first horizontal synchronization signal output terminal is used for To output the first horizontal synchronization signal (or called the first H-sync signal).
  • the first horizontal synchronization signal is generated based on the first clock signal, and the first horizontal synchronization signal is used to perform line synchronization of the first display area;
  • the second display driving circuit further includes a first Two horizontal synchronization signal output terminals (or called the second H-sync output terminal), and the second horizontal synchronization signal output terminal is used to output a second horizontal synchronization signal (or called the second H-sync signal).
  • the second horizontal synchronization signal is generated based on the first clock signal, the second horizontal synchronization signal is used for line synchronization of the second display area, and the first horizontal synchronization signal and the The second horizontal synchronization signal is a signal with the same phase.
  • each of the multiple display drive circuits in the electronic device receives the first clock signal sent by the main controller, and generates a horizontal synchronization signal based on the first clock signal, so that multiple displays
  • the horizontal synchronization signal output by the driving circuit to the display screen is generated based on the same clock signal. Therefore, the frequency error of the horizontal synchronization signal between different display driving circuits can be reduced, and the difference between the horizontal synchronization signal and the GOA clock signal can be reduced.
  • the timing error between time improves the display performance of the display.
  • the vertical synchronization signal and the horizontal synchronization signal output by the display driving circuit can also adopt the solution in the prior art, that is, the auxiliary display driving circuit generates the vertical synchronization signal and the horizontal synchronization signal based on the clock signal output by the main display driving circuit.
  • the auxiliary display driving circuit generates the vertical synchronization signal and the horizontal synchronization signal based on the clock signal output by the main display driving circuit.
  • the GOA clock signal received by different display areas is synchronized, so the vertical
  • the time error between the synchronization signal (or horizontal synchronization signal) and the GOA clock signal is fixed within the time interval of each frame (or each line), and will not accumulate as time increases, so the display on the screen The performance impact is limited.
  • the first display driving circuit further includes a first EM signal output terminal for outputting a first EM signal to the display screen, and the first EM signal is used for controlling the The pixel circuit in the first display area emits light or does not emit light, wherein the first EM signal is generated based on the first clock signal;
  • the second display driving circuit further includes a second EM signal output terminal, the The second EM signal output terminal is used to output a second EM signal to the display screen, and the second EM signal is used to control the pixel circuit in the second display area to emit light or not, wherein the second EM signal It is generated based on the first clock signal.
  • each of the multiple display drive circuits in the electronic device receives the first clock signal sent by the main controller, and generates an EM signal based on the first clock signal, so that multiple display drive circuits
  • the EM signal output by the circuit to the display screen is generated based on the same clock signal, so the frequency error of the EM signal between different display driving circuits can be reduced, and the timing error between the EM signal and the GOA clock signal can be reduced, Improved the display performance of the display.
  • FIG. 11 is a schematic structural diagram of a display driving circuit according to an embodiment of the present application.
  • the display driving circuit in FIG. 11 can be applied to the display driving circuit 120 and/or the display driving circuit 130 in FIG. 1, FIG. 2, FIG. 9 or FIG.
  • the display driving circuit includes but is not limited to the following modules: a video processing module, a clock processing module, an internal clock generation module, a GOA management module, and an EM management module.
  • the structure in FIG. 11 is only an example and not a limitation.
  • the display driving circuit may include more or less functional modules than the above-mentioned modules.
  • the display driving circuit may also include a power management module, etc.
  • the working principle of the modules and the connection relationship between the modules can be expanded and deformed according to actual applications, which is not limited in the embodiment of the present application.
  • the video processing module is used to receive video data sent by the main controller, and process the video data to generate a video source signal.
  • the video processing module includes a digital circuit part and an analog circuit part, and the video data is processed by the digital circuit and the analog circuit in sequence.
  • FIG. 12 is a schematic structural diagram of a digital circuit of a video processing module of a display driving circuit according to an embodiment of the present application.
  • the digital circuit part may include but is not limited to: frame buffers, decoders, and pixel pipelines.
  • the pixel pipeline includes a plurality of digital modules used for pipeline processing of pixel data, such as digital modules for brightness adjustment.
  • Video data can be processed through the frame buffer, decoder, and pixel pipeline in sequence.
  • FIG. 13 is a schematic structural diagram of an analog circuit of a video processing module of a display driving circuit according to an embodiment of the present application.
  • the analog circuit part includes, but is not limited to, modules such as a shift register (shifter register), a data latch, a digital to analog converter (DAC), and a data output buffer.
  • the video data stream processed by the digital circuit can be processed by modules such as shift registers, data latches, DACs, and data output buffers in turn, and then generate video source signals.
  • the clock processing module receives the first clock signal sent by the main controller, and generates a second clock signal based on the first clock signal, and outputs the second clock signal to
  • the GOA management module serves as a reference clock signal of the GOA management module.
  • the GOA management module generates a GOA clock signal based on the second clock signal, and the GOA clock signal may include the aforementioned GCK signal and/or GCB signal.
  • the clock processing module may include a clock frequency divider circuit.
  • the first clock signal output by the main controller is usually a high-frequency signal, and the display drive circuit needs to divide the frequency of the first clock signal to obtain a low-frequency second clock signal, and then use the second clock signal as a display driver The reference clock signal inside the circuit.
  • the display drive circuit may further include an EM management module, the EM management module may generate an EM signal based on the second clock signal, the EM signal is used to control the display screen
  • the pixel circuit emits light or does not emit light.
  • the display driving circuit may use the first clock signal as the main reference clock signal inside the display driving circuit.
  • the first clock signal may be used as the clock signal of the digital circuit part and the module circuit part in the video processing module.
  • each clock signal in the display drive circuit is generated based on the same clock signal, this will cause the frequency range of the clock signal inside the display drive circuit to be inflexible and adjustable, which will bring timing closure and electromagnetic interference to the display drive circuit ( electro-magnetic interference, EMI) and other issues.
  • the display driving circuit may use the third clock signal generated by the internal clock generating module as the reference clock signal of the digital circuit part of the display driving circuit.
  • the first clock signal can be used as a reference clock signal for the analog circuit part of the display driving circuit, the EM management module and/or the GOA management module.
  • the internal clock generation module is used to generate a third clock signal, and the third clock signal can be used as a reference clock signal for the digital circuit part of the video processing module, such as a frame buffer , Decoders and digital modules in the pixel pipeline.
  • the third clock signal is a clock signal generated inside the display driving circuit.
  • the internal clock generation module includes an oscillator (oscillator, OSC).
  • the first clock signal may be used as the reference clock signal of the analog circuit part of the video processing module.
  • the first clock signal may be frequency-divided by the clock processing module to obtain the second clock signal, and the second clock signal may be used as a reference signal for the analog circuit part of the video processing module.
  • the second clock signal may be used to control the shift register and the analog circuit module after the shift register.
  • FIG. 14 is a schematic diagram of a video processing module in a display driving circuit of an embodiment of the present application. As shown in FIG. 14, as an example, the buffer may be provided between the pixel pipeline module of the digital circuit part and the shift register of the analog circuit part.
  • the second clock signal may also be subjected to one or more frequency division, frequency multiplication processing or other types of processing before being input to each module in the video processing module.
  • the display driving circuit does not need to perform processing such as frequency division or frequency multiplication on the first clock signal, and may directly input the first clock signal into each module as a reference clock signal.
  • the clock processing module in FIG. 11 is only used as an example, and the first clock signal may not undergo any processing before being input to each module, or undergo multiple frequency division and frequency multiplication processing.
  • the second clock signal can represent one or more clock signals, that is, the second clock signal input to each module can be the same signal with the same frequency, or multiple signals with different frequencies.
  • the clock signal is only used as an exemplary illustration of the clock signal generated based on the first clock signal.
  • the third clock signal is only used as an exemplary illustration of the clock signal generated based on the internal clock signal of the display driving circuit.
  • the disclosed system, device, and method may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solution of this application essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (read-only memory, ROM), random access memory (random access memory, RAM), magnetic disk or optical disk and other media that can store program code .

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本申请提供了一种显示驱动电路、显示模组、显示屏的驱动方法以及电子设备，能够提高显示屏的显示性能。电子设备包括：显示屏，包括第一显示区域和第二显示区域；主控制器用于分别向第一显示驱动电路和第二显示驱动电路发送第一时钟信号；第一显示驱动电路用于接收第一时钟信号；第一显示驱动电路还用于向显示屏输出第一GOA时钟信号，其中，第一GOA时钟信号是基于第一时钟信号生成的；第二显示驱动电路用于接收第一时钟信号；第二显示驱动电路还用于向显示屏输出第二GOA时钟信号，其中，第二GOA时钟信号是基于第一时钟信号生成的。

Description

显示驱动电路、显示模组、显示屏的驱动方法及电子设备
本申请要求在2019年2月23日提交中国国家知识产权局、申请号为PCT/CN2019/075981、发明名称为“Gate in Panel Synchronization in Cascade Driving System”的国际申请优先权，在2019年9月6日提交中国国家知识产权局、申请号为201910844205.0、发明名称为“显示驱动电路、显示模组、显示屏的驱动方法及电子设备”的中国专利申请的优先权其全部内容通过引用结合在本申请中。
技术领域
本申请涉及终端技术领域，尤其涉及显示驱动电路、显示模组、显示屏的驱动方法及电子设备。
背景技术
随着电子技术的飞速发展，智能终端、平板电脑等电子设备极大地改变着人们的生活和工作方式。为了满足用户娱乐、办公、观看视频或浏览网页等各种各样的不同需求，电子设备的显示屏的面积设计的越来越大，对显示驱动电路的性能要求也越来越高。因此，可能会出现单个显示驱动电路的能力不足以驱动显示屏面板的情况。在这种情况下，可以使用多个显示驱动电路实现对显示屏的驱动，这种驱动结构可以称为多显示驱动电路系统。在多显示驱动电路系统中，多个显示驱动电路之间需要进行时钟信号同步，才能保障显示屏输出正常的视频图像。
在一种多显示驱动电路系统中的同步方法中，多个显示驱动电路中可包括一个主显示驱动电路和至少一个辅显示驱动电路。主显示驱动电路将其内部产生的时钟信号发送至辅显示驱动电路，辅显示驱动电路基于接收到的时钟信号进行时间同步，以此来实现多个显示驱动电路之间的同步。但是，这种同步方式只用于同步多个显示驱动电路之间的垂直同步信号(vertical synchronization,V-Sync)和水平同步(horizontal synchronization,H-Sync)信号。其中，垂直同步信号用于扫描图像的帧与帧之间的同步，水平同步信号用于扫描图像的行与行(line-to-line)之间的同步。而位于扫描每行像素的行内的时钟信号是基于各个显示驱动电路的内部时钟信号产生的，并没有进行时钟同步。由于不同的显示驱动电路的内部时钟频率存在误差，因此会影响显示屏的显示性能。
发明内容
本申请提供一种显示驱动电路、显示模组、显示屏的驱动方法及电子设备，能够提高显示屏的显示性能。
第一方面，提供了一种电子设备，包括：显示屏，包括第一显示区域和第二显示区域；主控制器，包括第一时钟输出端，所述第一时钟输出端用于分别向第一显示驱动电路和第二显示驱动电路发送第一时钟信号；所述第一显示驱动电路，包括第一时钟接收端，所述 第一时钟接收端用于接收所述第一时钟信号；所述第一显示驱动电路还包括第一门驱动阵列GOA时钟信号输出端，所述第一GOA时钟信号输出端用于向所述显示屏输出第一GOA时钟信号，所述第一GOA时钟信号用于控制所述第一显示区域的GOA开启或关闭，其中，所述第一GOA时钟信号是基于所述第一时钟信号生成的；所述第二显示驱动电路，包括第二时钟接收端，所述第二时钟接收端用于接收所述第一时钟信号；所述第二显示驱动电路还包括第二GOA时钟信号输出端，所述第二GOA时钟信号输出端用于向所述显示屏输出第二GOA时钟信号，所述第二GOA时钟信号用于控制所述第二显示区域的GOA开启或关闭，其中，所述第二GOA时钟信号是基于所述第一时钟信号生成的。
在本申请实施例中，电子设备中的多个显示驱动电路中的每个显示驱动电路可以接收主控制器发送的第一时钟信号，并基于该第一时钟信号生成GOA时钟信号，从而多个显示驱动电路向所述显示屏输出的GOA时钟信号都是基于同一时钟信号生成的，可以减少不同的显示驱动电路之间的GOA时钟信号的频率之间的误差，提高了显示屏的显示性能。
结合第一方面，在一种可能的实现方式中，所述第一显示驱动电路还包括第一垂直同步信号输出端，用于向所述显示屏输出第一垂直同步信号，其中，所述第一垂直同步信号是基于所述第一时钟信号生成的，所述第一垂直同步信号用于进行所述第一显示区域的帧同步；所述第二显示驱动电路还包括第二垂直同步信号输出端，用于向所述显示屏输出第二垂直同步信号，其中，所述第二垂直同步时钟信号是基于所述第一时钟信号生成的，所述第二垂直同步信号用于进行所述第二显示区域的帧同步，所述第一垂直同步信号和所述第二垂直同步信号为相位相同的信号。
在本申请实施例中，电子设备中的多个显示驱动电路中的每个显示驱动电路可以接收主控制器发送的第一时钟信号，并基于该第一时钟信号生成垂直同步信号，从而多个显示驱动电路向所述显示屏输出的垂直同步信号是基于相同的信号生成的，因此可以减少不同的显示驱动电路之间的垂直同步信号的频率的误差，以及减少垂直同步信号与GOA时钟信号之间的定时误差，提高了显示屏的显示性能。
结合第一方面，在一种可能的实现方式中，所述第一显示驱动电路还包括第一水平同步信号输出端，用于向所述显示屏输出第一水平同步信号，其中，所述第一水平同步信号是基于所述第一时钟信号生成的，所述第一水平同步信号用于进行所述第一显示区域的行同步；所述第二显示驱动电路还包括第二水平同步信号输出端，用于向所述显示屏输出第二水平同步信号，其中，所述第二水平同步信号是基于所述第一时钟信号生成的，所述第二水平同步信号用于进行所述第二显示区域的行同步。
在本申请实施例中，电子设备中的多个显示驱动电路中的每个显示驱动电路接收主控制器发送的第一时钟信号，并基于该第一时钟信号生成水平同步信号，从而多个显示驱动电路向所述显示屏输出的水平同步信号是基于相同的时钟信号生成的，因此可以减少不同的显示驱动电路之间的水平同步信号的频率的误差，以及减少水平同步信号与GOA时钟信号之间的定时误差，提高了显示屏的显示性能。
结合第一方面，在一种可能的实现方式中，所述第一显示驱动电路还包括第一发光EM信号输出端，用于向所述显示屏输出第一EM信号，所述第一EM信号用于控制所述第一显示区域中的像素电路发光或不发光，其中，所述第一EM信号是基于所述第一时钟信号生成的；和/或，所述第二显示驱动电路还包括第二EM信号输出端，用于向所述显 示屏输出第二EM信号，所述第二EM信号用于控制所述第二显示区域中的像素电路发光或不发光，其中，所述第二EM信号是基于所述第一时钟信号生成的。
在本申请实施例中，电子设备中的多个显示驱动电路中的每个显示驱动电路接收主控制器发送的第一时钟信号，并基于该第一时钟信号生成EM信号，从而多个显示驱动电路向所述显示屏输出EM信号是基于相同的时钟信号生成的，因此可以减少不同的显示驱动电路之间的EM信号的频率的误差，以及减少EM信号与GOA时钟信号之间的定时误差，提高了显示屏的显示性能。
结合第一方面，在一种可能的实现方式中，所述第一显示驱动电路中包括视频处理模块，所述视频处理模块用于处理所述主控制器输入的视频数据，以生成向所述显示屏发送的视频源信号，所述视频处理模块中的数字电路的参考时钟为所述第一显示驱动电路的内部时钟产生模块生成的第三时钟信号，所述视频处理模块中的模拟电路的参考时钟为所述第一时钟信号。
在本申请实施例中，显示驱动电路利用主控制器发送的第一时钟信号作为显示驱动电路中的模拟电路的参考时钟，同时利用内部产生的第三时钟信号作为显示驱动电路中的数字电路的参考时钟，从而又可以减少多个显示驱动电路的时钟信号之间的频率的误差，又可以减少时序收敛以及电磁干扰等问题。
结合第一方面，在一种可能的实现方式中，所述视频处理模块中设置有第一缓冲器，所述第一缓冲器设置于所述视频处理模块中的数字电路和模拟电路之间。
第二方面，提供了一种显示驱动电路，所述显示驱动电路包括：第一时钟接收端，用于接收主控制器发送的第一时钟信号；第一门驱动阵列GOA时钟信号输出端，所述第一GOA时钟信号输出端用于向所述显示屏输出第一GOA时钟信号，所述第一GOA时钟信号用于控制所述显示屏的GOA开启或关闭，其中，所述第一GOA时钟信号是基于所述第一时钟信号生成的。
应理解，第二方面的显示驱动电路，和第一方面的电子设备基于相同的发明构思，因此第二方面的技术方案能够取得的有益技术效果，可以参考第一方面的说明，不再赘述。
结合第二方面，在一种可能的实现方式中，所述显示驱动电路还包括第一垂直同步信号输出端，用于向所述显示屏输出第一垂直同步信号，其中，所述第一垂直同步信号是基于所述第一时钟信号生成的，所述第一垂直同步信号用于进行所述显示屏的帧同步。
结合第二方面，在一种可能的实现方式中，所述显示驱动电路还包括第一水平同步信号输出端，用于向所述显示屏输出第一水平同步信号，其中，所述第一水平同步信号是基于所述第一时钟信号生成的，所述第一水平同步信号用于进行所述显示屏的行同步。
结合第二方面，在一种可能的实现方式中，所述第一显示驱动电路还包括第一发光EM信号输出端，用于向所述显示屏输出第一EM信号，所述第一EM信号用于控制所述显示屏的像素电路发光或不发光，其中，所述第一EM信号是基于所述第一时钟信号生成的。
结合第二方面，在一种可能的实现方式中，所述显示驱动电路中包括视频处理模块，所述视频处理模块用于处理所述主控制器输入的视频数据，以生成向所述显示屏发送的视频源信号，所述视频处理模块中的数字电路的参考时钟为所述显示驱动电路的内部时钟产 生模块生成的第三时钟信号，所述视频处理模块中的模拟电路的参考时钟为所述第一时钟信号。
结合第二方面，在一种可能的实现方式中，所述视频处理模块中设置有第一缓冲器，所述第一缓冲器设置于所述视频处理模块中的数字电路和模拟电路之间。
第三方面，提供了一种显示屏的驱动方法，所述显示屏包括第一显示区域和第二显示区域，所述方法包括：主控制器分别向第一显示驱动电路和第二显示驱动电路发送第一时钟信号；所述第一显示驱动电路向所述显示屏输出第一门驱动阵列GOA时钟信号，所述第一GOA时钟信号用于控制所述第一显示区域的GOA开启或关闭，其中，所述第一GOA时钟信号是基于所述第一时钟信号生成的；所述第二显示驱动电路向所述显示屏输出第二GOA时钟信号，所述第二GOA时钟信号用于控制所述第二显示区域的GOA开启或关闭，其中，所述第二GOA时钟信号是基于所述第一时钟信号生成的。
应理解，第三方面的显示屏的驱动方法，和第一方面的电子设备基于相同的发明构思，因此第三方面的技术方案能够取得的有益技术效果，可以参考第一方面的说明，不再赘述。
结合第三方面，在一种可能的实现方式中，所述方法还包括：所述第一显示驱动电路向所述显示屏输出第一垂直同步信号，其中，所述第一垂直同步信号是基于所述第一时钟信号生成的，所述第一垂直同步信号用于进行所述第一显示区域的帧同步；
所述第二显示驱动电路向所述显示屏输出第二垂直同步信号，其中，所述第二垂直同步时钟信号是基于所述第一时钟信号生成的，所述第二垂直同步信号用于进行所述第二显示区域的帧同步，所述第一垂直同步信号和所述第二垂直同步信号为相位相同的信号。
结合第三方面，在一种可能的实现方式中，所述第一显示驱动电路还包括第一水平同步信号输出端，用于向所述显示屏输出第一水平同步信号，其中，所述第一水平同步信号是基于所述第一时钟信号生成的，所述第一水平同步信号用于进行所述第一显示区域的行同步；所述第二显示驱动电路还包括第二水平同步信号输出端，用于向所述显示屏输出第二水平同步信号，其中，所述第二水平同步信号是基于所述第一时钟信号生成的，所述第二水平同步信号用于进行所述第二显示区域的行同步。
结合第三方面，在一种可能的实现方式中，所述第一显示驱动电路还包括第一发光EM信号输出端，用于向所述显示屏输出第一EM信号，所述第一EM信号用于控制所述第一显示区域中的像素电路发光或不发光，其中，所述第一EM信号是基于所述第一时钟信号生成的；所述第二显示驱动电路还包括第二EM信号输出端，用于向所述显示屏输出第二EM信号，所述第二EM信号用于控制所述第二显示区域中的像素电路发光或不发光，其中，所述第二EM信号是基于所述第一时钟信号生成的。
结合第三方面，在一种可能的实现方式中，所述第一显示驱动电路中包括视频处理模块，所述视频处理模块用于处理所述主控制器输入的视频数据，以生成向所述显示屏发送的视频源信号，所述视频处理模块中的数字电路的参考时钟为所述第一显示驱动电路的内部时钟产生模块生成的第三时钟信号，所述视频处理模块中的模拟电路的参考时钟为所述第一时钟信号。
结合第三方面，在一种可能的实现方式中，所述视频处理模块中设置有第一缓冲器，所述第一缓冲器设置于所述视频处理模块中的数字电路和模拟电路之间。
第四方面，提供了一种显示模组，包括：显示屏，包括第一显示区域和第二显示区域； 第一显示驱动电路，包括第一时钟接收端，所述第一时钟接收端用于接收主控制器发送的第一时钟信号；所述第一显示驱动电路还包括第一门驱动阵列GOA时钟信号输出端，所述第一GOA时钟信号输出端用于向所述显示屏输出第一GOA时钟信号，所述第一GOA时钟信号用于控制所述第一显示区域的GOA开启或关闭，其中，所述第一GOA时钟信号是基于所述第一时钟信号生成的；第二显示驱动电路，包括第二时钟接收端，所述第二时钟接收端用于接收所述第一时钟信号；所述第二显示驱动电路还包括第二GOA时钟信号输出端，所述第二GOA时钟信号输出端用于向所述显示屏输出第二GOA时钟信号，所述第二GOA时钟信号用于控制所述第二显示区域的GOA开启或关闭，其中，所述第二GOA时钟信号是基于所述第一时钟信号生成的。
应理解，第四方面的显示模组，和第一方面的电子设备基于相同的发明构思，因此第四方面的技术方案能够取得的有益技术效果，可以参考第一方面的说明，不再赘述。
第四方面，在一种可能的实现方式中，所述第一显示驱动电路还包括第一垂直同步信号输出端，用于向所述显示屏输出第一垂直同步信号，其中，所述第一垂直同步信号是基于所述第一时钟信号生成的，所述第一垂直同步信号用于进行所述第一显示区域的帧同步；所述第二显示驱动电路还包括第二垂直同步信号输出端，用于向所述显示屏输出第二垂直同步信号，其中，所述第二垂直同步时钟信号是基于所述第一时钟信号生成的，所述第二垂直同步信号用于进行所述第二显示区域的帧同步，所述第一垂直同步信号和所述第二垂直同步信号为相位相同的信号。
第四方面，在一种可能的实现方式中，所述第一显示驱动电路还包括第一水平同步信号输出端，用于向所述显示屏输出第一水平同步信号，其中，所述第一水平同步信号是基于所述第一时钟信号生成的，所述第一水平同步信号用于进行所述第一显示区域的行同步；所述第二显示驱动电路还包括第二水平同步信号输出端，用于向所述显示屏输出第二水平同步信号，其中，所述第二水平同步信号是基于所述第一时钟信号生成的，所述第二水平同步信号用于进行所述第二显示区域的行同步。
第四方面，在一种可能的实现方式中，所述第一显示驱动电路还包括第一发光EM信号输出端，用于向所述显示屏输出第一EM信号，所述第一EM信号用于控制所述第一显示区域中的像素电路发光或不发光，其中，所述第一EM信号是基于所述第一时钟信号生成的；所述第二显示驱动电路还包括第二EM信号输出端，所述第二EM信号输出端用于向所述显示屏输出第二EM信号，所述第二EM信号用于控制所述第二显示区域中的像素电路发光或不发光，其中所述第二EM信号是基于所述第一时钟信号生成的。
第四方面，在一种可能的实现方式中，所述第一显示驱动电路中包括视频处理模块，所述视频处理模块用于处理所述主控制器输入的视频数据，以生成向所述显示屏发送的视频源信号，所述视频处理模块中的数字电路的参考时钟为所述第一显示驱动电路的内部时钟产生模块生成的第三时钟信号，所述视频处理模块中的模拟电路的参考时钟为所述第一时钟信号。
第四方面，在一种可能的实现方式中，所述视频处理模块中设置有第一缓冲器，所述第一缓冲器设置于所述视频处理模块中的数字电路和模拟电路之间。
第五方面，本申请提供一种电路系统，包括处理器。所述处理器用于读取并执行存储器中存储的计算机程序，以执行第三方面或其任意可能的实现方式中的方法，或者，执行 第四方面或其任意可能的实现方式中的方法。
可选地，所述电路还包括存储器，存储器与处理器通过电路或电线与存储器连接。
进一步可选地，所述电路系统还包括通信接口。
第六方面，本申请提供一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机指令，当计算机指令在计算机上运行时，使得计算机执行第三方面或其任意可能的实现方式中的方法。
第七方面，本申请提供一种计算机程序产品，所述计算机程序产品包括计算机程序代码，当所述计算机程序代码在计算机上运行时，使得计算机执行第三方面或其任意可能的实现方式中的方法。
附图说明
图1是本申请一实施例的电子设备的结构示意图。。
图2是本申请一实施例的多显示驱动电路系统处理处理视频数据的流程示意图。
图3是本申请一实施例的像素电路的电路示意图。
图4是本申请一实施例的像素电路的复位阶段的电路示意图。
图5是本申请一实施例的像素电路的数据电压Vdata写入阶段的电路示意图。
图6是本申请一实施例的像素电路的发光阶段的电路示意图。
图7是本申请一实施例的门驱动阵列(gate driver on array,GOA)的结构示意图。
图8是本申请一实施例的GOA的时序示意图。
图9是本申请一实施例的电子设备的结构示意图。
图10是本申请又一实施例的电子设备的结构示意图。
图11是本申请一实施例的显示驱动电路的结构示意图。、
图12是本申请一实施例的显示驱动电路中的视频处理模块的数字电路的结构示意图。
图13是本申请一实施例的显示驱动电路中的视频处理模块的模拟电路的结构示意图。
图14是本申请一实施例的视频处理模块的结构示意图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
本申请实施例提供了一种显示驱动电路、多显示驱动电路系统的驱动方法以及电子设备，能够提高显示屏的显示性能。其中所述显示驱动电路可以安装在所述电子设备中。
本申请实施例中的电子设备可以包括用户设备、移动终端、手机、平板电脑(pad)等任何包括显示屏的电子设备，本申请实施例对此并不限定。
本申请实施例中的电子设备包括多显示驱动系统，所述多显示驱动系统包括多个显示驱动电路。本申请实施例中以多显示驱动系统包括两个显示驱动电路为例进行描述，本领域技术人员能够理解，本申请同样可以应用于包括两个以上显示驱动电路的多显示驱动电路系统。
图1是本申请一实施例的电子设备的结构示意图。该电子设备100为多显示驱动电路 系统。如图1所示，电子设备100包括主控制器110、第一显示驱动电路120、第二显示驱动电路130以及显示屏140。为了便于说明，下面描述图1中涉及的术语的定义。
主控制器110：用于向显示驱动电路(120,130)输出待处理的视频数据、时钟同步信号、信令等。主控制器可以包括但不限于片上系统(system on chip,SOC)、应用处理器(application processor,AP)或者通用处理器等各种类型的处理器。
显示驱动电路(120，130)：用于接收从所述主控制器110发送的视频数据，并在对所述视频数据进行数字部分处理以及模拟部分处理之后，得到视频源信号。所述视频源信号用于输出到所述显示屏130中，以驱动所述显示屏130显示图像。另外，显示驱动电路120还可以对显示屏130进行发光(emission,EM)控制管理、门驱动阵列(gate driver on array,GOA)控制管理以及电源电压管理，并且向显示屏输出发光(emission,EM)信号、发光层正电压(emission layer VDD,ELVDD)信号、发光层负电压(emission layer VSS,ELVSS)信号、GOA时钟信号等。在本申请实施例中，视频源信号也可以称为源信号。
可选地，多个显示驱动电路之间可以通过接口相连，以便于进行时钟同步或交互。在一些示例中，显示驱动电路也可以称为显示驱动集成电路(display driver integrated circuit,DDIC)。
显示屏140，用于分别从显示驱动电路120和显示驱动电路130接收视频源信号，并显示图像。显示屏可以包括折叠显示屏，也可以包括非折叠显示屏。所述显示屏140可以采用柔性屏或者硬质显示屏实现。所述柔性屏例如可以包括有机发光二极管(organic light-emitting diode,OLED)显示屏等结构，本申请实施例对此不作限定。
图2是本申请一实施例的多显示驱动电路系统处视频数据的流程示意图。如图2所示，显示屏140可以被划分第一显示区域11和第二显示区域12，第一显示区域11与第一显示驱动电路120对应，第二显示区域12与第二显示驱动电路130对应。不同的显示驱动电路(120,130)用于驱动不同的显示区域。可选地，第一显示驱动电路120与第二显示驱动电路130之间可以存在接口，并通过所述接口进行时钟同步或者信令交互。
其中，主控制器110可以根据多个显示区域，将视频数据划分为多个子视频数据，并分别向不同的显示驱动电路发送所述子视频数据。多个显示驱动电路中的每个显示驱动电路对相应的子视频数据进行处理之后，得到多个子视频源信号。多个显示驱动电路可以分别向显示屏发送所述多个子视频源信号，以驱动显示屏的不同显示区域显示图像。
为了便于理解本申请的方案，接下来结合附图，介绍本申请实施例的显示屏中的像素电路和GOA的结构和工作原理。需要说明的是，以下描述仅仅作为像素电路的示例而非对本申请的保护范围的限定。本领域人员根据本申请的方案，不经过创造性劳动而获取的方案或其变形也落入本申请的保护范围。
像素电路是显示屏中的最小电路单元，一个像素电路相当于显示屏中的一个亚像素(或称子像素)，显示屏中包括多行亚像素。基于像素电路的结构，显示屏中的亚像素是逐行扫描并发光的，因此当显示一帧图像时，第一行亚像素发光后，需要保持发光的状态直至最后一行亚像素发光，才能够实现一帧图像的显示。GOA用于控制显示屏中的每行GOA的开启或关闭，以控制为每行像素电路输入选通信号。
图3是本申请一实施例的像素电路的电路示意图。如图3所示，像素电路50可以包括电容Cst、发光器件L以及多个晶体管(M1、M2、M3、M4、M5、M6、M7)。其中， 为了方便说明，晶体管M1称为第一复位晶体管，晶体管M7称为第二复位晶体管，晶体管M4称为驱动晶体管，晶体管M6称为第一发光控制晶体管，晶体管M5称为第二发光控制晶体管。需要说明的是，这仅仅是一个像素电路的示例，像素电路还可以采用其他的设计，例如只包括2个晶体管和1个电容的2T1C电路、包括4个晶体管和1个电容的4T1C电路、包括5个晶体管和2个电容的5T2C电路等，这些像素电路的设计都可以通过EM信号来控制某个与发光器件串联的晶体管的导通和截止，从而实现对所述发光器件发光的控制，本申请实施例对此不作限定。
需要说明的是，上述发光器件L可以为有机发光二极管(organic light emitting diode，OLED)。在此情况下，显示屏为OLED显示屏。或者，发光器件L可以为微型发光二极管(mirco light emitting diode，mirco LED)。在此情况下，显示屏为mirco LED显示屏。以下为了方便描述，均是以发光器件L为OLED进行的举例说明。
基于图3所示的像素电路50的结构，该像素电路50的工作过程包括图4-图6所示的三个阶段，第一阶段①、第二阶段②以及第三阶段③。图4、图5以及图6中为了方便说明，在截止的晶体管上采用添加“×”标记的方式进行区分。
第一阶段①，在选通信号GN-1的控制下，如图4所示，第一复位晶体管M1和第二复位晶体管M7导通。初始电压Vint通过第一复位晶体管M1传输至驱动晶体管M4的栅极，从而对驱动晶体管M4的栅极进行复位。此外，初始电压Vint通过第二复位晶体管M7传输至OLED的阳极(anode，a)，对OLED的阳极a进行复位。此时，OLED的阳极a的电压Va，以及驱动晶体管M4的栅极g的电压Vg4为Vint。
这样一来，在第一阶段①可以将驱动晶体管M4的栅极g以及OLED的阳极a的电压复位至初始电压Vint，从而避免上一图像帧残留于驱动晶体管M4的栅极g以及OLED的阳极a的电压对下一图像帧造成影响。因此，上述第一阶段①可以称为复位阶段。
第二阶段②，在选通信号GN的控制下，如图5所示，晶体管M2和晶体管M3导通。在晶体管M3导通的情况下，驱动晶体管M4的栅极g与漏极(drain，简称d)相耦接，该驱动晶体管M4成二极管导通状态。此时，数据电压Vdata通过导通的晶体管M2写入至驱动晶体管M4的源极s。因此上述第二阶段②可以称为像素电路的数据电压Vdata写入阶段。
第三阶段③，在发光控制信号EM的控制下，第二发光控制晶体管M5和第一发光控制晶体管M6导通，高电源电压ELVDD与低电源电压ELVSS之间的电流通路导通。该驱动晶体管M4产生的驱动电流I通过上述电流通路传输至OLED，以驱动OLED进行发光。
由于OLED在上述第三阶段③发光，因此上述第三阶段③可以称为发光阶段。由第三阶段③的描述可知，EM信号可以控制像素电路中处于发光状态或者不发光状态。
下面结合图7和图8介绍本申请实施例中的GOA电路的工作原理。其中，图7是本申请一实施例的GOA的结构示意图。图8是本申请一实施例的GOA电路的时序示意图。
如图7所示，GOA包括GCK时钟输入端和GCB时钟输入端，用于接收GCK时钟信号和GCB时钟信号。其中，GCK时钟信号和GCB时钟信号为一对相互反相的时钟信号。可以由显示驱动电路中的GOA管理模块向显示屏输入GCK时钟信号和GCB时钟信号。GOA还包括GN-1信号输入端，用于接收显示屏的上一行像素电路的选通信号。GOA还 包括GN信号输出端，用于输出GOA对应的本行像素电路的选通信号。
图8中的G1信号、G2信号、…、GN-1信号、GN信号分别表示显示屏中的第一行至第N行的像素电路的选通信号。即GN信号和GN-1信号相当于图3-图6中的选通信号GN和GN-1。STV信号表示启动信号。在GCK时钟信号和GCB时钟信号的控制下，STV信号启动之后，选通信号G1、G2依次控制每行像素电路开始刷新。GCK控制选通信号依次刷新每行像素电路，直至扫描完显示屏中的所有显示区域。
为了使显示屏中的多个显示区域能够同步显示图像，多显示驱动系统中的多个显示驱动电路之间需进行时钟同步。在一种时钟同步方案中，可以将多个显示驱动电路分为一个主显示驱动电路和至少一个辅显示驱动电路。主显示驱动电路向辅显示驱动电路输出时钟同步信号，辅显示驱动电路根据从主显示驱动电路接收到的时钟同步信号来进行辅显示驱动电路的内部电路的时钟同步。例如，上述时钟同步信号可包括垂直同步(vertical synchronization,V-Sync)信号和水平同步(horizontal synchronization,H-Sync)信号。其中垂直同步信号用于进行扫描图像的帧与帧之间的同步，而水平同步信号用于进行扫描图像的行与行之间的同步。但是位于扫描每行像素的行内的时钟信号是各个显示驱动电路的内部参考时钟生成的，不同的显示驱动电路的内部时钟频率存在误差，因此会影响显示屏的显示性能。例如，由于工作环境(例如，温度、湿度等)、器件本身存在差异，不同的显示驱动电路的内部时钟频率并不能做到完全相同
在现有技术中，门驱动阵列(gate driver on array,GOA)时钟信号就是基于显示驱动电路的内部参考时钟信号生成的，因此不同显示驱动电路的GOA时钟信号的频率存在误差。其中，GOA时钟信号用于控制显示屏的GOA的开启或关闭。对于辅显示驱动电路来说，其GOA时钟信号与水平同步信号是基于不同的参考时钟信号生成的，在行扫描时间间隔内，辅显示驱动电路所驱动的显示区域的GOA开启时间将减少，导致行内像素电路的充电时间不足，从而影响显示屏的性能。其中，作为示例，GOA时钟信号可以包括图7或图8的示例中的GCK信号和GCB信号。
为了解决上述问题，本申请实施例提出了一种多显示驱动系统的驱动方案。在该方案中，多个显示驱动电路中的每个显示驱动电路均接收主控制器发送的第一时钟信号，并基于该第一时钟信号生成GOA时钟信号，由于多个显示驱动电路输出的GOA时钟信号均基于第一时钟信号生成，因此多个显示驱动电路输出的GOA时钟信号之间的频率的误差减少，从而多个显示驱动电路之间的GOA时钟信号可以进行有效的时钟同步，以提高了显示屏的显示性能。
图9是本申请一实施例的电子设备的示意图，如图9所示，该电子设备包括主控制器110、显示驱动电路120、显示驱动电路130和显示屏140，上述模块的功能如下描述。
显示屏140：包括第一显示区域11和第二显示区域12。
主控制器110：包括第一时钟输出端，所述第一时钟输出端用于分别向第一显示驱动电路和第二显示驱动电路发送第一时钟信号。
作为示例，所述第一时钟输出端可以为主控制器的MIPI TX接口。该接口可以输出较高频率且稳定度较高的时钟频率，例如几十到几百兆赫兹的频率。
第一显示驱动电路120：包括第一时钟接收端，所述第一时钟接收端用于接收所述第一时钟信号；所述第一显示驱动电路120还包括第一门驱动阵列GOA时钟信号输出端， 所述第一GOA时钟信号输出端用于向所述显示屏输出第一GOA时钟信号，所述第一GOA时钟信号用于控制所述第一显示区域的GOA开启或关闭，其中，所述第一GOA时钟信号是基于所述第一时钟信号生成的。
第二显示驱动电路130：包括第二时钟接收端，所述第二时钟接收端用于接收所述第一时钟信号；所述第二显示驱动电路130还包括第二GOA时钟信号输出端，所述第二GOA时钟信号输出端用于向所述显示屏输出第二GOA时钟信号，所述第二GOA时钟信号用于控制所述第二显示区域的GOA开启或关闭，其中，所述第二GOA时钟信号是基于所述第一时钟信号生成的.
以图7或图8为例，所述第一GOA时钟信号可以为对应于第一显示区域的GCK信号,所述第二GOA时钟信号可以为对应于第二显示区域的GCK信号。或者，第一GOA时钟信号可以为对应于第一显示区域的GCB信号，第二GOA时钟信号可以为对应与第二显示区域的时钟信号GCB信号。其中，GCK信号和GCB信号为一对相互反相的时钟信号。
可选地，所述第一GOA时钟信号和所述第二GOA时钟信号可以为相位相同的信号。
其中，所述第一GOA时钟信号基于所述第一时钟信号生成，可以指所述第一GOA时钟信号以所述第一时钟信号为参考时钟信号。在一个示例中，可以对所述第一时钟信号进行分频或倍频处理，得到第二时钟信号，所述第一GOA时钟信号可以基于所述第二时钟信号生成。第二GOA时钟信号或者其它时钟信号的情况也类似，为了简洁，此处不再赘述。
在本申请实施例中，电子设备中的多个显示驱动电路中的每个显示驱动电路可以接收主控制器发送的第一时钟信号，并基于该第一时钟信号生成GOA时钟信号，从而多个显示驱动电路向所述显示屏输出的GOA时钟信号都是基于同一时钟信号生成的，可以减少不同的显示驱动电路之间的GOA时钟信号的频率之间的误差，提高了显示屏的显示性能。
如图10所示，在一个示例中，所述第一显示驱动电路120包括第一GCK信号输出端和第一GCB信号输出端，分别用于输出第一GCK信号和第一GCB信号。所述第二显示驱动电路130包括第二GCK信号输出端和第二GCB信号输出端。所述第一GCK信号和所述第二GCK信号的相位可以相同。所述第一GCB信号和所述第二GCB信号的相位可以相同。所述第一GCK信号、第二GCK信号、第一GCB信号、第二GCB信号均基于所述第一时钟信号生成。换句话说，图9中的所述第一GOA时钟信号输出端包括所述第一GCK信号输出端和/或所述第一GCB输出端，所述第二GOA时钟信号输出端包括所述第二GCK信号输出端和/或所述第二GCB信号输出端。
可选地，所述多个显示驱动电路中的每个显示驱动电路还可以基于所述主控制器发送的第一时钟信号生成垂直同步信号(即V-sync信号)，所述垂直同步信号用于扫描图像的帧与帧之间的同步。作为一个示例，每个时间帧的时长可以为16.67ms(毫秒)，即显示屏的刷新率为60Hz(赫兹)。则V-sync的频率为60Hz。
继续参见图10，在一个示例中，所述第一显示驱动电路还包括第一垂直同步信号输出端(或者称为，第一V-sync信号输出端)，所述第一垂直同步信号输出端用于输出第一垂直同步信号(或者称为，第一V-sync信号)。其中，所述第一垂直同步信号是基于所述第一时钟信号生成的，所述第一垂直同步信号用于进行所述第一显示区域的帧同步； 所述第二显示驱动电路还包括第二垂直同步信号输出端(或者称为，第二V-sync信号输出端)，所述第二垂直同步信号端用于输出第二垂直同步信号(或者称为，第二V-sync信号)。其中，所述第二垂直同步时钟信号是基于所述第一时钟信号生成的，所述第二垂直同步信号用于进行所述第二显示区域的帧同步。可选地，所述第一垂直同步信号和所述第二垂直同步信号为相位相同的信号。
在本申请实施例中，电子设备中的多个显示驱动电路中的每个显示驱动电路可以接收主控制器发送的第一时钟信号，并基于该第一时钟信号生成垂直同步信号，从而多个显示驱动电路向所述显示屏输出的垂直同步信号是基于相同的信号生成的，因此可以减少不同的显示驱动电路之间的垂直同步信号的频率的误差，以及减少垂直同步信号与GOA时钟信号之间的定时误差，提高了显示屏的显示性能。
可选地，所述多个显示驱动电路中的每个显示驱动电路还可以基于所述主控制器发送的第一时钟信号生成水平同步信号，所述水平同步信号用于扫描图像的行与行之间的同步。作为一个示例，每个时间帧的时长可以为16.67ms(毫秒)，即显示屏的刷新率为60赫兹。则V-sync的频率为60Hz。则水平同步信号的频率为刷新率乘以行数。例如，若显示屏2000行像素，则H-sync的频率为120kHz(千赫兹)。
继续参见图10，在一个示例中，所述第一显示驱动电路还包括第一水平同步信号输出端(或者称为，第一H-sync输出端)，所述第一水平同步信号输出端用于输出第一水平同步信号(或者称为，第一H-sync信号)。其中，所述第一水平同步信号是基于所述第一时钟信号生成的，所述第一水平同步信号用于进行所述第一显示区域的行同步；所述第二显示驱动电路还包括第二水平同步信号输出端(或者称为第二H-sync输出端)，所述第二水平同步信号输出端用于输出第二水平同步信号(或者称为第二H-sync信号)。其中，所述第二水平同步信号是基于所述第一时钟信号生成的，所述第二水平同步信号用于进行所述第二显示区域的行同步，所述第一水平同步信号和所述第二水平同步信号为相位相同的信号。
在本申请实施例中，电子设备中的多个显示驱动电路中的每个显示驱动电路接收主控制器发送的第一时钟信号，并基于该第一时钟信号生成水平同步信号，从而多个显示驱动电路向所述显示屏输出的水平同步信号是基于相同的时钟信号生成的，因此可以减少不同的显示驱动电路之间的水平同步信号的频率的误差，以及减少水平同步信号与GOA时钟信号之间的定时误差，提高了显示屏的显示性能。
作为一个示例，显示驱动电路输出的垂直同步信号和水平同步信号也可以采用现有技术中的方案，即辅显示驱动电路基于主显示驱动电路输出的时钟信号生成垂直同步信号和水平同步信号。这种方案中，虽然显示屏的不同显示区域接收到的垂直同步信号(或水平同步信号)与GOA时钟信号之间存在误差，但由于不同显示区域接收的GOA时钟信号是同步的，因此，垂直同步信号(或水平同步信号)与GOA时钟信号之间的时间误差在每帧(或每行)的时间间隔内都是固定的，并不会随着时间增加而累积，因此对显示屏的显示性能的影响有限。
继续参见图10，在一个示例中，所述第一显示驱动电路还包括第一EM信号输出端，用于向所述显示屏输出第一EM信号，所述第一EM信号用于控制所述第一显示区域中的像素电路发光或不发光，其中，所述第一EM信号是基于所述第一时钟信号生成的；所述 第二显示驱动电路还包括第二EM信号输出端，所述第二EM信号输出端用于向所述显示屏输出第二EM信号，所述第二EM信号用于控制所述第二显示区域中的像素电路发光或不发光，其中所述第二EM信号是基于所述第一时钟信号生成的。
在本申请实施例中，电子设备中的多个显示驱动电路中的每个显示驱动电路接收主控制器发送的第一时钟信号，并基于该第一时钟信号生成EM信号，从而多个显示驱动电路向所述显示屏输出EM信号是基于相同的时钟信号生成的，因此可以减少不同的显示驱动电路之间的EM信号的频率的误差，以及减少EM信号与GOA时钟信号之间的定时误差，提高了显示屏的显示性能。
图11是本申请一实施例的显示驱动电路的结构示意图。图11中的显示驱动电路可以应用于图1、图2、图9或图10中的显示驱动电路120和/或显示驱动电路130。如图10所示，该显示驱动电路包括但不限于以下模块：视频处理模块、时钟处理模块、内部时钟产生模块、GOA管理模块和EM管理模块。需要说明的是，图11中的结构仅作为示例而非限制，显示驱动电路中可以包括比上述模块更多或更少的功能模块，例如，显示驱动电路中还可以包括电源管理模块等，各个模块的工作原理以及模块之间的连接关系可以根据实际应用扩展和变形，本申请实施例对此不作限定。
其中，所述视频处理模块用于接收主控制器发送的视频数据，并对所述视频数据进行处理，生成视频源信号。视频处理模块包括数字电路部分和模拟电路部分，所述视频数据依次经过数字电路和模拟电路的处理。
图12是本申请一实施例的显示驱动电路的视频处理模块的数字电路的结构示意图。如图12所示，所述数字电路部分可以包括但不限于：帧缓冲器(frame buffers)、解码器(decoder)、像素流水线(pixel pipeline)。其中，所述像素流水线包括用于对像素数据进行流水线处理的多个数字模块，例如进行亮度调整的数字模块等。视频数据可以依次通过帧缓冲器、解码器以及像素流水线的处理。
在经过数字电路部分的处理之后的视频数据流需要继续经过模拟电路部分的处理，才能输出到显示屏。图13是本申请一实施例的显示驱动电路的视频处理模块的模拟电路的结构示意图。如图13所示，所述模拟电路部分包括但不限于移位寄存器(shifter register)、数据锁存器、数模转换器(digital to analog converter,DAC)、数据输出缓冲器等模块。经过数字电路处理后的视频数据流可以依次通过移位寄存器、数据锁存器、DAC、数据输出缓冲器等模块的处理，然后生成视频源信号。
继续参见图11，在一个示例中，所述时钟处理模块接收主控制器发送的第一时钟信号，并基于所述第一时钟信号生成第二时钟信号，并将所述第二时钟信号输出至所述GOA管理模块，作为所述GOA管理模块的参考时钟信号。所述GOA管理模块基于所述第二时钟信号生成GOA时钟信号，所述GOA时钟信号可以包括上述GCK信号和/或GCB信号。
在一个示例中，所述时钟处理模块可以包括时钟分频电路。所述主控制器输出的第一时钟信号通常为高频信号，所述显示驱动电路需要对第一时钟信号进行分频处理，得到低频的第二时钟信号，然后以第二时钟信号作为显示驱动电路内部的参考时钟信号。
继续参见图11，在一个示例中，所述显示驱动电路中还可以包括EM管理模块，所述EM管理模块可以基于所述第二时钟信号生成EM信号，所述EM信号用于控制显示屏 中的像素电路发光或不发光。
在一种可能的方案中，显示驱动电路可以使用第一时钟信号作为显示驱动电路内部的主参考时钟信号。例如，可以将所述第一时钟信号作为视频处理模块中的数字电路部分和模块电路部分的时钟信号。但是由于显示驱动电路中的各时钟信号都基于同一时钟信号生成，这将导致显示驱动电路内部的时钟信号的频率范围没有灵活性可调，因此会为显示驱动电路带来时序收敛以及电磁干扰(electro-magnetic interference,EMI)等问题。
为了避免上述问题产生，在本申请实施例中，显示驱动电路可以使用内部时钟产生模块产生的第三时钟信号作为显示驱动电路的数字电路部分的参考时钟信号。而第一时钟信号可以作为显示驱动电路的模拟电路部分、EM管理模块和/或GOA管理模块的参考时钟信号。
继续参见图11，在一个示例中，所述内部时钟产生模块用于生成第三时钟信号，所述第三时钟信号可作为所述视频处理模块的数字电路部分的参考时钟信号，例如帧缓冲器、解码器和像素流水线中的数字模块。所述第三时钟信号为所述显示驱动电路内部产生的时钟信号，在一个示例中，所述内部时钟产生模块包括振荡器(oscillator,OSC)。
继续参见图11，在一个示例中，所述第一时钟信号可以作为所述视频处理模块的模拟电路部分的参考时钟信号。作为一个示例，可以通过时钟处理模块对第一时钟信号进行分频处理，得到第二时钟信号，所述第二时钟信号可以作为视频处理模块中的模拟电路部分的参考信号。例如，所述第二时钟信号可以用于控制移位寄存器以及移位寄存器之后的模拟电路模块。
如图11所示，由于数字电路的参考时钟信号和后端模拟电路的参考时钟是解耦的，为了补偿不同参考时钟之间可能产生的定时误差，可以在数字电路部分和模拟电路部分之间增加第一缓冲器(buffer)，第一缓冲器可以用于补偿数字电路部分和模拟电路部分之间由于参考时钟信号不同产生的时延。第一缓冲器接收第二时钟信号和第三时钟信号，并根据上述时钟信号对输入的视频数据进行缓冲处理，以补偿定时误差。图14是本申请一实施例的显示驱动电路中的视频处理模块的示意图。如图14所示，作为示例，所述缓冲器可以设置于数字电路部分的像素流水线模块与模拟电路部分的移位寄存器之间。
需要说明的是，在图11中，第二时钟信号在输入至视频处理模块中的各个模块之前还可能进行一次或多次分频、倍频处理或者其它类型的处理，本申请实施例以第二时钟信号为例进行说明。或者，在一些示例中，显示驱动电路无需对第一时钟信号进行分频、倍频等处理，可以直接将第一时钟信号输入到各个模块中作为参考时钟信号。换句话说，图11中的时钟处理模块仅仅作为示例，第一时钟信号在输入各个模块之前可以不作任何处理，或者经过多次分频、倍频处理。在图11中，第二时钟信号可以表示一个或多个时钟信号，即，输入到各个模块的第二时钟信号可以是频率相同的同一个信号，也可以是频率不同的多个信号，第二时钟信号仅作为基于第一时钟信号生成的时钟信号的示例性说明。类似地，第三时钟信号仅作为基于显示驱动电路的内部时钟信号生成的时钟信号的示例性说明。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可 以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read-only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (24)

  1. 一种电子设备，其特征在于，包括：
    显示屏，包括第一显示区域和第二显示区域；
    主控制器，包括第一时钟输出端，所述第一时钟输出端用于分别向第一显示驱动电路和第二显示驱动电路发送第一时钟信号；
    所述第一显示驱动电路，包括第一时钟接收端，所述第一时钟接收端用于接收所述第一时钟信号；
    所述第一显示驱动电路还包括第一门驱动阵列GOA时钟信号输出端，所述第一GOA时钟信号输出端用于向所述显示屏输出第一GOA时钟信号，所述第一GOA时钟信号用于控制所述第一显示区域的GOA开启或关闭，其中，所述第一GOA时钟信号是基于所述第一时钟信号生成的；
    所述第二显示驱动电路，包括第二时钟接收端，所述第二时钟接收端用于接收所述第一时钟信号；
    所述第二显示驱动电路还包括第二GOA时钟信号输出端，所述第二GOA时钟信号输出端用于向所述显示屏输出第二GOA时钟信号，所述第二GOA时钟信号用于控制所述第二显示区域的GOA开启或关闭，其中，所述第二GOA时钟信号是基于所述第一时钟信号生成的。
  2. 如权利要求1所述的电子设备，其特征在于，所述第一显示驱动电路还包括第一垂直同步信号输出端，用于向所述显示屏输出第一垂直同步信号，其中，所述第一垂直同步信号是基于所述第一时钟信号生成的，所述第一垂直同步信号用于进行所述第一显示区域的帧同步；
    所述第二显示驱动电路还包括第二垂直同步信号输出端，用于向所述显示屏输出第二垂直同步信号，其中，所述第二垂直同步时钟信号是基于所述第一时钟信号生成的，所述第二垂直同步信号用于进行所述第二显示区域的帧同步，所述第一垂直同步信号和所述第二垂直同步信号为相位相同的信号。
  3. 如权利要求1或2所述的电子设备，其特征在于，所述第一显示驱动电路还包括第一水平同步信号输出端，用于向所述显示屏输出第一水平同步信号，其中，所述第一水平同步信号是基于所述第一时钟信号生成的，所述第一水平同步信号用于进行所述第一显示区域的行同步；
    所述第二显示驱动电路还包括第二水平同步信号输出端，用于向所述显示屏输出第二水平同步信号，其中，所述第二水平同步信号是基于所述第一时钟信号生成的，所述第二水平同步信号用于进行所述第二显示区域的行同步。
  4. 如权利要求1至3中任一项所述的电子设备，其特征在于，所述第一显示驱动电路还包括第一发光EM信号输出端，用于向所述显示屏输出第一EM信号，所述第一EM信号用于控制所述第一显示区域中的像素电路发光或不发光，其中，所述第一EM信号是基于所述第一时钟信号生成的；
    所述第二显示驱动电路还包括第二EM信号输出端，用于向所述显示屏输出第二EM信号，所述第二EM信号用于控制所述第二显示区域中的像素电路发光或不发光，其中， 所述第二EM信号是基于所述第一时钟信号生成的。
  5. 如权利要求1至4中任一项所述的电子设备，其特征在于，所述第一显示驱动电路中包括视频处理模块，所述视频处理模块用于处理所述主控制器输入的视频数据，以生成向所述显示屏发送的视频源信号，所述视频处理模块中的数字电路的参考时钟为所述第一显示驱动电路的内部时钟产生模块生成的第三时钟信号，所述视频处理模块中的模拟电路的参考时钟为所述第一时钟信号。
  6. 如权利要求5所述的电子设备，其特征在于，所述视频处理模块中设置有第一缓冲器，所述第一缓冲器设置于所述视频处理模块中的数字电路和模拟电路之间。
  7. 一种显示驱动电路，其特征在于，所述显示驱动电路包括：
    第一时钟接收端，用于接收所述主控制器发送的第一时钟信号；
    第一门驱动阵列GOA时钟信号输出端，所述第一GOA时钟信号输出端用于向所述显示屏输出第一GOA时钟信号，所述第一GOA时钟信号用于控制所述显示屏的GOA开启或关闭，其中，所述第一GOA时钟信号是基于所述第一时钟信号生成的。
  8. 如权利要求7所述的显示驱动电路，其特征在于，所述显示驱动电路还包括第一垂直同步信号输出端，用于向所述显示屏输出第一垂直同步信号，其中，所述第一垂直同步信号是基于所述第一时钟信号生成的，所述第一垂直同步信号用于进行所述显示屏的帧同步。
  9. 如权利要求7或8所述的显示驱动电路，其特征在于，所述显示驱动电路还包括第一水平同步信号输出端，用于向所述显示屏输出第一水平同步信号，其中，所述第一水平同步信号是基于所述第一时钟信号生成的，所述第一水平同步信号用于进行所述显示屏的行同步。
  10. 如权利要求7至9中任一项所述的显示驱动电路，其特征在于，所述第一显示驱动电路还包括第一发光EM信号输出端，用于向所述显示屏输出第一EM信号，所述第一EM信号用于控制所述显示屏的像素电路发光或不发光，其中，所述第一EM信号是基于所述第一时钟信号生成的。
  11. 如权利要求7至10中任一项所述的显示驱动电路，其特征在于，所述显示驱动电路中包括视频处理模块，所述视频处理模块用于处理所述主控制器输入的视频数据，以生成向所述显示屏发送的视频源信号，所述视频处理模块中的数字电路的参考时钟为所述显示驱动电路的内部时钟产生模块生成的第三时钟信号，所述视频处理模块中的模拟电路的参考时钟为所述第一时钟信号。
  12. 如权利要求11所述的显示驱动电路，其特征在于，所述视频处理模块中设置有第一缓冲器，所述第一缓冲器设置于所述视频处理模块中的数字电路和模拟电路之间。
  13. 一种显示屏的驱动方法，其特征在于，所述显示屏包括第一显示区域和第二显示区域，所述方法包括：
    主控制器分别向第一显示驱动电路和第二显示驱动电路发送第一时钟信号；
    所述第一显示驱动电路向所述显示屏输出第一门驱动阵列GOA时钟信号，所述第一GOA时钟信号用于控制所述第一显示区域的GOA开启或关闭，其中，所述第一GOA时钟信号是基于所述第一时钟信号生成的；
    所述第二显示驱动电路向所述显示屏输出第二GOA时钟信号，所述第二GOA时钟 信号用于控制所述第二显示区域的GOA开启或关闭，其中，所述第二GOA时钟信号是基于所述第一时钟信号生成的。
  14. 如权利要求13所述的方法，其特征在于，所述方法还包括：所述第一显示驱动电路向所述显示屏输出第一垂直同步信号，其中，所述第一垂直同步信号是基于所述第一时钟信号生成的，所述第一垂直同步信号用于进行所述第一显示区域的帧同步；
    所述第二显示驱动电路向所述显示屏输出第二垂直同步信号，其中，所述第二垂直同步时钟信号是基于所述第一时钟信号生成的，所述第二垂直同步信号用于进行所述第二显示区域的帧同步，所述第一垂直同步信号和所述第二垂直同步信号为相位相同的信号。
  15. 如权利要求13或14所述的方法，其特征在于，所述第一显示驱动电路还包括第一水平同步信号输出端，用于向所述显示屏输出第一水平同步信号，其中，所述第一水平同步信号是基于所述第一时钟信号生成的，所述第一水平同步信号用于进行所述第一显示区域的行同步；
    所述第二显示驱动电路还包括第二水平同步信号输出端，用于向所述显示屏输出第二水平同步信号，其中，所述第二水平同步信号是基于所述第一时钟信号生成的，所述第二水平同步信号用于进行所述第二显示区域的行同步。
  16. 如权利要求13至15中任一项所述的方法，其特征在于，所述第一显示驱动电路还包括第一发光EM信号输出端，用于向所述显示屏输出第一EM信号，所述第一EM信号用于控制所述第一显示区域中的像素电路发光或不发光，其中，所述第一EM信号是基于所述第一时钟信号生成的；
    所述第二显示驱动电路还包括第二EM信号输出端，用于向所述显示屏输出第二EM信号，所述第二EM信号用于控制所述第二显示区域中的像素电路发光或不发光，其中，所述第二EM信号是基于所述第一时钟信号生成的。
  17. 如权利要求13至16中任一项所述的方法，其特征在于，所述第一显示驱动电路中包括视频处理模块，所述视频处理模块用于处理所述主控制器输入的视频数据，以生成向所述显示屏发送的视频源信号，所述视频处理模块中的数字电路的参考时钟为所述第一显示驱动电路的内部时钟产生模块生成的第三时钟信号，所述视频处理模块中的模拟电路的参考时钟为所述第一时钟信号。
  18. 如权利要求17所述的方法，其特征在于，所述视频处理模块中设置有第一缓冲器，所述第一缓冲器设置于所述视频处理模块中的数字电路和模拟电路之间。
  19. 一种显示模组，其特征在于，包括：
    显示屏，包括第一显示区域和第二显示区域；
    第一显示驱动电路，包括第一时钟接收端，所述第一时钟接收端用于接收主控制器发送的第一时钟信号；
    所述第一显示驱动电路还包括第一门驱动阵列GOA时钟信号输出端，所述第一GOA时钟信号输出端用于向所述显示屏输出第一GOA时钟信号，所述第一GOA时钟信号用于控制所述第一显示区域的GOA开启或关闭，其中，所述第一GOA时钟信号是基于所述第一时钟信号生成的；
    第二显示驱动电路，包括第二时钟接收端，所述第二时钟接收端用于接收所述第一时钟信号；
    所述第二显示驱动电路还包括第二GOA时钟信号输出端，所述第二GOA时钟信号输出端用于向所述显示屏输出第二GOA时钟信号，所述第二GOA时钟信号用于控制所述第二显示区域的GOA开启或关闭，其中，所述第二GOA时钟信号是基于所述第一时钟信号生成的。
  20. 如权利要求19所述的显示模组，其特征在于，所述第一显示驱动电路还包括第一垂直同步信号输出端，用于向所述显示屏输出第一垂直同步信号，其中，所述第一垂直同步信号是基于所述第一时钟信号生成的，所述第一垂直同步信号用于进行所述第一显示区域的帧同步；
    所述第二显示驱动电路还包括第二垂直同步信号输出端，用于向所述显示屏输出第二垂直同步信号，其中，所述第二垂直同步时钟信号是基于所述第一时钟信号生成的，所述第二垂直同步信号用于进行所述第二显示区域的帧同步，所述第一垂直同步信号和所述第二垂直同步信号为相位相同的信号。
  21. 如权利要求19或20所述的显示模组，其特征在于，所述第一显示驱动电路还包括第一水平同步信号输出端，用于向所述显示屏输出第一水平同步信号，其中，所述第一水平同步信号是基于所述第一时钟信号生成的，所述第一水平同步信号用于进行所述第一显示区域的行同步；
    所述第二显示驱动电路还包括第二水平同步信号输出端，用于向所述显示屏输出第二水平同步信号，其中，所述第二水平同步信号是基于所述第一时钟信号生成的，所述第二水平同步信号用于进行所述第二显示区域的行同步。
  22. 如权利要求19至21中任一项所述的显示模组，其特征在于，所述第一显示驱动电路还包括第一发光EM信号输出端，用于向所述显示屏输出第一EM信号，所述第一EM信号用于控制所述第一显示区域中的像素电路发光或不发光，其中，所述第一EM信号是基于所述第一时钟信号生成的；
    所述第二显示驱动电路还包括第二EM信号输出端，所述第二EM信号输出端用于向所述显示屏输出第二EM信号，所述第二EM信号用于控制所述第二显示区域中的像素电路发光或不发光，其中所述第二EM信号是基于所述第一时钟信号生成的。
  23. 如权利要求19至22中任一项所述的显示模组，其特征在于，所述第一显示驱动电路中包括视频处理模块，所述视频处理模块用于处理所述主控制器输入的视频数据，以生成向所述显示屏发送的视频源信号，所述视频处理模块中的数字电路的参考时钟为所述第一显示驱动电路的内部时钟产生模块生成的第三时钟信号，所述视频处理模块中的模拟电路的参考时钟为所述第一时钟信号。
  24. 如权利要求23中任一项所述的显示模组，其特征在于，所述视频处理模块中设置有第一缓冲器，所述第一缓冲器设置于所述视频处理模块中的数字电路和模拟电路之间。
PCT/CN2020/075721 2019-02-23 2020-02-18 显示驱动电路、显示模组、显示屏的驱动方法及电子设备 WO2020169027A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP20759437.5A EP3920172A4 (en) 2019-02-23 2020-02-18 DISPLAY CIRCUIT OPERATING, DISPLAY MODULE, METHOD OF OPERATION FOR A DISPLAY SCREEN, AND ELECTRONIC DEVICE
US17/433,201 US11508311B2 (en) 2019-02-23 2020-02-18 Display driver circuit, display module, method for driving display, and electronic device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN2019075981 2019-02-23
CNPCT/CN2019/075981 2019-02-23
CN201910844205.0 2019-09-06
CN201910844205.0A CN111613181B (zh) 2019-02-23 2019-09-06 显示驱动电路、显示模组、显示屏的驱动方法及电子设备

Publications (1)

Publication Number Publication Date
WO2020169027A1 true WO2020169027A1 (zh) 2020-08-27

Family

ID=72144134

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/075721 WO2020169027A1 (zh) 2019-02-23 2020-02-18 显示驱动电路、显示模组、显示屏的驱动方法及电子设备

Country Status (3)

Country Link
US (1) US11508311B2 (zh)
CN (1) CN114822377A (zh)
WO (1) WO2020169027A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12008956B2 (en) 2021-02-09 2024-06-11 Samsung Electronics Co., Ltd. Electronic device and method capable of reducing afterimage of display

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11620960B2 (en) * 2020-10-20 2023-04-04 Intermec Ip Corporation Synchronous display blinking

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5107255A (en) * 1988-11-15 1992-04-21 Sharp Kabushiki Kaisha Control device for a display apparatus
US20100253672A1 (en) * 2009-04-07 2010-10-07 Nec Lcd Technologies, Ltd. Liquid crystal display device, and timing controller and signal processing method used in same
CN201681587U (zh) * 2010-05-24 2010-12-22 北京京东方光电科技有限公司 双面液晶显示设备
CN102143275A (zh) * 2010-11-26 2011-08-03 华为终端有限公司 移动终端显示方法和移动终端
CN104536229A (zh) * 2015-01-12 2015-04-22 京东方科技集团股份有限公司 一种阵列基板及显示面板
CN105118450A (zh) * 2015-08-13 2015-12-02 深圳市华星光电技术有限公司 避免goa基板烧毁的液晶显示器

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006106394A (ja) * 2004-10-06 2006-04-20 Alps Electric Co Ltd 液晶駆動回路および液晶表示装置
TWI390485B (zh) * 2008-01-28 2013-03-21 Au Optronics Corp 顯示裝置及顯示影像之方法
CN101527134B (zh) * 2009-04-03 2011-05-04 华为技术有限公司 一种显示方法、显示控制器及显示终端
KR20110083409A (ko) 2010-01-14 2011-07-20 (주)엠씨테크놀로지 타이밍 제어기, 이를 이용하여 동기를 제어하는 장치
CN103065575B (zh) * 2011-10-20 2015-09-30 乐金显示有限公司 数字全息图像再现装置及其同步控制方法
JP6099311B2 (ja) 2012-02-10 2017-03-22 株式会社ジャパンディスプレイ 表示装置
CN103280205B (zh) * 2013-06-06 2015-09-23 青岛海信电器股份有限公司 显示装置、时序控制器及图像显示方法
KR102261510B1 (ko) * 2014-11-04 2021-06-08 삼성디스플레이 주식회사 표시 장치 및 표시 장치의 구동 방법
KR102297573B1 (ko) 2014-12-24 2021-09-06 엘지디스플레이 주식회사 컨트롤러, 소스 드라이버 집적회로, 표시장치 및 그 신호전송방법
KR102423007B1 (ko) 2015-09-17 2022-07-21 삼성디스플레이 주식회사 표시 장치 및 이를 포함하는 전자 기기
CN105469761B (zh) * 2015-12-22 2017-12-29 武汉华星光电技术有限公司 用于窄边框液晶显示面板的goa电路
KR102561294B1 (ko) * 2016-07-01 2023-08-01 삼성디스플레이 주식회사 화소 및 스테이지 회로와 이를 가지는 유기전계발광 표시장치
CN107633795B (zh) 2016-08-19 2019-11-08 京东方科技集团股份有限公司 显示装置和显示面板的驱动方法
KR102565753B1 (ko) 2016-12-28 2023-08-11 엘지디스플레이 주식회사 전계 발광 표시장치와 그 구동 장치
CN106504722B (zh) * 2017-01-12 2019-10-01 京东方科技集团股份有限公司 一种goa分区驱动方法和装置、goa单元
CN106898288A (zh) 2017-04-10 2017-06-27 深圳市华星光电技术有限公司 显示面板及显示装置
KR102423863B1 (ko) * 2017-08-04 2022-07-21 엘지디스플레이 주식회사 게이트 구동부 및 이를 구비한 평판 표시 장치
CN207781150U (zh) * 2017-11-13 2018-08-28 昆山龙腾光电有限公司 时序控制器及其显示装置
CN108877638B (zh) * 2018-09-21 2021-06-04 重庆惠科金渝光电科技有限公司 驱动电路、升压芯片及显示装置
TWI754235B (zh) * 2019-02-27 2022-02-01 聯詠科技股份有限公司 驅動電路、顯示裝置及其驅動方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5107255A (en) * 1988-11-15 1992-04-21 Sharp Kabushiki Kaisha Control device for a display apparatus
US20100253672A1 (en) * 2009-04-07 2010-10-07 Nec Lcd Technologies, Ltd. Liquid crystal display device, and timing controller and signal processing method used in same
CN201681587U (zh) * 2010-05-24 2010-12-22 北京京东方光电科技有限公司 双面液晶显示设备
CN102143275A (zh) * 2010-11-26 2011-08-03 华为终端有限公司 移动终端显示方法和移动终端
CN104536229A (zh) * 2015-01-12 2015-04-22 京东方科技集团股份有限公司 一种阵列基板及显示面板
CN105118450A (zh) * 2015-08-13 2015-12-02 深圳市华星光电技术有限公司 避免goa基板烧毁的液晶显示器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12008956B2 (en) 2021-02-09 2024-06-11 Samsung Electronics Co., Ltd. Electronic device and method capable of reducing afterimage of display

Also Published As

Publication number Publication date
US11508311B2 (en) 2022-11-22
US20220122543A1 (en) 2022-04-21
CN114822377A (zh) 2022-07-29

Similar Documents

Publication Publication Date Title
WO2019233120A1 (zh) 像素电路及其驱动方法、显示面板
TWI602169B (zh) 掃描驅動器及使用其之有機發光二極體顯示器
KR102622270B1 (ko) 디스플레이 패널, 디스플레이 디바이스 및 구동 방법
KR101857808B1 (ko) 스캔구동부와 이를 이용한 유기전계발광표시장치
KR102582032B1 (ko) 발광 구동부 및 이를 포함하는 표시 장치
KR102662925B1 (ko) 화소 회로 및 이를 포함하는 표시 장치
AU2019452478A1 (en) Display panel and display device
WO2020169036A1 (zh) 显示驱动系统、显示模组、显示屏的驱动方法及电子设备
WO2021022838A1 (zh) 触发驱动电路及显示装置
KR102496271B1 (ko) 분산형 메모리 패널
CN112449715B (zh) 显示面板、显示装置及驱动方法
KR20170126567A (ko) 표시 패널 구동부 및 이를 포함하는 표시 장치
JP2019504335A (ja) Ｇｉｐ回路及びその駆動方法、並びにフラットパネルディスプレイ装置
US11749210B2 (en) Signal control apparatus and method, display control apparatus and method, and display apparatus
WO2020187195A1 (zh) 像素电路及其驱动方法、显示面板和显示装置
KR20140083399A (ko) 유기 발광 표시 장치 및 이의 동시 발광 구동 방법
US11205389B2 (en) Scan driver and display device having same
KR20210036689A (ko) 반전 신호를 이용한 표시장치와 그 구동 방법
WO2020169027A1 (zh) 显示驱动电路、显示模组、显示屏的驱动方法及电子设备
EP3920172A1 (en) Display drive circuit, display module, drive method for display screen, and electronic device
US11676557B2 (en) Method and device for seamless mode transition between command mode and video mode
KR20200081975A (ko) 표시장치
KR20200123334A (ko) 화소 구동 장치 및 이를 포함하는 표시 장치
US20230419904A1 (en) Display panel, method for driving a display panel and display apparatus
KR20070042636A (ko) 액정 표시 장치 및 이의 구동방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20759437

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2020759437

Country of ref document: EP

Effective date: 20210902