WO2020156284A1 - 显示驱动装置、其控制方法及显示装置 - Google Patents

显示驱动装置、其控制方法及显示装置 Download PDF

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Publication number
WO2020156284A1
WO2020156284A1 PCT/CN2020/073025 CN2020073025W WO2020156284A1 WO 2020156284 A1 WO2020156284 A1 WO 2020156284A1 CN 2020073025 W CN2020073025 W CN 2020073025W WO 2020156284 A1 WO2020156284 A1 WO 2020156284A1
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Prior art keywords
frame
displayed
display data
processing chip
memory
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PCT/CN2020/073025
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English (en)
French (fr)
Chinese (zh)
Inventor
马希通
耿立华
李彦孚
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to US17/256,094 priority Critical patent/US11798450B2/en
Priority to EP20749432.9A priority patent/EP3920168B1/en
Priority to JP2020573176A priority patent/JP7540955B2/ja
Publication of WO2020156284A1 publication Critical patent/WO2020156284A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G09G5/397—Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/399—Control of the bit-mapped memory using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2350/00—Solving problems of bandwidth in display systems
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2352/00—Parallel handling of streams of display data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/06—Use of more than one graphics processor to process data before displaying to one or more screens
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/121—Frame memory handling using a cache memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/122—Tiling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/128—Frame memory using a Synchronous Dynamic RAM [SDRAM]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel

Definitions

  • the embodiment of the present disclosure relates to a display driving device, a control method thereof, and a display device.
  • the display data of the frame to be displayed is processed by the processing chip, and then output to the display panel, and the display panel is driven to display the image.
  • the requirements for storage bandwidth and transmission interfaces are getting higher and higher.
  • At least one embodiment of the present disclosure provides a control method of a display driving device, the display driving device comprising: at least two processing chips, and memories connected to the at least two processing chips in a one-to-one correspondence signal; each of the memories It includes a plurality of frame addresses set in sequence; each frame to be displayed includes at least two image areas, and the at least two image areas correspond to the at least two processing chips one-to-one; in the at least two processing chips One of the processing chips is the master processing chip, and the remaining processing chips are slave processing chips;
  • control method includes:
  • the main processing chip receives the display data of the corresponding image area in the current frame to be displayed; each of the slave processing chips receives the display data of the corresponding image area in the current frame to be displayed;
  • the master processing chip generates a read and write synchronization signal when buffering the received display data, and each of the slave processing chips receives the read and write synchronization signal;
  • the main processing chip buffers the received display data of the currently to-be-displayed frame into the frame address of the corresponding electrically connected memory, and caches the data in the electrically connected memory
  • the display data of the last frame to be displayed is read and processed before being transmitted to the display panel;
  • each of the slave processing chips buffers the received display data of the currently to-be-displayed frame into the frame address of the corresponding electrically connected memory in synchronization with the master processing chip And the display data of the last frame to be displayed buffered in the connected memory is read and processed in synchronization with the main processing chip and then transmitted to the display panel.
  • the master processing chip also receives the frame start signal when receiving the display data of the corresponding image area in the currently to be displayed frame; the slave processing chip is receiving the current to be displayed Receiving the frame start signal when displaying data corresponding to the image area in the frame picture;
  • control method Before the master processing chip generates a read-write synchronization signal when buffering the received display data, before each of the slave processing chips receives the read-write synchronization signal, the control method further includes:
  • the main processing chip generates a frame start synchronization signal according to the frame start signal, and the slave processing chip receives the frame start synchronization signal;
  • the master processing chip In response to the frame start synchronization signal and the frame start signal, the master processing chip generates a drive timing corresponding to the display data received by the master processing chip; each of the slave processing chips responds to the frame start The synchronization signal and the frame start signal are synchronized with the main processing chip to generate drive timing corresponding to the display data received from the processing chip.
  • the control method when the master processing chip buffers the received display data, the read and write synchronization signal is generated, and after each slave processing chip receives the read and write synchronization signal, the control method also includes:
  • the main processing chip buffers the received display data of the currently to-be-displayed frame picture and the corresponding drive timing into the frame address of the corresponding electrically connected memory, and compares The display data of the last frame to be displayed and the corresponding driving sequence buffered in the memory that are electrically connected are read and processed, and then transmitted to the display panel; and
  • each of the slave processing chips buffers the received display data of the currently to-be-displayed frame picture and the corresponding drive timing to the corresponding electrical connection in synchronization with the master processing chip
  • the display data of the last frame to be displayed and the corresponding drive sequence buffered in the memory that are electrically connected are read and processed in synchronization with the main processing chip and then transmitted to the The display panel.
  • the image area in each frame to be displayed extends along the column direction of the pixel units of the display panel, and is arranged along the row direction of the pixel units of the display panel.
  • the frame start signal is a field synchronization signal.
  • the sequence of buffering the frame addresses of the display data of the last frame to be displayed in the memory is before the sequence of buffering the frame addresses of the display data of the frame to be displayed currently.
  • the memory electrically connected to the master processing chip caches the frame address of the display data of the frame to be displayed currently and the memory electrically connected to each slave processing chip caches the frame to be displayed currently
  • the frame address of the display data of the screen is the same.
  • the memory electrically connected to the master processing chip caches the frame address of the display data of the frame to be displayed currently and the memory electrically connected to each slave processing chip caches the frame to be displayed currently The frame address of the display data of the screen is different.
  • the size of each image area is the same.
  • the multiple frame addresses of the memory corresponding to the processing chip and electrically connected are used to store the display data of each display frame in order and cyclically.
  • an embodiment of the present disclosure also provides a display driving device, including: at least two processing chips, and memories connected with the at least two processing chips in a one-to-one correspondence signal; each of the memories includes a plurality of memories arranged in order.
  • a frame address; each frame to be displayed includes at least two image areas, the at least two image areas correspond to the at least two processing chips one-to-one; one of the at least two processing chips is the main processing chip Processing chip, other processing chips are slave processing chips;
  • the main processing chip is configured to receive the display data of the corresponding image area in the current frame to be displayed and generate a read-write synchronization signal when buffering, and respond to the read-write synchronization signal to respond to the received frame to be displayed currently
  • the display data of is buffered into the frame address of the corresponding electrically connected memory, and the display data of the last frame to be displayed buffered in the electrically connected memory is read and processed and then transmitted to the display panel;
  • Each of the slave processing chips is configured to receive the display data of the corresponding image area in the currently to-be-displayed frame picture and the read-write synchronization signal, and in response to the read-write synchronization signal, send the received current to-be-displayed
  • the display data of the displayed frame picture is buffered in the frame address of the corresponding electrically connected memory in synchronization with the main processing chip, and the display data of the last frame picture to be displayed is buffered in the connected memory and all
  • the main processing chip performs reading and processing synchronously and transmits it to the display panel.
  • the main processing chip is further configured to receive the frame start signal when receiving the display data of the corresponding image area in the frame picture currently to be displayed, and generate a frame according to the frame start signal.
  • Start synchronization signal in response to the frame start synchronization signal and the frame start signal, generate a drive timing corresponding to the display data received by the main processing chip; respond to the read and write synchronization signal to receive the
  • the display data of the current frame to be displayed and the corresponding driving timing are cached in the frame address of the corresponding electrically connected memory, and the display data of the last frame to be displayed and the corresponding driving timing are cached in the electrically connected memory After reading and processing, it is transmitted to the display panel;
  • the slave processing chip is further configured to receive the frame start synchronization signal, and receive the frame start signal when receiving the display data of the corresponding image area in the frame to be displayed currently; in response to the frame start
  • the start synchronization signal and the frame start signal are synchronized with the main processing chip to generate a drive timing corresponding to the display data received from the processing chip; in response to the read and write synchronization signal, the received current to-be-displayed
  • the display data of the frame picture and the corresponding drive timing are cached in the frame address of the corresponding electrically connected memory in synchronization with the main processing chip, and the display data of the last frame picture to be displayed cached in the electrically connected memory
  • the corresponding driving timing is read and processed in synchronization with the main processing chip and then transmitted to the display panel.
  • each of the processing chips is further configured to receive display data of corresponding image areas in at least two to-be-displayed frame pictures; and cyclically use the multiple frame addresses of the memory in order, Buffer the received display data of the at least two frames to be displayed in an electrically connected memory, and for the plurality of frame addresses of the memory, sequentially and cyclically buffer the corresponding to be stored in the electrically connected memory.
  • the display data of the display frame is read, converted, and transmitted to the display panel.
  • the processing chip includes: a field programmable logic gate array chip.
  • the memory includes: a double-rate synchronous dynamic random access memory.
  • At least one embodiment of the present disclosure also provides a display device, including: a display panel and any of the above display driving devices,
  • the display panel is configured to receive the display data transmitted by the display driving device.
  • FIG. 1 is a schematic structural diagram of a display driving device in at least one embodiment of the present disclosure
  • Fig. 2 is a flowchart of a control method in at least one embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a VS signal in at least one embodiment of the disclosure.
  • FIG. 4 is a schematic diagram of a specific structure of a display driving device in at least one embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of a display device in at least one embodiment of the disclosure.
  • the general processing chip can be set as a field programmable logic gate array (Field Programmable Gate Array, FPGA) chip.
  • FPGA Field Programmable Gate Array
  • the display data of the frame to be displayed can be processed by the FPGA chip and then output to the display panel, so as to drive the display panel and realize the image display.
  • a common practice is to buffer the display data of several frames to be displayed into the memory electrically connected to the FPGA chip through the FPGA chip, and then the FPGA chip reads and processes the display data buffered in the memory and outputs it to the display panel.
  • the frame address of the memory is shared between each FPGA chip. That is, when an FPGA chip stores the display data of a certain frame to be displayed in the frame address of the corresponding memory, the frame addresses of the memory corresponding to the remaining FPGA chips also change synchronously, so that the display data of the frame to be displayed Synchronously store to the frame address of the corresponding memory.
  • the memory initialization fails or the transmission interface cannot be locked, etc., it may cause a sudden change in the frame address of the memory of a certain FPGA chip, such as a reset.
  • the frame address of the memory is shared between FPGA chips, if the frame address of the memory of a certain FPGA chip changes, the frame addresses of the memory of the other FPGA chips will also change. This may cause the display data stored and read by each FPGA chip from the memory to not belong to the same frame of picture, resulting in abnormal display of the picture.
  • Each memory 200_m includes a plurality of frame addresses set in order.
  • the memory 200_m may have K frame addresses set in order, that is, frame addresses 0, 1, 2...K-1; where K is an integer greater than 1. .
  • each frame to be displayed may include at least two image areas AA_m.
  • each image area AA_m corresponds to one processing chip 100_m.
  • the image area AA_1 corresponds to the processing chip 100_1
  • the image area AA_2 corresponds to the processing chip 100_2, and the rest is the same, which will not be repeated here.
  • One of the M processing chips is defined as the master processing chip, and the remaining processing chips are defined as slave processing chips.
  • the processing chip 100_1 is defined as the master processing chip
  • the processing chips 100_2 to 100_M are defined as the slave processing chips.
  • control method of the display driving device may include the following steps:
  • the main processing chip receives the display data of the corresponding image area in the frame picture currently to be displayed; each slave processing chip receives the display data of the corresponding image area in the frame picture currently to be displayed;
  • the main processing chip generates a read and write synchronization signal when buffering the received display data, and each slave processing chip receives the read and write synchronization signal;
  • the main processing chip buffers the received display data of the currently to-be-displayed frame into the frame address of the corresponding electrically connected memory, and buffers the last to-be-displayed frame in the electrically connected memory. After reading and processing the display data, it is transmitted to the display panel; each slave processing chip synchronously buffers the received display data of the current frame to be displayed in the frame address of the corresponding electrically connected memory in response to the read and write synchronization signal , And synchronously read and process the display data of the last frame to be displayed buffered in the connected memory and transmit it to the display panel.
  • the master processing chip and each slave processing chip in response to the read-write synchronization signal, synchronously buffer the received display data of the currently to-be-displayed frame into the frame address of the corresponding electrically connected memory, and synchronize The display data of the last frame to be displayed buffered in the connected memory is read and processed before being transmitted to the display panel.
  • one master processing chip and multiple slave processing chips are provided, which can facilitate the design of a high-resolution display panel. Moreover, when the main processing chip buffers the received display data of the corresponding image area in the current frame to be displayed, it can generate a read-write synchronization signal and send the generated read-write synchronization signal to each slave processing chip.
  • the main processing chip and each slave processing chip are controlled by the read-write synchronization signal to buffer the received display data of the currently to-be-displayed frame into the frame address of the corresponding electrically connected memory, and the data buffered in the electrically connected memory
  • the display data of a frame to be displayed is read and processed and then transmitted to the display panel to drive the display panel to display the picture.
  • the main processing chip and each slave processing chip control the storage and reading operations of the memory through the read and write synchronization signal, it is possible to avoid sharing the frame address of the memory between the processing chips, so that the frame of the memory corresponding to a certain processing chip When the address changes, it will not affect the frame address of the memory corresponding to the other processing chips, thus ensuring that the display data output by each processing chip belongs to the same frame of screen, thereby eliminating the problem of abnormal screen display caused by asynchronization of multiple processing chips .
  • different application environments have different requirements for the value of M, so the value of M can be designed and determined according to the actual application environment, which is not limited here.
  • each processing chip 100_m is connected to the same signal receiving interface 400 to receive the display data of the frame to be displayed through the signal receiving interface 400.
  • the frame address of the memory that is electrically connected to the main processing chip to buffer the display data of the frame to be displayed currently is the same as the frame address of the memory that is electrically connected to each slave processing chip to buffer the display data of the frame to be displayed. .
  • the frame address for reading the stored display data from the memory is also the same. For example, if a certain video has 300 consecutive pictures, the memory 200_m can store 3 frame addresses: frame address 0, frame address 1, and frame address 2 as an example.
  • the master processing chip 100_1 stores the display data corresponding to the image area AA_m in the first frame to be displayed in the frame address 0 of the corresponding memory 200_1, and the slave processing chips 100_2 ⁇ 100_M are also in the frame address 0 of the corresponding memory 200_2 ⁇ 100_M Store the display data corresponding to the image area AA_m in the first frame to be displayed.
  • the master processing chip 100_1 stores the display data corresponding to the image area AA_m in the second frame to be displayed in the frame address 1 of the corresponding memory 200_1, and the slave processing chips 100_2 ⁇ 100_M are also in the frame address 1 of the corresponding memory 200_2 ⁇ 100_M Store the display data of the corresponding image area AA_m in the second frame to be displayed.
  • the memory electrically connected to the main processing chip can also buffer the frame address of the display data of the frame to be displayed currently and the memory electrically connected to each slave processing chip buffer the frame address of the display data of the frame to be displayed currently They are not the same, and are not limited here.
  • the order of the frame addresses of the display data of the last frame to be displayed in the memory can be buffered before the order of the frame addresses of the display data of the frame to be displayed currently. This can ensure that the read frame address is before the stored frame address, thereby avoiding display abnormalities.
  • the processing chip 100_m stores the display data corresponding to the image area AA_m in the first frame to be displayed in the frame address 0 of the corresponding memory 200_m, and the processing chip 100_m responds to the read and write synchronization signal in the frame of the corresponding memory 200_m
  • the display data of the corresponding image area AA_m in the second frame to be displayed is stored in address 1, and the display data of the first frame to be displayed stored in the frame address 0 of the corresponding memory 200_m is read and converted before transmission To the display panel.
  • the display data corresponding to the image area AA_m in the third frame to be displayed is stored in the frame address 2 of the corresponding memory 200_m, and the second stored in the frame address 1 of the corresponding memory 200_m
  • the display data of each frame to be displayed is read and converted and transmitted to the display panel. The rest is the same, so I won't repeat it here.
  • each processing chip 100_m may be configured to receive the display data corresponding to the image area AA_m in the at least two to-be-displayed frame pictures, and display the received at least two to-be-displayed frame pictures in response to the read-write synchronization signal
  • the data is circularly buffered to the frame address of the electrically connected memory 200_m in order, and the display data of the frame to be displayed buffered in the corresponding memory 200_m is sequentially read and converted to the display panel.
  • each processing chip 100_m may be configured to receive the display data corresponding to the image area AA_m in the at least two frames to be displayed, and in response to the read and write synchronization signal, the plurality of electrically connected memories 200_m are used in sequence and cyclically.
  • the frame address buffers the received display data of at least two frames to be displayed in the electrically connected memory 200_m (for example, according to the aforementioned frame address 1, frame address 2, frame address 0, frame address 1, frame address 2...
  • the display data of the frame to be displayed buffered in the corresponding memory 200_m is read and converted to the display panel (for example, according to The above-mentioned frame address 0, frame address 1, frame address 2, frame address 0, frame address 1... are read cyclically in order). This can avoid storing and reading the frame address in the same memory, thereby avoiding display abnormalities.
  • the number of frame addresses stored in the memory 200_m may be N.
  • the memory 200_m can store 3 frame addresses: frame address 0, frame address 1, and frame address 2.
  • a certain new video has 300 continuous pictures, and the processing chip 100_m cyclically receives the display data corresponding to the image area AA_m in the 3 frames to be displayed.
  • the processing chip 100_m buffers the received display data of the 3 frames to be displayed (that is, the display data of 3 consecutive frames to be displayed) to the frame address of the electrically connected memory 200_m in order, and stores the corresponding memory
  • the display data of the 3 to-be-displayed frames buffered in 200_m are read and converted in sequence and transferred to the display panel, which means: in response to the read and write synchronization signal, they are first stored in the frame address 0 of the corresponding memory 200_m
  • the display data of the first frame to be displayed of the new video, and the display data of the frame to be displayed of the previous video stored in the frame address 0 are read, converted, and transmitted to the display panel.
  • the display data of the second frame to be displayed is stored in the frame address 1 of the corresponding memory 200_m, and the display data of the first frame to be displayed stored in the frame address 0 is read After taking and converting, it is transmitted to the display panel so that the display panel displays the first frame to be displayed.
  • the display data of the third frame to be displayed is stored in the frame address 2 of the corresponding memory 200_m, and the display data of the second frame to be displayed stored in the frame address 1 is read After fetching and converting, it is transmitted to the display panel so that the display panel displays the second frame to be displayed.
  • the display data of the fourth frame to be displayed is stored in the frame address 0 of the corresponding memory 200_m, and the display data of the third frame to be displayed stored in the frame address 2 is read After fetching and converting, it is transmitted to the display panel so that the display panel displays the third frame to be displayed.
  • the display data of the fifth frame to be displayed is stored in the frame address 1 of the corresponding memory 200_m, and the display data of the fourth frame to be displayed stored in the frame address 0 is read After taking and converting, it is transmitted to the display panel, so that the display panel displays the fourth frame to be displayed.
  • the display data of the sixth frame to be displayed is stored in the frame address 2 of the corresponding memory 200_m, and the display data of the fifth frame to be displayed stored in the frame address 1 is read After taking and converting, it is transmitted to the display panel so that the display panel displays the fifth frame to be displayed. After that, cyclic storage is performed in the order of frame address 0, frame address 1, and frame address 2, and cyclic reading is performed in the order of frame address 2, frame address 0, and frame address 1 to drive the display panel to display, which will not be repeated here.
  • the main processing chip also receives the display data of the corresponding image area in the frame to be displayed currently The frame start signal
  • the slave processing chip also receives the frame start signal when receiving the display data of the corresponding image area in the current frame to be displayed. That is, each processing chip also receives the frame start signal when receiving the display data of the corresponding image area in the current frame to be displayed.
  • control method when the master processing chip generates a read and write synchronization signal when buffering the received display data, before each slave processing chip receives the read and write synchronization signal, the control method according to at least one embodiment of the present disclosure may further include:
  • the main processing chip generates a frame start synchronization signal according to the frame start signal, and receives the frame start synchronization signal from the processing chip;
  • the master processing chip In response to the frame start synchronization signal and the frame start signal, the master processing chip generates a drive timing corresponding to the display data received by the master processing chip; each slave processing chip generates corresponding slave processing in response to the frame start synchronization signal and the frame start signal. The drive timing of the display data received by the chip.
  • control method may include:
  • the main processing chip buffers the received display data of the currently to-be-displayed frame picture and the corresponding drive timing into the frame address of the corresponding electrically connected memory, and then caches the last to-be-displayed data in the electrically connected memory.
  • the display data of the display frame picture and the corresponding drive timing are read and processed and then transmitted to the display panel; each slave processing chip will receive the display data of the current frame to be displayed and the corresponding drive timing in response to the read and write synchronization signal Synchronously buffer into the frame address of the corresponding electrically connected memory, and synchronously read and process the display data of the last frame to be displayed and the corresponding driving sequence buffered in the electrically connected memory, and then transmit to the display panel.
  • the master processing chip and each slave processing chip in response to the read-write synchronization signal, synchronously buffer the received display data of the currently to-be-displayed frame and the corresponding drive timing to the frame of the corresponding electrically connected memory In the address, the display data of the last frame to be displayed and the corresponding drive sequence buffered in the electrically connected memory are read and processed synchronously, and then transmitted to the display panel.
  • the main processing chip also receives the frame start signal when receiving the display data of the corresponding image area in the current frame to be displayed, and generates the frame start synchronization signal according to the frame start signal; then, responds to the frame start synchronization signal and the frame start signal.
  • the start signal is generated corresponding to the driving timing of the display data received by the main processing chip.
  • the main processing chip After that, the main processing chip generates a read and write synchronization signal when buffering the received display data, so as to respond to the read and write synchronization signal to buffer the received display data of the currently to-be-displayed frame and the corresponding drive timing to the corresponding electrical connection
  • the display data of the last frame to be displayed and the corresponding driving sequence buffered in the electrically connected memory are read and processed, and then transmitted to the display panel.
  • the slave processing chip also receives the frame start signal when receiving the display data of the corresponding image area in the current frame to be displayed; and, the slave processing chip also receives the frame start synchronization signal sent by the master processing chip, and responds to the frame start signal.
  • the synchronization signal and the frame start signal are synchronized with the main processing chip to generate drive timing corresponding to the display data received from the processing chip.
  • each slave processing chip receives the read and write synchronization signal, and in response to the read and write synchronization signal, buffers the received display data of the current frame to be displayed and the corresponding drive timing to the corresponding electrical connection in synchronization with the main processing chip.
  • the display data of the last frame to be displayed and the corresponding drive sequence buffered in the electrically connected memory are read and processed in synchronization with the main processing chip and then transmitted to the display panel.
  • the main processing chip can determine the start of a frame through the frame start signal, thereby generating a frame start synchronization signal to simultaneously control the driving of the main processing chip and the slave processing chip corresponding to the respective received display data through the frame start synchronization signal. Timing, so that the timing of driving the display data can be aligned, so that the screen is refreshed synchronously.
  • the field synchronization signal (VS) is set in the display panel.
  • the function of the VS signal is to select the effective field signal interval in the display panel. For example, when the falling edge of the VS signal, it can indicate a new display
  • the display data of the frame picture is transmitted sequentially according to the pixel units of the first row to the last row in the display panel.
  • the frame start signal may be set as a field synchronization signal. In this way, it can be ensured that the memory stores the display data of the corresponding image area in the frame address according to the order of the pixel units of the first row to the last row.
  • the display panel will also be provided with a line synchronization signal (HS), effective display data strobe signal (DE) and other signals.
  • HS line synchronization signal
  • DE effective display data strobe signal
  • each processing chip is receiving the current frame to be displayed.
  • At least one of the HS signal and the DE signal can also be received when the display data of the corresponding image area is displayed, which is not limited here.
  • the functions of the HS signal and the DE signal are basically the same as the existing functions, which should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be used as a limitation to the present disclosure.
  • each image area AA_m may be the same. In this way, the data stored, read, and processed by each processing chip can be more uniform, so that the power consumption of each processing chip is more uniform, so that the life of each processing chip is more uniform.
  • the main processing chip 100_1 is configured to receive the display data corresponding to the image area AA_1 in the current frame to be displayed and generate a read-write synchronization signal.
  • the main processing chip 100_1 responds to the read-write synchronization signal and will receive the current standby
  • the display data of the display frame is buffered into the frame address of the corresponding electrically connected memory 200_1, and the display data of the last frame to be displayed buffered in the electrically connected memory 200_1 is read and processed, and then transmitted to the display panel 300.
  • Each slave processing chip 100_2 ⁇ 100_M (M is an integer greater than 1) is configured to receive the display data AA_2 ⁇ AA_M of the corresponding image area in the current frame to be displayed and the read-write synchronization signal, and will receive the read-write synchronization signal in response to the read-write synchronization signal.
  • the received display data of the current frame to be displayed is synchronously buffered to the frame address of the corresponding electrically connected memory 200_2 ⁇ 200_M, and the display data of the last frame to be displayed buffered in the connected memory 200_2 ⁇ 200_M is synchronously read After the processing and processing, it is transmitted to the display panel 300.
  • the master processing chip 100_1 and each of the slave processing chips 100_2 to 100_M synchronously buffer the received display data of the current frame to be displayed to the corresponding electrically connected memory 200_1 to In the frame address of 200_M, the display data of the last frame to be displayed buffered in the connected memories 200_1 to 200_M is read and processed, and then transmitted to the display panel 300.
  • the main processing chip buffers the received display data of the corresponding image area in the current frame to be displayed, it can generate a read-write synchronization signal and send the generated read-write synchronization signal to each slave processing chip.
  • the main processing chip and each slave processing chip are controlled by the read-write synchronization signal to buffer the received display data of the currently to-be-displayed frame into the frame address of the corresponding electrically connected memory, and the data buffered in the electrically connected memory
  • the display data of a frame to be displayed is read and processed and then transmitted to the display panel to drive the display panel to display the picture.
  • the main processing chip and each slave processing chip control the storage and reading operations of the memory through the read and write synchronization signal, it is possible to avoid sharing the frame address of the memory between the processing chips, so that the frame of the memory corresponding to a certain processing chip When the address changes, it will not affect the frame address of the memory corresponding to the other processing chips, thus ensuring that the display data output by each processing chip belongs to the same frame of screen, thereby eliminating the problem of abnormal screen display caused by asynchronization of multiple processing chips .
  • the display driving device may be applicable to a 4K (3840*2160) display panel, an 8K (7680*4320) display panel, etc., which is not limited by the embodiment of the present disclosure.
  • each processing chip is configured to receive the display data of the corresponding image area in the at least two frames to be displayed; the multiple frame addresses of the electrically connected memory are cyclically used in order to receive The received display data of the at least two frames to be displayed are cached in the electrically connected memory, and the multiple frame addresses of the electrically connected memory are sequentially and cyclically displayed corresponding to the frame to be displayed cached in the electrically connected memory
  • the data is read and converted and transmitted to the display panel; among them, for each frame to be displayed, in response to the read and write synchronization signal, the received display data of the frame to be displayed is buffered into the frame address of the electrically connected memory , And synchronously read and process the display data of the last frame to be displayed buffered in the connected memory in response to the read-write synchronization signal, and then transmit it to the display panel.
  • the main processing chip is also configured to receive the frame start signal when receiving the display data of the corresponding image area in the frame picture currently to be displayed, and generate the frame start synchronization signal according to the frame start signal. Signal; In response to the frame start synchronization signal and the frame start signal, generate the drive timing corresponding to the display data received by the main processing chip; In response to the read and write synchronization signal, it will receive the display data and corresponding drive timing of the current frame to be displayed Buffer to the frame address of the corresponding electrically connected memory, and read and process the display data of the last frame to be displayed and the corresponding drive sequence buffered in the electrically connected memory, and then transmit to the display panel;
  • the slave processing chip is also configured to receive the frame start synchronization signal, and receive the frame start signal when receiving the display data of the corresponding image area in the current frame to be displayed; in response to the frame start synchronization signal and the frame start signal are generated synchronously Corresponding to the drive timing of the display data received from the processing chip; in response to the read-write synchronization signal, the received display data of the frame to be displayed and the corresponding drive timing are cached to the corresponding electrically connected memory in synchronization with the main processing chip In the frame address, the display data of the last frame to be displayed and the corresponding drive sequence buffered in the electrically connected memory are read and processed in synchronization with the main processing chip and then transmitted to the display panel.
  • the memory may include: Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM).
  • DDR SDRAM Double Data Rate Synchronous Dynamic Random Access Memory
  • the memory can also be other types of memory, which is not limited here.
  • the processing chip 100_m may include: a field programmable logic gate array chip (FPGA chip).
  • the FPGA chip in the processing chip 100_m may include: input interfaces RX1_m and RX2_m, a first input first output (FIFO) storage module 110_m, a timing generation module 120_m, a write memory controller 130_m, Read memory controller 140_m and output port 170_m.
  • the processing chip can also be other chips, which are not limited here.
  • the aforementioned FIFO storage module 110, timing generation module 120_m, write memory controller 130_m, and read memory controller 140_m may be implemented by software, hardware, firmware, or a combination thereof.
  • the input interfaces RX1_m and RX2_m are electrically connected to the signal receiving interface 400.
  • the input interfaces RX1_m and RX2_m may include: High Definition Multimedia Interface (HDMI).
  • HDMI 2.0 interface For example, HDMI 2.0 interface.
  • the input interfaces RX1_m and RX2_m can also be other interfaces that can realize the effects of the present disclosure, which are not limited here.
  • the FIFO storage module may be a FIFO memory, which may be a random access memory (RAM) inside the FPGA chip, which is used to store the display signals received by the input interfaces RX1_m and RX2_m.
  • the FIFO memory in the master processing chip is also used to generate a frame start synchronization signal according to the frame start signal, and provide it to the timing generation module 120_1 in each slave processing chip.
  • the structure of the FIFO memory can be basically the same as the existing structure and its variants, and will not be repeated here.
  • the timing generating module 120_m may include a timing generator for responding to the frame start synchronization signal and the corresponding frame start signal to synchronously generate the driving timing corresponding to the display data received by each processing chip 100_m.
  • the write memory controller 130_m may include a write direct memory access (WDMA) engine.
  • WDMA write direct memory access
  • the structure of the WDMA engine can be basically the same as the existing structure and its variants, and will not be repeated here.
  • the read memory controller 140_m may include a read direct memory access (RDMA) engine.
  • RDMA read direct memory access
  • the structure of the RDMA engine can be basically the same as the existing structure and its variants, which will not be repeated here.
  • the output port 170_m may include a V-By-One interface.
  • the structure of the V-By-One interface can be basically the same as the existing structure and its variants, and will not be repeated here.
  • the FPGA chip in the processing chip 100_m generally may also include: an AXI (Advanced eXtensible Interface) bus module 150_m and a data interaction module 160_m; wherein, the write memory controller 130_m can pass through the AXI bus module 150_m and The data interaction module 160_m performs data interaction with the memory 200_m. Further, the data interaction module 160_m can also be used to initialize the bottom storage in the memory 200_m. Among them, the structure of the AXI bus module 150_m and the data interaction module 160_m may be basically the same as the existing structure and its variants, and will not be repeated here.
  • AXI Advanced eXtensible Interface
  • the frame addresses stored in the memory 200_m are: frame address 0, frame address 1, and frame address 3 as an example for description.
  • the main processing chip 100_1 receives the display data and the frame start signal corresponding to the image area AA_1 in the first frame to be displayed through the input interfaces RX1_1 and RX2_1, and receives the display data corresponding to the image area AA_1 in the current frame to be displayed
  • the frame start signal is first stored in the FIFO storage module 110_1.
  • the processing chip 100_2 receives the display data and the frame start signal corresponding to the image area AA_2 in the first frame to be displayed through the input interfaces RX1_2 and RX2_2, and receives the display data corresponding to the image area AA_2 in the current frame to be displayed
  • the frame start signal is first stored in the FIFO storage module 110_2.
  • the FIFO storage module 110_1 generates a frame start synchronization signal FS_1 according to the frame start signal, and sends it to the timing generation module 120_1 of the master processing chip 100_1 and the timing generation module 120_2 of the slave processing chip 100_2.
  • the timing generating module 120_1 in the main processing chip 100_1 generates a driving timing corresponding to the display data received by the main processing chip 100_1 in response to the frame start synchronization signal FS_1 and the corresponding frame start signal.
  • the timing generation module 120_2 in the slave processing chip 100_2 synchronously generates the driving timing corresponding to the display data received from the processing chip 100_2 in response to the frame start synchronization signal FS_1 and the corresponding frame start signal.
  • the main processing chip 100_1 and the display data received from the processing chip 100_2 are processed synchronously, so that the display data in the two chips are aligned.
  • the write memory controller 130_1 in the main processing chip 100_1 receives the display data stored in the FIFO storage module 110_1 and the drive timing corresponding to the display data, generates a read and write synchronization signal DX_1, and sends the read and write synchronization signal DX_1 to the main processor
  • the write memory controller 130_1 in the main processing chip 100_1 buffers the received display data of the first frame to be displayed and the corresponding drive timing into the frame address 0 of the electrically connected memory 200_1 in response to the read and write synchronization signal DX_1, In response to the read and write synchronization signal DX_1, the display data of the last frame to be displayed and the corresponding driving sequence buffered in the memory 200_1 are read and processed, and then transmitted to the display panel 200 through the port 170_1. In addition, in response to the read and write synchronization signal DX_1, the slave memory write controller 130_2 in the processing chip 100_2 buffers the received display data of the first frame to be displayed and the corresponding drive timing to the frame address 0 of the electrically connected memory 200_2.
  • the display data of the last frame to be displayed and the corresponding driving sequence buffered in the memory 200_2 are read and processed, and then transmitted to the display panel 200 through the port 170_2. In this way, the display panel 200 can display the picture of the previous frame.
  • the main processing chip 100_1 receives the display data and the frame start signal corresponding to the image area AA_1 in the second frame to be displayed through the input interfaces RX1_1 and RX2_1, and combines the received frame image corresponding to the image area AA_1 in the current frame to be displayed
  • the display data and the frame start signal are first stored in the FIFO storage module 110_1.
  • the processing chip 100_2 receives the display data and the frame start signal corresponding to the image area AA_2 in the second frame to be displayed through the input interfaces RX1_2 and RX2_2, and receives the display data corresponding to the image area AA_2 in the current frame to be displayed
  • the frame start signal is first stored in the FIFO storage module 110_2.
  • the FIFO storage module 110_1 generates a frame start synchronization signal FS_2 according to the frame start signal, and sends it to the timing generation module 120_1 of the master processing chip 100_1 and the timing generation module 120_2 of the slave processing chip 100_2.
  • the timing generating module 120_1 in the main processing chip 100_1 generates a driving timing corresponding to the display data received by the main processing chip 100_1 in response to the frame start synchronization signal FS_2 and the corresponding frame start signal.
  • the timing generation module 120_2 in the slave processing chip 100_2 synchronously generates a driving timing corresponding to the display data received from the processing chip 100_2 in response to the frame start synchronization signal FS_2 and the corresponding frame start signal.
  • the main processing chip 100_1 and the display data received from the processing chip 100_2 are processed synchronously, so that the display data in the two chips are aligned.
  • the write memory controller 130_1 in the main processing chip 100_1 receives the display data stored in the FIFO storage module 110_1 and the drive timing corresponding to the display data, generates a read and write synchronization signal DX_2, and sends the read and write synchronization signal DX_2 to the main processor
  • the write memory controller 130_1 in the main processing chip 100_1 buffers the received display data of the second frame to be displayed and the corresponding drive timing into the frame address 1 of the electrically connected memory 200_1 in response to the read and write synchronization signal DX_2, In response to the read and write synchronization signal DX_2, the display data of the first frame to be displayed and the corresponding driving sequence buffered in the memory 200_1 are read and processed, and then transmitted to the display panel 200 through the port 170_1.
  • the slave write memory controller 130_2 in the processing chip 100_2 buffers the received display data of the second frame to be displayed and the corresponding drive timing to the frame address 1 of the electrically connected memory 200_2
  • the display data of the first frame to be displayed and the corresponding driving sequence buffered in the memory 200_2 are read and processed, and then transmitted to the display panel 200 through the port 170_2. In this way, the display panel 200 can display the first frame to be displayed.
  • the main processing chip 100_1 receives the display data and the frame start signal corresponding to the image area AA_1 in the third frame to be displayed through the input interfaces RX1_1 and RX2_1, and combines the received frame image corresponding to the image area AA_1 in the current frame to be displayed
  • the display data and the frame start signal are first stored in the FIFO storage module 110_1.
  • the processing chip 100_2 receives the display data and frame start signal corresponding to the image area AA_2 in the third frame to be displayed through the input interfaces RX1_2 and RX2_2, and receives the display data corresponding to the image area AA_2 in the current frame to be displayed
  • the frame start signal is first stored in the FIFO storage module 110_2.
  • the FIFO storage module 110_1 generates a frame start synchronization signal FS_3 according to the frame start signal, and sends it to the timing generation module 120_1 of the master processing chip 100_1 and the timing generation module 120_2 of the slave processing chip 100_2.
  • the timing generating module 120_1 in the main processing chip 100_1 generates a driving timing corresponding to the display data received by the main processing chip 100_1 in response to the frame start synchronization signal FS_3 and the corresponding frame start signal.
  • the timing generation module 120_2 in the slave processing chip 100_2 synchronously generates the driving timing corresponding to the display data received from the processing chip 100_2 in response to the frame start synchronization signal FS_3 and the corresponding frame start signal.
  • the main processing chip 100_1 and the display data received from the processing chip 100_2 are processed synchronously, so that the display data in the two chips are aligned.
  • the write memory controller 130_1 in the main processing chip 100_1 receives the display data stored in the FIFO storage module 110_1 and the drive timing corresponding to the display data, generates a read and write synchronization signal DX_3, and sends the read and write synchronization signal DX_3 to the main processor
  • the write memory controller 130_1 in the main processing chip 100_1 buffers the received display data of the third frame to be displayed and the corresponding drive timing into the frame address 2 of the electrically connected memory 200_1 in response to the read and write synchronization signal DX_3, In response to the read and write synchronization signal DX_2, the display data of the second frame to be displayed and the corresponding driving sequence buffered in the memory 200_1 are read and processed, and then transmitted to the display panel 200 through the port 170_1.
  • the slave write memory controller 130_2 in the processing chip 100_2 buffers the received display data of the third frame to be displayed and the corresponding drive timing to the frame address 2 of the electrically connected memory 200_2
  • the display data of the second frame to be displayed and the corresponding driving sequence buffered in the memory 200_2 are read and processed, and then transmitted to the display panel 200 through the port 170_1. In this way, the display panel 200 can display the second frame to be displayed. The same applies afterwards, and so on, so I won’t repeat them here.
  • the memory electrically connected to the main processing chip can buffer the frame address of the display data of the frame to be displayed currently and the memory electrically connected to each slave processing chip can buffer the frame address of the display data of the frame to be displayed currently the same. In this way, the frame address for reading the stored display data from the memory is also the same.
  • the memory electrically connected to the main processing chip can also buffer the frame address of the display data of the frame to be displayed currently and the memory electrically connected to each slave processing chip can buffer the display data of the frame to be displayed currently.
  • the frame addresses are not the same, which is not limited in the embodiment of the present disclosure.
  • an embodiment of the present disclosure further provides a display device.
  • the display device 500 includes a display panel 510 and a display driving device 520 provided by the embodiment of the present disclosure.
  • the display panel 510 is configured to receive the display data transmitted by the display driving device 520.
  • the display panel 510 includes, but is not limited to, a 4K (3840*2160) display panel, an 8K (7680*4320) display panel, and so on.
  • 4K 3840*2160
  • 8K 7680*4320
  • the display panel may be, for example, a liquid crystal display panel or an electroluminescence display panel, which is not limited herein.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display panel, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a display panel, a notebook computer, a digital photo frame, and a navigator.
  • Other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present disclosure.
  • the main processing chip buffers the received display data of the corresponding image area in the current frame to be displayed, it can generate a read-write synchronization signal and send the generated read-write synchronization signal to each slave processing chip.
  • the main processing chip and each slave processing chip are controlled by the read-write synchronization signal to buffer the received display data of the currently to-be-displayed frame into the frame address of the corresponding electrically connected memory, and compare the data buffered in the electrically connected memory.
  • the display data of a frame to be displayed is read and processed, and then transmitted to the display panel to drive the display panel to display the picture.
  • the main processing chip and each slave processing chip control the storage and reading operations of the memory through the read and write synchronization signal, it is possible to avoid sharing the frame address of the memory between the processing chips, so that the frame of the memory corresponding to a certain processing chip When the address changes, it will not affect the frame address of the memory corresponding to the other processing chips, so that the display data output by each processing chip can be guaranteed to belong to the same frame of screen, and the problem of abnormal screen display caused by asynchronization of multiple processing chips can be eliminated .

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