WO2020156239A1 - 光电二极管及其制备方法、电子设备 - Google Patents

光电二极管及其制备方法、电子设备 Download PDF

Info

Publication number
WO2020156239A1
WO2020156239A1 PCT/CN2020/072742 CN2020072742W WO2020156239A1 WO 2020156239 A1 WO2020156239 A1 WO 2020156239A1 CN 2020072742 W CN2020072742 W CN 2020072742W WO 2020156239 A1 WO2020156239 A1 WO 2020156239A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
amorphous silicon
electrode layer
facing away
semiconductor
Prior art date
Application number
PCT/CN2020/072742
Other languages
English (en)
French (fr)
Inventor
杜建华
李超
强朝辉
高宇鹏
关峰
黄睿
王治
吕杨
罗超
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/958,120 priority Critical patent/US11469336B2/en
Publication of WO2020156239A1 publication Critical patent/WO2020156239A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PIN type
    • H01L31/1055—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PIN type the devices comprising amorphous materials of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022466—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0232—Optical elements or arrangements associated with the device
    • H01L31/02327—Optical elements or arrangements associated with the device the optical elements being integrated or being directly associated to the device, e.g. back reflectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0376—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including amorphous semiconductors
    • H01L31/03762—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including amorphous semiconductors including only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1884—Manufacture of transparent electrodes, e.g. TCO, ITO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells

Definitions

  • the present disclosure relates to the field of photoelectric conversion technology, and in particular to a photodiode and a preparation method thereof, and an electronic device containing the photodiode.
  • a photodiode is a semiconductor device that converts received optical signals into electrical signals. At present, when the photodiode is working, part of the light received by the photodiode is reflected, resulting in low conversion efficiency of the photodiode.
  • the present disclosure provides a photodiode, including:
  • the semiconductor structure includes:
  • a first semiconductor layer provided on the surface of the first electrode layer
  • one of the first semiconductor film layer and the second semiconductor layer is a P-type semiconductor layer, and the other is an N-type semiconductor layer.
  • the first semiconductor layer includes an N-type amorphous silicon layer
  • the second semiconductor layer includes a P-type amorphous silicon layer
  • the P-type amorphous silicon layer faces away from the surface of the first electrode layer.
  • the surface has the first uneven structure.
  • the first semiconductor layer includes a P-type amorphous silicon layer
  • the second semiconductor layer includes an N-type amorphous silicon layer
  • the N-type amorphous silicon layer faces away from the first electrode layer.
  • the surface has the first uneven structure.
  • the semiconductor structure further includes an intrinsic amorphous silicon layer disposed between the N-type amorphous silicon layer and the P-type amorphous silicon layer.
  • the semiconductor structure further includes an intrinsic amorphous silicon layer
  • the first semiconductor layer includes a P-type amorphous silicon layer
  • the intrinsic amorphous silicon layer is located on a surface of the P-type amorphous silicon layer facing away from the first electrode layer, and the intrinsic amorphous silicon layer
  • the surface of the crystalline silicon layer facing away from the first electrode layer has a third uneven structure formed by crystallizing the amorphous silicon on the surface;
  • the second semiconductor layer includes an N-type metal oxide semiconductor layer disposed on the surface of the intrinsic amorphous silicon layer facing away from the first electrode layer, and the N-type metal oxide semiconductor layer facing away from the first electrode layer.
  • the surface of the first electrode layer has the first uneven structure.
  • the semiconductor structure further includes an intrinsic amorphous silicon layer
  • the first semiconductor layer includes an N-type metal oxide semiconductor layer, and the intrinsic amorphous silicon layer is located on a surface of the N-type metal oxide semiconductor layer facing away from the first electrode layer;
  • the second semiconductor layer includes a P-type amorphous silicon layer disposed on the surface of the intrinsic amorphous silicon layer facing away from the first electrode layer, and the P-type amorphous silicon layer facing away from the first electrode layer
  • the surface of an electrode layer has the first uneven structure formed by crystallizing amorphous silicon on the surface.
  • the semiconductor structure further includes an intrinsic amorphous silicon layer
  • the first semiconductor layer includes an N-type metal oxide semiconductor layer
  • the intrinsic amorphous silicon layer is located on the surface of the N-type metal oxide semiconductor layer facing away from the first electrode layer, and the intrinsic amorphous silicon layer
  • the surface of the amorphous silicon layer facing away from the first electrode layer has a third uneven structure formed by crystallizing the amorphous silicon on the surface;
  • the second semiconductor layer includes a P-type amorphous silicon layer disposed on the surface of the intrinsic amorphous silicon layer facing away from the first electrode layer, and the P-type amorphous silicon layer facing away from the first electrode layer
  • the surface of an electrode layer has the first uneven structure.
  • the first concave-convex structure, the second concave-convex structure and the third concave-convex structure have substantially the same profile.
  • the height of the protrusions in the first concavo-convex structure, the second concavo-convex structure and the third concavo-convex structure in a direction perpendicular to the surface of the first electrode layer in contact with the semiconductor structure is 30 nm to 80 nm, which is parallel to
  • the maximum width in the direction of the surface of the first electrode layer in contact with the semiconductor structure is 0.1 ⁇ m to 0.5 ⁇ m, and the distance between adjacent protrusions is 0.1 ⁇ m to 0.4 ⁇ m.
  • the second electrode layer is a transparent electrode layer.
  • the present disclosure also provides an electronic device including the photodiode described in any one of the above.
  • the present disclosure also provides a method for manufacturing a photodiode, including:
  • a second electrode layer is deposited on the surface of the semiconductor structure facing away from the first electrode layer, wherein a second concave-convex structure is formed on the surface of the second electrode layer facing away from the first electrode layer.
  • the step of preparing a semiconductor structure on the surface of the first electrode layer includes:
  • one of the first semiconductor layer and the second semiconductor layer is a P-type semiconductor layer, and the other is an N-type semiconductor layer.
  • the step of preparing the first semiconductor layer and the second semiconductor layer includes:
  • the surface of the second semiconductor layer facing away from the first electrode layer is irradiated with a laser to crystallize the surface of the second semiconductor layer facing away from the first electrode layer to form the first uneven structure.
  • the method further includes preparing an intrinsic amorphous silicon layer, the intrinsic amorphous silicon layer being between the N-type amorphous silicon layer and the P-type amorphous silicon layer.
  • the step of preparing the first semiconductor layer and the second semiconductor layer includes:
  • An N-type metal oxide semiconductor layer is deposited on the surface of the intrinsic amorphous silicon layer facing away from the first electrode layer, and the N-type metal oxide semiconductor layer is facing away from the surface of the first electrode layer
  • the first concave-convex structure is formed thereon.
  • the step of preparing the first semiconductor layer and the second semiconductor layer includes:
  • a P-type amorphous silicon layer is deposited on the surface of the intrinsic amorphous silicon layer facing away from the first electrode layer, and a laser is used to irradiate the P-type amorphous silicon layer facing away from the first electrode layer. On the surface, the P-type amorphous silicon layer is crystallized away from the surface of the first electrode layer to form the first uneven structure.
  • the step of preparing the first semiconductor layer and the second semiconductor layer includes:
  • An intrinsic amorphous silicon layer is prepared on the surface of the N-type metal oxide semiconductor layer facing away from the first electrode layer, and a laser is used to irradiate the intrinsic amorphous silicon layer facing away from the first electrode layer. Surface, crystallizing the intrinsic amorphous silicon layer facing the surface of the first electrode layer to form a third uneven structure; and
  • a P-type amorphous silicon layer is deposited on the surface of the intrinsic amorphous silicon layer facing away from the first electrode layer, and the P-type amorphous silicon layer is formed on the surface facing away from the first electrode layer
  • the first concave-convex structure is deposited on the surface of the intrinsic amorphous silicon layer facing away from the first electrode layer, and the P-type amorphous silicon layer is formed on the surface facing away from the first electrode layer.
  • the step of preparing the P-type amorphous silicon layer, the intrinsic amorphous silicon layer, the N-type metal oxide semiconductor layer, and the second electrode layer includes:
  • a stacked P-type amorphous silicon film and an intrinsic amorphous silicon film are sequentially formed, and a laser is used to irradiate the intrinsic amorphous silicon film facing away from the first electrode layer.
  • a laser is used to irradiate the intrinsic amorphous silicon film facing away from the first electrode layer.
  • a stacked N-type metal oxide semiconductor film and a second electrode layer film are sequentially deposited, and simultaneously the N-type metal oxide semiconductor film Patterning with the second electrode layer film to form the N-type metal oxide semiconductor layer and the second electrode layer;
  • the P-type amorphous silicon film and the intrinsic amorphous silicon film are etched to form the P-type amorphous silicon film.
  • a crystalline silicon layer and the intrinsic amorphous silicon layer are etched to form the P-type amorphous silicon film.
  • the surface to be crystallized is washed with an acid solution; and/or after the surface of the semiconductor layer is crystallized, the surface to be crystallized is washed with an acid solution.
  • the second electrode layer is a transparent electrode layer.
  • FIG. 1 is a schematic diagram of the structure of a photodiode according to an embodiment of the present disclosure.
  • FIGS. 2a-2e are schematic diagrams of the structure prepared by each step in the method for preparing a photodiode according to an embodiment of the present disclosure.
  • 3 is a transmission electron microscope image of the surface of the semiconductor layer after the surface of the semiconductor layer is crystallized in the method according to an embodiment of the present disclosure.
  • 4a-4b are scanning electron micrographs of the transparent electrode layer surface before and after acid etching the transparent electrode layer surface of the photodiode in the related art.
  • the photodiode mainly includes: a semiconductor structure; and a first electrode and a second electrode respectively provided on two opposite surfaces of the semiconductor structure. At least one of the first electrode and the second electrode is a transparent electrode and serves as a window layer for receiving light.
  • the working principle of the photodiode is: light enters the photodiode through the transparent electrode of the photodiode, the photodiode converts the received light signal into an electrical signal, and then outputs the electrical signal through the two electrodes of the photodiode.
  • the surface of the transparent electrode for receiving light is generally a substantially flat surface, so light is easily reflected by the flat surface when it is directed to the transparent electrode, resulting in low photoelectric conversion efficiency of the photodiode.
  • an acid solution is usually used to etch the surface of the transparent electrode for receiving light, so that the surface is uneven, thereby playing an anti-reflection effect.
  • this method has poor controllability of the microstructure, is more destructive to the electrode film, and easily adversely affects the performance of the photoelectric conversion diode.
  • the present disclosure provides a photodiode, a manufacturing method thereof, and an electronic device including the photodiode, which solves the problem of low photoelectric conversion efficiency of the photodiode.
  • a photodiode including a first electrode layer and a semiconductor structure arranged in a stack; and a second electrode layer arranged on a surface of the semiconductor structure facing away from the first electrode layer, wherein The surface of the semiconductor structure facing away from the first electrode layer has a first uneven structure, and the surface of the second electrode layer facing away from the first electrode layer has a second uneven structure.
  • the second electrode layer is a transparent electrode layer.
  • the visible light transmittance of the transparent electrode layer is 70% or more.
  • the transparent electrode layer is thick In the case of an ITO layer, the transmittance of 400nm visible light is 70% or more.
  • the light when external light is received through the transparent electrode layer, the light enters the photodiode from the surface with the second concave-convex structure, which reduces the reflection effect of the transparent electrode layer on the light;
  • the surface of the semiconductor structure receiving light is formed with a first uneven structure, so that when light enters the semiconductor structure through the surface with the first uneven structure, the reflection effect of the semiconductor structure on the light is further reduced. Therefore, according to the above-mentioned embodiments of the present disclosure, the reflection of light from the transparent electrode layer and the semiconductor structure can be effectively reduced, so that the light can be incident to the semiconductor structure to the maximum, thereby improving the conversion efficiency of the photodiode.
  • the above-mentioned embodiments according to the present disclosure avoid etching the surface of the transparent electrode layer for receiving light by using an acid solution in the related art, thereby avoiding damage to the electrode layer caused by acid solution etching. , And adverse effects on the performance of photoelectric conversion diodes.
  • an embodiment of the present disclosure provides a photodiode, including: a first electrode layer 41 and a semiconductor structure 2 arranged in a stack; and a photodiode arranged on the semiconductor structure 2 facing away from the first electrode layer 41
  • a photodiode including: a first electrode layer 41 and a semiconductor structure 2 arranged in a stack; and a photodiode arranged on the semiconductor structure 2 facing away from the first electrode layer 41
  • the surface of the semiconductor structure 2 facing away from the first electrode layer 41 has a first uneven structure 31
  • the surface of the transparent electrode layer 42 facing away from the first electrode layer 41 has a second uneven structure 32.
  • the first electrode layer 41 can be formed on the substrate 1, and then the semiconductor structure 2 is prepared on the surface of the first electrode layer 41 facing away from the substrate 1, and the semiconductor structure 2 is facing away from the first electrode.
  • the first uneven structure 31 is formed on the surface of the layer 41, and finally a transparent electrode layer 42 is formed on the surface of the semiconductor structure 2 where the first uneven structure 31 is formed, so that the transparent electrode layer 42 faces away from the surface of the first electrode layer 41.
  • the first electrode layer 41 can optionally be a non-transparent electrode.
  • the size of the semiconductor structure 2 and the first concave-convex structure 31 formed thereon can be set according to actual needs.
  • the size of the semiconductor structure 2 is set so that its orthographic projection on the substrate 1 is surrounded by the orthographic projection of the first electrode layer 41 on the substrate 1.
  • the size of the first concave-convex structure 31 is set to completely cover the surface of the semiconductor structure 2 facing away from the first electrode layer 41.
  • the size of the transparent electrode layer 42 can also be set according to actual needs. For example, the size of the transparent electrode layer 42 is set to completely cover the first uneven structure 31, or the size of the transparent electrode layer 42 is set to cover a part of the first uneven structure 31.
  • the photodiode of the above embodiment When the photodiode of the above embodiment is in operation, light enters the photodiode from the surface of the transparent electrode layer 42 with the second uneven structure 32, and enters the semiconductor structure 2 through the surface of the semiconductor structure 2 with the first uneven structure 31 After the semiconductor structure 2 converts the received light into an electrical signal, the electrical signal is output through the two electrodes of the photodiode.
  • the first concave-convex structure 31 is formed on the surface of the semiconductor structure 2 facing away from the first electrode layer 41, and
  • the surface of the transparent electrode layer 42 facing away from the first electrode layer 41 forms the second concave-convex structure 32, which reduces the reflection effect of the transparent electrode layer 42 and the semiconductor structure 2 on light. Therefore, the photodiode provided by the embodiments of the present disclosure can maximize the incidence of light into the semiconductor structure 2, thereby improving the photoelectric conversion efficiency of the photodiode.
  • the embodiments of the present disclosure avoid damage to the electrode layer caused by etching the transparent electrode layer with an acid solution in the related art.
  • the aforementioned semiconductor structure 2 may specifically include: a first semiconductor layer disposed on the surface of the first electrode layer; and a second semiconductor layer disposed on the surface of the first semiconductor layer facing away from the first electrode layer .
  • the surface of the second semiconductor layer facing away from the first electrode layer has a first uneven structure, and one of the first semiconductor layer and the second semiconductor layer is a P-type semiconductor layer, and the other is an N-type semiconductor layer .
  • the above-mentioned semiconductor structure 2 may specifically include the following two structures.
  • the first structure is that the semiconductor structure 2 includes a P-type semiconductor layer provided on the surface of the first electrode layer, and an N-type semiconductor layer provided on the surface of the P-type semiconductor layer facing away from the first electrode layer.
  • the second structure is that the semiconductor structure 2 includes an N-type semiconductor layer disposed on the surface of the first electrode layer, and a P-type semiconductor layer disposed on the surface of the N-type semiconductor layer facing away from the first electrode layer.
  • the above-mentioned semiconductor structure 2 is provided to include an N-type semiconductor layer and a P-type semiconductor layer, so that the semiconductor structure 2 is formed with a PN junction. Moreover, in order to facilitate receiving incident light, the area of the PN junction can be made as large as possible. After light (ie, photons carrying energy) enters the PN junction through the transparent electrode layer of the photodiode, the energy can be transferred to the bound electrons on the covalent bond in the PN junction, so that part of the electrons break free from the covalent bond, thereby generating electrons-empty Acupoint pairs, they participate in drifting motion under the action of reverse voltage, which makes the reverse current obviously increase. The greater the intensity of light, the greater the reverse current generated.
  • the first semiconductor layer includes a P-type amorphous silicon layer
  • the second semiconductor layer includes an N-type amorphous silicon layer
  • the surface of the N-type amorphous silicon layer facing away from the first electrode layer has a first uneven structure.
  • a P-type amorphous silicon layer may be prepared on the surface of the first electrode layer; then, an N-type amorphous silicon layer may be prepared on the surface of the P-type amorphous silicon layer facing away from the first electrode layer.
  • the amorphous silicon layer is irradiated with a laser on the surface of the N-type amorphous silicon layer facing away from the first electrode layer, so that the surface of the N-type amorphous silicon layer facing away from the first electrode layer is crystallized to form a first uneven structure.
  • the first semiconductor layer includes an N-type amorphous silicon layer
  • the second semiconductor layer includes a P-type amorphous silicon layer
  • the surface of the P-type amorphous silicon layer facing away from the first electrode layer has a first uneven structure.
  • an N-type amorphous silicon layer may be prepared on the surface of the first electrode layer; then, a P-type amorphous silicon layer may be prepared on the surface of the N-type amorphous silicon layer facing away from the first electrode layer.
  • the surface of the P-type amorphous silicon layer facing away from the first electrode layer is irradiated with a laser to crystallize the surface of the P-type amorphous silicon layer facing away from the first electrode layer to form a first uneven structure.
  • an amorphous silicon film may be formed first, and then the amorphous silicon film may be doped accordingly to form the corresponding P-type amorphous silicon layer or N-type amorphous silicon layer.
  • the surface of the P-type amorphous silicon layer or the N-type amorphous silicon layer irradiated by the laser can form regularly arranged bumps. That is, the first concavo-convex structure, whereby the P-type amorphous silicon layer or the N-type amorphous silicon layer is formed as a film layer with anti-reflection effect.
  • the embodiments of the present disclosure perform laser crystallization on the surface of the P-type amorphous silicon layer or the N-type amorphous silicon layer, so that the P-type amorphous silicon layer or the N-type amorphous silicon layer has an anti-reflection effect. It is necessary to increase the patterning process to avoid damage to the semiconductor structure, thereby ensuring the performance of the photodiode.
  • the semiconductor structure according to an embodiment of the present disclosure may further include an intrinsic amorphous silicon layer disposed between the N-type amorphous silicon layer and the P-type amorphous silicon layer.
  • an intrinsic amorphous silicon layer is provided between the N-type amorphous silicon layer and the P-type amorphous silicon layer, so that the semiconductor structure is formed as a PIN node.
  • the photodiode adopts the semiconductor structure 2 of this structure, it has the advantages of small junction capacitance, short transit time, and high sensitivity.
  • the intrinsic amorphous silicon layer is generally an N-type semiconductor layer with a low doping concentration (for example, an N-type amorphous silicon layer).
  • the intrinsic semiconductor layer introduced in the PN junction increases the thickness in the direction perpendicular to the surface of the first electrode layer 41 in contact with the semiconductor structure 2.
  • the N-type amorphous silicon layer and the P-type amorphous silicon layer located on both sides of the intrinsic semiconductor layer are thinner in the direction perpendicular to the surface of the first electrode layer in contact with the semiconductor structure 2 and absorb incident light in a small proportion. Therefore, the influence of diffusion movement is reduced, and the response speed of the photodiode is improved.
  • the semiconductor structure 2 provided by the above embodiments further includes an intrinsic amorphous silicon layer 21. Therefore, the first semiconductor layer 2 includes a stacked P-type amorphous silicon layer 20, an intrinsic amorphous silicon layer 21, and an N-type amorphous silicon layer 22.
  • the intrinsic amorphous silicon layer 21 is located on the surface of the P-type amorphous silicon layer 20 facing away from the first electrode layer 41, and the intrinsic amorphous silicon layer 21 is crystallized away from the surface layer 211 of the first electrode layer 41 to form a third Concave-convex structure 33.
  • the second semiconductor layer includes an N-type metal oxide semiconductor layer 22 disposed on the surface of the intrinsic amorphous silicon layer 21 facing away from the first electrode layer 41, and the surface of the N-type metal oxide semiconductor layer 22 facing away from the first electrode layer 41 There is a first concave-convex structure 31.
  • the first concave-convex structure 31 has substantially the same contour as the third concave-convex structure 33.
  • the semiconductor structure 2 includes a P-type amorphous silicon layer 20, an intrinsic amorphous silicon layer 21, and an N-type metal oxide semiconductor layer 22 that are sequentially stacked and disposed on the first electrode layer 41
  • the laser can be used to irradiate the present
  • the surface of the intrinsic amorphous silicon layer 21 facing away from the first electrode layer 41 is crystallized to form the third uneven structure 33.
  • a thinner P-type amorphous silicon layer with grain boundary protrusions 210 is formed on the surface layer 211 of the intrinsic amorphous silicon layer facing away from the first electrode layer 41.
  • an N-type metal oxide semiconductor layer 22 is deposited on the surface of the P-type amorphous silicon layer facing away from the first electrode layer 41, so that the formed N-type metal oxide semiconductor layer 22 faces away from the surface of the first electrode layer 41.
  • the surface has a first uneven structure 31.
  • a transparent electrode layer 42 is formed on the surface of the N-type metal oxide semiconductor layer facing away from the first electrode layer 41, so that the formed transparent electrode layer 42 has a second uneven structure 32 on the surface facing away from the first electrode layer 41.
  • the above-mentioned embodiments of the present disclosure reduce the reflection of incident light by forming uneven structures on the surfaces of the intrinsic amorphous silicon layer 21, the N-type metal oxide semiconductor layer 22 and the transparent electrode layer 42. Therefore, the above-mentioned embodiments of the present disclosure can further effectively improve the photoelectric conversion efficiency of the photodiode, and enable the photodiode to achieve a higher signal-to-noise ratio. In addition, the above-mentioned embodiments of the present disclosure realize multiple ways of reducing the reflection of incident light without adding additional patterning processes, and will not cause damage to the semiconductor structure 2.
  • the semiconductor structure further includes an intrinsic amorphous silicon layer, wherein the first semiconductor layer includes an N-type metal oxide semiconductor layer, and the intrinsic amorphous silicon layer is located opposite to the N-type metal oxide semiconductor layer.
  • the surface of the first electrode layer; the second semiconductor layer includes a P-type amorphous silicon layer disposed on the surface of the intrinsic amorphous silicon layer facing away from the first electrode layer, and the P-type amorphous silicon layer facing away from the surface of the first electrode layer It has a first concave-convex structure.
  • an N-type metal oxide semiconductor layer may be prepared on the surface of the first electrode layer, and then prepared on the surface of the N-type metal oxide semiconductor layer facing away from the first electrode layer.
  • An intrinsic amorphous silicon layer, a P-type amorphous silicon layer is prepared on the surface of the intrinsic amorphous silicon layer facing away from the first electrode layer, and a laser is used to irradiate the P-type amorphous silicon layer facing away from the first electrode layer
  • the P-type amorphous silicon layer is crystallized against the surface of the first electrode layer to form regularly arranged protrusions, that is, the first uneven structure.
  • the P-type amorphous silicon layer is formed as a film layer with anti-reflection effect
  • the transparent electrode layer formed on the surface of the P-type amorphous silicon layer facing away from the first electrode layer also has a concave-convex structure with the same or similar contours, namely the first The two concavo-convex structure, so the transparent electrode layer also has an anti-reflection effect.
  • the above method of laser crystallization on the surface of the P-type amorphous silicon layer, so that the P-type amorphous silicon layer has an anti-reflection effect, does not need to increase the patterning process, and will not damage the semiconductor structure, thereby ensuring the photodiode Performance.
  • the embodiments of the present disclosure also provide an electronic device including the photodiode of any of the above embodiments.
  • the electronic device provided in the embodiments of the present disclosure includes the light-emitting diode provided in any of the foregoing embodiments, and therefore the electronic device also has the foregoing beneficial effects, which will not be repeated here.
  • the embodiment of the present disclosure also provides a method for preparing a photodiode, which is used to prepare the photodiode provided in any of the above embodiments, as shown in FIGS. 2a to 2e, the method includes:
  • a transparent electrode layer 42 is deposited on the surface of the semiconductor structure 2 facing away from the first electrode layer 41, wherein the transparent electrode layer 42 has a second uneven structure 32 formed on the surface facing away from the first electrode layer 41.
  • a conductive material may be used to prepare the first electrode layer 41 on the substrate 1 first.
  • the degree of transparency of the first electrode layer 41 is not limited.
  • the semiconductor structure 2 is prepared on the surface of the first electrode layer 41, and the first uneven structure 31 is formed on the surface of the semiconductor structure 2 facing away from the first electrode layer 41.
  • the size of the semiconductor structure 2 and the first concave-convex structure 31 formed thereon can be set according to actual needs.
  • a transparent electrode layer 42 is prepared on the surface of the semiconductor structure 2 where the first uneven structure 31 is formed.
  • the transparent electrode layer 42 will continue the contour of the first uneven structure to form an uneven structure, that is, the transparent electrode layer 42 faces away from the first electrode layer.
  • the surface of 41 can form the second uneven structure 32.
  • the size of the transparent electrode layer 42 can also be set according to actual needs.
  • the first concave-convex structure 31 is formed on the surface of the semiconductor structure 2 facing away from the first electrode layer 41, and the first concave-convex structure 31 is formed on the surface of the semiconductor structure 2
  • the transparent electrode layer 42 can form the second concavo-convex structure 32.
  • the transparent electrode layer 42 receives external light, the reflection effect of the transparent electrode layer 42 and the semiconductor structure 2 on the light is reduced. Therefore, the photodiode provided by the embodiment of the present disclosure enables light to be incident to the semiconductor structure 2 to the maximum, thereby improving the conversion efficiency of the photodiode.
  • the method for preparing a photodiode in the embodiments of the present disclosure is a non-destructive solution.
  • the step of preparing a semiconductor structure on the surface of the first electrode layer specifically includes:
  • a second semiconductor layer is prepared on the surface of the first semiconductor layer facing away from the first electrode layer, and a first uneven structure is formed on the surface of the second semiconductor layer facing away from the first electrode layer.
  • one of the first semiconductor layer and the second semiconductor layer is a P-type semiconductor layer, and the other is an N-type semiconductor layer.
  • the semiconductor structure prepared by the above method includes the following two structures.
  • the semiconductor structure includes a P-type semiconductor layer disposed on the surface of the first electrode layer, and an N-type semiconductor layer disposed on the surface of the P-type semiconductor layer facing away from the first electrode layer.
  • the semiconductor structure includes an N-type semiconductor layer disposed on the surface of the first electrode layer, and a P-type semiconductor layer disposed on the surface of the N-type semiconductor layer facing away from the first electrode layer.
  • the above-mentioned semiconductor structure is arranged to include an N-type semiconductor layer and a P-type semiconductor layer, so that the semiconductor structure is formed as a PN junction.
  • the semiconductor structure After the light enters the PN junction through the transparent electrode layer of the photodiode, energy can be transferred to the bound electrons on the covalent bond in the PN junction, so that some electrons break away from the covalent bond, thereby generating electron-hole pairs. They participate in drifting motion under the action of reverse voltage, which makes the reverse current significantly larger. The greater the intensity of light, the greater the reverse current generated.
  • the steps of preparing the first semiconductor layer and the second semiconductor layer may specifically include: preparing an N-type amorphous silicon layer on the surface of the first electrode layer; and placing the N-type amorphous silicon layer facing away from the second semiconductor layer.
  • a P-type amorphous silicon layer is prepared on the surface of an electrode layer, and the surface of the P-type amorphous silicon layer facing away from the first electrode layer is irradiated with a laser so that the P-type amorphous silicon layer facing away from the surface of the first electrode layer Crystallizing to form the first uneven structure.
  • the steps of preparing the first semiconductor layer and the second semiconductor layer may specifically include: preparing a P-type amorphous silicon layer on the surface of the first electrode layer; An N-type amorphous silicon layer is prepared on the surface of the first electrode layer, and the surface of the N-type amorphous silicon layer facing away from the first electrode layer is irradiated with a laser to crystallize the N-type amorphous silicon layer facing away from the surface of the first electrode layer , To form a first concave-convex structure.
  • an amorphous silicon film may be formed first, and then the amorphous silicon film may be doped accordingly to form the corresponding P-type amorphous silicon layer and N-type amorphous silicon layer.
  • the surface of the P-type amorphous silicon layer or the N-type amorphous silicon layer irradiated by the laser can form regularly arranged bumps. That is, the first concavo-convex structure allows the P-type amorphous silicon layer or the N-type amorphous silicon layer to be formed as a film layer with anti-reflection effect.
  • the surface of the P-type amorphous silicon layer or the N-type amorphous silicon layer is crystallized by laser irradiation, so that the P-type amorphous silicon layer or the N-type amorphous silicon layer has an anti-reflection effect.
  • the method does not need to increase the patterning process and will not damage the semiconductor structure, thereby ensuring the working performance of the photodiode.
  • the preparation method according to the embodiment of the present disclosure may further include preparing an intrinsic amorphous silicon layer between the N-type amorphous silicon layer and the P-type amorphous silicon layer.
  • the intrinsic amorphous silicon layer is generally an N-type amorphous silicon layer with a low doping concentration.
  • the amorphous silicon layer may be formed first, and then low-concentration ion doping is performed on it to form the intrinsic amorphous silicon layer.
  • an intrinsic amorphous silicon layer is provided between the N-type amorphous silicon layer and the P-type amorphous silicon layer, so that the semiconductor structure is formed as a PIN node.
  • the photodiode adopts the semiconductor structure of this structure, it has the advantages of small junction capacitance, short transit time, and high sensitivity.
  • the step of preparing the first semiconductor layer and the second semiconductor layer may further specifically include:
  • a P-type amorphous silicon layer is deposited on the surface of the intrinsic amorphous silicon layer facing away from the first electrode layer, and the surface of the P-type amorphous silicon layer facing away from the first electrode layer is irradiated with a laser to make the P-type amorphous silicon layer
  • the surface of the layer facing away from the first electrode layer is crystallized to form a first uneven structure.
  • an N-type metal oxide semiconductor layer can be prepared on the surface of the first electrode layer;
  • An intrinsic amorphous silicon layer, a P-type amorphous silicon layer is prepared on the surface of the intrinsic amorphous silicon layer facing away from the first electrode layer, and a laser is used to irradiate the P-type amorphous silicon layer facing away from the first electrode layer
  • the P-type amorphous silicon layer is crystallized against the surface of the first electrode layer to form regularly arranged protrusions, that is, the first uneven structure.
  • the P-type amorphous silicon layer is formed as a film layer with anti-reflection effect, and the transparent electrode layer formed on the surface of the P-type amorphous silicon layer facing away from the first electrode layer continues to form the same or similar uneven structure, thus the transparent electrode The layer also has an anti-reflection effect.
  • the above method of laser crystallization on the surface of the P-type amorphous silicon layer, so that the P-type amorphous silicon layer has an anti-reflection effect, does not need to increase the patterning process, and will not damage the semiconductor structure, thereby ensuring the photodiode Performance.
  • the step of preparing the first semiconductor layer and the second semiconductor layer may further specifically include:
  • An intrinsic amorphous silicon layer 21 is prepared on the surface of the P-type amorphous silicon layer 20 facing away from the first electrode layer 41, and the surface of the intrinsic amorphous silicon layer 21 facing away from the first electrode layer 41 is irradiated with a laser to make the intrinsic amorphous silicon layer
  • the surface of the amorphous silicon layer 21 facing away from the first electrode layer 41 is crystallized;
  • N-type metal oxide semiconductor layer 22 is deposited on the surface of the intrinsic amorphous silicon layer 21 facing away from the first electrode layer 41, and a first electrode layer 41 is formed on the surface of the N-type metal oxide semiconductor layer 22 facing away from the first electrode layer 41.
  • the semiconductor structure 2 includes a P-type amorphous silicon layer 20, an intrinsic amorphous silicon layer 21, and an N-type metal oxide semiconductor layer 22 that are sequentially stacked and arranged on the first electrode layer 41
  • laser irradiation may be used first.
  • the surface of the intrinsic amorphous silicon layer 21 facing away from the first electrode layer 41 is crystallized on the surface of the intrinsic amorphous silicon layer 21 facing away from the first electrode layer 41.
  • a thinner P-type amorphous silicon layer with grain boundary protrusions 210 is formed on the surface of the intrinsic amorphous silicon layer facing away from the first electrode layer 41, and the P-type amorphous silicon layer facing away from the first electrode layer 41 Regularly arranged bumps 210 are formed on the surface.
  • an N-type metal oxide semiconductor layer 22 is deposited on the surface of the P-type amorphous silicon layer facing away from the first electrode layer 41, so that the formed N-type metal oxide semiconductor layer 22 can continue the P-type amorphous silicon layer.
  • the shape of the protrusions 210 makes the N-type metal oxide semiconductor layer 22 have the first uneven structure 31 on the surface facing away from the first electrode layer 41.
  • a transparent electrode layer 42 is formed on the surface of the N-type metal oxide semiconductor layer 22 facing away from the first electrode layer 41, so that the formed transparent electrode layer 42 is facing away from the surface of the first electrode layer 41 and continues the first uneven structure 31.
  • a second uneven structure 32 is formed.
  • the first concave-convex structure 31 and the second concave-convex structure have the same or similar convex contours.
  • the formed thinner P-type amorphous silicon layer with grain boundary protrusions 210 has a lower light absorption coefficient than that of the intrinsic amorphous silicon layer, so the formation is thinner.
  • the P-type amorphous silicon layer with grain boundary protrusions 210 will not increase the attenuation of incident light, which is more conducive to increasing the amount of incident light.
  • the above-mentioned preparation method according to the embodiment of the present disclosure performs laser crystallization on the surface of the intrinsic amorphous silicon layer 21 to form regularly arranged protrusions 210, thereby causing the N-type metal oxide semiconductor layer 22 to face away from the first
  • the first uneven structure 31 is continuously formed on the surface of an electrode layer 41
  • the second uneven structure 32 is continuously formed on the surface of the transparent electrode layer 42 facing away from the first electrode layer 41, thereby realizing the intrinsic amorphous silicon layer 21
  • the surfaces of the N-type metal oxide semiconductor layer 22 and the transparent electrode layer 42 for receiving light are all uneven and function as an anti-reflection layer for incident light.
  • the embodiments of the present disclosure can effectively improve the photoelectric conversion efficiency of the photodiode, so that the photodiode can achieve a higher signal-to-noise ratio. Moreover, the above-mentioned way of realizing the function of the incident light anti-reflection layer does not need to increase the patterning process, and will not cause damage to the semiconductor structure 2, thereby ensuring the working performance of the photodiode.
  • the preparation method provided in the embodiments of the present disclosure is not only applicable to photodiodes with metal oxide heterojunctions, but also applicable to conventional photodiodes that only include amorphous silicon homojunctions.
  • the surface of the film to be crystallized can be cleaned with an acid solution (for example, low-concentration hydrofluoric acid) to ensure the crystallization effect.
  • an acid solution for example, low-concentration hydrofluoric acid
  • the surface of the crystallized film layer can also be cleaned with an acid solution to remove impurities generated during the crystallization process.
  • silicon oxide SiO x , where 0 ⁇ x ⁇ 2
  • SiO x silicon oxide
  • the intrinsic amorphous silicon layer is crystallized with an acid solution
  • Cleaning the surface of the silicon oxide can remove the generated silicon oxide SiO x , which is more conducive to ensuring a good crystallization effect.
  • the size of the protrusion 210 generated on the crystallized surface of the film can be controlled by adjusting the speed and energy density of laser irradiation.
  • the height of the generated bump 210 in the direction perpendicular to the contact surface of the first electrode layer 41 and the semiconductor layer 2 may be 30 nm to 80 nm, and the bump 210 is parallel to the contact between the first electrode layer 41 and the semiconductor layer 2.
  • the maximum width in the direction of the surface may be 0.1 ⁇ m to 0.5 ⁇ m, and the distance between adjacent protrusions 210 may be 0.1 ⁇ m to 0.4 ⁇ m.
  • the above steps of preparing the P-type amorphous silicon layer 20, the intrinsic amorphous silicon layer 21, the N-type metal oxide semiconductor layer 22 and the transparent electrode layer 42 specifically include the following steps.
  • a P-type amorphous silicon film 70 and an intrinsic amorphous silicon film 80 are formed in order on the surface of the first electrode layer 41.
  • the surface of the intrinsic amorphous silicon film 80 facing away from the first electrode layer 41 is irradiated with a laser 90.
  • the intrinsic amorphous silicon film 80 is crystallized against the surface of the first electrode layer 41 to form the third uneven structure 33.
  • the straight line between the intrinsic amorphous silicon film 80 and the protrusion 210 represents a schematic cross-sectional line of the interface between the crystallized and non-crystallized semiconductor layer. In practice, the cross-section of the interface is not linear, and it is just an illustration here.
  • the third uneven structure 33 formed on the surface of the intrinsic layer by the crystallization method of the embodiment of the present disclosure has uniform protrusions.
  • the N-type semiconductor layer oxide semiconductor layer or amorphous silicon semiconductor layer
  • the P-type semiconductor layer can form uniform protrusions as shown in FIG. 3.
  • the related art often uses acid to etch transparent oxide electrodes to form bumps to reduce reflection.
  • the method is to directly soak the deposited electrode film (such as ZnO) in an acid solution (such as HCl). Because process parameters such as soaking time and temperature are difficult to uniformly control, the uniformity of the formed protrusions is poor, ranging from a few tenths of a micrometer to a large number of micrometers. For example, as shown in the scanning electron micrographs of FIGS. 4a and 4b, the size of the protrusions formed on the surface of the transparent electrode is not uniform. Moreover, the acid is extremely corrosive, and is highly corrosive to the transparent electrode, thereby destroying the electrode performance. In the method of the present disclosure, the laser crystallization method does not cause damage to the electrode, and is a non-destructive solution.
  • an N-type metal oxide semiconductor film 50 and a transparent electrode film 60 are sequentially deposited on the surface of the intrinsic amorphous silicon film 80 facing away from the first electrode layer 41. Then, the N-type metal oxide semiconductor film 50 and the transparent electrode film 60 are patterned to form the N-type metal oxide semiconductor layer 22 and the transparent electrode layer 42.
  • the P-type amorphous silicon film 70 and the intrinsic amorphous silicon film 80 are etched to form a P-type amorphous silicon film.
  • the photodiode shown in FIG. 1 was prepared.
  • a P-type amorphous silicon film 70 may be formed on the surface of the first electrode layer 41 first, and an intrinsic amorphous silicon film 80 may be formed on the surface of the P-type amorphous silicon film 70 facing away from the first electrode layer 41. . Then the surface of the intrinsic amorphous silicon film 80 facing away from the first electrode layer 41 is irradiated with a laser, so that the surface of the intrinsic amorphous silicon film 80 facing away from the first electrode layer 41 is crystallized to form a concave-convex structure with uniform protrusions 210 33.
  • an N-type metal oxide semiconductor material is deposited on the surface of the intrinsic amorphous silicon film 80 facing away from the first electrode layer 41 to form an N-type metal oxide semiconductor film 50.
  • a transparent conductive material is used to deposit a transparent electrode film 60.
  • the transparent electrode film 60 and the N-type metal oxide semiconductor film 50 overlap in a direction perpendicular to the surface of the first electrode layer 41 in contact with the semiconductor layer.
  • a photoresist is formed on the surface of the transparent electrode film 60 facing away from the first electrode layer 41, and the photoresist is exposed by a mask to form a photoresist retention area and a photoresist removal area.
  • the photoresist reserved area corresponds to the area where the N-type metal oxide semiconductor layer 22 and the transparent electrode layer 42 are located, and the photoresist removal area corresponds to other than the area where the N-type metal oxide semiconductor layer 22 and the transparent electrode layer 42 are located. area.
  • the photoresist located in the photoresist removal area is removed by a developer, and the N-type metal oxide semiconductor film 50 and the transparent electrode film 60 located in the photoresist removal area are etched to remove the photoresist located in the photoresist removal area.
  • the N-type metal oxide semiconductor film 50 and the transparent electrode film 60 are removed to form an N-type metal oxide semiconductor layer 22 and a transparent electrode layer 42.
  • the photoresist located in the photoresist reserved area is stripped.
  • N-type metal oxide semiconductor materials there are various types of N-type metal oxide semiconductor materials that can be selected. For example, multiple materials of indium, gallium, zinc and oxygen can be selected, such as indium gallium zinc oxide (IGZO); or multiple materials of indium, gallium, zinc and oxygen can be mixed with different contents of tin (Sn). Material, such as: IGZTO.
  • IGZO indium gallium zinc oxide
  • Sn tin
  • the N-type metal oxide semiconductor layer 22 and the transparent electrode layer 42 can be directly used as a mask to compare the P-type amorphous silicon film 70 and the transparent electrode layer.
  • the intrinsic amorphous silicon film 80 is dry-etched, thereby forming the P-type amorphous silicon layer 20 and the intrinsic amorphous silicon layer 21.
  • the above method of preparing the P-type amorphous silicon layer 20 and the intrinsic amorphous silicon layer 21 can not only form the P-type amorphous silicon layer 20 and the intrinsic amorphous silicon layer 21 at the same time through a single patterning process, but also can directly use the N-type amorphous silicon layer
  • the metal oxide semiconductor layer 22 and the transparent electrode layer 42 are masks, and the P-type amorphous silicon film 70 and the intrinsic amorphous silicon film 80 are patterned. Therefore, the method avoids separately preparing masks for patterning the P-type amorphous silicon film 70 and the intrinsic amorphous silicon film 80, thereby simplifying the manufacturing process of the photodiode and saving the manufacturing cost.
  • the foregoing method of preparing the N-type metal oxide semiconductor layer 22 and the transparent electrode layer 42 can realize the simultaneous formation of the N-type metal oxide semiconductor layer 22 and the transparent electrode layer 42 through a single patterning process, thereby further simplifying the preparation of the photodiode. Process flow and save preparation cost.
  • the relative position relationship may also change accordingly.
  • an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, the element can be “directly” on or “under” the other element, or may be present Intermediate element.
  • specific features, structures, materials or characteristics can be combined in an appropriate manner in any one or more embodiments or examples.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Light Receiving Elements (AREA)
  • Photovoltaic Devices (AREA)

Abstract

本公开涉及一种光电二极管及其制备方法、电子设备。所述光电二极管包括：层叠设置的第一电极层和半导体结构，所述半导体结构背向所述第一电极层的表面具有第一凹凸结构；设置在所述半导体结构背向所述第一电极层的表面上的第二电极层，所述第二电极层背向所述第一电极层的表面具有第二凹凸结构。

Description

光电二极管及其制备方法、电子设备
相关申请的交叉参考
本公开主张在2019年2月2日在中国提交的中国专利申请号No.201910108010.X的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及光电转换技术领域，尤其涉及一种光电二极管及其制备方法、以及包含该光电二极管的电子设备。
背景技术
光电二极管是一种将接收到的光信号转换成电信号的半导体器件。目前光电二极管在工作时，其所接受到的光线有一部分被反射，导致光电二极管的转换效率低。
发明内容
一方面，本公开提供一种光电二极管，包括：
层叠设置的第一电极层和半导体结构，其中，所述半导体结构背向所述第一电极层的表面具有第一凹凸结构；和
设置在所述半导体结构背向所述第一电极层的表面上的第二电极层，其中，所述第二电极层背向所述第一电极层的表面具有第二凹凸结构。
可选地，所述半导体结构包括：
设置在所述第一电极层的表面上的第一半导体层；和
设置在所述第一半导体层背向所述第一电极层的一侧的第二半导体层，其中，所述第二半导体层背向所述第一电极层的表面具有所述第一凹凸结构；
其中，所述第一半导体膜层和所述第二半导体层之一为P型半导体层，另一个为N型半导体层。
可选地，所述第一半导体层包括N型非晶硅层，所述第二半导体层包括P型非晶硅层，并且所述P型非晶硅层背向所述第一电极层的表面具有所述 第一凹凸结构。
可选地，所述第一半导体层包括P型非晶硅层，所述第二半导体层包括N型非晶硅层，并且所述N型非晶硅层背向所述第一电极层的表面具有所述第一凹凸结构。
可选地，所述半导体结构还包括设置在所述N型非晶硅层和所述P型非晶硅层之间的本征非晶硅层。
可选地，所述半导体结构还包括本征非晶硅层；
其中，所述第一半导体层包括P型非晶硅层，所述本征非晶硅层位于所述P型非晶硅层背向所述第一电极层的表面，且所述本征非晶硅层背向所述第一电极层的表面具有通过使其表面的非晶硅结晶而形成的第三凹凸结构；
其中，所述第二半导体层包括设置在所述本征非晶硅层背向所述第一电极层的表面的N型金属氧化物半导体层，所述N型金属氧化物半导体层背向所述第一电极层的表面具有所述第一凹凸结构。
可选地，所述半导体结构还包括本征非晶硅层；
其中，所述第一半导体层包括N型金属氧化物半导体层，所述本征非晶硅层位于所述N型金属氧化物半导体层背向所述第一电极层的表面；
其中，所述第二半导体层包括设置在所述本征非晶硅层背向所述第一电极层的表面的P型非晶硅层，所述P型非晶硅层背向所述第一电极层的表面具有通过使其表面的非晶硅结晶而形成的所述第一凹凸结构。
可选地，所述半导体结构还包括本征非晶硅层；
其中，所述第一半导体层包括N型金属氧化物半导体层，所述本征非晶硅层位于所述N型金属氧化物半导体层背向所述第一电极层的表面，且所述本征非晶硅层背向所述第一电极层的表面具有通过使其表面的非晶硅结晶而形成的第三凹凸结构；
其中，所述第二半导体层包括设置在所述本征非晶硅层背向所述第一电极层的表面的P型非晶硅层，所述P型非晶硅层背向所述第一电极层的表面具有所述第一凹凸结构。
可选地，所述第一凹凸结构、第二凹凸结构和第三凹凸结构具有基本上相同的轮廓。
可选地，所述第一凹凸结构、第二凹凸结构和第三凹凸结构中的凸起在垂直于第一电极层与半导体结构接触的表面的方向上的高度为30nm～80nm，在平行于第一电极层与半导体结构接触的表面的方向上的最大宽度为0.1μm～0.5μm，相邻的凸起之间的间距为0.1μm～0.4μm。
可选地，在上述的光电二极管中，所述第二电极层为透明电极层。
另一方面，本公开还提供一种电子设备，包括上述任一项所述的光电二极管。
再一方面，本公开还提供一种制备光电二极管的方法，包括：
制备第一电极层；
在所述第一电极层的表面上制备半导体结构，其中，所述半导体结构背向所述第一电极层的表面形成有第一凹凸结构；以及
在所述半导体结构背向所述第一电极层的表面上沉积形成第二电极层，其中，所述第二电极层背向所述第一电极层的表面形成有第二凹凸结构。
可选地，在所述第一电极层的表面制备半导体结构的步骤包括：
在所述第一电极层的表面上制备第一半导体层；以及
在所述第一半导体层背向所述第一电极层的一侧制备第二半导体层，并且所述第二半导体层背向所述第一电极层的表面形成有所述第一凹凸结构；
其中，所述第一半导体层和所述第二半导体层之一为P型半导体层，另一个为N型半导体层。
可选地，制备第一半导体层和第二半导体层的步骤包括：
利用激光照射所述第二半导体层背向所述第一电极层的表面，使所述第二半导体层背向所述第一电极层的表面结晶，以形成所述第一凹凸结构。
可选地，所述方法还包括制备本征非晶硅层，所述本征非晶硅层处在所述N型非晶硅层和所述P型非晶硅层之间。
可选地，制备第一半导体层和第二半导体层的步骤包括：
在所述第一电极层的表面上制备P型非晶硅层；
在所述P型非晶硅层背向所述第一电极层的表面制作本征非晶硅层，并且利用激光照射所述本征非晶硅层背向所述第一电极层的表面，使所述本征非晶硅层背向所述第一电极层的表面结晶，以形成第三凹凸结构；以及
在所述本征非晶硅层背向所述第一电极层的表面上沉积形成N型金属氧化物半导体层，并且所述N型金属氧化物半导体层背向所述第一电极层的表面上形成有所述第一凹凸结构。
可选地，制备第一半导体层和第二半导体层的步骤包括：
在所述第一电极层的表面上制备N型金属氧化物半导体层；
在所述N型金属氧化物半导体层背向所述第一电极层的表面上制备本征非晶硅层；以及
在所述本征非晶硅层背向所述第一电极层的表面上沉积形成P型非晶硅层，并且利用激光照射所述P型非晶硅层背向所述第一电极层的表面，使所述P型非晶硅层背向所述第一电极层的表面结晶，以形成所述第一凹凸结构。
可选地，制备第一半导体层和第二半导体层的步骤包括：
在所述第一电极层的表面上制备N型金属氧化物半导体层；
在所述N型金属氧化物半导体层背向所述第一电极层的表面上制备本征非晶硅层，并且利用激光照射所述本征非晶硅层背向所述第一电极层的表面，使所述本征非晶硅层背向所述第一电极层的表面结晶，以形成第三凹凸结构；以及
在所述本征非晶硅层背向所述第一电极层的表面上沉积形成P型非晶硅层，并且使所述P型非晶硅层背向所述第一电极层的表面形成所述第一凹凸结构。
可选地，制备所述P型非晶硅层、本征非晶硅层、N型金属氧化物半导体层和所述第二电极层的步骤包括：
在所述第一电极层的表面上依次形成层叠设置的P型非晶硅薄膜和本征非晶硅薄膜，并且利用激光照射所述本征非晶硅薄膜背向所述第一电极层的表面，使所述本征非晶硅薄膜背向所述第一电极层的表面结晶；
在所述本征非晶硅薄膜背向所述第一电极层的表面上依次沉积层叠设置的N型金属氧化物半导体薄膜和第二电极层薄膜，同时对所述N型金属氧化物半导体薄膜和所述第二电极层薄膜进行构图，以形成所述N型金属氧化物半导体层和所述第二电极层；以及
以所述N型金属氧化物半导体层和所述第二电极层为掩膜，对所述P型 非晶硅薄膜和所述本征非晶硅薄膜进行刻蚀，以形成所述P型非晶硅层和所述本征非晶硅层。
可选地，在半导体层的表面进行结晶化之前，用酸性溶液对待结晶化的表面进行清洗；和/或在半导体层的表面进行结晶化之后，用酸性溶液对待结晶化的表面进行清洗。
可选地，在上述制备光电二极管的方法中，所述第二电极层为透明电极层。
附图说明
图1是根据本公开的实施例的光电二极管的结构示意图。
图2a-2e是根据本公开实施例的制备光电二极管的方法中的各步骤所制备的结构体的示意图。
图3是根据本公开实施例的方法中对半导体层表面进行结晶后的半导体层表面的透射电镜图。
图4a-4b是相关技术中对光电二极管的透明电极层表面进行酸腐蚀前后的透明电极层表面的扫描电镜图。
具体实施方式
为了进一步说明本公开实施例提供的光电二极管及其制备方法、电子设备，下面结合说明书附图对此实施例进行详细描述。以下本公开的实施例仅仅用于解释本公开的技术方案，但并不构成对本公开的限制。
在相关技术中，光电二极管主要包括：半导体结构；以及分别设置在半导体结构相对的两个表面上的第一电极和第二电极。第一电极和第二电极中的至少一个电极为透明电极，作为用于接收光线的窗口层。光电二极管的工作原理是：光线经光电二极管的透明电极射入光电二极管内，光电二极管将接收到的光信号转换为电信号后，将该电信号经光电二极管的两个电极输出。
用于接收光线的透明电极的表面通常为基本上平坦的表面，因此光线在射向该透明电极时容易被该平坦的表面反射，导致光电二极管的光电转换效率低。在相关技术中，为了解决上述光电转换效率较低的问题，通常会采用 酸溶液对透明电极中用于接收光线的表面进行刻蚀，使得该表面凹凸不平，从而起到减反射的作用。但是，该方法对微观结构可控性较差，对电极膜层的破坏性较强，容易对光电转换二极管的性能产生不利影响。
基于上述相关技术中存在的问题，本公开提供了一种光电二极管及其制备方法、以及包括该光电二极管的电子设备，其解决了光电二极管的光电转换效率低的问题。
根据本公开的实施例提供了一种光电二极管，包括层叠设置的第一电极层和半导体结构；和设置在所述半导体结构背向所述第一电极层的表面上的第二电极层，其中，所述半导体结构背向所述第一电极层的表面具有第一凹凸结构，并且所述第二电极层背向所述第一电极层的表面具有第二凹凸结构。
可选地，所述第二电极层为透明电极层。所述透明电极层的可见光透过率为70％以上。例如，当透明电极层是厚度为
Figure PCTCN2020072742-appb-000001
的ITO层时，对400nm可见光的透过率为70％以上。
在根据本公开的上述实施例中，在通过透明电极层接收外界光线时，光线从具有第二凹凸结构的表面射入光电二极管，减小了透明电极层对光线产生的反射作用；而且，由于半导体结构接收光线的表面形成有第一凹凸结构，使得光线在经具有第一凹凸结构的表面射入半导体结构时，进一步减小了半导体结构对光线产生的反射作用。因此，根据本公开的上述实施例可以有效地减小透明电极层和半导体结构对光线的反射作用，使得光线能够最大限度的射入到半导体结构中，从而提升了光电二极管的转换效率。此外，根据本公开的上述实施例避免了相关技术中通过采用酸溶液对透明电极层中用于接收光线的表面进行刻蚀，由此避免了因酸溶液刻蚀而导致的对电极层的破坏、以及对光电转换二极管的性能产生的不利影响。
具体地，如图1所示的，本公开实施例提供了一种光电二极管，包括：层叠设置的第一电极层41和半导体结构2；以及设置在半导体结构2背向第一电极层41的表面的透明电极层42，其中，半导体结构2背向第一电极层41的表面具有第一凹凸结构31，透明电极层42背向第一电极层41的表面具有第二凹凸结构32。
在制备上述光电二极管时，可以先在基底1上形成第一电极层41，然后在第一电极层41背向基底1的表面上制备半导体结构2，并在该半导体结构2背向第一电极层41的表面上形成第一凹凸结构31，最后在半导体结构2形成有第一凹凸结构31的表面制作透明电极层42，以使透明电极层42背向第一电极层41的表面能够形成第二凹凸结构32。该第一电极层41可选为非透明的电极。半导体结构2和形成在其上的第一凹凸结构31的尺寸均可以根据实际需要设置。例如，设置半导体结构2的尺寸以使得其在基底1上的正投影被第一电极层41在基底1上的正投影包围。例如，设置第一凹凸结构31的尺寸以使其完全覆盖半导体结构2背向第一电极层41的表面。透明电极层42的尺寸同样可以根据实际需要设置。例如，设置透明电极层42的尺寸以完全覆盖第一凹凸结构31，或者设置透明电极层42的尺寸以覆盖部分第一凹凸结构31。
上述实施例的光电二极管在工作时，光线从透明电极层42具有第二凹凸结构32的表面射入光电二极管内，并通过半导体结构2具有第一凹凸结构31的表面射入到半导体结构2内部，半导体结构2将接收到的光线转换为电信号后，将该电信号经光电二极管的两个电极输出。
根据上述光电二极管的具体结构、制备过程和工作过程可知，在本公开实施例提供的光电二极管中，通过在半导体结构2背向第一电极层41的表面形成了第一凹凸结构31，以及在透明电极层42背向第一电极层41的表面形成第二凹凸结构32，减小了透明电极层42和半导体结构2对光线产生的反射作用。因此，本公开实施例提供的光电二极管能够使光线最大限度的射入到半导体结构2中，从而提升了光电二极管的光电转换效率。此外，本公开实施例避免了相关技术中通过采用酸溶液对透明电极层进行刻蚀而导致的对电极层的破坏。
在一些实施例中，上述半导体结构2可以具体包括：设置在第一电极层的表面上的第一半导体层；以及设置在第一半导体层背向第一电极层的表面上的第二半导体层。
在一下实施例中，第二半导体层背向第一电极层的表面具有第一凹凸结 构，并且第一半导体层和第二半导体层中之一为P型半导体层，另一个为N型半导体层。更详细地说，上述半导体结构2可以具体包括如下两种结构。第一种结构为，半导体结构2包括设置在第一电极层的表面上的P型半导体层、和设置在P型半导体层背向第一电极层的表面上的N型半导体层。第二种结构为，半导体结构2包括设置在第一电极层的表面上的N型半导体层、和设置在N型半导体层背向第一电极层的表面上的P型半导体层。
设置上述半导体结构2包括N型半导体层和P型半导体层，使得半导体结构2形成有PN结。而且，为了有利于接受入射光线，可以将PN结的面积尽量做得大一些。在光线(即携带能量的光子)经光电二极管的透明电极层射入PN结后，能够把能量传给PN结中共价键上的束缚电子，使部分电子挣脱共价键，从而产生电子—空穴对，它们在反向电压作用下参加漂移运动，使反向电流明显变大。光的强度越大，产生的反向电流也越大。
在一些实施例中，上述第一半导体层包括P型非晶硅层，第二半导体层包括N型非晶硅层，N型非晶硅层背向第一电极层的表面具有第一凹凸结构。具体地，在制备上述结构的半导体结构时，可以先在第一电极层的表面上制备P型非晶硅层；然后在P型非晶硅层背向第一电极层的表面上制备N型非晶硅层，并利用激光照射N型非晶硅层背向第一电极层的表面，使N型非晶硅层背向第一电极层的表面结晶，以形成第一凹凸结构。
在一些实施例中，上述第一半导体层包括N型非晶硅层，第二半导体层包括P型非晶硅层，P型非晶硅层背向第一电极层的表面具有第一凹凸结构。具体地，在制备上述结构的半导体结构时，可先在第一电极层的表面制备N型非晶硅层；然后在N型非晶硅层背向第一电极层的表面制备P型非晶硅层，并利用激光照射该P型非晶硅层背向第一电极层的表面，使P型非晶硅层背向第一电极层的表面结晶，以形成第一凹凸结构。
对于上述两个实施例，在制备P型非晶硅层或N型非晶硅层时，可先形成非晶硅薄膜，然后在对该非晶硅薄膜进行相应的掺杂，从而形成对应的P型非晶硅层或N型非晶硅层。
另外，在利用激光对P型非晶硅层或N型非晶硅层进行结晶化时，P型 非晶硅层或N型非晶硅层被激光照射的表面能够形成规则排列的凸起，即第一凹凸结构，由此P型非晶硅层或N型非晶硅层形成为具有减反射作用的膜层。因此，本公开的实施例通过对P型非晶硅层或N型非晶硅层的表面进行激光结晶化，使得P型非晶硅层或N型非晶硅层具有减反射作用的方式不需要增加构图工艺，不会对半导体结构产生损伤，由此确保了光电二极管的性能。
可选地，根据本公开的实施例的半导体结构还可以包括设置在N型非晶硅层和P型非晶硅层之间的本征非晶硅层。
具体地，在N型非晶硅层和P型非晶硅层之间设置本征非晶硅层，使得半导体结构形成为PIN节。当光电二极管采用这种结构的半导体结构2时，其具有结电容小、渡越时间短、灵敏度高等优点。更详细地说，本征非晶硅层一般为掺杂浓度低的N型半导体层(例如，N型非晶硅层)。在PN结中引入的本征半导体层增加了在垂直于第一电极层41与半导体结构2接触的表面的方向上的厚度。这不仅增大了半导体结构的耗尽区的宽度，而且其几乎占据了整个耗尽区，使得绝大部分的入射光在本征半导体层内被吸收并产生大量的电子-空穴对，而位于本征半导体层两侧的N型非晶硅层和P型非晶硅层在垂直于第一电极层与半导体结构2接触的表面的方向上厚度较薄，吸收入射光的比例小。因此减小了扩散运动的影响，提高了光电二极管的响应速度。
在一些实施例中，如图1所示的，上述实施例提供的半导体结构2还包括本征非晶硅层21。因此，第一半导体层包2括层叠的P型非晶硅层20、本征非晶硅层21和N型非晶硅层22。本征非晶硅层21位于P型非晶硅层20背向第一电极层41的表面，且本征非晶硅层21背向第一电极层41的表面层211结晶，以形成第三凹凸结构33。第二半导体层包括设置在本征非晶硅层21背向第一电极层41的表面的N型金属氧化物半导体层22，N型金属氧化物半导体层22背向第一电极层41的表面具有第一凹凸结构31。可选地，所述第一凹凸结构31具有与第三凹凸结构33基本上相同的轮廓。
具体地，当半导体结构2包括依次层叠设置在第一电极层41上的P型非晶硅层20、本征非晶硅层21和N型金属氧化物半导体层22时，可以利用激 光照射本征非晶硅层21背向第一电极层41的表面，使本征非晶硅层21背向第一电极层41的表面结晶化以形成第三凹凸结构33。然后，在本征非晶硅层背向第一电极层41的表面层211形成较薄的带晶界凸起210的P型非晶硅层。然后，在该P型非晶硅层背向第一电极层41的表面上沉积形成N型金属氧化物半导体层22，使得形成的N型金属氧化物半导体层22背向第一电极层41的表面具有第一凹凸结构31。最后，在N型金属氧化物半导体层背向第一电极层41的表面上形成透明电极层42，使得形成的透明电极层42背向第一电极层41的表面具有第二凹凸结构32。
由此可见，本公开的上述实施例通过在本征非晶硅层21、N型金属氧化物半导体层22和透明电极层42的表面均形成具有凹凸不平的结构来降低入射光的反射。因此，本公开的上述实施例能够进一步有效地提高光电二极管的光电转换效率，并且使得光电二极管能够实现较高的信噪比。此外，本公开的上述实施例实现多重降低入射光被反射的作用方式不需要增加额外的构图工艺，还不会对半导体结构2产生损害。
在一些实施例中，所述半导体结构还包括本征非晶硅层，其中，第一半导体层包括N型金属氧化物半导体层，本征非晶硅层位于N型金属氧化物半导体层背向第一电极层的表面；第二半导体层包括设置在本征非晶硅层背向第一电极层的表面的P型非晶硅层，P型非晶硅层背向第一电极层的表面具有第一凹凸结构。
具体地，在制备上述结构的半导体结构时，可以先在第一电极层的表面上制备N型金属氧化物半导体层，然后在N型金属氧化物半导体层背向第一电极层的表面上制备本征非晶硅层，再在本征非晶硅层背向第一电极层的表面上制备P型非晶硅层，并利用激光照射该P型非晶硅层背向第一电极层的表面，使P型非晶硅层背向第一电极层的表面结晶，以形成规则排列的凸起，即第一凹凸结构。P型非晶硅层形成为具有减反射作用的膜层，并且形成在P型非晶硅层背向第一电极层的表面上的透明电极层同样具有相同或类似轮廓的凹凸结构，即第二凹凸结构，由此透明电极层同样地具有减反射作用。
上述通过对P型非晶硅层的表面进行激光结晶化，使得P型非晶硅层具 有减反射作用的方式不需要增加构图工艺，还不会对半导体结构产生损伤，由此确保了光电二极管的工作性能。
本公开实施例还提供了一种电子设备，包括上述任一实施例的光电二极管。
本公开实施例提供的电子设备包括上述任一实施例提供的发光二极管，因此该电子设备也具有上述有益效果，此处不再赘述。
本公开实施例还提供了一种制备光电二极管的方法，用于制备上述任一实施例提供的光电二极管，如图2a至图2e所示的，所述方法包括：
制备第一电极层41；
在第一电极层41的表面上制备半导体结构2，其中，所述半导体结构2背向第一电极层41的表面形成有第一凹凸结构31；以及
在半导体结构2背向第一电极层41的表面上沉积形成透明电极层42，其中，所述透明电极层42背向第一电极层41的表面形成有第二凹凸结构32。
具体地，可以先采用导电材料在基底1上制备第一电极层41。该第一电极层41的透明程度不做限定。然后在第一电极层41的表面上制备半导体结构2，并在半导体结构2背向第一电极层41的表面形成第一凹凸结构31。值得注意的是，半导体结构2和形成在其上的第一凹凸结构31的尺寸均可以根据实际需要设置。最后在半导体结构2形成有第一凹凸结构31的表面上制备透明电极层42，透明电极层42会延续第一凹凸结构的轮廓而形成凹凸结构，即：透明电极层42背向第一电极层41的表面能够形成第二凹凸结构32。透明电极层42的尺寸同样可以根据实际需要来设置。
本公开实施例提供的制备光电二极管的方法中，通过在半导体结构2背向第一电极层41的表面形成了第一凹凸结构31，以及在半导体结构2形成第一凹凸结构31的表面制备的透明电极层42能够形成第二凹凸结构32，当通过透明电极层42接收外界光线时，减小了透明电极层42和半导体结构2对光线产生的反射作用。因此，本公开实施例提供的光电二极管使光线能够最大限度的射入到半导体结构2中，提升了光电二极管的转换效率。而且，通过在半导体结构2和透明电极层42的表面均设置凹凸结构，避免了相关技 术中通过采用酸溶液对透明电极层42的表面进行刻蚀，由此避免了因酸溶液刻蚀而导致的对电极层的破坏、以及对光电转换二极管的性能产生的不利影响。因此，本公开实施例的制备光电二极管的方法是一种无破坏性的方案。
可选地，在第一电极层的表面上制备半导体结构的步骤具体包括：
在第一电极层的表面上制备第一半导体层；以及
在第一半导体层背向第一电极层的表面上制备第二半导体层，并且第二半导体层背向第一电极层的表面形成有第一凹凸结构。
可选地，第一半导体层和第二半导体层中之一为P型半导体层，另一个为N型半导体层。具体地，采用上述方法制备的半导体结构包括如下两种结构。
第一种，半导体结构包括设置在第一电极层的表面上的P型半导体层，和设置在P型半导体层背向第一电极层的表面上的N型半导体层。
第二种，半导体结构包括设置在第一电极层的表面的N型半导体层，和设置在N型半导体层背向第一电极层的表面上的P型半导体层。
设置上述半导体结构包括N型半导体层和P型半导体层，使得半导体结构形成为PN结。在光线经光电二极管的透明电极层射入PN结后，能够把能量传给PN结中共价键上的束缚电子，使部分电子挣脱共价键，从而产生电子—空穴对。它们在反向电压作用下参加漂移运动，使反向电流明显变大。光的强度越大，产生的反向电流也越大。
在一些实施例中，上述制备第一半导体层和第二半导体层的步骤可以具体包括：在第一电极层的表面上制备N型非晶硅层；以及在N型非晶硅层背向第一电极层的表面上制备P型非晶硅层，并且利用激光照射P型非晶硅层背向第一电极层的表面，使所述P型非晶硅层背向第一电极层的表面结晶，以形成所述第一凹凸结构。
在另一些实施例中，上述制备第一半导体层和第二半导体层的步骤可具体包括：在第一电极层的表面上制备P型非晶硅层；以及在P型非晶硅层背向第一电极层的表面上制备N型非晶硅层，并且利用激光照射N型非晶硅层背向第一电极层的表面，使N型非晶硅层背向第一电极层的表面结晶，以形 成第一凹凸结构。
对于上述两个实施例，在制备P型非晶硅层和N型非晶硅层时，可以先形成非晶硅薄膜，然后在对该非晶硅薄膜进行相应的掺杂，从而形成对应的P型非晶硅层和N型非晶硅层。
另外，在利用激光对P型非晶硅层或N型非晶硅层进行结晶化时，P型非晶硅层或N型非晶硅层被激光照射的表面能够形成规则排列的凸起，即第一凹凸结构，从而使得P型非晶硅层或N型非晶硅层形成为具有减反射作用的膜层。因此，本公开的实施例通过对P型非晶硅层或N型非晶硅层的表面通过激光照射而结晶化，使得P型非晶硅层或N型非晶硅层具有减反射作用的方式不需要增加构图工艺，不会对半导体结构产生损伤，由此确保了光电二极管的工作性能。
可选地，根据本公开实施例的制备方法还可以包括在N型非晶硅层和P型非晶硅层之间制备本征非晶硅层。具体地，本征非晶硅层一般为掺杂浓度低的N型非晶硅层。在制备该本征非晶硅层时，可以先形成非晶硅层，然后再对其进行低浓度的离子掺杂，以形成本征非晶硅层。更详细地说，在N型非晶硅层和P型非晶硅层之间设置本征非晶硅层，使得半导体结构形成为PIN节。当光电二极管采用这种结构的半导体结构时，其具有结电容小、渡越时间短、灵敏度高等优点。
在一些实施例中，所述制备第一半导体层和第二半导体层的步骤还可以具体包括：
在第一电极层的表面行制备N型金属氧化物半导体层；
在N型金属氧化物半导体层背向第一电极层的表面上制备本征非晶硅层；以及
在本征非晶硅层背向第一电极层的表面上沉积形成P型非晶硅层，并且利用激光照射P型非晶硅层背向第一电极层的表面，使P型非晶硅层背向第一电极层的表面结晶，以形成第一凹凸结构。
具体地，在制备上述结构的半导体结构时，可以先在第一电极层的表面上制备N型金属氧化物半导体层；然后在N型金属氧化物半导体层背向第一 电极层的表面上制备本征非晶硅层，再在本征非晶硅层背向第一电极层的表面上制备P型非晶硅层，并利用激光照射该P型非晶硅层背向第一电极层的表面，使P型非晶硅层背向第一电极层的表面结晶，以形成规则排列的凸起，即第一凹凸结构。P型非晶硅层形成为具有减反射作用的膜层，并且形成在P型非晶硅层背向第一电极层的表面的透明电极层延续形成相同或类似的凹凸结构，由此透明电极层同样具有减反射作用。
上述通过对P型非晶硅层的表面进行激光结晶化，使得P型非晶硅层具有减反射作用的方式不需要增加构图工艺，还不会对半导体结构产生损伤，由此确保了光电二极管的工作性能。
在另一些实施例中，如图1所示，所述制备第一半导体层和第二半导体层的步骤还可以具体包括：
在第一电极层41的表面上制备P型非晶硅层20；
在P型非晶硅层20背向第一电极层41的表面上制备本征非晶硅层21，并且利用激光照射本征非晶硅层21背向第一电极层41的表面，使本征非晶硅层21背向第一电极层41的表面结晶；以及
在本征非晶硅层21背向第一电极层41的表面上沉积形成N型金属氧化物半导体层22，N型金属氧化物半导体层22背向第一电极层41的表面形成有第一凹凸结构31。
具体地，当半导体结构2包括依次层叠设置在第一电极层41上的P型非晶硅层20、本征非晶硅层21和N型金属氧化物半导体层22时，可以先利用激光照射本征非晶硅层21背向第一电极层41的表面，使本征非晶硅层21背向第一电极层41的表面结晶化。然后在本征非晶硅层背向第一电极层41的表面形成较薄的带晶界凸起210的P型非晶硅层，该P型非晶硅层背向第一电极层41的表面形成规则排列的凸起210。然后在该P型非晶硅层背向第一电极层41的表面沉积形成N型金属氧化物半导体层22，使得形成的N型金属氧化物半导体层22能够延续P型非晶硅层产生的凸起210形貌，使得N型金属氧化物半导体层22在背向第一电极层41的表面具有第一凹凸结构31。最后在N型金属氧化物半导体层22背向第一电极层41的表面形成透明电极 层42，使得形成的透明电极层42背向第一电极层41的表面延续所述第一凹凸结构31而形成第二凹凸结构32。可选地，所述第一凹凸结构31和第二凹凸结构具有相同或相似的凸起轮廓。
需要说明的是，形成的较薄的带晶界凸起210的P型非晶硅层对光线的吸收系数相比于本征非晶硅层对光线的吸收系数较低，因此形成的较薄的带晶界凸起210的P型非晶硅层不会使入射光衰减加强，更有利于提高光线的入射量。
同样地，根据本公开的实施例的上述制备方法通过对本征非晶硅层21的表面进行激光结晶化以形成规则排列的凸起210，由此使N型金属氧化物半导体层22背向第一电极层41的表面延续形成有第一凹凸结构31，以及使透明电极层42背向第一电极层41的表面延续形成有第二凹凸结构32，从而实现了使得本征非晶硅层21、N型金属氧化物半导体层22和透明电极层42用于接收光线的表面均凹凸不平，起到了入射光减反层的作用。因此，本公开的实施例能够有效地提高光电二极管的光电转换效率，使得光电二极管能够实现较高的信噪比。而且，上述实现入射光减反层的作用的方式不需要增加构图工艺，还不会对半导体结构2产生损伤，确保了光电二极管的工作性能。
从上述各实施例可以看出，本公开实施例提供的制备方法不仅适用于具有金属氧化物异质结的光电二极管，还适用于常规的仅包括非晶硅同质结的光电二极管。
在上述各实施例中，在利用激光进行结晶化操作之前，可以利用酸性溶液(例如，低浓度的氢氟酸)对待结晶化的膜层的表面进行清洗，以保证结晶化效果。而且，在结晶化操作之后，同样可以利用酸性溶液对结晶化后的膜层的表面进行清洗，以将结晶化过程中产生的杂质清除。
例如，当利用激光照射本征非晶硅层时，容易在本征非晶硅层的表面产生氧化硅(SiO x，其中0<x≤2)，利用酸性溶液对本征非晶硅层结晶化的表面进行清洗，能够将产生的氧化硅SiO x去除，更有利于保证良好的结晶化效果。
可选地，在利用激光对半导体层进行结晶化时，可通过调节激光照射的速度和能量密度来控制膜层结晶化表面产生的凸起210的尺寸。例如，产生 的凸起210在垂直于第一电极层41与半导体层2的接触面的方向上的高度可以为30nm～80nm，凸起210在平行于第一电极层41与半导体层2的接触面的方向上的最大宽度可以为0.1μm～0.5μm，相邻的凸起210之间的间距可以为0.1μm～0.4μm。
进一步地，如图2a-2e所示的，上述制备P型非晶硅层20、本征非晶硅层21、N型金属氧化物半导体层22和透明电极层42的步骤具体包括以下步骤。
如图2a所示的，第一电极层41的表面依次形成层叠设置的P型非晶硅薄膜70和本征非晶硅薄膜80。如图2b所示的，利用激光90照射本征非晶硅薄膜80背向第一电极层41的表面。如图2c所示，使本征非晶硅薄膜80背向第一电极层41的表面结晶，以形成第三凹凸结构33。在图2c中，本征非晶硅薄膜80和凸起210之间的直线代表结晶化和未被结晶化的半导体层的界面的截面示意线。实际中该界面的截面并不是呈直线状，这里只是示意。
由图3所示的透射电镜图可以看出，通过本公开实施例的结晶化方法在本征层的表面形成的第三凹凸结构33具有均匀凸起。不仅在本征层，而且在N型半导体层(氧化物半导体层或非晶硅半导体层)或P型半导体层上均可以形成如图3所示的均匀凸起。
相比之下，相关技术常常采用酸腐蚀透明氧化物电极来形成凸起以起到减反射的作用。该方法是将沉积后的电极薄膜(如ZnO)直接浸泡在酸溶液(如HCl)中。由于诸如浸泡时间、温度等工艺参数难以均匀控制，所以形成的凸起的均匀性欠佳，小到零点几微米，大到几微米不等。例如，如图4a和4b的扫描电镜照片可知，透明电极表面形成的凸起的尺寸不均匀。而且，酸腐蚀性极强，对透明电极具有强腐蚀性，由此破坏电极性能。而本公开的方法中，激光结晶化方法没有对电极造成损伤，是一种无破坏性的方案。
如图2d和2e所示的，在本征非晶硅薄膜80背向第一电极层41的表面依次沉积层叠设置的N型金属氧化物半导体薄膜50和透明电极薄膜60。然后对N型金属氧化物半导体薄膜50和透明电极薄膜60进行构图，以形成N型金属氧化物半导体层22和透明电极层42。
如图2e所示的，以N型金属氧化物半导体层22和透明电极层42为掩膜，对P型非晶硅薄膜70和本征非晶硅薄膜80进行刻蚀，以形成P型非晶硅层20和本征非晶硅层21。由此制备得到图1所示的光电二极管。
具体地，可以先在第一电极层41的表面上形成P型非晶硅薄膜70，并在P型非晶硅薄膜70背向第一电极层41的表面上形成本征非晶硅薄膜80。然后利用激光照射本征非晶硅薄膜80背向第一电极层41的表面，使本征非晶硅薄膜80背向第一电极层41的表面结晶，以形成具有均匀凸起210的凹凸结构33。然后采用N型金属氧化物半导体材料在本征非晶硅薄膜80背向第一电极层41的表面上沉积形成N型金属氧化物半导体薄膜50。然后在N型金属氧化物半导体薄膜50背向第一电极层41的表面上，采用透明导电材料来沉积形成透明电极薄膜60。在垂直于第一电极层41与半导体层接触的表面的方向上，透明电极薄膜60和N型金属氧化物半导体薄膜50重叠。接着在透明电极薄膜60背向第一电极层41的表面形成光刻胶，利用掩膜板对光刻胶进行曝光，形成光刻胶保留区域和光刻胶去除区域。光刻胶保留区域对应N型金属氧化物半导体层22和透明电极层42所在的区域，光刻胶去除区域对应除N型金属氧化物半导体层22和透明电极层42所在的区域之外的其它区域。利用显影液将位于光刻胶去除区域的光刻胶去除，并对位于光刻胶去除区域的N型金属氧化物半导体薄膜50和透明电极薄膜60进行刻蚀，以将位于光刻胶去除区域的N型金属氧化物半导体薄膜50和透明电极薄膜60去除，形成N型金属氧化物半导体层22和透明电极层42。最后将位于光刻胶保留区域的光刻胶剥离。
上述可以选用的N型金属氧化物半导体材料的种类多种多样。例如，可以选用铟、镓、锌和氧的多元材料，如铟镓锌氧化物(IGZO)；或可以选用在铟、镓、锌和氧的多元材料中掺入不同含量锡(Sn)的多元材料，如：IGZTO。
可选地，在形成N型金属氧化物半导体层22和透明电极层42之后，可直接以N型金属氧化物半导体层22和透明电极层42为掩膜，对P型非晶硅薄膜70和本征非晶硅薄膜80进行干法刻蚀，从而形成P型非晶硅层20和本征非晶硅层21。
上述制备P型非晶硅层20和本征非晶硅层21的方法，不仅能够通过一次构图工艺同时形成P型非晶硅层20和本征非晶硅层21，而且可以直接以N型金属氧化物半导体层22和透明电极层42为掩膜，对P型非晶硅薄膜70和本征非晶硅薄膜80进行图形化。因此，该方法避免了单独制备用于对P型非晶硅薄膜70和本征非晶硅薄膜80进行图形化的掩膜，从而简化了光电二极管的制备工艺流程和节约了制备成本。另外，上述制备N型金属氧化物半导体层22和透明电极层42的方法，能够实现通过一次构图工艺同时形成N型金属氧化物半导体层22和透明电极层42，从而进一步简化了光电二极管的制备工艺流程和节约制备成本。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”、“第三”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。在上述实施例中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的可选实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种光电二极管，包括：
    层叠设置的第一电极层和半导体结构，其中，所述半导体结构背向所述第一电极层的表面具有第一凹凸结构；和
    设置在所述半导体结构背向所述第一电极层的表面上的第二电极层，其中，所述第二电极层背向所述第一电极层的表面具有第二凹凸结构。
  2. 根据权利要求1所述的光电二极管，其中，所述半导体结构包括：
    设置在所述第一电极层的表面上的第一半导体层；和
    设置在所述第一半导体层背向所述第一电极层的一侧的第二半导体层，其中，所述第二半导体层背向所述第一电极层的表面具有所述第一凹凸结构；
    其中，所述第一半导体层和所述第二半导体层之一为P型半导体层，另一个为N型半导体层。
  3. 根据权利要求2所述的光电二极管，其中，所述第一半导体层包括N型非晶硅层，所述第二半导体层包括P型非晶硅层，并且所述P型非晶硅层背向所述第一电极层的表面具有所述第一凹凸结构。
  4. 根据权利要求2所述的光电二极管，其中，所述第一半导体层包括P型非晶硅层，所述第二半导体层包括N型非晶硅层，并且所述N型非晶硅层背向所述第一电极层的表面具有所述第一凹凸结构。
  5. 根据权利要求3或4所述的光电二极管，其中，所述半导体结构还包括设置在所述N型非晶硅层和所述P型非晶硅层之间的本征非晶硅层。
  6. 根据权利要求2所述的光电二极管，其中，所述半导体结构还包括本征非晶硅层；
    其中，所述第一半导体层包括P型非晶硅层，所述本征非晶硅层位于所述P型非晶硅层背向所述第一电极层的表面，且所述本征非晶硅层背向所述第一电极层的表面具有通过使其表面的非晶硅结晶而形成的第三凹凸结构；
    其中，所述第二半导体层包括设置在所述本征非晶硅层背向所述第一电极层的表面的N型金属氧化物半导体层，所述N型金属氧化物半导体层背向所述第一电极层的表面具有所述第一凹凸结构。
  7. 根据权利要求2所述的光电二极管，其中，所述半导体结构还包括本征非晶硅层；
    其中，所述第一半导体层包括N型金属氧化物半导体层，所述本征非晶硅层位于所述N型金属氧化物半导体层背向所述第一电极层的表面；
    其中，所述第二半导体层包括设置在所述本征非晶硅层背向所述第一电极层的表面的P型非晶硅层，所述P型非晶硅层背向所述第一电极层的表面具有通过使其表面的非晶硅结晶而形成的所述第一凹凸结构。
  8. 根据权利要求2所述的光电二极管，其中，所述半导体结构还包括本征非晶硅层；
    其中，所述第一半导体层包括N型金属氧化物半导体层，所述本征非晶硅层位于所述N型金属氧化物半导体层背向所述第一电极层的表面，且所述本征非晶硅层背向所述第一电极层的表面具有通过使其表面的非晶硅结晶而形成的第三凹凸结构；
    其中，所述第二半导体层包括设置在所述本征非晶硅层背向所述第一电极层的表面的P型非晶硅层，所述P型非晶硅层背向所述第一电极层的表面具有所述第一凹凸结构。
  9. 根据权利要求6或8所述的光电二极管，其中，所述第一凹凸结构、第二凹凸结构和第三凹凸结构具有基本上相同的轮廓。
  10. 根据权利要求9所述的光电二极管，其中，所述第一凹凸结构、第二凹凸结构和第三凹凸结构中的凸起在垂直于第一电极层与半导体结构接触的表面的方向上的高度为30nm～80nm，在平行于第一电极层与半导体结构接触的表面的方向上的最大宽度为0.1μm～0.5μm，相邻的凸起之间的间距为0.1μm～0.4μm。
  11. 根据权利要求1所述的光电二极管，其中，所述第二电极层为透明电极层。
  12. 一种电子设备，包括如权利要求1～11中任一项所述的光电二极管。
  13. 一种制备光电二极管的方法，包括：
    制备第一电极层；
    在所述第一电极层的表面上制备半导体结构，其中，所述半导体结构背 向所述第一电极层的表面形成有第一凹凸结构；以及
    在所述半导体结构背向所述第一电极层的表面上沉积形成第二电极层，其中，所述第二电极层背向所述第一电极层的表面形成有第二凹凸结构。
  14. 根据权利要求13所述的方法，其中，在所述第一电极层的表面制备半导体结构的步骤包括：
    在所述第一电极层的表面上制备第一半导体层；以及
    在所述第一半导体层背向所述第一电极层的一侧制备第二半导体层，并且在所述第二半导体层背向所述第一电极层的表面形成所述第一凹凸结构；其中，所述第一半导体层和所述第二半导体层之一为P型半导体层，另一个为N型半导体层。
  15. 根据权利要求14所述的方法，其中，
    利用激光照射所述第二半导体层背向所述第一电极层的表面，使所述第二半导体层背向所述第一电极层的表面结晶，以形成所述第一凹凸结构。
  16. 根据权利要求15所述的方法，其中，所述方法还包括制备本征非晶硅层，所述本征非晶硅层处在所述N型非晶硅层和所述P型非晶硅层之间。
  17. 根据权利要求14所述的方法，其中，制备第一半导体层和第二半导体层的步骤包括：
    在所述第一电极层的表面上制备P型非晶硅层；
    在所述P型非晶硅层背向所述第一电极层的表面制作本征非晶硅层，并且利用激光照射所述本征非晶硅层背向所述第一电极层的表面，使所述本征非晶硅层背向所述第一电极层的表面结晶，以形成第三凹凸结构；以及
    在所述本征非晶硅层背向所述第一电极层的表面上沉积形成N型金属氧化物半导体层，并且所述N型金属氧化物半导体层背向所述第一电极层的表面上形成有所述第一凹凸结构。
  18. 根据权利要求14所述的方法，其中，制备第一半导体层和第二半导体层的步骤包括：
    在所述第一电极层的表面上制备N型金属氧化物半导体层；
    在所述N型金属氧化物半导体层背向所述第一电极层的表面上制备本征非晶硅层；以及
    在所述本征非晶硅层背向所述第一电极层的表面上沉积形成P型非晶硅层，并且利用激光照射所述P型非晶硅层背向所述第一电极层的表面，使所述P型非晶硅层背向所述第一电极层的表面结晶，以形成所述第一凹凸结构。
  19. 根据权利要求14所述的方法，其中，制备第一半导体层和第二半导体层的步骤包括：
    在所述第一电极层的表面上制备N型金属氧化物半导体层；
    在所述N型金属氧化物半导体层背向所述第一电极层的表面上制备本征非晶硅层，并且利用激光照射所述本征非晶硅层背向所述第一电极层的表面，使所述本征非晶硅层背向所述第一电极层的表面结晶，以形成第三凹凸结构；以及
    在所述本征非晶硅层背向所述第一电极层的表面上沉积形成P型非晶硅层，并且使所述P型非晶硅层背向所述第一电极层的表面形成所述第一凹凸结构。
  20. 根据权利要求16-17中任一项所述的方法，其中，制备所述P型非晶硅层、本征非晶硅层、N型金属氧化物半导体层和所述第二电极层的步骤包括：
    在所述第一电极层的表面上依次形成层叠设置的P型非晶硅薄膜和本征非晶硅薄膜，并且利用激光照射所述本征非晶硅薄膜背向所述第一电极层的表面，使所述本征非晶硅薄膜背向所述第一电极层的表面结晶；
    在所述本征非晶硅薄膜背向所述第一电极层的表面上依次沉积层叠设置的N型金属氧化物半导体薄膜和第二电极层薄膜，同时对所述N型金属氧化物半导体薄膜和所述第二电极层薄膜进行构图，以形成所述N型金属氧化物半导体层和所述第二电极层；以及
    以所述N型金属氧化物半导体层和所述第二电极层为掩膜，对所述P型非晶硅薄膜和所述本征非晶硅薄膜进行刻蚀，以形成所述P型非晶硅层和所述本征非晶硅层。
  21. 根据权利要求17或19所述的方法，其中，在使所述本征非晶硅层背向所述第一电极层的表面结晶之前和/或之后，用酸性溶液对所述本征非晶硅层背向所述第一电极层的表面进行清洗。
  22. 根据权利要求13所述的方法，其中，所述第二电极层为透明电极层。
PCT/CN2020/072742 2019-02-02 2020-01-17 光电二极管及其制备方法、电子设备 WO2020156239A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/958,120 US11469336B2 (en) 2019-02-02 2020-01-17 Photodiode, method for preparing the same, and electronic device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910108010.X 2019-02-02
CN201910108010.XA CN109817731B (zh) 2019-02-02 2019-02-02 一种光电二极管及其制作方法、电子设备

Publications (1)

Publication Number Publication Date
WO2020156239A1 true WO2020156239A1 (zh) 2020-08-06

Family

ID=66606451

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/072742 WO2020156239A1 (zh) 2019-02-02 2020-01-17 光电二极管及其制备方法、电子设备

Country Status (3)

Country Link
US (1) US11469336B2 (zh)
CN (1) CN109817731B (zh)
WO (1) WO2020156239A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109817731B (zh) 2019-02-02 2021-10-12 京东方科技集团股份有限公司 一种光电二极管及其制作方法、电子设备
CN112151554B (zh) * 2020-09-18 2024-03-19 Tcl华星光电技术有限公司 一种阵列基板及其制备方法
CN116156917A (zh) * 2021-11-15 2023-05-23 Tcl科技集团股份有限公司 复合物、复合物的制备方法、电致发光器件及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101779295A (zh) * 2008-03-28 2010-07-14 三菱重工业株式会社 光电转换装置及其制造方法
CN102150281A (zh) * 2008-09-12 2011-08-10 株式会社爱发科 太阳能电池和太阳能电池的制造方法
US20110278548A1 (en) * 2010-05-14 2011-11-17 Tokyo Institute Of Technology Microlens for organic el element, organic el element using the same, and manufacturing methods thereof
CN102652366A (zh) * 2009-12-15 2012-08-29 索尼公司 光电转换器件及光电转换器件的制造方法
CN104081534A (zh) * 2011-12-20 2014-10-01 住友金属矿山株式会社 透明导电膜层叠体及其制造方法和薄膜太阳能电池及其制造方法
CN109817731A (zh) * 2019-02-02 2019-05-28 京东方科技集团股份有限公司 一种光电二极管及其制作方法、电子设备

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2771414B2 (ja) * 1992-12-28 1998-07-02 キヤノン株式会社 太陽電池の製造方法
JP2892921B2 (ja) * 1993-11-09 1999-05-17 三洋電機株式会社 光起電力装置
DE10042733A1 (de) * 2000-08-31 2002-03-28 Inst Physikalische Hochtech Ev Multikristalline laserkristallisierte Silicium-Dünnschicht-Solarzelle auf transparentem Substrat
KR101303471B1 (ko) * 2009-09-09 2013-09-05 엘지디스플레이 주식회사 박막 태양전지 및 그 제조방법
KR102296283B1 (ko) * 2012-09-18 2021-08-31 옥스포드 유니버시티 이노베이션 리미티드 광전자 디바이스
CN104377251B (zh) * 2013-08-12 2016-09-14 上海理想万里晖薄膜设备有限公司 一种多尺度陷光的柔性大面积叠层太阳能电池及制备方法
CN109004047A (zh) * 2018-07-23 2018-12-14 江苏顺风光电科技有限公司 N型高效晶体硅太阳电池及其制备方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101779295A (zh) * 2008-03-28 2010-07-14 三菱重工业株式会社 光电转换装置及其制造方法
CN102150281A (zh) * 2008-09-12 2011-08-10 株式会社爱发科 太阳能电池和太阳能电池的制造方法
CN102652366A (zh) * 2009-12-15 2012-08-29 索尼公司 光电转换器件及光电转换器件的制造方法
US20110278548A1 (en) * 2010-05-14 2011-11-17 Tokyo Institute Of Technology Microlens for organic el element, organic el element using the same, and manufacturing methods thereof
CN104081534A (zh) * 2011-12-20 2014-10-01 住友金属矿山株式会社 透明导电膜层叠体及其制造方法和薄膜太阳能电池及其制造方法
CN109817731A (zh) * 2019-02-02 2019-05-28 京东方科技集团股份有限公司 一种光电二极管及其制作方法、电子设备

Also Published As

Publication number Publication date
CN109817731B (zh) 2021-10-12
CN109817731A (zh) 2019-05-28
US11469336B2 (en) 2022-10-11
US20210217909A1 (en) 2021-07-15

Similar Documents

Publication Publication Date Title
WO2020156239A1 (zh) 光电二极管及其制备方法、电子设备
JP6106403B2 (ja) 光電変換素子及び光電変換素子の製造方法
JP5868503B2 (ja) 太陽電池およびその製造方法
US8384179B2 (en) Black silicon based metal-semiconductor-metal photodetector
US20100024871A1 (en) Photovoltaic device and method of manufacturing the same
KR100847741B1 (ko) ｐ-ｎ접합 계면에 패시베이션층을 구비하는 점 접촉 이종접합 실리콘 태양전지 및 그의 제조방법
US20100193027A1 (en) Solar cell and method for manufacturing the same
KR101948206B1 (ko) 태양 전지와, 이의 제조 방법
JP2009246025A (ja) 太陽電池およびその製造方法
US20120094421A1 (en) Method of manufacturing solar cell
US20230282754A1 (en) Photovoltaic cell, method for forming same, and photovoltaic module
TWI401810B (zh) 太陽能電池
US20100212721A1 (en) Thin film type solar cell and method for manufacturing the same
JP6207414B2 (ja) 光起電力素子およびその製造方法
US11158748B2 (en) Solar cell, solar cell module, and solar cell manufacturing method
JP2014183073A (ja) 光電変換素子および光電変換素子の製造方法
WO2019227804A1 (zh) 一种太阳能电池及其制备方法
WO2015015694A1 (ja) 光起電力装置
JPH02164077A (ja) アモルファスシリコン太陽電池
JP2013168605A (ja) 太陽電池の製造方法
KR102423371B1 (ko) 집적 회로 광검출기
KR101178445B1 (ko) 태양 전지 및 그 제조 방법
KR102516860B1 (ko) 임의 배열된 금속 나노입자를 이용한 실리콘 광검출기 및 그 제작방법
KR101315644B1 (ko) 태양전지 및 이의 제조방법
JP2013197547A (ja) 半導体受光素子の製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20747569

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20747569

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20747569

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 25/01/2022)

122 Ep: pct application non-entry in european phase

Ref document number: 20747569

Country of ref document: EP

Kind code of ref document: A1