WO2020156057A1 - 显示器及其显示面板 - Google Patents

显示器及其显示面板 Download PDF

Info

Publication number
WO2020156057A1
WO2020156057A1 PCT/CN2020/070732 CN2020070732W WO2020156057A1 WO 2020156057 A1 WO2020156057 A1 WO 2020156057A1 CN 2020070732 W CN2020070732 W CN 2020070732W WO 2020156057 A1 WO2020156057 A1 WO 2020156057A1
Authority
WO
WIPO (PCT)
Prior art keywords
display panel
vdd
wiring
display
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2020/070732
Other languages
English (en)
French (fr)
Inventor
常苗
李威龙
张露
胡思明
韩珍珍
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kunshan Govisionox Optoelectronics Co Ltd
Original Assignee
Kunshan Govisionox Optoelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kunshan Govisionox Optoelectronics Co Ltd filed Critical Kunshan Govisionox Optoelectronics Co Ltd
Publication of WO2020156057A1 publication Critical patent/WO2020156057A1/zh
Priority to US17/144,545 priority Critical patent/US11963405B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/911—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using passive elements as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/921—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/931—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the dispositions of the protective arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/3827—Portable transceivers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • This application relates to the field of display technology, in particular to a display and a display panel thereof.
  • full-screen technology is the mainstream in the industry.
  • the full screen technology can not only increase the viewing area of the mobile phone, but also enhance the appearance of the mobile phone, making the mobile phone look more technological.
  • the front area of the fuselage can accommodate a larger screen, which has a significant visual experience. Promote.
  • at least one corner of the full-screen display panel is usually designed to be irregular. For example, as shown in FIG. 1, the lower left corner and the lower right corner of the display panel are arc-shaped.
  • the non-display area is arranged with data lines for providing data signals and VDD lines for providing display signals.
  • VDD lines for providing display signals.
  • the display panel of an embodiment of the present application includes an irregular display area and pixels arranged in an array in the irregular display area.
  • a display of an embodiment of the present application includes a driving circuit and a display panel.
  • the display panel includes an irregular display area and pixels arranged in an array in the irregular display area. How many pixels are arranged in the non-display area outside the irregular display area There are two data lines, one VDD line and multiple conduction lines, each data line is electrically connected to a corresponding pixel, and multiple conduction lines electrically connect one VDD line to the corresponding pixel.
  • the driving circuit is electrically coupled to the data line of the display panel and the VDD line.
  • a VDD trace is added to the irregular display area, and the VDD trace is connected to the pixels in the irregular display area through the conduction line, thereby reducing the regular display area and the irregular display area
  • the current difference received by the pixels can avoid the risk of split screen caused by the large voltage divider impedance.
  • only one VDD trace is provided in the irregular display area, which can reduce the space occupied by the VDD trace in the non-display area, which is beneficial to the narrow border design.
  • FIG. 1 is a top view of the structure of an embodiment of a special-shaped display panel of the present application
  • FIG. 2 is a schematic diagram of a partial wiring structure of an embodiment of the irregular display area shown in FIG. 1;
  • FIG. 3 is a schematic diagram of a pixel circuit of an embodiment of the irregular display area shown in FIG. 2;
  • Fig. 4 is a partial cross-sectional view of the special-shaped display area shown in Fig. 2 along the A-A direction.
  • the primary purpose of this application is to add a VDD trace in the special-shaped display area, which connects to the pixels in the special-shaped display area through multiple conductive traces, which reduces the current difference between the regular display area and the pixels in the special-shaped display area. , In order to avoid the risk of splitting the screen caused by the large voltage divider impedance. At the same time, only one VDD trace is arranged in the special-shaped display area, which occupies a small space in the non-display area, which is conducive to narrow frame design.
  • the display panel 10 includes a display area 11 and a non-display area 12 located at the periphery of the display area.
  • the display area 11 has pixels 112 arranged in an array. As shown in FIG. 2, these pixels 112 may be R (Red) sub-pixels, G (Green, green) sub-pixels, and B (Blue, blue). Sub-pixel. Each pixel 112 can display a different gray scale under the control of the driving circuit, so that the display panel 10 can display a color image.
  • At least one corner of the display area 11 is an arc-shaped corner, that is, the display area 11 has at least two adjacent straight sides, and an arc-shaped corner is formed between the two adjacent straight sides.
  • the lower left corner and the lower right corner of the display area 11 are both arc-shaped corners.
  • the area in the display area 11 that is composed of non-straight edges is called the irregular display area 111
  • the area in the display area 11 that is composed of straight edges is called the regular display area (not labeled in the figure).
  • the display panel 10 has at least two adjacent rows of pixels 112 with different numbers.
  • the number of pixels 112 in the second row is greater than that in the first row.
  • the number of 112 is one more, so that the two adjacent rows of pixels 112 are formed with steps.
  • the size of any two steps in the row direction may be the same or different, and the difference in the size of the two steps in the row direction may be equal to an integer multiple of a pixel 112 in the row direction, which depends on the pixels of the display panel 10. Structural design.
  • the non-display area 12 a driving circuit for driving the pixel 112 to emit light and corresponding signal wiring are distributed.
  • the non-display area 12 may include a wiring area.
  • the wiring area is arranged close to the periphery of the display area 11 (including the special-shaped display area 111), and different types of signal wiring are arranged in the wiring area, and the signal wiring is for various types of wiring for signal transmission.
  • it includes, for example, a scan drive output line.
  • One end of the scan drive output line is connected to the gate drive unit, and the other end is connected to the pixel circuit, thereby providing a scan drive signal to the pixel 112 connected to it.
  • the signal wiring further includes a VDD wiring 121 and a plurality of data lines 122.
  • the area occupied by these data lines 122 in the non-display area 12 is called the Data wiring area 123, as shown in FIG.
  • One data line 122 can be connected to a column of pixels 112 correspondingly.
  • the number of VDD wiring 121 is one, and the one VDD wiring 121 is located at the periphery of the Data wiring area 123.
  • a plurality of conductive traces 124 are arranged in the non-display area 12, and the conductive traces 124 connect the VDD trace 121 and the corresponding pixel 112, and each conductive trace 124 crosses Data
  • the wiring area 123 for example, the orthographic projection of a plurality of conductive wires 124 on the display panel 10 is located in the data wiring area 123.
  • FIG. 3 is a schematic diagram of a pixel circuit of an embodiment of the irregular display area shown in FIG. 2. 3, taking the OLED (organic light emitting diode) display panel 10 as an example, the pixel circuit 31 is connected to the scan line 32, the data line 122 and the VDD wiring 121 adjacent to the pixel circuit 31. In response to the scan pulse from the scan line 32, the current flowing in the OLED device is controlled according to the data signal Vdata from the data line 122.
  • the pixel circuit 31 may include a switching transistor Tsw, a driving transistor Tdr, and a capacitor Cst.
  • the switching transistor Tsw is switched according to the scan pulse supplied to the scan line 32, and the switching transistor Tsw supplies the driving transistor Tdr with the data signal Vdata supplied to the data line 122.
  • the driving transistor Tdr is switched according to the data signal Vdata supplied from the switching transistor Tsw, and the driving transistor Tdr controls the current from the VDD wiring 121 that drives the OLED device to emit light.
  • the capacitor Cst is connected between the gate and the source of the driving transistor Tdr, and is used to store a voltage corresponding to the data signal Vdata supplied to the gate of the driving transistor Tdr, and to turn on the driving transistor Tdr by the stored voltage.
  • the OLED device includes at least: an anode electrode (or pixel electrode) connected to the source of the driving transistor Tdr; an organic light emitting layer formed on the anode electrode; and a cathode electrode layer formed on the organic light emitting layer.
  • the OLED device displays a predetermined image by emitting light according to a display signal supplied from the driving transistor Tdr.
  • a VDD trace 121 is arranged in the special-shaped display area 111, which can help avoid the risk of split screen caused by a large voltage divider impedance.
  • the pixels in the irregular display area provide current through the VDD wiring in the regular display area, and the VDD wiring in the regular display area transmits the current to In the pixels in the regular display area, the current is transferred to the adjacent pixels in turn and finally to the pixels in the special-shaped display area.
  • the path of current transmission to the pixels in the special-shaped display area is much larger than that of the pixels in the regular display area.
  • the irregular display area 111 of the present application also receives current through a VDD wire 121, which reduces the difference in current received by the pixels 112 in the regular display area and the irregular display area, thereby reducing the difference in display brightness between the regular display area and the irregular display area. This helps to avoid the risk of splitting the screen caused by a large voltage divider impedance.
  • VDD trace 121 is arranged in the irregular display area 111, and the number of VDD traces is small, so that the area occupied by the VDD trace in the non-display area 12 can be reduced, which is beneficial to the narrow frame of the display panel 10. design.
  • the multiple conductive traces 124 occupy the existing Data wiring area 123 in the non-display area 12, so the area occupied by the signal traces in the non-display area 12 will not be increased, and the display panel 10 will not be affected. Narrow bezel design.
  • the direction of the VDD wiring 121 and the shape of the Data wiring area 123 change in accordance with the shape of the irregular display area 111, so that the wiring area is as close as possible to the irregular display area 111, thereby reducing the size of the non-display area 12.
  • Area which is also conducive to the realization of the narrow frame design of the display panel 10.
  • the extension direction of the VDD wiring 121 can be designed to fit as closely as possible to the outer edge of the Data wiring area 123, so as to make the frame of the display panel 10 as narrow as possible.
  • the signal traces including the VDD trace 121 and the multiple conduction traces 124 can be optimally designed according to space.
  • a conductive trace 124 is connected to a column of pixels 112.
  • the VDD trace 121 transmits the display signal to each conductive trace 124 according to a predetermined timing, and then transmits it to the corresponding connected Pixel 112.
  • one conductive trace 124 can also connect multiple columns of pixels 112.
  • a conductive trace 124 connects two columns of pixels 112.
  • the VDD trace 121 transmits the display signal to each conductive trace 124 according to a predetermined timing, and then transmits it to the corresponding connected pixel 112.
  • the timing control of the display signal can be realized by a demultiplexing circuit.
  • the demultiplexing circuit When the demultiplexing circuit is turned on and controls the display signal to be transmitted to a column of pixels 112 connected to a certain conductive trace 124, the demultiplexing circuit is turned off, and The display signal is not transmitted to other columns of pixels 112 connected to the conductive trace 124, which is well known to those skilled in the art and will not be repeated.
  • one conductive trace 124 can also connect more than two columns of pixels 112.
  • the conductive trace 124 may be a single-layer structure made of metals or alloys such as Mo (molybdenum) and Cu (copper), or may be a multilayer structure made of conductive materials. In order to control the line impedance, in this application, materials with lower impedance should be used as much as possible to make the conductive trace 124.
  • the conduction trace 124 is preferably located on the same layer as the source of the driving transistor Tdr of the pixel 112, and furthermore, the manufacturing materials of the two may be the same.
  • the aforementioned conduction wiring 124 can be formed in the process of forming the source of the driving transistor Tdr, so that the process of the entire display panel 10 is not increased.
  • the display panel 10 includes an array substrate stacked by multiple layers, the VDD wiring 121 and the data line 122 are located in the same layer of the array substrate, and a plurality of conductive wiring 124
  • the VDD and VDD traces 121 are located in different layers of the array substrate.
  • the multiple conductive traces 124 can be arranged on the upper layer (as shown in FIG. 4) or the lower layer of the multiple data lines 122, but the multiple conductive traces 124 A first insulating layer 41 is provided between the plurality of data lines 122.
  • the VDD wiring 121 and the data line 122 can be formed through a photomask process, and then a first insulating layer 41 is formed in the projection area of the Data wiring area 123, and the first insulating layer 41 is provided with exposed VDD
  • the via hole of the trace 121 is then formed by a photomask process to form a conductive trace 124, and the conductive material forming the conductive trace 124 is deposited in the via and connected to the VDD trace 121.
  • the manufacturing materials of the multiple conductive traces 124 and the VDD trace 121 can be the same, which can help control the lateral line impedance.
  • the non-display area 12 located at the periphery of the regular display area may be called a straight-edge area
  • the non-display area 12 located at the periphery of the irregular display area 111 may be called a special-shaped area.
  • a number of VDD traces are also provided inside.
  • the VDD traces 121 at the periphery of the aforementioned irregular display area 111 (that is, in the non-display area 12) and the VDD traces in the straight-side area can be formed by the same photomask process.
  • the display panel 10 may also include a first electrostatic protection component 21 and a second electrostatic protection component 22.
  • the first electrostatic protection component 21 is connected to the VDD trace 121
  • the second electrostatic protection component 22 is connected to the first electrostatic protection component.
  • the orthographic projection of the component 21 on the display panel 10 at least partially overlaps.
  • first electrostatic protection component 21 and the second electrostatic protection component 22 are not located on the same layer, and a second insulating layer is provided between the two.
  • first electrostatic protection component 21 and the second electrostatic protection component 22 are sandwiched
  • the second insulating layer between the two is coupled to form a capacitor.
  • the capacitor protrudes outside the VDD trace 121, causing a spike effect, so that the first electrostatic protection component 21 and the second electrostatic protection component 22 can be generated on at least one of the VDD trace 121 and the conduction trace 124 Electrostatic discharge.
  • the first electrostatic protection component 21 and the second electrostatic protection component 22 are used to guide the static electricity generated on at least one of the VDD wiring 121 and the conductive wiring 124 to the first electrostatic protection component 21 and the second electrostatic protection component 21.
  • the electrostatic protection component 22 detonates at the area where it is located.
  • the first electrostatic protection component 21 and the second electrostatic protection component 22 provide an electrostatic protection function for the display panel 10.
  • the first electrostatic protection component 21 and the second electrostatic protection component 22 guide the static electricity generated on the display panel 10 to the area where the first electrostatic protection component and the second electrostatic protection component are located and explode, thereby reducing damage to the display panel 10 caused by static electricity.
  • the first electrostatic protection component 21 may extend from one end of the VDD trace 121, that is, the extension direction of the first electrostatic protection component 21 is parallel to the extension direction of the VDD trace 121, and the extension of the second electrostatic protection component 22 The direction is perpendicular to the extension direction of the VDD trace 121.
  • the first electrostatic protection component 21 is electrically connected to the VDD wiring 121, and the first electrostatic protection component 21 and the VDD wiring 121 are arranged in the same layer.
  • the first electrostatic protection component 21 is preferably a part of the VDD wiring 121. Therefore, the two can be formed by the same process, so there is no additional process.
  • the second electrostatic protection component 22 is preferably arranged in the same layer as the conductive traces 124 but spaced apart from the conductive traces 124.
  • the second electrostatic protection component 22 and the conductive traces may be formed by the same manufacturing process. Route 124.
  • the display panel 10 of the foregoing embodiment of the present application also includes other structures.
  • the display panel 10 may also include an encapsulation area.
  • the aforementioned wiring area is disposed between the gate driving area and the encapsulation area.
  • the line area is attached to protect the display panel 10.
  • the packaging area is usually arranged on the outermost side of the non-display area to isolate water vapor and oxygen, avoid water vapor and oxygen from adversely affecting the driving circuit and wiring structure in the display panel 10, and ensure the normal operation of the display panel 10.
  • the present application does not limit the type of the display panel 10.
  • the display panel 10 may be an OLED (Organic Light-Emitting Diode) display panel based on LTPS (Low Temperature Poly-silicon), PSVA (Polymer -Stabilized Vertical Alignment, polymer stabilized vertical alignment), or MVA (Multi-domain Vertical Alignment, multi-domain vertical alignment) technology liquid crystal display panel, can also be a flexible touch display panel.
  • the capacitive touch display panel compared with the resistive touch display panel, the capacitive touch display panel has the advantages of long life, high light transmittance, and multi-touch support.
  • the display panel 10 may be a capacitive touch display panel.
  • the present application also provides a display.
  • the display includes a drive circuit and a display panel.
  • the drive circuit is electrically coupled to the data line of the display panel and the VDD wiring.
  • the display panel may have the same structural design as the display panel 10 of any of the foregoing embodiments, and therefore has the same beneficial effects.
  • the display includes, but is not limited to, mobile terminals such as smart phones, PDAs (Personal Digital Assistants, or tablet computers), and wearable devices that are worn on limbs or embedded in clothing, jewelry, and accessories.
  • mobile terminals such as smart phones, PDAs (Personal Digital Assistants, or tablet computers)
  • wearable devices that are worn on limbs or embedded in clothing, jewelry, and accessories.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种显示器及其显示面板（10），通过在异形显示区（111）增加一条VDD走线（121），该条VDD走线（121）通过多条导通走线（124）接入异形显示区（111）内的像素（112），从而能够在有利于窄边框设计的同时避免阻抗较大导致的分屏风险。

Description

显示器及其显示面板 【技术领域】
本申请涉及显示技术领域，具体涉及一种显示器及其显示面板。
【背景技术】
从传统的按键型手机到如今的触摸型智能机，手机越来越朝着高屏占比的方向发展，这其中全面屏技术更是业界主流。全面屏技术不仅可以增大手机的可视面积，而且提升了手机的颜值，让手机看上去更有科技感，另外同样机身正面的面积可以容纳更大的屏幕，对于视觉体验有着显著的提升。在此基础上，为了满足人们多样化的需求，全面屏显示面板的至少一边角通常被设计成异形，例如结合图1所示，显示面板的左下角和右下角为圆弧形。使用传统技术制造异形显示面板时，需要在异形显示区外围的非显示区内进行布线，包括用于驱动像素的相关电路和走线。具体地，该非显示区排布有用于提供data信号的数据线和提供显示信号的VDD走线。然而，受限于这些信号走线复杂的布线环境，压缩该非显示区的难度很大，对窄边框设计的实现造成障碍。
【申请内容】
基于此，本申请有必要提供一种显示器及其显示面板，以在有利于窄边框设计的同时避免阻抗较大导致的分屏风险。
本申请一实施例的显示面板，包括异形显示区及位于异形显示区内的阵列排布的像素，在异形显示区外围的非显示区内，排布有多条数据线、一条VDD走线和多条导通走线，每条数据线与对应的像素电连接，多条导通走线将一条VDD走线与对应的像素电连接。
本申请一实施例的显示器，包括驱动电路以及显示面板，该显示面板包括异形显示区及位于异形显示区内的阵列排布的像素，在异形显示区外围的非显示区内，排布有多条数据线，一条VDD走线和多条导通走线，每条数据线与对 应的像素电连接，多条导通走线将一条VDD走线与对应的像素电连接。驱动电路电性耦接显示面板的数据线和VDD走线。
本申请提供的显示器及其显示面板，通过在异形显示区增加一条VDD走线，该条VDD走线通过导通走线接入异形显示区内的像素，缩小了规则显示区和异形显示区内像素所接收的电流差异从而能够避免分压阻抗较大导致的分屏风险，另外异形显示区仅设置一条VDD走线，能够减小VDD走线在非显示区内所占空间，有利于窄边框设计。
【附图说明】
图1是本申请的异形显示面板一实施例的结构俯视图；
图2是图1所示异形显示区一实施例的局部布线结构示意图；
图3是图2所示异形显示区一实施例的像素电路示意图；
图4是图2所示异形显示区沿A-A方向的局部剖视图。
【具体实施方式】
本申请的首要目的是：在异形显示区增加一条VDD走线，其通过多条导通走线接入异形显示区内的像素，缩小了规则显示区和异形显示区内像素所接收的电流差异，以此避免分压阻抗较大导致的分屏风险。同时，异形显示区仅排布有一条VDD走线，其在非显示区内所占空间较小，有利于窄边框设计。
基于上述目的，下面将结合本申请实施例的附图，对本申请实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处描述的具体实施例仅用于解释本申请，而非对本申请的限定。在不冲突的情况下，下述各实施例及其中的技术特征可相互组合。另外还需要说明的是，为了便于描述，所述附图中仅示出了与本申请相关的部分而非全部结构。基于本申请的实施例，本领域普通技术人员在没有作出创造性劳动前提下获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1所示，所述显示面板10包括显示区11以及位于该显示区外围周边的非显示区12。
显示区11内具有阵列排布的像素112，如图2所示，这些像素112可以分别为R(Red,红色)子像素、G(Green,绿色)子像素、以及B(Blue,蓝色)子像素。每个像素112在驱动电路的控制下能够显示不同的灰阶，从而使显示面板10能够显示彩色图像。
显示区11的至少一个边角为弧形边角，也就是说，该显示区11具有至少两条相邻的直边，相邻两条直边之间形成有一弧形边角。例如，参阅图1，显示区11的左下角和右下角均为弧形边角。基于此设计，显示区11中包括由非直边构成的区域称之为异形显示区111，而显示区11中均由直边构成的区域称之为规则显示区(图中未标号)。
在异形显示区111内，所述显示面板10存在至少相邻两行数量不相同的像素112，例如在图2中，沿从下至上的方向，第二行像素112的数量比第一行像素112的数量多一个，从而导致该相邻两行像素112形成有台阶。其中，任意两个台阶在行方向上的尺寸可以相同也可以不相同，且这两个台阶在行方向上的尺寸之差可以等于一个像素112在行方向上的整数倍，这取决于显示面板10的像素结构设计。例如在图2中，沿从下至上的方向，对于第一行像素112和第二行像素112所形成的台阶与第二行像素112和第三行像素112所形成的台阶，这两个台阶在行方向上的尺寸之差等于一个像素112的在行方向上的尺寸。而在规则显示区内，任意相邻两行像素112在行方向上均对齐。
非显示区12内分布有用于驱动像素112发光的驱动电路和相应的信号走线。具体地，该非显示区12可以包括走线区。
走线区紧贴显示区11(包括异形显示区111)的外围而设置，走线区内排布有不同类型的信号走线，所述信号走线为实现信号传输的各种类型走线的总称，例如其包括扫描驱动输出线，该扫描驱动输出线的一端连接栅极驱动单元，另一端连接像素电路，由此向与其连接的像素112提供扫描驱动信号。又例如，所述信号走线还包括VDD走线121以及多条数据线122，这些数据线122在非显示区12内所占据的区域称之为Data布线区123，如图2所示，每条数据线122可以对应连接一列像素112。
与现有技术不同的是，在异形显示区111外围的非显示区12内，VDD走线121的排布数量为一条，该一条VDD走线121位于Data布线区123的外围。另外，非显示区12内还排布有多条导通走线124，该导通走线124连接所述VDD走线121和对应的像素112，且每一导通走线124均跨过Data布线区123，例如 多条导通走线124在显示面板10上的正投影位于Data布线区123内。
下面结合图3介绍本申请的显示面板10通过上述VDD走线121和多条导通走线124实现画面显示的原理及过程。
图3是图2所示异形显示区一实施例的像素电路示意图。结合图3所示，以为OLED(有机发光二极管)显示面板10为例，其像素电路31连接至与该像素电路31相邻的扫描线32、数据线122和VDD走线121。响应于来自扫描线32的扫描脉冲、根据来自数据线122的数据信号Vdata来控制在OLED器件中流动的电流。所述像素电路31可以包括开关晶体管Tsw、驱动晶体管Tdr和电容Cst。
根据供应至扫描线32的扫描脉冲来切换开关晶体管Tsw，并且开关晶体管Tsw向驱动晶体管Tdr供应被供应至数据线122的数据信号Vdata。根据从开关晶体管Tsw供应的数据信号Vdata来切换驱动晶体管Tdr，并且驱动晶体管Tdr控制来自VDD走线121的驱动OLED器件发光的电流。电容Cst连接在驱动晶体管Tdr的栅极与源极之间，用于存储与供应至驱动晶体管Tdr的栅极的数据信号Vdata对应的电压，并且通过所存储的电压来使驱动晶体管Tdr接通。
所述OLED器件至少包括：连接至驱动晶体管Tdr的源极的阳极电极(或像素电极)；形成在阳极电极上的有机发光层；以及形成在有机发光层上的阴极电极层。所述OLED器件通过根据从驱动晶体管Tdr供应的显示信号而发光来显示预定图像。
本申请在异形显示区111排布有一条VDD走线121，能够有利于避免分压阻抗较大导致的分屏风险。具体地，对于异形显示区内未设置独立的VDD走线的现有设计，异形显示区内的像素通过规则显示区内的VDD走线提供电流，规则显示区内的VDD走线将电流传输给规则显示区内的像素，电流在相邻像素依次传递并最终传输给异形显示区内的像素，电流传输至异形显示区内像素的路径远远大于传输至规则显示区内像素的路径，路径较长，且相邻像素之间的分压阻抗较大，电流衰减大，由此导致规则显示区和异形显示区的显示亮度差异，出现分屏风险的几率较高。而本申请的异形显示区111还通过一条VDD走线121接收电流，缩小了规则显示区和异形显示区内像素112所接收的电流差异，从而缩小规则显示区和异形显示区的显示亮度差异，从而有利于避免分压阻抗较大导致的分屏风险。
本申请在异形显示区111内仅排布一条VDD走线121，VDD走线的数量较 少，从而能够减小VDD走线在非显示区12内占据的面积，有利于显示面板10的窄边框设计。而多条导通走线124在非显示区12内占据的是原本就存在的Data布线区123，因此并不会增加信号走线在非显示区12内占据的区域，不会影响显示面板10的窄边框设计。
在本申请中，所述VDD走线121的走向和Data布线区123的形状顺应异形显示区111的形状而变化，使得走线区尽可能贴近异形显示区111，从而减小非显示区12的面积，这也有利于实现显示面板10的窄边框设计。例如，本申请可以设计VDD走线121的延伸方向与Data布线区123的外边缘走向尽可能贴合，以此使得显示面板10的边框尽可能窄。另外，包括VDD走线121和多条导通走线124在内的信号走线可依据空间进行最优化设计。
请继续参阅图2，一条导通走线124连接一列像素112，在异形显示区111内，VDD走线121将显示信号按照预定时序传递给各条导通走线124，继而传输至对应连接的像素112。
为了减少导通走线124的数量并以此降低布线的复杂度，一条导通走线124也可以连接多列像素112。例如，一条导通走线124连接两列像素112，在异形显示区111内，VDD走线121将显示信号按照预定时序传递给各条导通走线124，继而传输至对应连接的像素112，具体可以通过解复用电路来实现显示信号的时序控制，解复用电路导通并控制显示信号传输给某一导通走线124所连接的一列像素112时，该解复用电路关闭，并不将显示信号传输给该条导通走线124所连接的其他列像素112，这是本领域的技术人员公知的，不再赘述。当然，一条导通走线124还可以连接两列以上像素112。
导通走线124可以为采用Mo(钼)、Cu(铜)等金属或合金制成的单层结构，也可以为采用导电材料制成的多层叠加结构。为了控制线路阻抗，本申请应尽量选用阻抗较低的材料来制成导通走线124。
所述导通走线124优选地与像素112的驱动晶体管Tdr的源极位于同一层，进一步两者的制造材料可以相同。于此，本申请可以在形成驱动晶体管Tdr的源极的制程中一并形成前述导通走线124，从而不会增加整个显示面板10的制程。
请一并参阅图2和图4，所述显示面板10包括由多个层堆叠而成的阵列基板，VDD走线121和数据线122位于阵列基板的同一层中，多条导通走线124和VDD走线121位于阵列基板的不同层中，多条导通走线124可以设置于多条 数据线122的上层(如图4所示)或下层，但所述多条导通走线124和多条数据线122之间设置有第一绝缘层41。具体地，本申请可以通过一道光罩制程形成VDD走线121和数据线122，然后在Data布线区123的投影区域内形成一层第一绝缘层41，该第一绝缘层41开设有暴露VDD走线121的过孔，再通过一道光罩制程形成导通走线124，形成导通走线124的导电材料沉积于所述过孔中并与VDD走线121连接。其中，所述多条导通走线124和VDD走线121的制造材料可以相同，以此能够有利于控制横向线路阻抗。
请继续参阅图1图和图2，位于规则显示区外围的非显示区12可以称之为直边区，而位于异形显示区111外围的非显示区12可以称之为异形区，所述直边区内也设置有多条VDD走线，前述异形显示区111外围(即非显示区12内)的VDD走线121和所述直边区的VDD走线可以通过同一道光罩制程形成。
请继续参阅图2，显示面板10还可以包括第一静电保护组件21和第二静电保护组件22，第一静电保护组件21与VDD走线121连接，第二静电保护组件22与第一静电保护组件21在显示面板10上的正投影至少部分重叠。
其中，第一静电保护组件21和第二静电保护组件22并非位于同一层，两者之间设置有第二绝缘层，于此，第一静电保护组件21和第二静电保护组件22通过夹设于两者之间的第二绝缘层耦合形成一电容。该电容外突起于VDD走线121，产生尖峰效应，从而使得第一静电保护组件21与第二静电保护组件22可以将产生在VDD走线121和导通走线124中的至少之一上的静电引导释放。因此，第一静电保护组件21与第二静电保护组件22用于将产生在VDD走线121和导通走线124中的至少之一上的静电导引至第一静电保护组件21与第二静电保护组件22所在区域处引爆。
第一静电保护组件21和第二静电保护组件22为显示面板10提供了静电保护功能。第一静电保护组件21和第二静电保护组件22将显示面板10上产生的静电导引至第一静电保护组件与第二静电保护组件所在区域处引爆，从而减少静电对显示面板10造成损害。
具体的，第一静电保护组件21可以从VDD走线121的一端延伸而来，即第一静电保护组件21的延伸方向平行于VDD走线121的延伸方向，而第二静电保护组件22的延伸方向垂直于VDD走线121的延伸方向。
第一静电保护组件21与VDD走线121电连接，且第一静电保护组件21与VDD走线121设置在同一层中，本申请优选第一静电保护组件21为VDD走线 121的一部分，于此，两者可以由同一制程形成，从而不会额外增加制程。而第二静电保护组件22优选地与导通走线124设置在同一层中但与导通走线124间隔设置，于此，本实施例可以由同一制程形成第二静电保护组件22与导通走线124。
应该理解，本申请前述实施例的显示面板10还包括其他结构，例如，所述显示面板10还可以包括封装区，前述走线区设置于栅极驱动区和封装区之间，封装区与走线区贴合，用于保护显示面板10。具体地，封装区通常布置在非显示区的最外侧，用于隔离水汽和氧气，避免水汽和氧气对显示面板10内的驱动电路和走线结构造成不良影响，保证显示面板10的正常工作。
另外，本申请并不限定显示面板10的类型，例如显示面板10可以为OLED(Organic Light-Emitting Diode，有机发光二极管)显示面板，基于LTPS(Low Temperature Poly-silicon,低温多晶硅)、PSVA(Polymer-stabilized Vertical Alignment,聚合物稳定垂直配向)、或者MVA(Multi-domain Vertical Alignment,多畴垂直配向)技术的液晶显示面板，也可以为柔性触控显示面板。并且，相对于电阻式触控显示面板，电容式触控显示面板具有寿命长、透光率高、可支持多点触控等优点，所述显示面板10可以为电容式触控显示面板。
本申请还提供一种显示器，所述显示器包括驱动电路以及显示面板，所述驱动电路电性耦接显示面板的数据线和VDD走线。该显示面板可以具有与前述任一实施例的显示面板10相同的结构设计，因此具有与其相同的有益效果。
所述显示器包括但不限于智能手机、PDA(Personal Digital Assistant，个人数字助理或平板电脑)等移动终端，以及佩戴于肢体或者嵌入于衣物、首饰、配件中的可穿戴设备。
再次说明，以上所述仅为本申请的实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种显示面板，包括：
    异形显示区；
    位于所述异形显示区内的阵列排布的像素；
    形成于所述异形显示区外围的非显示区，在所述非显示区内排布有多条数据线、一条VDD走线和多条导通走线，每条所述数据线与对应的所述像素电连接，所述多条导通走线将所述一条VDD走线与对应的所述像素电连接。
  2. 根据权利要求1所述的显示面板，其中，所述多条数据线形成Data布线区，所述一条VDD走线位于所述Data布线区的外围，所述导通走线跨过所述Data布线区并与所述多条数据线绝缘。
  3. 根据权利要求2所述的显示面板，其中，所述多条导通走线在所述显示面板上的正投影位于所述Data布线区内。
  4. 根据权利要求2所述的显示面板，其中，所述VDD走线的走向和所述Data布线区的形状顺应所述异形显示区的形状而变化。
  5. 根据权利要求1所述的显示面板，其中，所述显示面板包括由多个层堆叠而成的阵列基板，所述多条导通走线和所述VDD走线位于所述阵列基板的不同层中。
  6. 根据权利要求5所述的显示面板，其中，所述VDD走线和所述多条数据线位于所述阵列基板的同一层中，所述多条导通走线和所述多条数据线之间设置有第一绝缘层。
  7. 根据权利要求6所述的显示面板，其中，所述第一绝缘层开设有暴露所述VDD走线的过孔，所述导通走线的部分沉积于所述过孔中并与所述VDD走线电连接。
  8. 根据权利要求5所述的显示面板，其中，所述导通走线为单层结构或多层叠加结构。
  9. 根据权利要求5所述的显示面板，其中，所述多条导通走线和所述VDD走线的制造材料相同。
  10. 根据权利要求5所述的显示面板，其中，所述多条导通走线与所述像素的驱动晶体管的源极位于所述阵列基板的同一层中，并且二者的制造材料相同。
  11. 根据权利要求1所述的显示面板，其中，所述显示面板还包括第一静电 保护组件和第二静电保护组件，所述第一静电保护组件与所述VDD走线连接，所述第二静电保护组件与所述第一静电保护组件在所述显示面板上的正投影至少部分重叠，并且所述第一、第二静电保护组件之间设置有第二绝缘层，以耦合形成电容。
  12. 根据权利要求11所述的显示面板，其中，所述第一静电保护组件与所述VDD走线设置在同一层中。
  13. 根据权利要求11所述的显示面板，其中，所述第二静电保护组件与所述导通走线设置在同一层中，并且所述第二静电保护组件与所述导通走线相互间隔设置。
  14. 根据权利要求11所述的显示面板，其中，所述第一静电保护组件的延伸方向平行于所述VDD走线的延伸方向，所述第二静电保护组件的延伸方向垂直于所述VDD走线的延伸方向。
  15. 根据权利要求1所述的显示面板，其中，所述显示面板还包括直边区，所述直边区设置有VDD走线，所述异形显示区外围的VDD走线和所述直边区的VDD走线电连通。
  16. 根据权利要求1所述的显示面板，其中，所述显示面板为柔性显示面板。
  17. 一种显示器，其中，所述显示器包括驱动电路以及显示面板，所述显示面板包括异形显示区及位于所述异形显示区内的阵列排布的像素，在所述异形显示区外围的非显示区内，排布有多条数据线，一条VDD走线和多条导通走线，每条所述数据线与对应的所述像素电连接，所述多条导通走线将所述一条VDD走线与对应的所述像素电连接；所述驱动电路电性耦接所述显示面板的数据线和VDD走线。
  18. 根据权利要求17所述的显示器，其中，所述多条数据线形成Data布线区，所述一条VDD走线位于所述Data布线区的外围，所述导通走线跨过所述Data布线区并与所述多条数据线绝缘。
  19. 根据权利要求17所述的显示器，其中，所述显示面板包括由多个层堆叠而成的阵列基板，所述多条导通走线和所述VDD走线位于所述阵列基板的不同层中。
  20. 根据权利要求17所述的显示器，其中，所述显示面板还包括第一静电保护组件和第二静电保护组件，所述第一静电保护组件与所述VDD走线连接，所述第二静电保护组件与所述第一静电保护组件在所述显示面板上的正投影至 少部分重叠，并且所述第一、第二静电保护组件之间设置有第二绝缘层，以耦合形成电容。
PCT/CN2020/070732 2019-01-28 2020-01-07 显示器及其显示面板 Ceased WO2020156057A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/144,545 US11963405B2 (en) 2019-01-28 2021-01-08 Display, display panel, and electronic terminal

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910081913.3 2019-01-28
CN201910081913.3A CN109742128B (zh) 2019-01-28 2019-01-28 显示器及其显示面板

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/144,545 Continuation US11963405B2 (en) 2019-01-28 2021-01-08 Display, display panel, and electronic terminal

Publications (1)

Publication Number Publication Date
WO2020156057A1 true WO2020156057A1 (zh) 2020-08-06

Family

ID=66366456

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/070732 Ceased WO2020156057A1 (zh) 2019-01-28 2020-01-07 显示器及其显示面板

Country Status (3)

Country Link
US (1) US11963405B2 (zh)
CN (1) CN109742128B (zh)
WO (1) WO2020156057A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109742128B (zh) 2019-01-28 2021-01-01 昆山国显光电有限公司 显示器及其显示面板
CN110187070B (zh) * 2019-06-19 2021-09-14 山东瑞谱检测技术有限公司 一种植物检疫用的谷物水分测定仪
CN111682054B (zh) * 2020-06-24 2023-01-10 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置
KR20250090385A (ko) 2020-09-30 2025-06-19 보에 테크놀로지 그룹 컴퍼니 리미티드 디스플레이 패널 및 디스플레이 장치
CN112382646B (zh) * 2020-11-10 2022-07-15 昆山国显光电有限公司 Oled显示面板及触控显示屏幕
CN113470558A (zh) * 2021-06-01 2021-10-01 合肥维信诺科技有限公司 显示面板和显示装置
KR20220170385A (ko) * 2021-06-22 2022-12-30 삼성디스플레이 주식회사 표시 장치
WO2023159516A1 (zh) * 2022-02-25 2023-08-31 京东方科技集团股份有限公司 显示基板及显示装置
CN115295591B (zh) * 2022-08-09 2026-04-28 昆山国显光电有限公司 显示面板及电子设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160027380A1 (en) * 2014-07-24 2016-01-28 Lg Display Co., Ltd. Power Sharing Lines for Powering A Small Form Factor OLED Display Device
CN107991799A (zh) * 2018-01-02 2018-05-04 上海中航光电子有限公司 显示面板及显示装置
CN108648615A (zh) * 2018-05-14 2018-10-12 昆山国显光电有限公司 显示面板
CN109087591A (zh) * 2018-09-20 2018-12-25 京东方科技集团股份有限公司 一种异形显示面板及显示装置
CN109742128A (zh) * 2019-01-28 2019-05-10 昆山国显光电有限公司 显示器及其显示面板

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102457244B1 (ko) * 2016-05-19 2022-10-21 삼성디스플레이 주식회사 표시 장치
CN106910823B (zh) 2017-04-05 2019-08-06 上海天马微电子有限公司 一种柔性显示面板和柔性显示装置
CN107146527B (zh) 2017-04-27 2020-01-03 上海天马微电子有限公司 一种柔性显示屏和柔性显示装置
KR102341412B1 (ko) * 2017-08-29 2021-12-22 삼성디스플레이 주식회사 표시 장치
CN107978622B (zh) * 2017-11-22 2020-08-11 上海天马有机发光显示技术有限公司 一种阵列基板、显示面板和显示装置
CN108010942B (zh) * 2017-11-28 2020-06-30 武汉天马微电子有限公司 一种有机发光显示面板和有机发光显示装置
CN108445684A (zh) * 2018-02-27 2018-08-24 上海中航光电子有限公司 阵列基板、显示面板与显示装置
CN108648695B (zh) 2018-05-14 2021-06-11 昆山国显光电有限公司 显示面板、触控显示面板和触控显示设备
CN108877519B (zh) 2018-06-26 2020-10-23 上海天马微电子有限公司 一种显示装置
CN108962030A (zh) 2018-07-18 2018-12-07 昆山国显光电有限公司 柔性显示屏、其制备方法以及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160027380A1 (en) * 2014-07-24 2016-01-28 Lg Display Co., Ltd. Power Sharing Lines for Powering A Small Form Factor OLED Display Device
CN107991799A (zh) * 2018-01-02 2018-05-04 上海中航光电子有限公司 显示面板及显示装置
CN108648615A (zh) * 2018-05-14 2018-10-12 昆山国显光电有限公司 显示面板
CN109087591A (zh) * 2018-09-20 2018-12-25 京东方科技集团股份有限公司 一种异形显示面板及显示装置
CN109742128A (zh) * 2019-01-28 2019-05-10 昆山国显光电有限公司 显示器及其显示面板

Also Published As

Publication number Publication date
US20210134936A1 (en) 2021-05-06
CN109742128B (zh) 2021-01-01
CN109742128A (zh) 2019-05-10
US11963405B2 (en) 2024-04-16

Similar Documents

Publication Publication Date Title
KR102443121B1 (ko) 디스플레이 패널 및 그 제조 방법 및 디스플레이 디바이스
WO2020156057A1 (zh) 显示器及其显示面板
KR102893375B1 (ko) 표시 장치
CN115004376B (zh) 显示基板及显示装置
CN108831302B (zh) 显示面板及显示装置
CN107633812B (zh) 一种显示面板及显示装置
US12317717B2 (en) Display panel and display device
CN110416226B (zh) 一种显示面板及其制作方法和显示装置
CN109857279B (zh) 显示面板及显示装置
CN107481669A (zh) 一种显示面板及显示装置
JP2020166239A (ja) 表示装置
KR20200124352A (ko) 표시 장치
US12111992B2 (en) Touch panel with chip region having display pins and touch pins, preparation method therefor, and display apparatus
WO2021207930A9 (zh) 显示基板及显示装置
US11387310B2 (en) Array substrate with connection portion connecting power bus and power line and display panel
CN113272885B (zh) 显示面板、显示装置、防止显示面板中的电磁干扰的方法以及制造显示面板的方法
WO2022041281A1 (zh) 一种显示面板及显示装置
WO2024250598A1 (zh) 显示面板
CN114356138A (zh) 一种触控显示面板及显示装置
CN113196371A (zh) 阵列基板及其制备方法、像素驱动方法、显示面板
WO2022134038A1 (zh) 显示面板及显示装置
CN117296477A (zh) 显示基板和显示装置
KR20240136512A (ko) 발광 표시 장치
US20250056890A1 (en) Display panels including metal layer having fan-out segment and display terminals including the same
US12364142B2 (en) Display panel and display device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20748522

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20748522

Country of ref document: EP

Kind code of ref document: A1