WO2020155107A1 - 薄膜晶体管及其制造方法、驱动电路、显示屏 - Google Patents

薄膜晶体管及其制造方法、驱动电路、显示屏 Download PDF

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Publication number
WO2020155107A1
WO2020155107A1 PCT/CN2019/074446 CN2019074446W WO2020155107A1 WO 2020155107 A1 WO2020155107 A1 WO 2020155107A1 CN 2019074446 W CN2019074446 W CN 2019074446W WO 2020155107 A1 WO2020155107 A1 WO 2020155107A1
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Prior art keywords
gate
thin film
film transistor
active layer
layer
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PCT/CN2019/074446
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English (en)
French (fr)
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晏国文
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深圳市柔宇科技有限公司
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Priority to PCT/CN2019/074446 priority Critical patent/WO2020155107A1/zh
Priority to CN201980073529.7A priority patent/CN113261103A/zh
Publication of WO2020155107A1 publication Critical patent/WO2020155107A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present invention relates to electronic technology, in particular to a thin film transistor, a manufacturing method of the thin film transistor, a driving circuit of a display screen and a display screen.
  • TFT Thin Film Transistor
  • AMOLED Active-matrix organic light-emitting diode
  • I DS drain-source current
  • Embodiments of the present invention provide a thin film transistor, a method for manufacturing a thin film transistor, a driving circuit of a display screen, and a display screen.
  • the thin film transistor of the embodiment of the present invention includes a substrate, a first gate formed on the substrate, a buffer layer covering the substrate and the first gate, an active layer formed on the buffer layer, and
  • the gate insulating layer on the active layer, the second gate formed on the gate insulating layer, the interlayer dielectric covering the active layer and the second gate, are formed on the A drain electrode on the interlayer dielectric and a source electrode formed on the interlayer dielectric.
  • the first gate has a ring shape.
  • the gate insulating layer has a ring shape.
  • the second gate has a ring shape.
  • the interlayer dielectric is formed with a first opening and a second opening.
  • the drain is connected to the active layer through the first opening.
  • the source electrode is connected to the active layer through the second opening.
  • the driving circuit of the display screen of the embodiment of the present invention includes the above-mentioned thin film transistor, the thin film transistor is used as the driving thin film transistor of the driving circuit, and the driving circuit further includes a switching thin film transistor, and the switching thin film transistor is used to control the driving A thin film transistor switch, the driving thin film transistor is used to drive the light emitting diode of the display screen to emit light.
  • the method of manufacturing a thin film transistor includes: providing a substrate; forming a first gate on the substrate, the first gate having a ring shape; forming a buffer layer, the buffer layer covering the substrate and the substrate The first gate; an active layer is formed on the buffer layer; a gate insulating layer is formed on the active layer, the gate insulating layer is ring-shaped; a second gate insulating layer is formed on the gate insulating layer Two gates, the second gate has a ring shape; an interlayer dielectric is formed on the active layer and the second gate, and a first opening and a second opening are opened on the interlayer dielectric; A drain is formed on the interlayer dielectric, and the drain is connected to the active layer through the first opening; a source is formed on the interlayer dielectric, and the source is connected to the active layer through the second opening.
  • the active layer is connected.
  • the embodiments of the present invention provide a thin film transistor, a method for manufacturing a thin film transistor, a driving circuit of a display screen, and a display screen. Since the thin film transistor of the embodiment of the present invention has two gates (equivalent to two single-gate thin film transistors in parallel), the drain-source current of the thin film transistor can be enhanced when the thin film transistor is working, thereby effectively reducing RC delay and IR. The influence of drop makes the drain-source current fluctuation smaller. In addition, since the first gate and the second gate are both ring-shaped, the drain-source current of the thin film transistor can also be enhanced, effectively reducing the effects of RC delay and IR drop, and making the drain-source current more stable. Further, since the second gate is formed on the active layer (that is, the thin film transistor has a top gate structure), the overlap between the second gate and the source is small, so the parasitic capacitance of the thin film transistor is small.
  • FIG. 1 is a schematic diagram of the structure of a thin film transistor according to some embodiments of the present invention.
  • FIG. 3 is a schematic diagram of the circuit structure of a display screen according to some embodiments of the present invention.
  • FIG. 4 is a schematic flowchart of a method for manufacturing a thin film transistor according to some embodiments of the present invention.
  • Display screen 1000 driving circuit 100, thin film transistor (driving thin film transistor) 10, substrate 11, first gate 12, buffer layer 13, active layer 14, gate insulating layer 15, second gate 16, interlayer dielectric 17.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features.
  • “plurality” means two or more, unless otherwise specifically defined.
  • connection should be understood in a broad sense unless otherwise clearly specified and limited.
  • they can be fixed or detachable.
  • Connected or integrally connected it can be mechanically connected, or electrically connected or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal communication of two components or the interaction of two components relationship.
  • the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
  • the thin film transistor 10 of the embodiment of the present invention includes a substrate 11, a first gate 12, a buffer layer 13, an active layer 14, a gate insulating layer 15, a second gate 16, and an interlayer dielectric 17. Drain 18 and source 19.
  • the first grid 12 is formed on the substrate 11, and the first grid 12 has a ring shape.
  • the buffer layer 13 covers the substrate 11 and the first gate 12.
  • the active layer 14 is formed on the buffer layer 13.
  • the gate insulating layer 15 is formed on the active layer 14, and the gate insulating layer 15 has a ring shape.
  • the second gate 16 is formed on the gate insulating layer 15 and the second gate 16 has a ring shape.
  • the interlayer dielectric 17 covers the active layer 14 and the second gate 16, and the interlayer dielectric 17 is formed with a first opening 172 and a second opening 174.
  • the drain 18 is formed on the interlayer dielectric 17, and the drain 18 is connected to the active layer 14 through the first opening 172.
  • the source electrode 19 is formed on the interlayer dielectric 17, and the source electrode 19 is connected to the active layer 14 through the second opening 174.
  • the thin film transistor 10 of the embodiment of the present invention has two gates (equivalent to two single-gate thin film transistors in parallel), so the drain-source current of the thin film transistor 10 can be enhanced when the thin film transistor 10 is working, thereby effectively reducing the RC delay. And the influence of IR drop makes the leakage-source current less fluctuating.
  • the first gate 12 and the second gate 16 are both ring-shaped, the drain-source current of the thin film transistor 10 can be enhanced, and the influence of RC delay and IR drop can be effectively reduced, so that the drain-source current is more stable.
  • the second gate 16 is formed on the active layer 14 (that is, the thin film transistor 10 has a top gate structure), the overlap between the second gate 16 and the source 19 is small, so the parasitic capacitance of the thin film transistor 10 is small.
  • the substrate 11 may be a flexible substrate or a rigid substrate.
  • the material of the flexible substrate includes, for example, at least one of polyimide, polyethylene naphthalate, and polycarbonate.
  • the material of the rigid substrate includes, for example, a glass substrate. The material used for the substrate 11 can be determined according to needs, and is not specifically limited here.
  • the material of the first gate 12 and the second gate 16 may be a conductive material, for example, including at least one of Au, Ag, Cu, Al and the like.
  • the materials of the first gate 12 and the second gate 16 can be determined according to requirements, and are not specifically limited here.
  • the first grid 12 and the second grid 16 may both have an annular shape.
  • the ring-shaped first gate 12 and the second gate 16 facilitate the transport of carriers and can increase the mobility of carriers, thereby enhancing the drain-source current of the thin film transistor 10 when the thin film transistor 10 is working, thereby effectively The RC delay and IR drop in the circuit including the thin film transistor 10 are reduced.
  • the first grid 12 and the second grid 16 may also have a square ring shape, a racetrack shape, etc., which are not specifically limited here.
  • the first gate 12 has a bottom gate structure. It should be noted that the first gate 12 of the bottom gate structure needs to be connected to other elements through connectors (not shown), so that the overlap between the first gate 12 and the source 19 is relatively large.
  • the first gate 12 can also be designed as a top gate structure, which is not specifically limited here. Since in the embodiment of the present invention, there is at least one top gate structure (the second gate 16 is a top gate structure), compared to two bottom gate structures, the parasitic capacitance of the thin film transistor 10 can be made smaller.
  • the material of the active layer 14 may be at least one of single crystal silicon, polycrystalline silicon, and oxide semiconductor materials.
  • the material of the active layer 14 is an oxide semiconductor, and the oxide semiconductor includes, for example, IGZO, indium tin oxide, ZnO, and the like.
  • the active layer 14 may have other shapes such as a circle or a rectangle, which is not specifically limited herein.
  • the circular active layer 14 can also facilitate the transport of carriers, thereby increasing the mobility of carriers.
  • the material of the drain electrode 18 and the source electrode 19 may be conductive materials, such as metals such as Au, Ag, Cu, Al, ITO, or conductive metal oxides.
  • the projection of the first opening 172 on the active layer 14 is located outside the projection of the second gate 16 on the active layer 14, and the projection of the second opening 174 on the active layer 14 is located on the first
  • the two gates 16 are within the projection on the active layer 14.
  • the drain electrode 18 is connected to the edge region of the active layer 14 through the first opening 172
  • the source electrode 19 is connected to the middle region of the active layer 14 through the second opening 174.
  • the first gate 12 and the second gate 16 are located between the drain 18 and the source 19.
  • the drain electrode 18 may have a ring shape, for example, a circular ring shape, a square ring shape, etc.
  • the source electrode 19 may have a circular shape or a square shape.
  • the projection of the first opening 172 on the active layer 14 is located within the projection of the second gate 16 on the active layer 14, and the projection of the second opening 174 on the active layer 14 is located on the first
  • the second gate 16 is outside the projection on the active layer 14.
  • the drain electrode 18 is connected to the middle region of the active layer 14 through the first opening 172
  • the source electrode 19 is connected to the edge region of the active layer 14 through the second opening 174.
  • the first gate 12 and the second gate 16 are located between the drain 18 and the source 19.
  • the drain electrode 18 may have a circular shape or a square shape
  • the source electrode 19 may have a ring shape, such as a circular ring shape or a square ring shape.
  • the thin film transistor 10 further includes a planarization layer 10b formed on the protective layer 10a.
  • the planarization layer 10b is used to further protect the thin film transistor 10 and planarize the protective layer 10a.
  • the planarization layer 10b may be formed of organic materials such as acrylic and/or inorganic materials such as silicon oxide.
  • the protective layer 10a and the planarization layer 10b are provided with through holes 10c communicating with each other.
  • the thin film transistor 10 further includes an anode electrode layer 10d formed on the planarization layer 10b, and the anode electrode layer 10d passes through the through holes. 10c is connected to the source 19.
  • the anode electrode layer 10d may use a conductive material, for example, including at least one of Au, Ag, Cu, Al and the like.
  • the anode electrode layer 10d can expand the contact area between the source electrode 19 and other components, thereby facilitating electrical connection between the source electrode 19 and other components.
  • the source electrode 19 can be connected to the light emitting diode through the anode electrode layer 10d.
  • the driving circuit 100 can be used for the display screen 1000.
  • the driving circuit 100 includes the thin film transistor 10 of any one of the above embodiments.
  • the thin film transistor 10 is used as the driving thin film transistor 10 of the driving circuit 100.
  • the first gate 12 and the second gate 16 of the driving thin film transistor 10 are both connected to the circuit.
  • the driving circuit 100 further includes a switching thin film transistor 30, and the switching thin film transistor 30 is used to control the switching of the driving thin film transistor 10.
  • the driving thin film transistor 10 is used to drive the light emitting diode 200 of the display screen 1000 to emit light.
  • the switching thin film transistor 30 is turned on, the working state of the driving thin film transistor 10 can be controlled by Vdata to control the light-emitting brightness of the light-emitting diode.
  • the switching thin film transistor 30 may also have a single gate structure, which is not specifically limited here.
  • the display screen 1000 of the embodiment of the present invention includes a light emitting diode 200 and a driving circuit 100 of any one of the above embodiments.
  • the manufacturing method of the embodiment of the present invention can be used to manufacture the thin film transistor 10 of any of the above embodiments.
  • Manufacturing methods include:
  • a first grid 12 is formed on the substrate 11, and the first grid 12 has a ring shape;
  • the buffer layer 13 is formed, and the buffer layer 13 covers the substrate 11 and the first gate 12;
  • An active layer 14 is formed on the buffer layer 13;
  • a gate insulating layer 15 is formed on the active layer 14, and the gate insulating layer 15 is ring-shaped;
  • a second gate 16 is formed on the gate insulating layer 15, and the second gate 16 has a ring shape;
  • An interlayer dielectric 17 is formed on the active layer 14 and the second gate 16 and a first opening 172 and a second opening 174 are opened on the interlayer dielectric 17;
  • a drain 18 is formed on the interlayer dielectric 17, and the drain 18 is connected to the active layer 14 through the first opening 172;
  • the first gate 12 may be formed on the substrate 11 by film formation, exposure and etching; the buffer layer 13 may be formed on the substrate 11 and the first gate 12 by film formation;
  • the active layer 14 is formed on the buffer layer 13 by film formation, exposure, etching, and annealing; the gate insulating layer 15 is formed on the active layer 14 by film formation, exposure and etching, and the gate insulating layer
  • a second gate 16 is formed on the 15;
  • an interlayer dielectric 17 is formed on the active layer 14 and the second gate 16 by film formation, exposure, and etching, and a first opening 172 and a second opening 172 are opened on the interlayer dielectric 17
  • a drain is formed on the interlayer dielectric 17 by film formation, exposure and etching, and a source is formed on the interlayer dielectric 17.
  • the drain 18 is connected to the active layer 14 through the first opening 172, and the source
  • the pole 19 is connected to the active layer 14 through the second opening 174.
  • a protective layer 10a may also be formed on the interlayer dielectric 17, the drain electrode 18, and the source electrode 19, and a planarization layer 10b is formed on the protective layer 10a, and the protective layer 10a and the planarization layer 10b are opened.
  • the anode electrode layer 10d is formed on the planarization layer 10b through the hole 10c, and the anode electrode layer 10d is connected to the source electrode 19 through the through hole 10c.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)
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Abstract

一种薄膜晶体管(10)及其制造方法、驱动电路(100)和显示屏(1000)。薄膜晶体管(10)包括基板(11)、形成在基板(11)上且呈环状的第一栅极(12)、覆盖基板(11)和第一栅极(12)的缓冲层(13)、形成在缓冲层(13)上的有源层(14)、形成在有源层(14)上且呈环状的栅极绝缘层(15)、形成在栅极绝缘层(15)上且呈环状的第二栅极(16)、覆盖有源层(14)和第二栅极(16)的层间电介质(17)、形成在层间电介质(17)上的漏极(18)和源极(19)。层间电介质(17)形成有第一开口(172)和第二开口(174)。漏极(18)通过第一开口(172)与有源层(14)连接。源极(19)通过第二开口(174)与有源层(14)连接。

Description

薄膜晶体管及其制造方法、驱动电路、显示屏 技术领域
本发明涉及电子技术，特别涉及一种薄膜晶体管、薄膜晶体管的制造方法、显示屏的驱动电路和显示屏。
背景技术
薄膜晶体管(Thin Film Transistor，TFT)被广泛地应用于主动矩阵有机发光二极体(Active-matrix organic light-emitting diode，AMOLED)显示屏的驱动电路中。然而，TFT存在漏源电流(I DS)较低、漏源电流波动较大的问题，从而导致AMOLED显示屏存在发光亮度较低、发光亮度不均一的问题。
发明内容
本发明的实施方式提供一种薄膜晶体管、薄膜晶体管的制造方法、显示屏的驱动电路和显示屏。
本发明实施方式的薄膜晶体管包括基板、形成在所述基板上的第一栅极、覆盖所述基板和所述第一栅极的缓冲层、形成在所述缓冲层上的有源层、形成在所述有源层上的栅极绝缘层、形成在所述栅极绝缘层上的第二栅极、覆盖所述有源层和所述第二栅极的层间电介质、形成在所述层间电介质上的漏极和形成在所述层间电介质上的源极。所述第一栅极呈环状。所述栅极绝缘层呈环状。所述第二栅极呈环状。所述层间电介质形成有第一开口和第二开口。所述漏极通过所述第一开口与所述有源层连接。所述源极通过所述第二开口与所述有源层连接。
本发明实施方式的显示屏的驱动电路包括上述薄膜晶体管，所述薄膜晶体管作为所述驱动电路的驱动薄膜晶体管，所述驱动电路还包括开关薄膜晶体管，所述开关薄膜晶体管用于控制所述驱动薄膜晶体管的开关，所述驱动薄膜晶体管用于驱动所述显示屏的发光二极管发光。
本发明实施方式的显示屏包括发光二极管和上述驱动电路。
本发明实施方式的薄膜晶体管的制造方法包括：提供基板；在所述基板上形成第一栅极，所述第一栅极呈环状；形成缓冲层，所述缓冲层覆盖所述基板和所述第一栅极；在所述缓冲层上形成有源层；在所述有源层上形成栅极绝缘层，所述栅极绝缘层呈环状；在所述栅极绝缘层上形成第二栅极，所述第二栅极呈环状；在所述有源层和所述第二栅极上形成层间电介质并在所述层间电介质上开设第一开口和第二开口；在所述层间电介质上形成 漏极，所述漏极通过所述第一开口与所述有源层连接；在所述层间电介质上形成源极，所述源极通过所述第二开口与所述有源层连接。
本发明实施方式提供了一种薄膜晶体管、薄膜晶体管的制造方法、显示屏的驱动电路和显示屏。由于本发明实施方式的薄膜晶体管具有两个栅极(相当于两个单栅的薄膜晶体管并联)，因此能够在薄膜晶体管工作时增强薄膜晶体管的漏源电流，从而有效地减小RC delay和IR drop的影响，使得漏源电流波动较小。另外，由于第一栅极和第二栅极均呈环状，也能够增强薄膜晶体管的漏源电流，有效地减小RC delay和IR drop的影响，使得漏源电流更加稳定。进一步地，由于第二栅极形成在有源层上(即薄膜晶体管具有顶栅结构)，第二栅极和源极交叠小，因此薄膜晶体管的寄生电容小。
本发明的实施方式的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本发明的实施方式的实践了解到。
附图说明
本发明的上述和/或附加的方面和优点从结合下面附图对实施方式的描述中将变得明显和容易理解，其中：
图1是本发明某些实施方式的薄膜晶体管的结构示意图；
图2是图1的薄膜晶体管沿线A-A的剖面示意图；
图3是本发明某些实施方式的显示屏的电路结构示意图；
图4是本发明某些实施方式的薄膜晶体管的制造方法的流程示意图。
主要元件符号附图说明：
显示屏1000、驱动电路100、薄膜晶体管(驱动薄膜晶体管)10、基板11、第一栅极12、缓冲层13、有源层14、栅极绝缘层15、第二栅极16、层间电介质17、第一开口172、第二开口174、漏极18、源极19、保护层10a、平坦化层10b、通孔10c、阳极电极层10d、开关薄膜晶体管30、开关栅极32、阻隔栅极34、发光二极管200。
具体实施方式
下面详细描述本发明的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
在本发明的描述中，需要理解的是，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中，“多 个”的含义是两个或两个以上，除非另有明确具体的限定。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通信；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
下面详细描述本发明的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
请参阅图1和图2，本发明实施方式的薄膜晶体管10包括基板11、第一栅极12、缓冲层13、有源层14、栅极绝缘层15、第二栅极16、层间电介质17、漏极18和源极19。第一栅极12形成在基板11上，第一栅极12呈环状。缓冲层13覆盖基板11和第一栅极12。有源层14形成在缓冲层13上。栅极绝缘层15形成在有源层14上，栅极绝缘层15呈环状。第二栅极16形成在栅极绝缘层15上，第二栅极16呈环状。层间电介质17覆盖有源层14和第二栅极16，层间电介质17形成有第一开口172和第二开口174。漏极18形成在层间电介质17上，漏极18通过第一开口172与有源层14连接。源极19形成在层间电介质17上，源极19通过第二开口174与有源层14连接。
本发明实施方式的薄膜晶体管10具有两个栅极(相当于两个单栅的薄膜晶体管并联)，因此能够在薄膜晶体管10工作时增强薄膜晶体管10的漏源电流，从而有效地减小RC delay和IR drop的影响，使得漏源电流波动较小。另外，由于第一栅极12和第二栅极16均呈环状，也能够增强薄膜晶体管10的漏源电流，有效地减小RC delay和IR drop的影响，使得漏源电流更加稳定。进一步地，由于第二栅极16形成在有源层14上(即薄膜晶体管10具有顶栅结构)，第二栅极16和源极19交叠小，因此薄膜晶体管10的寄生电容小。
在某些实施方式中，基板11可以是柔性基板或刚性基板。柔性基板的材料例如包括聚酰亚胺、聚萘二甲酸乙二醇酯、聚碳酸酯等材料中的至少一种。刚性基板的材料例如包括玻璃基板。基板11采用的材料可以根据需要确定，在此不做具体限定。
在某些实施方式中，第一栅极12和第二栅极16的材料可以是导电材料，例如包括Au、Ag、Cu、Al等材料中的至少一种。第一栅极12和第二栅极16的材料可以根据需要确定，在此不做具体限定。其中，第一栅极12和第二栅极16可以均呈圆环状。圆环状的第一栅极12和第二栅极16便于载流子的传输，可以提高载流子的迁移速率，从而在薄膜晶体管10工作时增强薄膜晶体管10的漏源电流，进而有效地减小包含薄膜晶体管10的电路中的RC delay和IR drop。当然，第一栅极12和第二栅极16也可以呈方环状、跑道状等，在此不做具体限定。
在本发明实施方式中，第一栅极12为底栅结构。需要说明的是，底栅结构的第一栅极12需要通过连接件(图未示)与其他元件连接，从而使得第一栅极12与源极19的交叠比较大。当然，第一栅极12也可以设计为顶栅结构，在此不做具体限定。由于本发明实施方式中，至少存在一个顶栅结构(第二栅极16是顶栅结构)，因此，相对于两个底栅结构，能够使得薄膜晶体管10的寄生电容较小。
缓冲层13和栅极绝缘层15的材料可以是绝缘材料，例如包括氧化硅、氮化硅、氧化铝等材料中的至少一种。缓冲层13可以是一层或多层(两层及两层以上)结构，栅极绝缘层15也可以是一层或多层(两层及两层以上)结构，在此不做具体限定。栅极绝缘层15呈环状，如此便于漏极18或源极19连接有源层14的中间区域。其中，栅极绝缘层15可以是圆环状、方环状、跑道状等，在此不做具体限定。
有源层14的材料可以是单晶硅、多晶硅和氧化物半导体材料等中的至少一种。在本发明实施方式中，有源层14的材料为氧化物半导体，氧化物半导体例如包括IGZO、氧化铟锡、ZnO等。有源层14可以呈圆形、或长方形等其他形状，在此不做具体限定。圆形的有源层14也可以便于载流子的传输，从而提高载流子的迁移速率。
层间电介质17的材料可以是绝缘材料，例如包括氧化硅和/或氮化硅等无机绝缘材料。当然，层间电介质17的材料也可以是有机绝缘材料，在此不做具体限定。
漏极18和源极19的材料可以是导电材料，例如包括Au、Ag、Cu、Al、ITO等金属或导电金属氧化物。
在本发明实施方式中，第一开口172在有源层14上的投影位于第二栅极16在有源层14上的投影之外，第二开口174在有源层14上的投影位于第二栅极16在有源层14上的投影之内。漏极18通过第一开口172与有源层14的边缘区域连接，源极19通过第二开口174与有源层14的中间区域连接。第一栅极12和第二栅极16位于漏极18和源极19之间。此时，漏极18可以呈环状，例如呈圆环状、方环状等，源极19可以呈圆形或方形等。
在某些实施方式中，第一开口172在有源层14上的投影位于第二栅极16在有源层14上的投影之内，第二开口174在有源层14上的投影位于第二栅极16在有源层14上的投影 之外。漏极18通过第一开口172与有源层14的中间区域连接，源极19通过第二开口174与有源层14的边缘区域连接。第一栅极12和第二栅极16位于漏极18和源极19之间。此时，漏极18可以呈圆形或方形等，源极19可以呈环状，例如呈圆环状、方环状等。
请参阅图2，在某些实施方式中，薄膜晶体管10还包括形成在层间电介质17、漏极18和源极19上的保护层10a。保护层10a用于保护薄膜晶体管10，保护层10a可以采用绝缘材料，例如氧化硅和/或氮化硅等。
在某些实施方式中，薄膜晶体管10还包括形成在保护层10a上的平坦化层10b。平坦化层10b用于进一步保护薄膜晶体管10并平坦化保护层10a。平坦化层10b可以采用丙烯酸等有机材料和/或氧化硅等无机材料形成。
在某些实施方式中，保护层10a和平坦化层10b上开设有相互连通的通孔10c，薄膜晶体管10还包括形成在平坦化层10b上的阳极电极层10d，阳极电极层10d通过通孔10c与源极19连接。阳极电极层10d可以采用导电材料，例如包括Au、Ag、Cu、Al等材料中的至少一种。通过阳极电极层10d可以扩大源极19与其他元件的接触面积，从而便于源极19与其他元件实现电连接，例如源极19可通过阳极电极层10d与发光二极管连接。
请参阅图3，本发明实施方式的驱动电路100，可以用于显示屏1000。驱动电路100包括上述任意一种实施方式的薄膜晶体管10，薄膜晶体管10作为驱动电路100的驱动薄膜晶体管10，驱动薄膜晶体管10的第一栅极12和第二栅极16均接入电路中。驱动电路100还包括开关薄膜晶体管30，开关薄膜晶体管30用于控制驱动薄膜晶体管10的开关。驱动薄膜晶体管10用于驱动显示屏1000的发光二极管200发光。在开关薄膜晶体管30开启时，可以通过Vdata控制驱动薄膜晶体管10的工作状态以控制发光二极管的发光亮度。
在某些实施方式中，开关薄膜晶体管30为双栅结构，开关薄膜晶体管30包括开关栅极32和阻隔栅极34，开关栅极32用于根据Vgate控制开关薄膜晶体管30的工作状态，阻隔栅极34设置在第一栅极12和开关薄膜晶体管30的基底之间以遮挡外界杂质扩散到开关薄膜晶体管30中。在双栅结构的开关薄膜晶体管30工作时，开关栅极32接入电路中，阻隔栅极34不接入电路中。
当然，在其他实施方式中，开关薄膜晶体管30也可以为单栅结构，在此不做具体限定。
请继续参阅图3，本发明实施方式的显示屏1000包括发光二极管200和上述任意一种实施方式的驱动电路100。
请参阅图4，本发明实施方式的制造方法，可以用于制造上述任意一种实施方式的薄膜晶体管10。制造方法包括：
01：提供基板11；
02：在基板11上形成第一栅极12，第一栅极12呈环状；
03：形成缓冲层13，缓冲层13覆盖基板11和第一栅极12；
04：在缓冲层13上形成有源层14；
05：在有源层14上形成栅极绝缘层15，栅极绝缘层15呈环状；
06：在栅极绝缘层15上形成第二栅极16，第二栅极16呈环状；
07：在有源层14和第二栅极16上形成层间电介质17并在层间电介质17上开设第一开口172和第二开口174；
08：在层间电介质17上形成漏极18，漏极18通过第一开口172与有源层14连接；
09：在层间电介质17上形成源极19，源极19通过第二开口174与有源层14连接。
在某些实施方式中，可以通过成膜、曝光和刻蚀的方式在基板11上形成第一栅极12；通过成膜的方式在基板11和第一栅极12上形成缓冲层13；通过成膜、曝光、刻蚀、退火的方式在缓冲层13上形成有源层14；通过成膜、曝光和刻蚀的方式在有源层14上形成栅极绝缘层15，在栅极绝缘层15上形成第二栅极16；通过成膜、曝光和刻蚀的方式在有源层14和第二栅极16上形成层间电介质17并在层间电介质17上开设第一开口172和第二开口174；通过成膜、曝光和刻蚀的方式在层间电介质17上形成漏极，在层间电介质17上形成源极，漏极18通过第一开口172与有源层14连接，源极19通过第二开口174与有源层14连接。
在某些实施方式中，还可以在层间电介质17、漏极18和源极19上形成保护层10a，在保护层10a上形成平坦化层10b，开设连通保护层10a和平坦化层10b的通孔10c并在平坦化层10b上形成阳极电极层10d，阳极电极层10d通过通孔10c与源极19连接。
通过制造方法制造薄膜晶体管10时，各层采用的材料以及形状等可以参考上述实施方式的薄膜晶体管10，在此不再赘述。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合所述实施方式或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。

Claims (11)

  1. 一种薄膜晶体管，其特征在于，包括：
    基板；
    形成在所述基板上的第一栅极，所述第一栅极呈环状；
    覆盖所述基板和所述第一栅极的缓冲层；
    形成在所述缓冲层上的有源层；
    形成在所述有源层上的栅极绝缘层，所述栅极绝缘层呈环状；
    形成在所述栅极绝缘层上的第二栅极，所述第二栅极呈环状；
    覆盖所述有源层和所述第二栅极的层间电介质，所述层间电介质形成有第一开口和第二开口；
    形成在所述层间电介质上的漏极，所述漏极通过所述第一开口与所述有源层连接；
    形成在所述层间电介质上的源极，所述源极通过所述第二开口与所述有源层连接。
  2. 根据权利要求1所述的薄膜晶体管，其特征在于，所述第一栅极和所述第二栅极均呈圆环状。
  3. 根据权利要求1所述的薄膜晶体管，其特征在于，所述第一开口在所述有源层上的投影位于所述第二栅极在所述有源层上的投影之外，所述第二开口在所述有源层上的投影位于所述第二栅极在所述有源层上的投影之内；
    或，所述第一开口在所述有源层上的投影位于所述第二栅极在所述有源层上的投影之内，所述第二开口在所述有源层上的投影位于所述第二栅极在所述有源层上的投影之外。
  4. 根据权利要求1所述的薄膜晶体管，其特征在于，所述有源层的材料为氧化物半导体。
  5. 根据权利要求1所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括形成在所述层间电介质、所述漏极和所述源极上的保护层。
  6. 根据权利要求5所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括形成在所述保护层上的平坦化层。
  7. 根据权利要求6所述的薄膜晶体管，其特征在于，所述保护层和所述平坦化层上开设有相互连通的通孔，所述薄膜晶体管还包括形成在所述平坦化层上的阳极电极层，所述阳极电极层通过所述通孔与所述源极连接。
  8. 一种显示屏的驱动电路，其特征在于，所述驱动电路包括权利要求1至7任意一项所述的薄膜晶体管，所述薄膜晶体管作为所述驱动电路的驱动薄膜晶体管，所述驱动电路还包括开关薄膜晶体管，所述开关薄膜晶体管用于控制所述驱动薄膜晶体管的开关，所述驱动薄膜晶体管用于驱动所述显示屏的发光二极管发光。
  9. 根据权利要求8所述的驱动电路，其特征在于，所述开关薄膜晶体管包括开关栅极和阻隔栅极，所述开关栅极用于控制所述开关薄膜晶体管的工作状态，所述阻隔栅极设置在所述第一栅极和所述开关薄膜晶体管的基底之间以遮挡外界杂质扩散到开关薄膜晶体管中。
  10. 一种显示屏，其特征在于，所述显示屏包括发光二极管和权利要求8或9所述的驱动电路。
  11. 一种薄膜晶体管的制造方法，其特征在于，所述制造方法包括：
    提供基板；
    在所述基板上形成第一栅极，所述第一栅极呈环状；
    形成缓冲层，所述缓冲层覆盖所述基板和所述第一栅极；
    在所述缓冲层上形成有源层；
    在所述有源层上形成栅极绝缘层，所述栅极绝缘层呈环状；
    在所述栅极绝缘层上形成第二栅极，所述第二栅极呈环状；
    在所述有源层和所述第二栅极上形成层间电介质并在所述层间电介质上开设第一开口和第二开口；
    在所述层间电介质上形成漏极，所述漏极通过所述第一开口与所述有源层连接；
    在所述层间电介质上形成源极，所述源极通过所述第二开口与所述有源层连接。
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