WO2020154983A1 - 薄膜晶体管及其制作方法、显示面板及显示装置 - Google Patents

薄膜晶体管及其制作方法、显示面板及显示装置 Download PDF

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Publication number
WO2020154983A1
WO2020154983A1 PCT/CN2019/074005 CN2019074005W WO2020154983A1 WO 2020154983 A1 WO2020154983 A1 WO 2020154983A1 CN 2019074005 W CN2019074005 W CN 2019074005W WO 2020154983 A1 WO2020154983 A1 WO 2020154983A1
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Prior art keywords
layer
gate
thin film
film transistor
electrode
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PCT/CN2019/074005
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English (en)
French (fr)
Inventor
邹灿
蔡武卫
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深圳市柔宇科技有限公司
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Priority to CN201980073511.7A priority Critical patent/CN113261114A/zh
Priority to PCT/CN2019/074005 priority patent/WO2020154983A1/zh
Publication of WO2020154983A1 publication Critical patent/WO2020154983A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the embodiments of the present application relate to the technical field of thin film transistor manufacturing, in particular to a thin film transistor and a manufacturing method thereof, a display panel and a display device.
  • Thin Film Transistors are widely used in the display field. Thin Film Transistors have the advantages of thin thickness, small size, and superior switching performance.
  • the traditional thin film transistor adopts a single gate structure, and the parasitic capacitance is relatively large, which greatly affects the driving of the display panel, thereby reducing the display effect of the display screen.
  • the embodiments of the present application provide a thin film transistor and a manufacturing method thereof, a display panel and a display device, which can reduce parasitic capacitance.
  • a thin film transistor including:
  • the second gate layer is stacked on the second insulating layer and far away from the active layer, wherein the plane where the active layer is located is the projection surface, and the first gate layer is on the projection surface
  • the orthographic projection of and the orthographic projection of the second gate layer on the projection surface at least partially overlap
  • the drain-source layer is in contact with the active layer, and the third insulating layer is located between the drain-source layer and the second gate layer.
  • the orthographic projection of the first gate layer on the projection surface and the orthographic projection of the second gate layer on the projection surface all overlap.
  • the first gate layer and the second gate layer have the same electric potential.
  • both the first gate layer and the second gate layer have a ring shape.
  • the drain-source layer includes:
  • the first electrode layer has a ring shape, the first electrode layer is in contact with the active layer, and the first electrode layer surrounds the outer circumference of the third insulating layer, and the first electrode layer includes an inner diameter hollow portion ;
  • the second electrode layer is laminated on the inner diameter hollow portion, and the second electrode layer is in contact with the active layer, and the third insulating layer is located between the second electrode layer and the first electrode layer between.
  • the first electrode layer is a drain layer, and the second electrode layer is a source layer;
  • the first electrode layer is a source layer
  • the second electrode layer is a drain layer
  • the thin film transistor further includes a fourth insulating layer laminated on a part of the first electrode layer and the entire area of the second electrode layer.
  • the fourth insulating layer is further laminated on the third insulating layer and away from the second gate layer.
  • the thin film transistor further includes a first electrode terminal connected to a part of the first electrode layer that is not laminated with the fourth insulating layer.
  • a through hole is opened in a region where the fourth insulating layer is laminated on the second electrode layer;
  • the thin film transistor further includes a second electrode terminal, and the second electrode terminal is connected to the second electrode layer through the through hole.
  • the thin film transistor further includes a first gate terminal, and the first gate terminal is connected to the first gate layer.
  • the thin film transistor further includes a second gate terminal, and the second gate terminal is connected to the second gate layer.
  • the thin film transistor further includes an interlayer dielectric layer, and the interlayer dielectric layer is located between the first electrode layer and the first insulating layer.
  • a thin film transistor substrate includes the thin film transistor.
  • a display panel including:
  • the thin film transistor substrate and
  • the light-emitting module is arranged on the thin film transistor substrate.
  • a display device includes:
  • the display panel can be contained in the casing.
  • a method for manufacturing a thin film transistor including:
  • a second insulating layer, a second gate layer, and a third insulating layer are sequentially formed on a partial area of the active layer, wherein, taking the plane where the active layer is located as the projection plane, the first gate layer
  • the orthographic projection on the projection surface and the orthographic projection of the second grid layer on the projection surface at least partially overlap;
  • a drain-source layer is formed on the third insulating layer and the remaining area of the active layer to obtain a thin film transistor.
  • the orthographic projection of the first gate layer on the projection surface and the orthographic projection of the second gate layer on the projection surface all overlap.
  • both the first gate layer and the second gate layer have a ring shape.
  • the forming a first gate layer on the substrate includes:
  • the bottom gate metal film is patterned to obtain a ring-shaped first gate layer.
  • the step of sequentially forming a second insulating layer and a second gate layer on a partial area of the active layer includes:
  • the top gate metal film is patterned to obtain a ring-shaped second gate layer.
  • the forming a drain-source layer on the third insulating layer and the remaining area of the active layer includes:
  • the electrode metal film is patterned to obtain a first electrode layer and a second electrode layer, wherein the first electrode layer has a ring shape, the first electrode layer includes an inner diameter hollow portion, and the second electrode layer is laminated on the In the inner diameter hollow portion, the second electrode layer is in contact with the active layer, and the third insulating layer is located between the second electrode layer and the first electrode layer.
  • the first electrode layer is a drain layer, and the second electrode layer is a source layer;
  • the first electrode layer is a source layer
  • the second electrode layer is a drain layer
  • the method further includes:
  • An interlayer dielectric layer is formed between the first electrode layer and the first insulating layer.
  • the method further includes:
  • a fourth insulating layer is formed on a partial area of the first electrode layer, all areas of the second electrode layer, and the third insulating layer.
  • the method further includes:
  • a first electrode terminal is drawn in a part of the first electrode layer that is not laminated with the fourth insulating layer.
  • the method further includes:
  • a through hole is opened in the area where the fourth insulating layer is laminated on the second electrode layer;
  • the second electrode terminal is led out from the through hole.
  • the method further includes:
  • a first gate terminal is drawn from the first gate layer.
  • the method further includes:
  • a second gate terminal is drawn from the second gate layer.
  • the forming a first insulating layer and an active layer on the substrate includes:
  • the active layer is patterned.
  • the plane where the active layer is located is the projection plane
  • the orthographic projection of the first gate layer on the projection plane is the same as that of the second gate layer on the projection plane.
  • the orthographic projections are at least partially overlapped. Therefore, when the same external voltage is applied to the first gate layer and the second gate layer, the respective potentials of the first gate layer and the second gate layer in the overlapped portion of the orthographic projection are also equal to each other.
  • the electric field force of the first gate layer in the overlapping part of the orthographic projection on the active layer is equal to the electric field force of the second gate layer in the active layer of the overlapping part of the orthographic projection.
  • the thin film transistor with this structure can reduce the parasitic capacitance.
  • FIG. 1a is a schematic cross-sectional view of a thin film transistor provided by an embodiment of the present application
  • FIG. 1b is a schematic projection view of the first gate layer and the second gate layer in FIG. 1a with the active layer as the projection surface;
  • 2a is a schematic structural diagram of a thin film transistor when the second gate layer is exposed according to another embodiment of the present application;
  • FIG. 2b is a schematic cross-sectional view of the thin film transistor provided in FIG. 2a taken along the AA" direction;
  • FIG. 2c is a schematic cross-sectional view of the thin film transistor provided in FIG. 2a taken along the BB" direction;
  • FIG. 2d is a schematic cross-sectional view of the thin film transistor provided in FIG. 2a taken along the CC" direction;
  • FIG. 2e is a schematic cross-sectional view of the thin film transistor provided in FIG. 2a taken along the DD" direction;
  • Fig. 3a is a schematic diagram of a conductive channel of a rectangular thin film transistor provided by the conventional technology in a saturated state;
  • Fig. 3b is a schematic diagram of a conductive channel of a ring-shaped thin film transistor provided by the conventional technology in a saturated state;
  • FIG. 4 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • FIG. 6a is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present application
  • 6b is a schematic flowchart of a method for manufacturing a thin film transistor provided by an embodiment of the present application.
  • Figure 6c is a block diagram of the flow of S62 in Figure 6a;
  • Fig. 6d is a flowchart of S63 in Fig. 6a;
  • Fig. 6e is a flowchart of S64 in Fig. 6a;
  • FIG. 6f is a flowchart of a method for manufacturing a thin film transistor according to another embodiment of the present application.
  • the positional relationship between the layers uses terms such as “laminated” or “formed” or “applied” or “set”. It can be understood by those skilled in the art that: any term such as “stacking” or “forming” or “applying” can cover all the ways, types and techniques of “stacking”.
  • sputtering electroplating, molding, chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), evaporation, hybrid physical-chemical vapor deposition (Hybrid Physical-Chemical Vapor Deposition, HPCVD) , Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), etc.
  • CVD chemical Vapor Deposition
  • PVD physical vapor deposition
  • evaporation hybrid physical-chemical vapor deposition
  • HPCVD Hybrid Physical-Chemical Vapor Deposition
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • the structural shape of the thin film transistor provided by the embodiments of the present application can be square, rectangular, ring or diamond, etc. It is understandable that the "ring" herein includes an approximate ring, as long as those skilled in the art according to the content described herein, Other replacements or improvements are made to the structure and shape of the thin film transistor, and all thin film transistors with a certain structure and shape should fall within the protection scope of the embodiments of the present application.
  • a thin film transistor 10 provided by the present invention includes: a first gate layer 11, a first insulating layer 12, an active layer 13, a second insulating layer 14, a second gate layer 15, a third insulating layer Layer 16 and drain-source layer 17.
  • the first gate layer 11 includes a deposition surface 11 a, the first insulating layer 12 is laminated on the deposition surface 11 a, and the active layer 13 is laminated on the first insulating layer 12 and away from the first gate layer 11.
  • the second insulating layer 14 is stacked on a partial area of the active layer 13 and away from the first insulating layer 12.
  • the second gate layer 15 is stacked on the second insulating layer 14 and away from the active layer 13, and the third insulating layer 16 surrounds the second gate layer 15.
  • the drain-source layer 17 is in contact with the active layer 13, and the third insulating layer 16 is located between the drain-source layer 17 and the second gate layer 15.
  • the orthographic projection of the first gate layer 11 on the projection plane and the orthographic projection of the second gate layer 15 on the projection plane are at least partially coincide.
  • the first shadow pattern 131 formed on the plane where the active layer 13 is located is the first gate layer. 11 orthographic projection.
  • the second shadow pattern 132 formed on the plane where the active layer 13 is located is the front of the second gate layer 15. projection.
  • there is at least a partial overlap between the first shadow pattern 131 and the second shadow pattern 132 for example, the overlap area 1b1 as shown in FIG. 1b.
  • the potentials of the corresponding gate portions between the first gate layer 11 and the second gate layer 15 are equal to each other.
  • the electric field force of the first gate layer 11 on the active layer 13 of the overlapped portion is equal to the electric field force of the second gate layer 15 on the active layer 13 of the overlapped portion of the orthographic projection. Therefore, the first gate layer of the overlapped portion of the orthographic projection 11 and the active layer 13 and between the second gate layer 15 and the active layer 13 in the overlapped portion of the orthographic projection do not constitute conditions for generating parasitic capacitance. Therefore, the thin film transistor with this structure can reduce the parasitic capacitance. .
  • the orthographic projection of the first gate layer 11 on the projection surface and the orthographic projection of the second gate layer 15 on the projection surface all overlap, that is, the first gate layer 11 and the second gate layer 15 It is opposite, and the shape and structure of the first gate layer 11 and the second gate layer 15 are the same. Since the electric field force of the entire first gate layer 11 on the active layer 13 is equal to the electric field force of the entire second gate layer 15 on the active layer 13, the first gate layer 11 and the active layer 13 There are no conditions for generating parasitic capacitance between the second gate layer 15 and the active layer 13. Therefore, the thin film transistor with this structure can greatly reduce the parasitic capacitance.
  • the first gate layer 11 and the second gate layer 15 may be directly connected by wires.
  • the first gate layer 11 may be formed by depositing metal on the substrate using a related deposition process.
  • the materials of the first gate layer 11, the second gate layer 15 and the drain-source layer 17 can be selected from metals or metal oxides with high work functions such as Cu, Ni, ITO, Au.
  • the first gate layer 11, the active layer 13, the second gate layer 15 and the drain-source layer 17 may have a multilayer structure.
  • the multilayer electrode includes a metal layer having Ag, Mg, Al, PS, Pd, Au, Ni, Nd, Ir, Cr or a mixture thereof and a transparent conductive oxide layer including a transparent conductive oxide material.
  • the transparent conductive oxide material may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), and the like.
  • the multilayer electrode may have a three-layer structure configured to include a first transparent conductive oxide layer, a metal layer, and a second transparent conductive oxide layer.
  • the multilayer electrode may also have a two-layer structure configured to include a transparent conductive oxide layer and a metal layer.
  • the first insulating layer 12 or the second insulating layer 14 uses ammonia (NH 3 ) and monosilane (SiH 4 ) as reaction source gases, and uses radio frequency plasma enhanced chemical vapor deposition (RF-PECVD)
  • RF-PECVD radio frequency plasma enhanced chemical vapor deposition
  • the method deposits a series of hydrogenated amorphous silicon nitride (a-SiNx:H) films on the corresponding layer structure.
  • the silicon nitride film has excellent insulation and withstand voltage performance and better interface characteristics.
  • the thickness of the first insulating layer 12 is 100-400 nm. Because of its good interface characteristics, the prepared semiconductor device has a smaller leakage current, which improves the electrical performance of the device.
  • the first insulating layer 12 or the second insulating layer 14 may also adopt a single-layer silicon dioxide (SiO 2 ) or double-layer silicon dioxide/silicon nitride (SiO 2 /SiNx) structure.
  • the active layer 13 is formed by sputtering a target material on the first insulating layer 12 using related processes.
  • the active layer 13 may be sputtered from a high-mobility amorphous indium gallium zinc oxide (a-IGZO) target and a common amorphous indium gallium zinc oxide target.
  • a-IGZO high-mobility amorphous indium gallium zinc oxide
  • the prepared active layer 13 has different electrical properties.
  • the active layer 13 has high carrier mobility.
  • Amorphous indium gallium zinc oxide (a-IGZO) semiconductors have many excellent properties, and a-IGZO semiconductors are superior to other amorphous semiconductors in performance.
  • the amorphous indium gallium zinc oxide thin film transistor (a-IGZO-SFS) has been able to achieve a switching current ratio of ⁇ 10 10 , and the electron mobility of a-IGZO is between 2-50cm 2 /Vs, which is an a-Si panel 20-50 times higher than that, and the wiring becomes thinner when prepared, which can achieve 4 times the resolution under the same transmittance.
  • IGZO thin film transistors have superior turn-off performance, low leakage current and low power consumption.
  • the active layer 13 may also be a variety of metal oxide semiconductors.
  • Quaternary metal oxides such as indium tin gallium zinc oxide (InSnGaZnO) based materials, such as indium gallium zinc oxide (InGaZnO) based materials, indium tin zinc oxide (InSnZnO) based materials, indium aluminum zinc oxide based Materials (InAlZnO), materials based on indium hafnium zinc oxide (InHfZnO), materials based on tin gallium zinc oxide (SnGaZnO), materials based on aluminum gallium zinc oxide (AlGaZnO), or materials based on tin aluminum zinc oxide (SnAlZnO) materials such as ternary metal oxides, and materials such as indium zinc oxide (InZnO)-based materials, tin-zinc oxide (SnZnO)-based materials, aluminum-zinc oxide (AlZnO)-based materials, zinc-magnesium-based materials,
  • the third insulating layer 16 serves as an interlayer insulating layer, which can passivate the back channel of the active layer, which helps to improve the electrical characteristics of the thin film transistor.
  • the third insulating layer 16 uses a silicon nitride insulating layer, which has excellent photoelectric properties, mechanical properties, and strong barriers to impurity particle diffusion and water vapor penetration.
  • the thinner silicon nitride insulating layer is not easy to block the diffusion phenomenon, and as the thickness of the third insulating layer 16 increases, the contaminant concentration at the interface of the active layer decreases, but when the thickness exceeds a critical value, the contaminant concentration The thickness of the third insulating layer 16 will not be greatly reduced but will reach a minimum value, so the thickness of the third insulating layer 16 is set to be 100-400 nm.
  • the third insulating layer 16 may also adopt a single-layer silicon dioxide (SiO 2 ) or double-layer silicon dioxide/silicon nitride (SiO 2 /SiNx) structure.
  • the first gate layer 11 and the second gate layer 15 are both in a ring shape.
  • the inner ring of the first gate layer 11 is hollow, and the first insulating layer 12 fills the inner ring of the first gate layer 11.
  • the first The inner ring of the second gate layer 15 is hollow, and the third insulating layer 16 and the drain-source layer 17 sequentially fill the inner ring of the second gate layer 15.
  • the first gate layer 11 and the second gate layer 15 is opposite to each other.
  • the first gate layer 11 and the second gate layer 15 may not be arranged in a manner of being opposite, and the two may be arranged in cross and staggered positions, that is, the first gate layer 11 At least partially overlap with the orthographic projection of the second gate layer 15 on the active layer 13 as the projection plane.
  • the cross-sectional shapes of the first gate layer 11 and the second gate layer 15 are trapezoidal, and in the thin film transistor 10, the first gate layer 11 serves as the bottom gate, and the second gate layer 15 serves as the top gate.
  • the thin film transistor 10 of the structure has a strong gate driving capability.
  • this article again provides cross-sectional views of the thin film transistor 10 shown in FIGS. 2c to 2e.
  • the thin film transistor 10 adopts a ring-shaped double gate structure, when the cross section of the thin film transistor 10 is viewed in the direction perpendicular to the CC" direction, the first structure layer as the bottom gate is blocked.
  • the gate layer 11 may show the second gate layer 15 as a top gate.
  • the thin film transistor 10 adopts a ring-shaped double-gate structure, when the cross-section of the thin film transistor 10 is viewed in a direction perpendicular to the DD" direction, other structural layers block the top gate.
  • the second gate layer 15 may show the first gate layer 11 as a bottom gate.
  • the drain-source layer 17 includes: a first electrode layer 171 and a second electrode layer 172.
  • the first electrode layer 171 has a ring shape, the first electrode layer 171 is in contact with the active layer 13, and the first electrode layer 171 surrounds the outer circumference of the third insulating layer 16, and the first electrode layer 171 includes an inner diameter hollow portion.
  • the second electrode layer 172 is located in the hollow part of the inner diameter, and the second electrode layer 172 is in contact with the active layer 13, and the third insulating layer 16 is located between the second electrode layer 172 and the first electrode layer 171.
  • the first electrode layer 171 is a drain layer
  • the second electrode layer 172 is a source layer.
  • the first electrode layer 171 is a source layer
  • the second electrode layer 172 is a drain layer.
  • the thin film transistor device provided by the traditional technology adopts the top gate structure, which is prone to short-channel effects, that is, when the thin film transistor device works in the saturation region and the device channel is short, the drain-source voltage V As ds increases, the effective channel length becomes shorter, and the drain-source current I ds increases significantly.
  • the following describes the technical effects brought about by the annular drain layer provided in the embodiments of the present application in conjunction with related examples. It can be understood that the description is not used to limit the protection scope of the present application, as described below:
  • I ds 0.5 ⁇ C OX ⁇ (V gs -V th ) 2 ⁇ W/L
  • I ds is the drain-source current
  • ⁇ is the electron mobility
  • C OX is the gate capacitance density
  • V gs is the drain-source voltage
  • V th is the threshold voltage
  • W is the conductive channel width
  • L is the conductive channel length
  • W EFF is the effective width of the conductive channel
  • W mask is the width of the conductive channel when masking
  • L EFF is the effective length of the conductive channel
  • L mask is the length of the conductive channel when masking
  • ⁇ L is the length of the depletion layer.
  • R 1 is the radius of the annular source
  • R 2 is the radius of the annular drain.
  • the drain applied voltage, W EFF changes with the change of L EFF , that is, L EFF decreases, and W EFF decreases.
  • the ring-shaped thin film transistor The output resistance of is infinite, so when the drain-source voltage V gs increases, the drain-source current I ds does not change.
  • the thin film transistor provided by the embodiments of the present application adopts a structure in which a ring-shaped drain layer and a source layer are filled in the hollow part of the inner diameter of the ring-shaped drain layer, and the channel size is short, which can overcome the short channel effect.
  • the thin film transistor adopts a dual-gate opposed structure. Compared with the traditional single gate structure (including bottom gate or top gate), its parasitic capacitance is small, and the output current is stable and large, which greatly improves the driving pixel The capacity of the unit.
  • the thin film transistor 10 further includes a fourth insulating layer 18, which is laminated on a part of the first electrode layer 171 and all of the second electrode layer 172 area.
  • a part of the fourth insulating layer 18 where the first electrode layer 171 is not laminated is used for drawing out the terminal of the first electrode layer 171, for example, drawing out the drain terminal of the drain layer.
  • the thin film transistor with such a structure can protect the first electrode layer 171 and the second electrode layer 172 from the influence of other impurity particles, and contribute to the improvement of the electrical characteristics of the thin film transistor.
  • the fourth insulating layer 18 is also stacked on the third insulating layer 16 and away from the second gate layer 15.
  • the fourth insulating layer 18 can planarize the third insulating layer 16 and help to pattern the third insulating layer 16.
  • the thin film transistor 10 further includes an interlayer dielectric layer 19, and the interlayer dielectric layer 19 is located between the first electrode layer 171 and the first insulating layer 12. Due to the need to lead out terminals on the first electrode layer 171 located on the interlayer dielectric layer 19, the interlayer dielectric layer 19 can protect the thin film transistor 10 from moving particles or other undesirable impurity charges, and it can attract Impurity charges prevent the active layer 13 from being affected by impurity charges and the like.
  • the thin film transistor 10 further includes a first electrode terminal 101, a second electrode terminal 102, a first gate terminal 103, and a second gate terminal 104.
  • the first electrode terminal 101 is connected to a partial region of the first electrode layer 171 that is not laminated with the fourth insulating layer 18.
  • a through hole 181 is opened in a region where the fourth insulating layer 18 is laminated on the second electrode layer 172, and the second electrode terminal 102 is connected to the second electrode layer 172 through the through hole 181.
  • the first electrode terminal 101 may be a drain terminal
  • the second electrode terminal 102 is a source terminal
  • the first electrode terminal 101 may be a source terminal and the second electrode terminal 102 is a drain terminal.
  • the first gate terminal 103 is connected to the first gate layer 11, and the second gate terminal 104 is connected to the second gate layer 15.
  • the first electrode terminal 101, the second electrode terminal 102, the first gate terminal 103, and the second gate terminal 104 can be connected to different voltages or ground terminals, so that the thin film transistor can complete specific electrical Features.
  • the thin film transistor 10 provided by the embodiment of the present application adopts a double-gate structure, and uses the plane where the active layer 13 is located as the projection surface.
  • the orthographic projection of the first gate layer 11 on the projection surface and the second gate layer 15 The orthographic projections on the projection surface are at least partially overlapped. Therefore, when the same external voltage is applied to the first gate layer 11 and the second gate layer 15, the orthographic projections overlap the first gate layer 11 and the second gate layer.
  • the respective potentials of the layers 15 are also equal to each other.
  • the electric field force of the first gate layer 11 on the active layer 13 in the overlapping part of the orthographic projection is equal to the electric field force of the second gate layer 15 on the active layer 13 in the overlapping part of the orthographic projection.
  • the thin film transistor 10 adopts a ring-shaped drain layer (or source layer).
  • the source layer is filled in the hollow part of the inner diameter of the ring-shaped drain layer.
  • the channel size is short, which can overcome the short channel effect, and the output current is stable and Relatively large, strong driving ability.
  • the thin film transistor provided by the embodiments of the present application can be applied to various types of suitable display panels, such as thin film transistor liquid crystal display panels (TFT-LCD) or OLED (Organic Light-Emitting Diode, organic light emitting diode) display panels, OLED displays
  • TFT-LCD thin film transistor liquid crystal display panels
  • OLED Organic Light-Emitting Diode, organic light emitting diode
  • the panel can be a flexible display panel, a transparent flexible display panel, and so on.
  • the thin film transistors provided by the embodiments of the present application can be combined with any suitable capacitors, resistors, etc. to form any suitable driving circuit.
  • the thin film transistors can be used to form a PMOLED drive or an AMOLED drive.
  • thin film transistors can also be made of various suitable types of materials. For example, they can be made into low-temperature poly-silicon thin film transistors (LTP-Si TFT), amorphous silicon TFTs, polysilicon TFTs, Oxide semiconductor TFT or organic TFT.
  • LTP-Si TFT low-temperature poly-silicon thin film transistors
  • amorphous silicon TFTs amorphous silicon TFTs
  • polysilicon TFTs polysilicon TFTs
  • Oxide semiconductor TFT Oxide semiconductor TFT or organic TFT.
  • the embodiments of the present application provide a thin film transistor substrate.
  • the thin film transistor substrate includes a plurality of thin film transistors.
  • the thin film transistors are fabricated on the thin film transistor substrate by any suitable process.
  • the thin film transistors may be as shown in FIG. 1a. To the thin film transistor illustrated in Figure 2e.
  • the thin film transistor substrate may use a flexible substrate.
  • the flexible substrate includes flexible materials such as thin glass, metal foil, or plastic substrate.
  • the plastic substrate includes coatings on both sides of the base film.
  • the base film includes such as polyimide (PI), polycarbonate (PC), polyethylene glycol terephthalate (PET), polyethersulfone (PES), polyethylene film (PEN), fiber reinforced Plastic (FRP) and other resins.
  • the plane where the active layer is located is the projection plane
  • the orthographic projection of the first gate layer on the projection plane and the orthographic projection of the second gate layer on the projection plane are at least partially Therefore, when the same external voltage is applied to the first gate layer and the second gate layer, the respective potentials of the first gate layer and the second gate layer in the overlapped portion of the orthographic projection are also equal to each other, and the overlapped portion of the orthographic projection
  • the electric field force of the first gate layer in the active layer is equal to the electric field force of the second gate layer in the overlapped part of the orthographic projection on the active layer.
  • the thin film transistor with this structure can reduce the parasitic capacitance.
  • the embodiments of the present application provide a display panel.
  • the display panel 40 includes a thin film transistor substrate 41 and a light emitting module 42, and the light emitting module 42 is disposed on the thin film transistor substrate 41.
  • Thin film transistors are prepared on the thin film transistor substrate 41, where the thin film transistors may be the thin film transistors illustrated in FIGS. 1a to 2e.
  • the light emitting module 42 is used to emit light sources, and it may include, for example, an anode, an organic functional layer, a cathode, a polarizer, a touch module, and so on.
  • the organic functional layer may be composed of the following structural layers in sequence: a hole injection layer, a hole transport layer, an organic light emitting layer, an electron transport layer, and an electron injection layer.
  • the plane where the active layer is located is the projection plane
  • the orthographic projection of the first gate layer on the projection plane and the orthographic projection of the second gate layer on the projection plane are at least partially Therefore, when the same external voltage is applied to the first gate layer and the second gate layer, the respective potentials of the first gate layer and the second gate layer in the overlapped portion of the orthographic projection are also equal to each other, and the overlapped portion of the orthographic projection
  • the electric field force of the first gate layer in the active layer is equal to the electric field force of the second gate layer in the overlapped part of the orthographic projection on the active layer.
  • the thin film transistor with this structure can reduce the parasitic capacitance.
  • the embodiments of the present application provide a display device.
  • the display device 50 includes a housing 51 and a display panel 52.
  • the display panel 52 can be accommodated in the housing 51.
  • the display panel 52 may be the display panel described in the foregoing embodiment.
  • the display panel 52 can be a flexible display panel.
  • the display panel 52 can be retracted into the housing 51, and the user can pull the display panel 52 out of the housing 51 by pulling the display panel 52 by hand.
  • the plane where the active layer is located is the projection plane
  • the orthographic projection of the first gate layer on the projection plane and the orthographic projection of the second gate layer on the projection plane are at least partially Therefore, when the same external voltage is applied to the first gate layer and the second gate layer, the respective potentials of the first gate layer and the second gate layer in the overlapped portion of the orthographic projection are also equal to each other, and the overlapped portion of the orthographic projection
  • the electric field force of the first gate layer in the active layer is equal to the electric field force of the second gate layer in the overlapped part of the orthographic projection on the active layer.
  • the thin film transistor with this structure can reduce the parasitic capacitance.
  • the embodiments of the present application provide a method for manufacturing a thin film transistor. Please refer to FIG. 6a and FIG. 6b together, the manufacturing method 600 of a thin film transistor includes:
  • the substrate is made of transparent materials such as glass, and has been pre-cleaned.
  • the substrate due to the relatively high content of metal impurities such as aluminum, barium, and sodium in the traditional soda glass, the diffusion of metal impurities is likely to occur during the high-temperature treatment process, so the substrate can also be made of alkali-free glass.
  • the substrate may also be made of flexible materials such as polyimide.
  • a first insulating layer (not shown) and an active layer 13 are sequentially grown on the first gate layer 11. Secondly, coat a layer of photoresist on the active layer 13, use a mask to expose the first insulating layer and the active layer 13, and develop after the exposure. After the development, the active layer 13 and the first insulating layer are respectively performed The layer is etched, and finally the photoresist is stripped to obtain a patterned active layer 13.
  • a second insulating layer, a second gate layer, and a third insulating layer are sequentially formed on a part of the active layer, wherein the plane where the active layer is located is the projection plane, and the first gate layer is on the projection plane.
  • the orthographic projection and the orthographic projection of the second grid layer on the projection surface at least partially overlap;
  • a second insulating layer (not shown) and a second gate layer 15 are grown on the patterned active layer 13.
  • a layer of photoresist is coated on the second gate layer 15 and a mask is used to expose the second gate layer 15 and the second insulating layer. After exposure and development, after the development, the second gate layer 15 and the second insulating layer are respectively etched, and finally the photoresist is stripped off, thereby obtaining a patterned second gate layer 15.
  • a third insulating layer 16 is grown on the patterned second gate layer 15.
  • the thin film transistor obtained by the thin film transistor manufacturing method provided by the embodiment of the present application adopts a double gate structure, and the plane where the active layer 13 is located is the projection surface.
  • the orthographic projection of the first gate layer 11 on the projection surface and the second gate The orthographic projection of the pole layer 15 on the projection surface at least partially overlaps, and therefore, its parasitic capacitance is small.
  • the orthographic projection of the first gate layer 11 on the projection surface and the orthographic projection of the second gate layer 15 on the projection surface all overlap, that is, the first gate layer 11 and the second gate layer 15 It is opposite, and the shape and structure of the first gate layer 11 and the second gate layer 15 are the same. Since the electric field force of the entire first gate layer 11 on the active layer 13 is equal to the electric field force of the entire second gate layer 15 on the active layer 13, the first gate layer 11 and the active layer 13 There are no conditions for generating parasitic capacitance between the second gate layer 15 and the active layer 13. Therefore, the thin film transistor with this structure can greatly reduce the parasitic capacitance.
  • the user can form the first gate layer 11 and the second gate layer 15 into a ring-shaped gate through a suitable patterning process.
  • S62 includes:
  • a buffer layer is formed on the substrate.
  • a bottom-gate metal film is deposited on the buffer layer.
  • a layer of photoresist (Photoresist, PR glue) is coated on the bottom grid metal film.
  • S63 includes:
  • a layer of photoresist is coated on the top gate metal film, and the top gate metal film and the second insulating layer are exposed using a mask. After the exposure, the top gate metal film is developed. Perform ring-shaped etching with the second insulating layer, strip the photoresist, and obtain a ring-shaped second gate layer 15.
  • the drain layer (or source layer) can be made into a ring shape, and the source layer (or drain layer) is filled in the hollow part of the inner diameter of the drain layer (or source layer) to produce such a structure
  • the thin film transistor has a short channel size, which can overcome the short channel effect, and the output current is stable and relatively large, and the driving ability is strong.
  • S64 includes:
  • first electrode layer 171 and a second electrode layer 172 Pattern the electrode metal film to obtain a first electrode layer 171 and a second electrode layer 172, wherein the first electrode layer has a ring shape, the first electrode layer 171 includes an inner diameter hollow portion, and the second electrode layer 172 is laminated on the inner diameter hollow portion , The second electrode layer 172 is in contact with the active layer, and the third insulating layer is located between the second electrode layer 172 and the first electrode layer 171.
  • an electrode metal film is grown on the patterned third insulating layer and the remaining area of the active layer.
  • coat a layer of photoresist on the electrode metal film and use a mask to expose the source and drain electrodes of the electrode metal film. After the development, the source and drain electrodes are etched and the photoresist is stripped to form a pattern.
  • the source and drain layer In some embodiments, the first electrode layer 171 is a drain layer, and the second electrode layer 172 is a source layer. In other embodiments, the first electrode layer 171 is a source layer, and the second electrode layer 172 is a drain layer.
  • an interlayer dielectric layer is formed between the first electrode layer 171 and the first insulating layer. Since it is necessary to lead out terminals on the first electrode layer 171 located on the interlayer dielectric layer, the interlayer dielectric layer can protect the thin film transistor from moving particles or other undesirable impurity charges, and it can attract impurity charges from the electrode terminals, Prevent the active layer from being affected by impurity charges and the like.
  • the manufacturing method 600 of a thin film transistor further includes:
  • the first electrode terminal 101 is led out in a part of the first electrode layer 171 that is not laminated by the fourth insulating layer.
  • the first electrode terminal 101 is Drain terminal.
  • a through hole is opened in the area where the fourth insulating layer is laminated on the second electrode layer 172, and the second electrode terminal is led out from the through hole.
  • the second electrode terminal 102 is the source terminal.
  • first A fourth insulating layer is grown on a partial area of the first electrode layer 171, the entire area of the second electrode layer 172, and the third insulating layer.
  • a layer of photoresist is coated on the fourth insulating layer.
  • the fourth insulating layer is exposed using a mask, and after the development is completed, etching and photoresist stripping are performed to obtain through holes.
  • the first gate terminal 103 is drawn from the first gate layer 11 and the second gate terminal 104 is drawn from the second gate layer 15.
  • the first electrode terminal 101, the second electrode terminal 102, the first gate terminal 103, and the second gate terminal 104 can be connected to different voltages or ground terminals, so that the thin film transistor can complete specific electrical Features.
  • the thin film transistor manufactured by the method provided in the embodiments of the present application has small parasitic capacitance, a channel size section, can overcome the short channel effect, and has a stable and relatively large output current, and has a strong driving ability.

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Abstract

本申请实施例公开薄膜晶体管及其制作方法、显示面板及显示装置，薄膜晶体管(10)包括依次层叠设置的第一栅极层(11)、第一绝缘层(12)、有源层(13)、第二绝缘层(14)、第二栅极层(15)、第三绝缘层(16)及漏源层(17)，以有源层(13)所在平面为投影面，第一栅极层(11)在投影面的正投影与第二栅极层(15)在投影面的正投影至少部分重合，由于第一栅极层(11)与有源层(13)之间以及第二栅极层(15)与有源层(13)之间都不构成产生寄生电容的条件，因此，其能够降低寄生电容。

Description

薄膜晶体管及其制作方法、显示面板及显示装置 技术领域
本申请实施例涉及薄膜晶体管制作技术领域，尤其涉及一种薄膜晶体管及其制作方法、显示面板及显示装置。
背景技术
薄膜晶体管(Thin Film Transistor，TFT)广泛应用于显示领域，薄膜晶体管具有厚度薄、体积小、开关性能优越等优点。
传统薄膜晶体管采用单栅结构，寄生电容比较大，极大影响显示面板的驱动，从而降低显示画面的显示效果。
发明内容
本申请实施例提供一种薄膜晶体管及其制作方法、显示面板及显示装置，其能够降低寄生电容。
本申请实施例解决其技术问题提供以下技术方案：
一种薄膜晶体管，包括：
第一栅极层；
第一绝缘层，层叠于所述第一栅极层上；
有源层，层叠于所述第一绝缘层上并远离所述第一栅极层；
第二绝缘层，层叠于所述有源层的部分区域并远离所述第一绝缘层；
第二栅极层，层叠于所述第二绝缘层上并远离所述有源层，其中，以所述有源层所在的平面为投影面，所述第一栅极层在所述投影面的正投影与所述第二栅极层在所述投影面的正投影至少部分重合；
第三绝缘层，围绕所述第二栅极层；
漏源层，与所述有源层接触，并且，所述第三绝缘层位于所述漏源层与所述第二栅极层之间。
可选地，所述第一栅极层在所述投影面的正投影与所述第二栅极层在所述投影面的正投影全部重合。
可选地，所述第一栅极层与所述第二栅极层的电势相同。
可选地，所述第一栅极层与所述第二栅极层皆呈环形。
可选地，所述漏源层包括：
第一电极层，呈环形，所述第一电极层与所述有源层接触，并且，所述第一电极层围绕所述第三绝缘层的外周，所述第一电极层包括内径中空部；
第二电极层，层叠于所述内径中空部，并且，所述第二电极层与所述有源层接触，所述第三绝缘层位于所述第二电极层与所述第一电极层之间。
可选地，所述第一电极层为漏极层，所述第二电极层为源极层；
或者，
所述第一电极层为源极层，所述第二电极层为漏极层。
可选地，所述薄膜晶体管还包括第四绝缘层，所述第四绝缘层层叠于所述第一电极层的部分区域以及所述第二电极层的全部区域。
可选地，所述第四绝缘层还层叠于所述第三绝缘层上并远离所述第二栅极层。
可选地，所述薄膜晶体管还包括第一电极端子，所述第一电极端子连接至所述第一电极层未被所述第四绝缘层层叠的部分区域。
可选地，在所述第四绝缘层层叠于所述第二电极层上的区域开设有通孔；
所述薄膜晶体管还包括第二电极端子，所述第二电极端子通过所述通孔与所述第二电极层连接。
可选地，所述薄膜晶体管还包括第一栅极端子，所述第一栅极端子连接至所述第一栅极层。
可选地，所述薄膜晶体管还包括第二栅极端子，所述第二栅极端子连接至所述第二栅极层。
可选地，所述薄膜晶体管还包括层间电介质层，所述层间电介质层位于所述第一电极层与所述第一绝缘层之间。
本申请实施例解决其技术问题提供以下技术方案：
一种薄膜晶体管基板，包括所述的薄膜晶体管。
本申请实施例解决其技术问题提供以下技术方案：
一种显示面板，包括：
所述的薄膜晶体管基板；以及
发光模组，设置于所述薄膜晶体管基板上。
本申请实施例解决其技术问题提供以下技术方案：
一种显示装置，包括：
壳体；以及
所述的显示面板，可收容于所述壳体内。
本申请实施例解决其技术问题提供以下技术方案：
一种薄膜晶体管的制作方法，包括：
提供基板；
在所述基板上依次形成第一栅极层、第一绝缘层及有源层；
在所述有源层的部分区域上依次形成第二绝缘层、第二栅极层及第三绝缘层，其中，以所述有源层所在的平面为投影面，所述第一栅极层在所述投影面的正投影与所述第二栅极层在所述投影面的正投影至少部分重合；
在所述第三绝缘层以及所述有源层的剩余区域形成漏源层，得到薄膜晶体管。
可选地，所述第一栅极层在所述投影面的正投影与所述第二栅极层在所述投影面的正投影全部重合。
可选地，所述第一栅极层与所述第二栅极层皆呈环形。
可选地，所述在所述基板上形成第一栅极层，包括：
在所述基板上形成缓冲层；
在所述缓冲层上形成底栅金属薄膜；
图形化所述底栅金属薄膜，得到环形的第一栅极层。
可选地，所述在所述有源层的部分区域上依次形成第二绝缘层与第二栅极层，包括：
在所述有源层的部分区域上形成第二绝缘层；
在所述第二绝缘层上形成顶栅金属薄膜；
图形化所述顶栅金属薄膜，得到环形的第二栅极层。
可选地，所述在所述第三绝缘层以及所述有源层的剩余区域形成漏源层，包括：
在所述第三绝缘层以及所述有源层的剩余区域形成电极金属薄膜；
图形化所述电极金属薄膜，得到第一电极层与第二电极层，其中，所述第一电极层呈环形，所述第一电极层包括内径中空部，所述第二电极层层叠于所述内径中空部，所述第二电极层与所述有源层接触，所述第三绝缘层位于所述第二电极层与所述第一电极层之间。
可选地，所述第一电极层为漏极层，所述第二电极层为源极层；
或者，
所述第一电极层为源极层，所述第二电极层为漏极层。
可选地，所述方法还包括：
在所述第一电极层与所述第一绝缘层之间形成层间电介质层。
可选地，所述方法还包括：
在所述第一电极层的部分区域、所述第二电极层的全部区域以及所述第三绝缘层上形成第四绝缘层。
可选地，所述方法还包括：
在所述第一电极层未被所述第四绝缘层层叠的部分区域引出第一电极端子。
可选地，所述方法还包括：
在所述第四绝缘层层叠于所述第二电极层上的区域开设有通孔；
由所述通孔引出第二电极端子。
可选地，所述方法还包括：
从所述第一栅极层引出第一栅极端子。
可选地，所述方法还包括：
从所述第二栅极层引出第二栅极端子。
可选地，所述在所述基板上形成第一绝缘层及有源层，包括：
在所述第一栅极层上依次生长第一绝缘层及有源层；
图形化所述有源层。
与现有技术相比较，在本申请实施例提供的薄膜晶体管中，以有源层所在的平面为投影面，第一栅极层在投影面的正投影与第二栅极层在投影面的正投影至少部分重合，因此，在第一栅极层与第二栅极层被施加同一外部电压时，正投影重合部分的第一栅极层与第二栅极层的各自电势也互相相等，正投影重合部分的第一栅极层在有源层的电场力等于正投影重合部分的第二栅极层在有源层的电场力，因此，正投影重合部分的第一栅极层与有源层之间以及正投影重合部分的第二栅极层与有源层之间都不构成产生寄生电容的条件，因此，采用此结构的薄膜晶体管，其能够降低寄生电容。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单地介绍。显而易见地，下面所描述的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1a是本申请实施例提供的一种薄膜晶体管的截面示意图；
图1b是图1a中第一栅极层、第二栅极层皆以有源层为投影面的投影示意图；
图2a是本申请另一实施例提供的暴露出第二栅极层时的薄膜晶体管的结构示意图；
图2b是沿着AA”方向剖切图2a提供的薄膜晶体管的截面示意图；
图2c是沿着BB”方向剖切图2a提供的薄膜晶体管的截面示意图；
图2d是沿着CC”方向剖切图2a提供的薄膜晶体管的截面示意图；
图2e是沿着DD”方向剖切图2a提供的薄膜晶体管的截面示意图；
图3a是传统技术提供的矩形薄膜晶体管在饱和状态下的导电沟道示意图；
图3b是传统技术提供的环形薄膜晶体管在饱和状态下的导电沟道示意图；
图4是本申请实施例提供的一种显示面板的结构示意图；
图5是本申请实施例提供的一种显示装置的结构示意图；
图6a是本申请实施例提供的一种薄膜晶体管的制作方法的流程框图；
图6b是本申请实施例提供的一种薄膜晶体管的制作方法的流程示意图；
图6c是图6a中S62的流程框图；
图6d是图6a中S63的流程框图；
图6e是图6a中S64的流程框图；
图6f是本申请另一实施例提供的一种薄膜晶体管的制作方法的流程框图。
具体实施方式
为了便于理解本申请，下面结合附图和具体实施例，对本申请进行更详细的说明。需要说明的是，当元件被表述“固定于”另一个元件，它可以直接在另一个元件上、或者其间可以存在一个或多个居中的元件。当一个元件被表述“连接”另一个元件，它可以是直接连接到另一个元件、或者其间可以存在一个或多个居中的元件。本说明书所使用的术语“垂直的”、“水平的”、“左”、“右”、“内”、“外”以及类似的表述只是为了说明的目的，并且仅表达实质上的位置关系，例如对于“垂直的”，如果某位置关系因为了实现某目的的缘故并非严格垂直，但实质上是垂直的，或者利用了垂直的特性，则属于本说明书所述“垂直的”范畴。
除非另有定义，本说明书所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是用于限制本申请。本说明书所使用的术语“和/或”包括一个或多个相关的所列项目的任意的和所有的组合。
可以理解地是，如本文所示的本申请实施例涉及的一个或多个层间物质，层与层之间的位置关系使用了诸如术语“层叠”或“形成”或“施加” 或“设置”进行表达，本领域技术人员可以理解的是：任何术语诸如“层叠”或“形成”或“施加”，其可覆盖“层叠”的全部方式、种类及技术。例如，溅射、电镀、模塑、化学气相沉积(Chemical Vapor Deposition，CVD)、物理气相沉积(Physical Vapor Deposition，PVD)、蒸发、混合物理-化学气相沉积(Hybrid Physical-Chemical Vapor Deposition，HPCVD)、等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)、低压化学气相沉积(Low Pressure Chemical Vapor Deposition，LPCVD)等。
此外，下面所描述的本申请不同实施例中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
本申请实施例提供的薄膜晶体管的结构形状可以呈正方形、长方形、环形或菱形等等，可以理解的是，此处的“环形”包括近似环形，只要本领域技术人员根据本文所描述的内容，对薄膜晶体管的结构形状作出其它替换或改进，所作的呈一定结构形状的薄膜晶体管皆应当落入本申请实施例的保护范围之内。
请参阅图1a，本发明提供的一种薄膜晶体管10包括：第一栅极层11、第一绝缘层12、有源层13、第二绝缘层14、第二栅极层15、第三绝缘层16及漏源层17。
第一栅极层11包括沉积面11a，第一绝缘层12层叠于沉积面11a上，有源层13层叠于第一绝缘层12上并远离第一栅极层11。第二绝缘层14层叠于有源层13的部分区域并远离第一绝缘层12。第二栅极层15层叠于第二绝缘层14上并远离有源层13，第三绝缘层16围绕第二栅极层15。漏源层17与有源层13接触，并且，第三绝缘层16位于漏源层17与第二栅极层15之间。
在本实施例中，请参阅图1b，以有源层13所在的平面为投影面，第一栅极层11在投影面的正投影与第二栅极层15在投影面的正投影至少部分重合。可以理解的是，平行投影线以垂直于有源层13所在的平面的方式投射第一栅极层11时，在有源层13所在的平面形成的第一阴影图形131为第一栅极层11的正投影。并且，平行投影线以垂直于有 源层13所在的平面的方式投射第二栅极层15时，在有源层13所在的平面形成的第二阴影图形132为第二栅极层15的正投影。其中，第一阴影图形131与第二阴影图形132之间至少存在部分重合，例如，如图1b所示的重合区域1b1。
当第一栅极层11在投影面的正投影与第二栅极层15在投影面的正投影至少部分重合，则第一栅极层11与第二栅极层15之间至少存在正对应的栅极部分。
当第一栅极层11与第二栅极层15被施加同一外部电压时，第一栅极层11与第二栅极层15之间各自正对应的栅极部分的电势互相相等，正投影重合部分的第一栅极层11在有源层13的电场力等于正投影重合部分的第二栅极层15在有源层13的电场力，因此，正投影重合部分的第一栅极层11与有源层13之间以及正投影重合部分的第二栅极层15与有源层13之间都不构成产生寄生电容的条件，因此，采用此结构的薄膜晶体管，其能够降低寄生电容。
在一些实施例中，第一栅极层11在投影面的正投影与第二栅极层15在投影面的正投影全部重合，亦即，第一栅极层11与第二栅极层15正相对，并且，第一栅极层11与第二栅极层15的形状构造皆相同。由于整层的第一栅极层11在有源层13的电场力等于整层的第二栅极层15在有源层13的电场力，因此，第一栅极层11与有源层13之间以及第二栅极层15与有源层13之间都不构成产生寄生电容的条件，因此，采用此结构的薄膜晶体管，其能够极大地降低寄生电容。优选地，第一栅极层11与第二栅极层15可通过引线直接连接。
在一些实施例中，第一栅极层11可以由采用相关沉积工艺在基板上沉积金属而形成的。第一栅极层11、第二栅极层15及漏源层17的材料可选择Cu、Ni、ITO、Au等功函数较高的金属或金属氧化物。第一栅极层11、有源层13、第二栅极层15及漏源层17可以多层结构。多层电极包括具有Ag、Mg、Al、PS、Pd、Au、Ni、Nd、Ir、Cr或其混合物的金属层和包括透明导电氧化物材料的透明导电氧化物层。所述透明导电氧化物材料可以包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、 氧化铟锡锌(ITZO)等。所述多层电极可以具有被配置为包括第一透明导电氧化物层、金属层和第二透明导电氧化物层的三层结构。所述多层电极也可以具有被配置为包括透明导电氧化物层和金属层的两层结构。
在一些实施例中，第一绝缘层12或第二绝缘层14是以氨气(NH 3)和甲硅烷(SiH 4)为反应源气体，采用射频等离子体增强化学气相沉积(RF-PECVD)法在对应层结构上沉积了一系列氢化非晶氮化硅(a-SiNx∶H)薄膜，所述氮化硅薄膜具有优良的绝缘耐压性能以及较好的界面特性。同时通过调整第一绝缘层12的厚度可改善有源层13背面界面的质量，防止在有源层13界面形成漏电的途径。第一绝缘层12的厚度为100-400nm，因为其良好的界面特性，所制备的半导体器件具有较小的泄露电流，提高了器件的电学性能。
在一些实施例中，第一绝缘层12或第二绝缘层14也可采用单层二氧化硅(SiO 2)或双层二氧化硅/氮化硅(SiO 2/SiNx)结构。
在一些实施例中，有源层13由采用相关工艺在第一绝缘层12上溅射靶材而形成的。在一些实施例中，有源层13可由高迁移率非晶铟镓锌氧化物(a-IGZO)靶材和普通非晶铟镓锌氧化物靶材溅射而成。通过在溅射过程中改变有源层13的厚度、溅射过程中的氧分压及不同的非晶铟镓锌氧化物靶材，所制备出的有源层13具有不同的电学性能。例如，有源层13具有高的载流子迁移率。
非晶铟镓锌氧化物(a-IGZO)半导体有着很多优异的性能，a-IGZO半导体在性能上优于其他非晶半导体。目前非晶铟镓锌氧化物薄膜晶体管(a-IGZO-SFS)已经能够实现≥10 10的开关电流比，a-IGZO的电子迁移率在2-50cm 2/V-s之间，是a-Si面板的20-50倍，且其制备的时配线变细，可实现同等透过率下4倍的分辨率。另外，IGZO薄膜晶体管的关断性能优越，具有漏电流低，功耗低的优点。
在一些实施例中，有源层13还可以为多种金属氧化物半导体。诸如基于铟锡镓锌氧化物(InSnGaZnO)的材料的四元金属氧化物、诸如基于铟镓锌氧化物(InGaZnO)的材料、基于铟锡锌氧化物(InSnZnO)的材料、基于铟铝锌氧化物(InAlZnO)的材料、基于铟铪锌氧化物(InHfZnO) 的材料、基于锡镓锌氧化物(SnGaZnO)的材料、基于铝镓锌氧化物(AlGaZnO)的材料、或者基于锡铝锌氧化物(SnAlZnO)的材料的三元金属氧化物、以及诸如基于铟锌氧化物(InZnO)的材料、基于锡锌氧化物(SnZnO)的材料、基于铝锌氧化物(AlZnO)的材料、基于锌镁氧化物(ZnMgO)的材料、基于锡镁氧化物(SnMgO)的材料、基于铟镁氧化物(InMgO)的材料、基于铟镓氧化物(InGaO)的材料的二元金属氧化物、基于铟氧化物(InO)的材料、基于锡氧化物(SnO)的材料、或者基于锌氧化物(ZnO)的材料的一元金属氧化物。
在一些实施例中，第三绝缘层16作为层间绝缘层，能够对有源层的背沟道进行钝化，有助于薄膜晶体管电学特性的提高。第三绝缘层16采用的是氮化硅绝缘层，所述氮化硅绝缘层具有优良的光电性能、机械性能以及强的阻挡杂质粒子扩散和水汽渗透等优点。较薄的所述氮化硅绝缘层不易阻隔扩散现象，并随着第三绝缘层16厚度的增加，有源层界面的污染物浓度随之降低，但当厚度超过一临界值，污染物浓度将不再大幅度降低而达到一极小值，因而设置第三绝缘层16的厚度为100-400nm。在一些实施例中，第三绝缘层16也可采用单层二氧化硅(SiO 2)或双层二氧化硅/氮化硅(SiO 2/SiNx)结构。
在一些实施例中，请一并图2a与图2b，第一栅极层11与第二栅极层15皆呈环形。如图2b所示，沿着AA”方向剖切薄膜晶体管10时，第一栅极层11的内环为中空，第一绝缘层12填充第一栅极层11的内环。同理，第二栅极层15的内环为中空，第三绝缘层16及漏源层17依次填充第二栅极层15的内环。在图2b中，第一栅极层11与第二栅极层15正相对，当然，在一些实施例中，第一栅极层11与第二栅极层15可以不是以正相对的方式设置，两者可以交叉错位设置，亦即，第一栅极层11与第二栅极层15各自在以有源层13为投影面的正投影至少部分重合。
第一栅极层11与第二栅极层15的截面形状呈梯形，并且，在薄膜晶体管10中，第一栅极层11作为底栅，第二栅极层15作为顶栅，采用双栅结构的薄膜晶体管10，其栅极的驱动能力强。
为了清楚、全方位地展示出薄膜晶体管10的各个角度的结构，本文再次提供图2c至图2e所示薄膜晶体管10的截面图。
如图2c所示，其可以很好地展示呈环形的双栅结构。
如图2d所示，由于薄膜晶体管10采用环形的双栅结构，当往与CC”方向垂直向上的方向观察剖切后的薄膜晶体管10的截面，由于其它结构层遮挡住作为底栅的第一栅极层11，可展示出作为顶栅的第二栅极层15。
如图2e所示，由于薄膜晶体管10采用环形的双栅结构，当往与DD”方向垂直向下的方向观察剖切后的薄膜晶体管10的截面，由于其它结构层遮挡住作为顶栅的第二栅极层15，可展示出作为底栅的第一栅极层11。
在一些实施例中，漏源层17包括：第一电极层171与第二电极层172。第一电极层171呈环形，第一电极层171与有源层13接触，并且，第一电极层171围绕第三绝缘层16的外周，第一电极层171包括内径中空部。第二电极层172位于内径中空部，并且，第二电极层172与有源层13接触，第三绝缘层16位于第二电极层172与第一电极层171之间。
请继续参阅图2b，第一电极层171为漏极层，第二电极层172为源极层。在一些实施例中，第一电极层171为源极层，第二电极层172为漏极层。
传统技术提供的薄膜晶体管器件采用顶栅结构，其容易出现短沟道效应(Short-channel effects)，亦即，薄膜晶体管器件工作在饱和区且器件沟道较短时，随着漏源电压V ds增大，有效沟道长度变短，漏源电流I ds有明显增大。以下结合相关例子对本申请实施例提供的环形的漏极层带来的技术效果作出说明，可以理解的是，所作的说明并不用于限制本申请保护范围，如下所述：
请参阅图3a，矩形(Rectangular)薄膜晶体管工作在饱和区时，其对应的漏源电流I ds为：
I ds＝0.5μ×C OX×(V gs-V th) 2×W/L
W＝W EFF≈W mask,L＝L EFF≈L mask-ΔL
其中，I ds为漏源电流，μ为电子迁移率，C OX为栅电容密度，V gs为漏源电压，V th为阈值电压，W为导电沟道宽度，L为导电沟道长度，W EFF为导电沟道有效宽度，W mask为掩膜时的导电沟道宽度，L EFF为导电沟道有效长度，L mask为掩膜时的导电沟道长度，ΔL为耗尽层长度。
对于矩形薄膜晶体管，工作在饱和区时，漏极施加电压，W EFF与ΔL无关，因此，漏源电流I ds随着漏源电压V gs增加而增加。
请参阅图3b，环形(Circular)薄膜晶体管工作在饱和区时，其对应的漏源电流I ds为：
Figure PCTCN2019074005-appb-000001
其中，R 1为环形源极的半径，R 2为环形漏极的半径。
对于环形薄膜晶体管，工作在饱和区时，漏极施加电压，W EFF随着L EFF变化而变化，亦即，L EFF减小，W EFF减小，通过W EFF的补偿作用，使得环形薄膜晶体管的输出电阻无穷大，因此，当漏源电压V gs增加时，漏源电流I ds却不变化。
因此，本申请实施例提供的薄膜晶体管采用环形的漏极层、源极层填充于环形的漏极层的内径中空部的结构，其沟道尺寸短，能够克服短沟道效应。并且，如前所述，薄膜晶体管采用双栅对置的结构，相对于传统的单个栅极结构(包括底栅或顶栅)，其寄生电容小，输出电流稳定与大，极大提高驱动像素单元的能力。
请继续一并参阅图2a与2b，在一些实施例中，薄膜晶体管10还包括第四绝缘层18，第四绝缘层18层叠于第一电极层171的部分区域以及第二电极层172的全部区域。第四绝缘层18未层叠第一电极层171的部分区域用于引出第一电极层171的端子，例如，引出漏极层的漏极端子。
采用此类结构的薄膜晶体管，其能够保护第一电极层171以及第二电极层172免受其它杂质粒子的影响，有助于薄膜晶体管电学特性的提高。
请继续一并参阅图2a与2b，在一些实施例中，第四绝缘层18还层叠于第三绝缘层16上并远离第二栅极层15。第四绝缘层18可平坦化第三绝缘层16，有助于图形化第三绝缘层16。
请继续一并参阅图2a与2b，在一些实施例中，薄膜晶体管10还包括层间电介质层19，层间电介质层19位于第一电极层171与第一绝缘层12之间。由于需要在位于层间电介质层19上的第一电极层171引出端子，层间电介质层19能够保护薄膜晶体管10不受移动粒子或者其它不期望的杂质电荷的影响，其能够吸引来自电极端子的杂质电荷，避免有源层13受到杂质电荷等等的影响。
请继续一并参阅图2a与2b，在一些实施例中，薄膜晶体管10还包括第一电极端子101、第二电极端子102、第一栅极端子103以及第二栅极端子104。
第一电极端子101连接至第一电极层171未被第四绝缘层18层叠的部分区域。在第四绝缘层18层叠于第二电极层172上的区域开设有通孔181，第二电极端子102通过通孔181与第二电极层172连接。
当第一电极层171为漏极，第二电极层172为源极，则第一电极端子101可以为漏极端子，第二电极端子102为源极端子。
当第一电极层171为源极，第二电极层172为漏极，则第一电极端子101可以为源极端子，第二电极端子102为漏极端子。
第一栅极端子103连接至第一栅极层11，第二栅极端子104连接至第二栅极层15。
薄膜晶体管应用在不同技术领域时，第一电极端子101、第二电极端子102、第一栅极端子103以及第二栅极端子104可连接不同电压或地端，以使薄膜晶体管能够完成特定电学功能。
总体而言，本申请实施例提供的薄膜晶体管10采用双栅结构，并且，以有源层13所在的平面为投影面，第一栅极层11在投影面的正投 影与第二栅极层15在投影面的正投影至少部分重合，因此，在第一栅极层11与第二栅极层15被施加同一外部电压时，正投影重合部分的第一栅极层11与第二栅极层15的各自电势也互相相等，正投影重合部分的第一栅极层11在有源层13的电场力等于正投影重合部分的第二栅极层15在有源层13的电场力，因此，正投影重合部分的第一栅极层11与有源层13之间以及正投影重合部分的第二栅极层15与有源层13之间都不构成产生寄生电容的条件，因此，其寄生电容小。并且，薄膜晶体管10采用环形漏极层(或源极层)，源极层填充于环形漏极层的内径中空部，其沟道尺寸短，能够克服短沟道效应，并且，输出电流稳定以及比较大，驱动能力强。
因此，本申请实施例提供的薄膜晶体管可以应用于各类合适的显示面板中，诸如薄膜晶体管液晶显示面板(TFT-LCD)或者OLED(Organic Light-Emitting Diode，有机发光二极管)显示面板，OLED显示面板可以为柔性显示面板，亦可以为透明柔性显示面板等等。
本申请实施例提供的薄膜晶体管可以与任何合适电容、电阻等等构成任何合适驱动电路，例如，在OLED显示面板中，薄膜晶体管可用于构成PMOLED驱动或AMOLED驱动。
并且，薄膜晶体管还可以由各类合适类型的材料制作而成，例如，可制作成低温多晶硅薄膜晶体管(Low Temperature Poly-Si Thin Film Transistor，LTP-Si TFT)、非晶硅TFT、多晶硅TFT、氧化物半导体TFT或者有机TFT。
作为本申请实施例另一方面，本申请实施例提供一种薄膜晶体管基板，该薄膜晶体管基板包括若干薄膜晶体管，薄膜晶体管通过任何合适工艺制作于薄膜晶体管基板上，其中，薄膜晶体管可以为图1a至图2e所阐述的薄膜晶体管。
在一些实施例中，薄膜晶体管基板可以使用柔性基板，柔性基板诸如包括薄玻璃、金属箔片或塑料基底等等具有柔性的材料，例如，塑料基底具有包括涂覆在基膜的两侧上的柔性结构，基膜包括诸如聚酰亚胺 (PI)、聚碳酸酯(PC)、聚乙二醇对酞酸酯(PET)、聚醚砜(PES)、聚乙烯薄膜(PEN)、纤维增强塑料(FRP)等等树脂。
在本申请实施例提供薄膜晶体管基板的薄膜晶体管中，以有源层所在的平面为投影面，第一栅极层在投影面的正投影与第二栅极层在投影面的正投影至少部分重合，因此，在第一栅极层与第二栅极层被施加同一外部电压时，正投影重合部分的第一栅极层与第二栅极层的各自电势也互相相等，正投影重合部分的第一栅极层在有源层的电场力等于正投影重合部分的第二栅极层在有源层的电场力，因此，正投影重合部分的第一栅极层与有源层之间以及正投影重合部分的第二栅极层与有源层之间都不构成产生寄生电容的条件，因此，采用此结构的薄膜晶体管，其能够降低寄生电容。
作为本申请实施例再另一方面，本申请实施例提供一种显示面板。请参阅图4，该显示面板40包括薄膜晶体管基板41与发光模组42，发光模组42设置于薄膜晶体管基板41上。
薄膜晶体管基板41上制备有薄膜晶体管，其中，薄膜晶体管可以为图1a至图2e所阐述的薄膜晶体管。
发光模组42用于出射光源，其可以包括诸如阳极、有机功能层、阴极、偏光片、触控模组等等。有机功能层可以依次由下列结构层构成：空穴注入层、空穴传输层、有机发光层、电子传输层、电子注入层。
在本申请实施例提供显示面板40的薄膜晶体管中，以有源层所在的平面为投影面，第一栅极层在投影面的正投影与第二栅极层在投影面的正投影至少部分重合，因此，在第一栅极层与第二栅极层被施加同一外部电压时，正投影重合部分的第一栅极层与第二栅极层的各自电势也互相相等，正投影重合部分的第一栅极层在有源层的电场力等于正投影重合部分的第二栅极层在有源层的电场力，因此，正投影重合部分的第一栅极层与有源层之间以及正投影重合部分的第二栅极层与有源层之间都不构成产生寄生电容的条件，因此，采用此结构的薄膜晶体管，其能够降低寄生电容。
作为本申请实施例再另一方面，本申请实施例提供一种显示装置。请参阅图5，显示装置50包括壳体51与显示面板52，显示面板52可收容于壳体51内，在本实施例中，显示面板52可以为上述实施例所阐述的显示面板。
在一些实施例中，显示面板52可以为柔性显示面板，例如，显示面板52可收缩于壳体51内，用户可以通过手拉显示面板52，以将显示面板52从壳体51内拉出。
在本申请实施例提供显示装置50的薄膜晶体管中，以有源层所在的平面为投影面，第一栅极层在投影面的正投影与第二栅极层在投影面的正投影至少部分重合，因此，在第一栅极层与第二栅极层被施加同一外部电压时，正投影重合部分的第一栅极层与第二栅极层的各自电势也互相相等，正投影重合部分的第一栅极层在有源层的电场力等于正投影重合部分的第二栅极层在有源层的电场力，因此，正投影重合部分的第一栅极层与有源层之间以及正投影重合部分的第二栅极层与有源层之间都不构成产生寄生电容的条件，因此，采用此结构的薄膜晶体管，其能够降低寄生电容。
作为本申请实施例再另一方面，本申请实施例提供一种薄膜晶体管的制作方法。请一并参阅图6a与图6b，薄膜晶体管的制作方法600包括：
S61、提供基板；
在一些实施例中，基板采用玻璃等透明材料制成，且经过预先清洗。在一些实施例中，因传统碱玻璃中铝、钡和钠等金属杂质含量较高，容易在高温处理工艺中发生金属杂质的扩散，因此基底也可以采用无碱玻璃制成。在另一些实施例中，基板也可采用聚酰亚胺等柔性材料制成。
S62、在基板上依次形成第一栅极层、第一绝缘层及有源层；
在一些实施例中，首先，在第一栅极层11上依次生长第一绝缘层(图未示)及有源层13。其次，在有源层13上涂布一层光刻胶，使用掩膜版对第一绝缘层及有源层13进行曝光，曝光后显影，显影结束后 分别进行有源层13和第一绝缘层的刻蚀，最后剥离光刻胶，从而得到图形化后的有源层13。
S63、在有源层的部分区域上依次形成第二绝缘层、第二栅极层及第三绝缘层，其中，以有源层所在的平面为投影面，第一栅极层在投影面的正投影与第二栅极层在投影面的正投影至少部分重合；
在一些实施例中，首先，在图形化后的有源层13上生长第二绝缘层(图未示)和第二栅极层15。其次，在第二栅极层15上涂布一层光刻胶，使用掩膜版来进行第二栅极层15和第二绝缘层的曝光。曝光后显影，显影结束后分别进行第二栅极层15和第二绝缘层的刻蚀，最后剥离光刻胶，从而得到图形化后的第二栅极层15。再次，在图形化后的第二栅极层15生长第三绝缘层16。再次，在第三绝缘层16上涂布一层光刻胶，使用掩膜版进行第三绝缘层曝光，曝光结束后进行显影，显影结束后进行第三绝缘层16的刻蚀和光刻胶的剥离，形成图形化后的第三绝缘层16。
S64、在第三绝缘层以及有源层的剩余区域形成漏源层，得到薄膜晶体管。
由本申请实施例提供的薄膜晶体管的制作方法得到的薄膜晶体管采用双栅结构，并且，以有源层13所在的平面为投影面，第一栅极层11在投影面的正投影与第二栅极层15在投影面的正投影至少部分重合，因此，其寄生电容小。
在一些实施例中，第一栅极层11在投影面的正投影与第二栅极层15在投影面的正投影全部重合，亦即，第一栅极层11与第二栅极层15正相对，并且，第一栅极层11与第二栅极层15的形状构造皆相同。由于整层的第一栅极层11在有源层13的电场力等于整层的第二栅极层15在有源层13的电场力，因此，第一栅极层11与有源层13之间以及第二栅极层15与有源层13之间都不构成产生寄生电容的条件，因此，采用此结构的薄膜晶体管，其能够极大地降低寄生电容。
在一些实施例中，用户可通过合适图形化工艺将第一栅极层11、第二栅极层15形成环形的栅极。请参阅图6c，S62包括：
S621、在基板上形成缓冲层；
S622、在缓冲层上形成底栅金属薄膜；
S623、图形化底栅金属薄膜，得到环形的第一栅极层。
在本实施例中，首先，在基板上形成缓冲层。其次，在缓冲层上沉积一层底栅金属薄膜。再次，在底栅金属薄膜上涂布一层光刻胶(Photoresist，PR胶)。最后，使用掩膜版对底栅金属薄膜进行到环形第一栅极层11图形曝光，曝光结束后进行显影，显影结束后进行底栅金属薄膜的刻蚀和光刻胶的剥离，从而得到环形的第一栅极层11。
在一些实施例中，请参阅图6d，S63包括：
S631、在有源层的部分区域上形成第二绝缘层；
S632、在第二绝缘层上形成顶栅金属薄膜；
S633、图形化顶栅金属薄膜，得到环形的第二栅极层。
在本实施例中，在顶栅金属薄膜涂布一层光刻胶，使用掩膜版对进行顶栅金属薄膜和第二绝缘层进行曝光，曝光后显影，显影结束后分别对顶栅金属薄膜和第二绝缘层进行环形刻蚀，剥离光刻胶，从而得到环形的第二栅极层15。
在一些实施例中，漏极层(或源极层)可以制作成环形，源极层(或漏极层)填充于漏极层(或源极层)的内径中空部，制作出此类结构的薄膜晶体管，其沟道尺寸短，能够克服短沟道效应，并且，输出电流稳定以及比较大，驱动能力强。请参阅图6e，S64包括：
S641、在第三绝缘层以及有源层的剩余区域形成电极金属薄膜；
S642、图形化电极金属薄膜，得到第一电极层171与第二电极层172，其中，第一电极层呈环形，第一电极层171包括内径中空部，第二电极层172层叠于内径中空部，第二电极层172与有源层接触，第三绝缘层位于第二电极层172与第一电极层171之间。
在本实施例中，首先，在图形化的第三绝缘层以及有源层的剩余区域上生长一层电极金属薄膜。其次，在电极金属薄膜上涂布一层光刻胶，使用掩膜版对电极金属薄膜进行源漏极曝光，显影结束后进行源漏极的刻蚀和光刻胶的剥离，形成图形化后的源漏极层。在一些实施例中，第 一电极层171为漏极层，第二电极层172为源极层。在另一些实施例中，第一电极层171为源极层，第二电极层172为漏极层。
在一些实施例中，在第一电极层171与第一绝缘层之间形成层间电介质层。由于需要在位于层间电介质层上的第一电极层171引出端子，层间电介质层能够保护薄膜晶体管不受移动粒子或者其它不期望的杂质电荷的影响，其能够吸引来自电极端子的杂质电荷，避免有源层受到杂质电荷等等的影响。
在一些实施例中，请参阅图6f，薄膜晶体管的制作方法600还包括：
S65、在第一电极层的部分区域、第二电极层的全部区域以及第三绝缘层上形成第四绝缘层。
为了引出各个电极的端子，以实现全面封装，在一些实施例中，在第一电极层171未被第四绝缘层层叠的部分区域引出第一电极端子101，例如，该第一电极端子101为漏极端子。
在第四绝缘层层叠于第二电极层172上的区域开设有通孔，由通孔引出第二电极端子，例如，第二电极端子102为源极端子，在形成通孔时，首先，在第一电极层171的部分区域、第二电极层172的全部区域以及第三绝缘层生长第四绝缘层。其次，在第四绝缘层上涂布一层光刻胶。再次，使用掩膜版对第四绝缘层进行曝光，显影结束后进行刻蚀和光刻胶的剥离，从而得到通孔。
在一些实施例中，从第一栅极层11引出第一栅极端子103，从第二栅极层15引出第二栅极端子104。
薄膜晶体管应用在不同技术领域时，第一电极端子101、第二电极端子102、第一栅极端子103以及第二栅极端子104可连接不同电压或地端，以使薄膜晶体管能够完成特定电学功能。
总体而言，由本申请实施例提供方法制作出的薄膜晶体管寄生电容小，沟道尺寸段，能够克服短沟道效应，并且，输出电流稳定以及比较大，驱动能力强。
本领域技术人员可以理解，本说明书中各实施例所描述工艺及材料仅为示例性，本申请实施例可以使用未来开发的适用于本申请的任何工 艺或材料。
需要说明的是，在上述各个实施例中，上述各步骤之间并不必然存在一定的先后顺序，本领域普通技术人员，根据本发明实施例的描述可以理解，不同实施例中，上述各步骤可以有不同的执行顺序，亦即，可以并行执行，亦可以交换执行等等。
需要说明的是，未在本申请实施例所详述的薄膜晶体管的制作方法的具体技术细节或有益效果，可参见本申请发明实施例所提供的薄膜晶体管，在此不赘述。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；在本申请的思路下，以上实施例或者不同实施例中的技术特征之间也可以进行组合，步骤可以以任意顺序实现，并存在如上所述的本申请的不同方面的许多其它变化，为了简明，它们没有在细节中提供；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (30)

  1. 一种薄膜晶体管，其特征在于，包括：
    第一栅极层；
    第一绝缘层，层叠于所述第一栅极层上；
    有源层，层叠于所述第一绝缘层上并远离所述第一栅极层；
    第二绝缘层，层叠于所述有源层的部分区域并远离所述第一绝缘层；
    第二栅极层，层叠于所述第二绝缘层上并远离所述有源层，其中，以所述有源层所在的平面为投影面，所述第一栅极层在所述投影面的正投影与所述第二栅极层在所述投影面的正投影至少部分重合；
    第三绝缘层，围绕所述第二栅极层；
    漏源层，与所述有源层接触，并且，所述第三绝缘层位于所述漏源层与所述第二栅极层之间。
  2. 根据权利要求1所述的薄膜晶体管，其特征在于，所述第一栅极层在所述投影面的正投影与所述第二栅极层在所述投影面的正投影全部重合。
  3. 根据权利要求1所述的薄膜晶体管，其特征在于，所述第一栅极层与所述第二栅极层的电势相同。
  4. 根据权利要求1所述的薄膜晶体管，其特征在于，所述第一栅极层与所述第二栅极层皆呈环形。
  5. 根据权利要求4所述的薄膜晶体管，其特征在于，所述漏源层包括：
    第一电极层，呈环形，所述第一电极层与所述有源层接触，并且，所述第一电极层围绕所述第三绝缘层的外周，所述第一电极层包括内径中空部；
    第二电极层，层叠于所述内径中空部，并且，所述第二电极层与所述有源层接触，所述第三绝缘层位于所述第二电极层与所述第一电极层之间。
  6. 根据权利要求4所述的薄膜晶体管，其特征在于，
    所述第一电极层为漏极层，所述第二电极层为源极层；
    或者，
    所述第一电极层为源极层，所述第二电极层为漏极层。
  7. 根据权利要求5所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括第四绝缘层，所述第四绝缘层层叠于所述第一电极层的部分区域以及所述第二电极层的全部区域。
  8. 根据权利要求7所述的薄膜晶体管，其特征在于，所述第四绝缘层还层叠于所述第三绝缘层上并远离所述第二栅极层。
  9. 根据权利要求7所述的薄膜晶体管，其特征在于，
    所述薄膜晶体管还包括第一电极端子，所述第一电极端子连接至所述第一电极层未被所述第四绝缘层层叠的部分区域。
  10. 根据权利要求7所述的薄膜晶体管，其特征在于，
    在所述第四绝缘层层叠于所述第二电极层上的区域开设有通孔；
    所述薄膜晶体管还包括第二电极端子，所述第二电极端子通过所述通孔与所述第二电极层连接。
  11. 根据权利要求1所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括第一栅极端子，所述第一栅极端子连接至所述第一栅极层。
  12. 根据权利要求1所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括第二栅极端子，所述第二栅极端子连接至所述第二栅极层。
  13. 根据权利要求1至11任一项所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括层间电介质层，所述层间电介质层位于所述第一电极层与所述第一绝缘层之间。
  14. 一种薄膜晶体管基板，其特征在于，包括如权利要求1至13任一项所述的薄膜晶体管。
  15. 一种显示面板，其特征在于，包括：
    如权利要求14所述的薄膜晶体管基板；以及
    发光模组，设置于所述薄膜晶体管基板上。
  16. 一种显示装置，其特征在于，包括：
    壳体；以及
    如权利要求15所述的显示面板，可收容于所述壳体内。
  17. 一种薄膜晶体管的制作方法，其特征在于，包括：
    提供基板；
    在所述基板上依次形成第一栅极层、第一绝缘层及有源层；
    在所述有源层的部分区域上依次形成第二绝缘层、第二栅极层及第三绝缘层，其中，以所述有源层所在的平面为投影面，所述第一栅极层在所述投影面的正投影与所述第二栅极层在所述投影面的正投影至少部分重合；
    在所述第三绝缘层以及所述有源层的剩余区域形成漏源层，得到薄膜晶体管。
  18. 根据权利要求17所述的制作方法，其特征在于，所述第一栅极层在所述投影面的正投影与所述第二栅极层在所述投影面的正投影全部重合。
  19. 根据权利要求17所述的制作方法，其特征在于，所述第一栅极层与所述第二栅极层皆呈环形。
  20. 根据权利要求19所述的制作方法，其特征在于，所述在所述基板上形成第一栅极层，包括：
    在所述基板上形成缓冲层；
    在所述缓冲层上形成底栅金属薄膜；
    图形化所述底栅金属薄膜，得到环形的第一栅极层。
  21. 根据权利要求19所述的制作方法，其特征在于，所述在所述有源层的部分区域上依次形成第二绝缘层与第二栅极层，包括：
    在所述有源层的部分区域上形成第二绝缘层；
    在所述第二绝缘层上形成顶栅金属薄膜；
    图形化所述顶栅金属薄膜，得到环形的第二栅极层。
  22. 根据权利要求19至21任一项所述的制作方法，其特征在于，所述在所述第三绝缘层以及所述有源层的剩余区域形成漏源层，包括：
    在所述第三绝缘层以及所述有源层的剩余区域形成电极金属薄膜；
    图形化所述电极金属薄膜，得到第一电极层与第二电极层，其中，所述第一电极层呈环形，所述第一电极层包括内径中空部，所述第二电极层层叠于所述内径中空部，所述第二电极层与所述有源层接触，所述第三绝缘层位于所述第二电极层与所述第一电极层之间。
  23. 根据权利要求22所述的制作方法，其特征在于，
    所述第一电极层为漏极层，所述第二电极层为源极层；
    或者，
    所述第一电极层为源极层，所述第二电极层为漏极层。
  24. 根据权利要求22所述的制作方法，其特征在于，所述方法还包括：
    在所述第一电极层与所述第一绝缘层之间形成层间电介质层。
  25. 根据权利要求22所述的制作方法，其特征在于，所述方法还包括：
    在所述第一电极层的部分区域、所述第二电极层的全部区域以及所述第三绝缘层上形成第四绝缘层。
  26. 根据权利要求25所述的制作方法，其特征在于，所述方法还包括：
    在所述第一电极层未被所述第四绝缘层层叠的部分区域引出第一电极端子。
  27. 根据权利要求25所述的制作方法，其特征在于，所述方法还包括：
    在所述第四绝缘层层叠于所述第二电极层上的区域开设有通孔；
    由所述通孔引出第二电极端子。
  28. 根据权利要求17所述的制作方法，其特征在于，所述方法还包括：
    从所述第一栅极层引出第一栅极端子。
  29. 根据权利要求17所述的制作方法，其特征在于，所述方法还包括：
    从所述第二栅极层引出第二栅极端子。
  30. 根据权利要求17所述的制作方法，其特征在于，所述在所述基板上形成第一绝缘层及有源层，包括：
    在所述第一栅极层上依次生长第一绝缘层及有源层；
    图形化所述有源层。
PCT/CN2019/074005 2019-01-30 2019-01-30 薄膜晶体管及其制作方法、显示面板及显示装置 WO2020154983A1 (zh)

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