WO2020154978A1 - 一种Hessian-Free的光刻掩模优化方法、装置及电子设备 - Google Patents
一种Hessian-Free的光刻掩模优化方法、装置及电子设备 Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
- G03F7/70508—Data handling in all parts of the microlithographic apparatus, e.g. handling pattern data for addressable masks or data transfer to or from different components within the exposure apparatus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
Definitions
- the invention relates to the field of integrated circuit mask design, and in particular to a Hessian-Free photolithography mask optimization method, device and electronic equipment.
- Lithography is one of the most important parts of the integrated circuit manufacturing process, which determines the advanced level of the integrated circuit manufacturing process.
- the lithography system is usually described as an optical imaging system, including the four basic elements of an illumination source, a mask, a projection objective system, and a silicon wafer coated with photoresist.
- the size of the pattern that needs to be exposed is much smaller than the wavelength of the light source in the lithography system.
- the optical proximity effect Optical Proximity Effects caused by the interference and diffraction effects of light waves in the lithography imaging system becomes more and more significant.
- the graphics are optimized to make the exposure graphics obtained on the silicon chip closer to the target graphics.
- the existing mask optimization methods are generally divided into first-order precision methods (steepest descent method, conjugate gradient method, etc.) and second-order precision methods (Newton method).
- the first-order precision method needs to calculate the first derivative of the objective function with respect to the optimized variable.
- the second-order precision optimization method needs to calculate the first derivative and the second derivative (Hessian matrix) of the objective function to the optimization variable. Since the second-order precision optimization method uses more information of the objective function, its numerical convergence speed will be much faster than the first-order precision optimization method.
- the number of variables is extremely large, often reaching millions of levels, and the lithography simulation calculation process is complicated.
- the calculation resources required to calculate the second derivative of the objective function to the optimization variable are extremely large.
- the Newton method is difficult to use in the inversion mask optimization problem, and a second-order precision method of the quasi-Newton method, such as the L-BFGS method, is usually used.
- the quasi-Newton method only needs to calculate the first derivative of the objective function to the optimized variable, and use some simple relations to approximate the second derivative (Hessian matrix). Due to the approximation of the Hessian matrix in this method, it cannot truly reflect the changing trend of the objective function, and in some cases it will cause the optimization method to converge very slowly or even fail to obtain good optimization results.
- the present invention provides a Hessian-Free photolithography mask optimization method, device and electronic equipment.
- the present invention provides a Hessian-Free photolithography mask optimization method for optimizing the mask to be optimized, including the following steps: S1, inputting the design layout of the mask to be optimized; S2 Place error monitoring points on the design layout of the mask to be optimized; S3, obtain the optimized variable x of the mask to be optimized; S4, provide the objective function cost on the optimized variable x; S5, use the Hessian-Free conjugate
- the gradient method optimizes the objective function cost to obtain the optimization result of the mask to be optimized.
- the objective function cost is defined as follows:
- ci represents the i-th exposure condition
- pj represents the j-th error monitoring point
- Power is a set positive and even value
- Signal(ci, pj) represents the j-th error monitoring point under the i-th exposure condition
- the signal error value at, the signal error value includes the intensity of the RI or the EPE value
- the RI is the intensity of the pattern on the photoresist
- the EPE is the edge positioning error.
- the mask to be optimized includes a main pattern
- the optimization variable x of the mask to be optimized includes edges of the main pattern and/or auxiliary pattern sampling points placed around the main pattern Or the side of the auxiliary graphic placed according to the signal value of the sampling point of the auxiliary graphic.
- the above step S55 includes the following steps:
- the RI can be obtained through the following steps:
- the q im is a photoresist coefficient
- the ⁇ n is the n-th eigen coefficient of the TCC matrix
- the h m, t are the characteristic vectors of the TCC matrix
- the st, o and d t, l are linear coefficients calculated from the mask to the latticed mask
- the E o represents the displacement variable of the graphic edge
- the P l represents the signal of the auxiliary graphic sampling point Value
- MI t (0) is the initial value, that is, the initial MI when E o and P l are both 0.
- v o is the o-th component of v, the eigenvector of the initial optimization, and v l is the first component of v;
- the It can be obtained by performing a complex conjugate operation on Rv(EI n, m ). Similarly, It can be obtained by the negative conjugate operation of h m, t , It can be obtained by the negative conjugate operation of EI n, m , It is obtained by Rv(MI t ) complex conjugate operation.
- the EPE can be obtained through the following steps:
- RI′ i is the gradient of RI at monitoring point i
- di ,j is the linear coefficient of the calculation from the mask to the latticed mask.
- the Rv(RI) can be calculated through the above steps T0261-T0264.
- the present invention also provides a Hessian-Free photolithography mask optimization device, which includes an input module, an error monitoring point placement module, an optimization variable generation module, an objective function generation module, and an optimization calculation module.
- the input module The configuration is used to input the design layout of the mask to be optimized; the error monitoring point placement module is configured to place the error monitoring points on the design layout of the mask to be optimized; the optimization variable generation module is configured to obtain the optimization The optimization variable x of the mask; the objective function generation module, which provides the objective function cost about the optimization variable x; and the optimization calculation module, which is configured to optimize the objective function cost based on the Hessian-Free conjugate gradient method to obtain The optimization result of the mask to be optimized.
- the objective function cost is optimized by using the Hessian-Free conjugate gradient method to obtain the optimization result of the mask to be optimized, without directly calculating the Hessian matrix of the objective function cost , Can reduce the computing resources in the optimization process, make the optimization process simpler, feasible, and improve the optimization efficiency; at the same time, there is no need to use the quasi-Newton method to obtain the approximate replacement matrix of the H matrix, which can improve the optimization result. Accuracy.
- the Hessian-Free-based conjugate gradient device and electronic equipment provided by the present invention have the same beneficial effects as the Hessian-Free-based conjugate gradient method.
- FIG. 1 is a schematic flowchart of the Hessian-Free photolithography mask optimization method provided in the first embodiment of the present invention
- FIG. 2 is a schematic diagram of the design layout of the mask to be optimized in the Hessian-Free photolithography mask optimization method provided in the first embodiment of the present invention
- FIG. 3 is a schematic diagram of error monitoring points placed by the Hessian-Free photolithography mask optimization method provided in the first embodiment of the present invention
- FIG. 4 is a schematic diagram of the optimization variable in the Hessian-Free photolithography mask optimization provided in the first embodiment of the present invention when the optimization variable is the edge of the main pattern;
- step S3 is a detailed flowchart of step S3 in the Hessian-Free photolithography mask optimization method provided in the first embodiment of the present invention
- FIG. 6 is a schematic diagram of the auxiliary pattern sampling point placement area in the Hessian-Free photolithography mask optimization method provided in the first embodiment of the present invention
- FIG. 7 is a schematic diagram of auxiliary pattern sampling points placed in the Hessian-Free photolithography mask optimization method provided in the first embodiment of the present invention.
- step S5 is a detailed flowchart of step S5 in the Hessian-Free photolithography mask optimization method in the first embodiment of the present invention.
- step S55 is a detailed flowchart of step S55 in the Hessian-Free photolithography mask optimization method in the first embodiment of the present invention.
- step S5 is a detailed flowchart of step S5 in a modified embodiment of the Hessian-Free photolithography mask optimization method in the first embodiment of the present invention
- FIG. 11 is a schematic diagram of the mask after the auxiliary pattern is placed in the auxiliary pattern placement area in the Hessian-Free photolithography mask optimization method provided in the first embodiment of the present invention
- FIG. 12 is a schematic diagram of a mask after the optimization variables in the Hessian-Free photolithography mask optimization method provided in the first embodiment of the present invention are optimized for the edges of the main pattern and the edges of the auxiliary pattern;
- FIG. 13 is a schematic diagram of a resist image formed by an optimized mask in the Hessian-Free photolithography mask optimization method provided in the first embodiment of the present invention
- FIG. 14 is a schematic diagram of modules of the Hessian-Free photolithography mask optimization device provided in the second embodiment of the present invention.
- 15 is a schematic diagram of modules of an electronic device provided in a third embodiment of the present invention.
- Fig. 16 is a schematic structural diagram of a computer system suitable for implementing a server according to an embodiment of the present invention.
- the first embodiment of the present invention provides a Hessian-Free photolithography mask optimization method for optimizing the mask to be optimized, including the following steps:
- a design pattern of a target chip is provided first, and a mask layout corresponding to the design pattern of the target chip is designed according to the design pattern of the target chip.
- the mask layout is laid out according to the lithography requirements of the design pattern of the target chip to obtain the Optimize the mask design layout, which includes at least one main pattern.
- the area M is the main pattern.
- the main pattern is also called the exposure pattern, which will be transferred to the semiconductor device after exposure.
- the area M is a rectangle.
- the main graphics may be other graphics, mainly depending on the specific shape of the target chip, such as trapezoids, irregular polygons, regular polygons and other graphics.
- the input mask design layout to be optimized exists in GDS format.
- a Hessian-Free photolithography mask optimization method further includes the following steps:
- the error monitoring point is placed on the layout of the mask to be optimized, that is, the error monitoring point is placed on the edge of the main graphic.
- the function of the error monitoring point is to determine whether the iteratively optimized mask is qualified by detecting the difference between the edge of the photoresist pattern after exposure and the edge of the design pattern simulated by the lithography software.
- the placement of the error monitoring points can be placed according to human experience. As shown in Figure 3, for the edges of the main graph, the error monitoring points can be placed on the edges. In some other implementation manners, error monitoring points may also be placed at the corners of the main graph, and the specific placement position is where the corners are close to the center position.
- a Hessian-Free photolithography mask optimization method further includes the following steps:
- the optimization variable x of the mask to be optimized includes the edges of the main graphic and/or auxiliary graphic sampling points placed around the main graphic; or the auxiliary graphic sampling points placed according to the signal values of the auxiliary graphic sampling points The side of the auxiliary figure.
- the edge of the main graph is used as the optimization variable x
- the main graph edge is cut into short sides of small line segments.
- Each short edge is marked as a different type according to its position.
- edges are used to obtain different optimization variables for short edges at different positions.
- the cutting process makes the optimized object more clear, single and accurate, and avoids the problem of overly complex situations when the overall optimization of the main graphics is performed.
- the optimization strategy that takes the short side as the first variable of optimization is mainly the movement of the corresponding line segment. Choose different moving directions and different moving step lengths according to the different line segment positions and the imaging characteristics of the pattern on the photoresist, step by step, and iterate multiple times until the final optimized result is obtained.
- a preset rule can be used to form auxiliary graphics placement areas around the auxiliary graphics , Place the auxiliary graphic sampling points in the auxiliary graphic placement area, use the auxiliary graphic sampling points to optimize the mask to be optimized, monitor the signal value of the placed auxiliary graphic sampling points, and obtain the required placement assistance according to the signal value of the auxiliary graphic sampling point
- the auxiliary graph sampling point of the graph As an implementation manner, the placement of sampling points of the auxiliary graphics specifically includes the following steps:
- the smallest variable x1 and the largest variable x2 are respectively the expansion coefficients of the main graph, wherein the smallest variable x1 is less than or equal to the largest variable x2, the smallest variable x1 is greater than or equal to zero, and the largest variable x2 is not equal to zero.
- the placement of the sampling points of the auxiliary graphics also includes the following steps:
- the placement of the sampling points of the auxiliary graphics also includes the following steps:
- the auxiliary graphic placement area is the area C formed by the edges of the graphic A and the graphic B, which corresponds to the filled area in FIG. 6, and it can be seen that the outline of the auxiliary graphic placement area is consistent with the outline of the main graphic. Area C is shown in Figure 6.
- the placement of the sampling points of the auxiliary graphics also includes the following steps:
- the initial signal value assigned to each auxiliary graphic signal sampling point is 0.
- the auxiliary graphics are placed at the position of the auxiliary graphics signal sampling corresponding to the point, otherwise, the auxiliary graphics are not placed.
- the auxiliary graph sampling points are placed according to a preset rule.
- the preset rule may be: setting multiple rows of auxiliary graphic sampling points, the spacing between any two adjacent auxiliary graphic sampling points in the same line is x, and the line spacing of any two adjacent lines is also x,
- the value of x can be adjusted according to the actual optimization effect.
- the auxiliary graphic placement area in order to place the auxiliary graphic sampling points more quickly and accurately, can be divided into multiple rectangular blocks, and the auxiliary graphic sampling points are placed in each rectangular block at a set interval x .
- the edge of the main graphic and the sampling point of the auxiliary graphic signal are used as the optimization variable x.
- the edge of the auxiliary graphic placed according to the signal value of the auxiliary graphic sampling point is used as the optimized variable, and the edge of the placed auxiliary graphic is used as the optimized variable to perform the auxiliary graphic.
- the optimization method is similar to the optimization method that uses the edges of the main graphics as optimization variables. The same is to segment the edges of the auxiliary graphics, and then move the short edges obtained by the segmentation by the corresponding displacement to optimize the auxiliary graphics. As shown in Figure 9, it is the final optimized mask pattern.
- a Hessian-Free photolithography mask optimization method further includes the following steps:
- step S4 the objective function cost is defined as follows:
- ci represents the i-th exposure condition
- pj represents the j-th error monitoring point
- Signal (ci, pj) represents the The signal error value at the j-th error monitoring point under i exposure conditions
- the signal error value includes one of the intensity of RI or the EPE value
- the RI is the intensity of the pattern on the photoresist
- the EPE is the edge Positioning error.
- the step S5 specifically includes the following steps:
- the corresponding initial optimized variable value x 0 is a randomly set moving distance, which can be specifically 2 nm.
- step S52 the gradient value g 0 of the initial optimization variable value x 0 of the objective function cost is calculated.
- the following example illustrates the gradient value g 0 when the initial optimization variable value x 0 is an edge of the main graph.
- the gradient of the objective function cost relative to the optimized variable value x 0 can be calculated based on the following cascade relation:
- Step S551 Calculate the coefficient ⁇ k , and define ⁇ k to be determined by the following relationship:
- v k+1 v k + ⁇ k p k ,
- the v k is a multi-dimensional vector.
- each component is the position change value of the main graph edge in the process of iterating K times of the optimized variable. It can be seen that it is a known The numerical value. It can be understood that when the optimized variable is the sampling point of the auxiliary graph, each component of the optimized variable corresponds to the change value of the sampling point signal of the auxiliary graph during the K iterations of the optimized variable.
- step S5 further includes the steps:
- Step S57 Determine whether
- obtaining H ⁇ p k includes the following steps:
- the RI can be obtained through the following steps:
- q im is the photoresist coefficient, which can be obtained by multiple measurements of a set of lithography models under a set of known illumination conditions
- AI m is the optical exposure dose value at position m, which can be obtained by Step T022 is calculated.
- ⁇ n is the n-th eigen coefficient of the TCC matrix
- EI n,m is the value of the n-th eigen electric field at position m.
- ⁇ n can be calculated based on TCC optical imaging theory, which specifically includes the following steps:
- T0222 calculate partial coherent kernel function.
- the cross transfer coefficient matrix can be calculated by the existing analytical method, integration method, and Fourier transform method.
- the Fourier transform method can adapt to different types of light sources and has a faster calculation rate.
- the Fourier transform method is selected for calculation.
- step T0222 firstly, the four-dimensional cross transfer coefficient matrix needs to be expressed as a two-dimensional matrix, and then eigenvalue decomposition is performed on it to obtain its eigen coefficients and eigenvectors. Among them, the calculated feature vector corresponds to the partial coherent kernel function.
- the eigenvalue decomposition of the cross transfer coefficient matrix is mainly based on the optical imaging model Hopkins (Hopkins statistics), and the first n items are retained, and each item is represented by an eigen coefficient and an eigenvector. Therefore, the n-th eigen coefficient ⁇ n and the feature vector are obtained.
- EI n, m is obtained by convolution calculation of MI and the feature vector, and specifically obtained by T023 calculation;
- h m, t is the feature vector of the TCC matrix, which can be obtained through the above step T0222;
- MI t is the mask image value at position t, which can be specifically calculated through step T024:
- the st, o and d t, l are linear coefficients calculated from the mask to the latticed mask
- the E o represents the displacement variable of the graphic edge
- the P l represents the signal of the auxiliary graphic sampling point Value
- MI t (0) is the initial value, that is, the initial MI when E o and P l are both 0. It can be understood that the MI t described above is only an example, and adjustments are made according to specific optimization variables in actual operations. For example, when the optimized variable is the edge of the main graph, then
- MI t (0) may be obtained by performing a convolution operation on the mask pattern determined by E, which specifically includes the following steps:
- T0232 Calculate each pixel in the mask pattern, calculate the product of the neighboring pixel of each pixel and the corresponding element of the low-pass filter matrix, and add the values of the corresponding elements to obtain Represents the feature value of the pixel position, thereby forming a feature map about the mask pattern.
- the feature value on the feature map corresponds to MI t (0). It should be noted that, in this step, performing a convolution operation on the mask pattern determined by E is a commonly used image filtering convolution operation algorithm, which will not be repeated here.
- v o is the o-th component of v, the eigenvector of the initial optimization, and v l is the first component of v.
- Rv(RI), the Rv(RI) can be calculated by the following steps:
- the It can be obtained by performing a complex conjugate operation on Rv(EI n, m ). Similarly, It can be obtained by the negative conjugate operation of h m, t , It can be obtained by the negative conjugate operation of EI n, m , It is obtained by Rv(MI t ) complex conjugate operation.
- the EPE when the Signal (ci, pj) is EPE (edge positioning error), the EPE can be obtained through the following steps:
- RI′ i is the gradient of RI at monitoring point i
- RI i the calculation of RI i can be obtained through the above steps: T021-T023 calculation, which will not be repeated here.
- d i,j are calculated linear coefficients from the mask to the latticed mask.
- the Rv(RI) can be calculated through the above steps T0261-T0264, and will not be repeated here.
- the calculation method of H j ⁇ v under each exposure condition can be obtained by the calculation provided above.
- multiple exposure conditions are used for testing, specifically including standard exposure conditions (NC), exposure dose +3% (PD3), exposure dose -3% (ND3), defocus +40nm (PF40), Focus -40nm (NF40).
- NC standard exposure conditions
- PD3 exposure dose +3%
- ND3 exposure dose -3%
- PF40 defocus +40nm
- NF40 Focus -40nm
- the standard exposure condition means that the lithography machine is in an ideal working state, that is, the exposure value is at the set standard value, and the lens focus is also at the set standard value without shift.
- the optimized mask layout is shown in Figure 11 with the edges of the main graphics and the sampling points of the auxiliary graphics signals as the optimized variables.
- the edges of the main graphics are moved accordingly, and based on the sampling points of the auxiliary graphics signals.
- the size of the signal value is placed with auxiliary graphics.
- the mask is optimized with the edges of the main graphics as the optimization variables and the edges of the auxiliary graphics as the optimization variables. As shown in FIG. 12, the graphics of the final optimized mask are shown.
- the resist image obtained by the optimization calculation of the final optimized mask is consistent with the monitoring points placed on the design layout of the initial design mask, so it can be explained that the Hessian-Free light provided by the present invention
- the engraving mask optimization method has a better optimization effect.
- EPE refers to the error between the figure on the silicon chip calculated by the objective function and the edge of the actually required figure (target figure).
- Pvband refers to the width of EPE distribution under different exposure conditions.
- the second embodiment of the present invention provides a Hessian-Free photolithography mask optimization device 200, which includes an input module 201, an error monitoring point placement module 202, an optimization variable generation module 203, an objective function generation module 204, and Optimization calculation module 205.
- the input module 201 is configured to input the design layout of the mask to be optimized
- An error monitoring point placement module 202 configured to place error monitoring points on the design layout of the mask to be optimized
- the optimization variable generation module 203 is configured to obtain the optimization variable x of the mask to be optimized
- the objective function generating module 204 provides an objective function cost on the optimization variable x.
- the optimization calculation module 205 is configured to optimize the objective function cost based on the Hessian-Free conjugate gradient method to obtain the optimization result of the mask to be optimized.
- a third implementation of the present invention provides an electronic device 300, which includes one or more processors 302;
- the storage device 301 is used to store one or more programs,
- the one or more processors 302 implement any step of the model-based data processing method provided in the first implementation.
- FIG. 16 shows a schematic structural diagram of a computer system 800 of a terminal device/server suitable for implementing embodiments of the present invention.
- the terminal device/server shown in FIG. 16 is only an example, and should not bring any limitation to the functions and scope of use of the embodiments of the present application.
- the computer system 800 includes a central processing unit (CPU) 801, which can be based on a program stored in a read-only memory (ROM) 802 or a program loaded from a storage portion 808 into a random access memory (RAM) 803 And perform various appropriate actions and processing.
- the RAM 803 also stores various programs and data required for the operation of the system 800.
- the CPU 801, the ROM 802, and the RAM 803 are connected to each other through a bus 804.
- An input/output (I/O) interface 805 is also connected to the bus 804.
- the following components are connected to the I/O interface 805: an input part 806 including a keyboard, a mouse, etc.; an output part 807 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and speakers, etc.; a storage part 808 including a hard disk, etc. ; And a communication section 809 including a network interface card such as a LAN card, a modem, etc. The communication section 809 performs communication processing via a network such as the Internet.
- the driver 810 is also connected to the I/O interface 805 as needed.
- a removable medium 811 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 810 as needed, so that the computer program read therefrom is installed into the storage section 808 as needed.
- the process described above with reference to the flowchart may be implemented as a computer software program.
- the embodiments of the present disclosure include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains program code for executing the method shown in the flowchart.
- the computer program may be downloaded and installed from the network through the communication part 809, and/or installed from the removable medium 811.
- the computer program is executed by the central processing unit (CPU) 801
- the above-mentioned functions defined in the method of the present invention are executed.
- the computer-readable medium of the present invention may be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two.
- the computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or a combination of any of the above. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable Programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above.
- the computer program code used to perform the operations of this application can be written in one or more programming languages or a combination thereof.
- the programming language includes object-oriented programming languages-such as Java, Smalltalk, C++, and also conventional Procedural programming language-such as "C" language or similar programming language.
- the program code can be executed entirely on the user's computer, partly on the user's computer, executed as an independent software package, partly on the user's computer and partly executed on a remote computer, or entirely executed on the remote computer or server.
- the remote computer can be connected to the user’s computer through any kind of network including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (for example, using an Internet service provider to pass Internet connection).
- LAN local area network
- WAN wide area network
- Internet service provider for example, using an Internet service provider to pass Internet connection.
- each block in the flowchart or block diagram can represent a module, program segment, or part of code, and the module, program segment, or part of code contains one or more for realizing the specified logic function Executable instructions.
- the functions marked in the block may also occur in a different order from the order marked in the drawings. For example, two blocks shown in succession can actually be executed substantially in parallel, or they can sometimes be executed in the reverse order, depending on the functions involved.
- each block in the block diagram and/or flowchart, and the combination of the blocks in the block diagram and/or flowchart can be implemented by a dedicated hardware-based system that performs the specified functions or operations Or it can be realized by a combination of dedicated hardware and computer instructions.
- the units involved in the embodiments described in the present invention can be implemented in software or hardware.
- the described unit can also be set in the processor, for example, it can be described as: a processor includes an input module, an error monitoring point placement module, an optimized variable generation module, an objective function generation module, and an optimized calculation module.
- the names of these units do not constitute a limitation on the unit itself under certain circumstances.
- the input module can also be described as "used to input the design layout of the mask to be optimized".
- the present invention also provides a computer-readable medium.
- the computer-readable medium may be included in the device described in the above embodiment; or it may exist alone without being assembled into the device.
- the above-mentioned computer-readable medium carries one or more programs, and when the above-mentioned one or more programs are executed by the device, the device is caused to: input the design layout of the mask to be optimized, and display it on the design layout of the mask to be optimized Place error monitoring points, obtain the optimized variable x of the mask to be optimized, provide the objective function coat about the optimized variable x, and optimize the objective function cost based on the Hessian-Free conjugate gradient method to obtain the Optimize the optimization result of the mask.
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Abstract
一种Hessian-Free的光刻掩模优化方法,包括如下步骤:S1、输入待优化掩模的设计版图;S2、在待优化掩模的设计版图上放置误差监测点;S3、获得待优化掩模的优化变量x;S4、提供关于优化变量x的目标函数cost;S5、利用基于Hessian-Free的共轭梯度方法对目标函数cost进行优化,以得到所述待优化掩模的优化结果。基于Hessian-Free的共轭梯度方法对目标函数cost进行优化,以得到待优化掩模的优化结果能很好的缩小优化过程中的计算资源,使得优化过程更简单可行,并且提高优化效率;同时不需要类似采用拟牛顿法获得关于H矩阵的近似替换矩阵,能很好的提高优化结果的准确性。还公开了一种Hessian-Free的光刻掩模优化装置及电子设备。
Description
本发明涉及集成电路掩模设计领域,尤其涉及一种Hessian-Free的光刻掩模优化方法、装置及电子设备。
光刻是集成电路制造工艺中最重要的部分之一,决定着集成电路制造工艺的先进程度。光刻系统通常被描述成一个光学成像系统,包括照明光源、掩模、投影物镜系统以及涂有光刻胶的硅片四个基本要素。随着集成电路关键尺寸进入45nm技术节点,并不断向更小的尺寸32nm甚至22nm节点迈进,所需要曝光的图形尺寸远远小于光刻系统中光源的波长。在这种情况下,光刻成像系统中光波的干涉、衍射效应造成的光学临近效应(Optical Proximity Effects)变得越来越显著。这导致硅胶片上所成的曝光图形相比所采用的掩模图形产生极大的畸形,因此,在实际设计用于光刻系统的掩模时,必要考虑这种光学临近效应,预先对掩模图形进行优化处理,使得硅片上获得的曝光图形更加接近目标图形。
在现有掩模的优化方法中,一般分为一阶精度法(最速下降法、共轭梯度法等)和二阶精度法(牛顿法)。一阶精度法需要计算目标函数对于优化变量的一阶导数。二阶精度优化方法需要计算目标函数对优化变量的一阶导数及二阶导数(Hessian矩阵)。由于二阶精度优化方法利用了目标函数更多的信息,其数值收敛速度会远远快于一阶精度优化方法。然而对于反演光刻技术的掩模优化问题,变量数目极大,往往会达到上百万级且光刻模拟计算过程复杂,计算目标函数对优化变量的二阶导数所需的计算资源极大,在实践上不可行。因而牛顿法很难用于反演掩模优化问题,通常采用一种拟牛顿法的二阶精度方法,例如L-BFGS方法。拟牛顿法只需计算目标函数对优化变量的一阶导数,并用一些简单的关系来近似得到二阶导数(Hessian矩阵)。由于该方法中的Hessian矩阵的近似性,不能真实反映目标函数的变化趋势,在一些情况下会导致该优化方法收敛速度很慢甚至不能得到很好的优化结果。
【发明内容】
为克现有掩模优化技术优化方法复杂的缺陷,本发明提供一种Hessian-Free的光刻掩模优化方法、装置及电子设备。
为了解决上述技术问题,本发明提供一种Hessian-Free的光刻掩模优化方法,用于对待优化掩模进行优化,包括如下步骤:S1、输入待优化掩模的设计版图;S2、在所述待优化掩模的设计版图上放置误差监测点;S3、获得所述待优化掩模的优化变量x;S4、提供关于优化变量x的目标函数cost;S5、利用基于Hessian-Free的共轭梯度方法对所述目标函数cost进行优化,以得到所述待优化掩模的优化结果。
优选地,定义所述目标函数cost如下:
式中:ci表示第i个曝光条件,pj表示第j个误差监测点,Power为一设定的正偶数值,Signal(ci,pj)表示在第i个曝光条件下第j个误差监测点处的信号误差值,所述信号误差值包括RI的强度或者EPE值,所述RI为光刻胶上的图样的强度,EPE为边缘定位误差。
优选地,所述待优化掩模包括主图形,所述步骤S3中,所述待优化掩模的优化变量x包括主图形的边和/或放置在所述主图形的周围的辅助图形采样点;或者根据所述辅助图形采样点的信号值放置的辅助图形的边。
优选地,所述步骤S5具体包括如下步骤:S51、设定一初始优化变量值x0;S52、计算所述目标函数cost的初始优化变量值x0的梯度值g0;S53、判定梯度值g0是否小于设定的阈值,若是;则执行如下步骤:S54、结束优化流程,得到所述待优化掩模的优化结果;若否,则执行如下步骤:S55、基于H·p
k与优化变量x
k的特征向量v
k的关系对所述优化变量x
k进行迭代更新以获得更新变量x
k+1,其中H为关于目标函数cost的Hessian矩阵,所述P
k=-g
k,所述g
k为优化变量x
k对于目标函数的梯度。
优选地,上述步骤S55包括如下步骤:
S552、计算,v
k+1=v
k+α
kp
k;S553、更新优化变量:x
k+1=x
0+v
k+1。
(H·v)
k可通过如下公式计算获得:
在所述步骤T02中,当所述Signal(ci,pj)为RI时,所述RI可通过如下步骤获得:
T021、计算:
T022、计算:
T023、计算:
T024、计算
其中,所述s
t,o和d
t,l为关于掩模到格点化掩模计算的线性系数,所述E
o表示图形边的位移变量,所述P
l表示辅助图形采样点的信号值,MI
t(0)为初始值,即E
o和P
l均为0时的初始MI。
T025、计算
T026、计算所述Rv(RI),所述Rv(RI)可通过如下步骤计算获得:
T0261、计算
T0262、计算
T0263、计算
T0264、计算
优选地,当所述Signal(ci,pj)为EPE时,所述EPE可通过如下步骤获得:
T027、计算
T028、计算
T029、计算
T030、计算
其中,d
i,j关于掩模到格点化掩模的计算的线性系数。
所述Rv(RI)可通过上述步骤T0261-T0264计算获得。
本发明为了解决上述技术问题还提供一种Hessian-Free的光刻掩模优化装置,其包括输入模块、误差监测点放置模块、优化变量生成模块、目标函数生成模块以及优化计算模块,输入模块,配置用于输入待优化掩模的设计版图;误差监测点放置模块,配置用于在所述待优化掩模的设计版图上放置误差监测点;优化变量生成模块,配置用于获得所述待优化掩模的优化变量x;目标函数生成模块,提供关于优化变量x的目标函数cost;及优化计算模块,配置用于基于Hessian-Free的共轭梯度方法对所述目标函数cost进行优化,以得到所述待优化掩模的优化结果。
本发明为了解决上述技术问题还提供一种电子设备,其包括一个或多个处理器;存储装置,用于存储一个或多个程序,当所述一个或多个程序被所述一个或多个处理器执行,使得所 述一个或多个处理器实现如上所述的任一项方法。
与现有技术相比,利用基于Hessian-Free的共轭梯度方法对所述目标函数cost进行优化,以得到所述待优化掩模的优化结果,不需要直接计算出关于目标函数cost的Hessian矩阵,能很好的缩小优化过程中的计算资源,使得优化过程更简单,可行,并且提高优化效率;同时不需要类似采用拟牛顿法获得关于H矩阵的近似替换矩阵,能很好的提高优化结果的准确性。
基于H·p
k与优化变量x
k的特征向量v
k的关系对所述优化变量x
k进行迭代更新以获得更新变量x
k+1,能很好避免优化过程中需要单独计算H矩阵带来的运算量大导致结果出错的问题,能大大提高计算效率。
本发明提供的基于Hessian-Free的共轭梯度装置以及电子设备具有和基于Hessian-Free的共轭梯度方法相同的有益效果。
图1是本发明第一实施例中提供的Hessian-Free的光刻掩模优化方法的流程示意图;
图2是本发明第一实施例中提供的Hessian-Free的光刻掩模优化方法中待优化掩模的设计版图的示意图;
图3是本发明第一实施例中提供的Hessian-Free的光刻掩模优化方法放置的误差监测点的示意图;
图4是本发明第一实施例中提供的Hessian-Free的光刻掩模优化中优化变量为主图形的边时的示意图;
图5是本发明第一实施例中提供的Hessian-Free的光刻掩模优化方法中步骤S3的细节流程图;
图6是本发明第一实施例中提供的Hessian-Free的光刻掩模优化方法中辅助图形采样点放置区示意图;
图7是本发明第一实施例中提供的Hessian-Free的光刻掩模优化方法中放置的辅助图形采样点的示意图;
图8是本发明第一实施例中Hessian-Free的光刻掩模优化方法中步骤S5的细节流程图;
图9是本发明第一实施例中Hessian-Free的光刻掩模优化方法中步骤S55的细节流程图;
图10是本发明第一实施例中Hessian-Free的光刻掩模优化方法中步骤S5在变形实施例中的细节流程图;
图11是本发明第一实施例中提供的Hessian-Free的光刻掩模优化方法中在辅助图形放置区域中放置了辅助图形后的掩模示意图;
图12是本发明第一实施例中提供的Hessian-Free的光刻掩模优化方法中优化变量为主图形的边以及辅助图形的边进行优化后的掩模示意图;
图13是本发明第一实施例中提供的Hessian-Free的光刻掩模优化方法中优化后掩模形成的抗蚀剂图像示意图;
图14是本发明第二实施例中提供的Hessian-Free的光刻掩模优化装置的模块示意图;
图15是本发明第三实施例中提供的电子设备的模块示意图;
图16是适于用来实现本发明实施例的服务器的计算机系统的结构示意图。
为了使本发明的目的,技术方案及优点更加清楚明白,以下结合附图及实施实例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。
请参阅图1,本发明第一实施例提供一种Hessian-Free的光刻掩模优化方法,用于对待优化掩模进行优化,包括如下步骤:
S1、输入待优化掩模的设计版图;
在本发明中,首先提供一目标芯片的设计图形,根据目标芯片的设计图形设计与该目标芯片设计图形对应的掩模版图,掩模版图根据目标芯片的设计图形的光刻需求布设即获得待优化掩模设计版图,其上包括至少一个主图形。在本步骤中,如图2为待优化掩模设计版图,则区域M即为主图形。通常主图形也称为曝光图形,曝光后其会转移到半导体器件上。本实施例中区域M为矩形,在其他实施方式中,主图形可以为其它图形,主要取决于目标芯片的具体形状而定,如梯形、不规则多边形、规则多边形等其他图形都可以。可选地,输入的待优化掩模设计版图以GDS格式存在。
请再次参阅图1,一种Hessian-Free的光刻掩模优化方法还包括如下步骤:
S2、在所述待优化掩模的设计版图上放置误差监测点;
请参阅图3,在所述待优化掩模设计版图上放置误差监测点,也就是在主图形的边上放置误差监测点。误差监测点的作用在于:通过检测光刻软件仿真出的曝光后光刻胶图形边缘与设计图形边缘之间的差值判定迭代优化后的掩模是否合格。误差监测点的放置可以按人为经验进行放置。如图3中所示,针对主图形的边,可以将误差监测点放置在边上。在一些其他的实施方式中,还可以针对主图形的拐角处放置误差监测点,具体的放置位置为拐角靠近中心位置的地方。
请再次参阅图1,一种Hessian-Free的光刻掩模优化方法还包括如下步骤:
S3、获得所述待优化掩模的优化变量x;
在本步骤中,所述待优化掩模的优化变量x包括主图形的边和/或放置在所述主图形的周围的辅助图形采样点;或者根据所述辅助图形采样点的信号值放置的辅助图形的边。
请参阅图4,以主图形的边作为优化变量x时主要是将主图形的边切割为小线段的短边,每条短边根据其位置的不同标记为不同的类型,优化过程中以短边作为处理的基本单位,对不 同位置的短边获得不同的优化变量。切割处理使优化的对象更加明确、单一以及准确,避免了对主图形进行整体优化时情形过于复杂的问题。在本步骤中,将短边作为优化的第一变量的优化策略主要是相应线段的移动。根据不同线段位置的不同和光刻胶上图样的成像特点选择不同的移动方向以及不同的移动步长,循序步进,多次迭代操作,直至获得最终优化结果。
在本发明第一实施例的第一变形实施例中,以放置在所述主图形的周围的辅助图形采样点作为优化变量x时可以一预设的规则在辅助图形的周围形成辅助图形放置区域,在辅助图形放置区域中放置辅助图形采样点,利用辅助图形采样点对待优化掩模进行优化,对放置的辅助图形采样点进行信号值监测,根据辅助图形采样点信号值的大小获得需要放置辅助图形的辅助图形采样点。请参阅图5,作为一种实施方式,辅助图形采样点的放置具体包括如下步骤:
S31、设定一辅助图形放置区域形成的最小变量x1,以及一辅助图形放置区域形成的最大变量x2;
在本步骤中,其中,最小变量x1和最大变量x2分别是主图形的扩大系数,其中最小变量x1小于等于最大变量x2,最小变量x1大于等于零,最大变量x2不等于零。
请再次参阅图5,辅助图形采样点的放置还包括如下步骤:
S32、将所述主图形扩大x1获得图形A,将所述主图形扩大x2获得图形B;最小变量x1和最大变量x2的设定可以按照如下方式进行:生成的图形A的边和主图形的边两者的最近距离为d1,生成的图形B的边和主图形的边的最近距离为d2,具体地,d1的数值范围为20-100nm,d2的数值范围为100-400nm。
在本步骤中,图形A和图形B如图6所示。
请再次参阅图5,辅助图形采样点的放置还包括如下步骤:
S33、对所述图形A和所述图形B进行异或运算以获得所述辅助图形放置区域;
在本步骤中,辅助图形放置区域即图形A和图形B的边缘围合形成的区域C,也即对应图6中的填充区域,可见,辅助图形放置区域的轮廓和主图形的轮廓相一致。区域C如图6所示。
请再次参阅图5,辅助图形采样点的放置还包括如下步骤:
S34、在所述辅助图形放置区域内放置辅助图形信号采样点。
在本步骤中,当放置了辅助图形信号采样点之后,赋予每个所述辅助图形信号采样点的初始信号值为0,在优化的过程中,当辅助图形信号采样点的信号值超过设定的阈值时,则在对应该点的辅助图形信号采样的位置放置辅助图形,反之,则不放置。
在本步骤中,按照一预设规则放置辅助图形采样点。具体地,所述预设规则可以是:设置多行辅助图形采样点,同一行中任意相邻的两个辅助图形采样点之间的间距为x,任意相邻两行的行距同样为x,在具体的优化过程中,可以根据实际的优化效果调节x值的大小。
在一些其他实施方式中,为了更快速和更准确的放置辅助 图形采样点,可以将辅助图形放置区域分割成多个矩形块,在每个矩形块中以设定的间距x放置辅助图形采样点。
在辅助图形放置区域放置的辅助图形采样点如图7所示。
在本发明第一实施例的第二变形实施例中,以主图形的边以及辅助图形信号采样点作为优化变量x。
在本发明第一实施例的第三变形实施例中,以根据所述辅助图形采样点的信号值放置的辅助图形的边为优化变量,以放置的辅助图形的边为优化变量对辅助图形进行优化的方式和以主图形的边为优化变量的优化方式相类似,同样是对辅助图形的边进行分割,然后对分割获得的短边进行移动相应的位移,对辅助图形进行优化。如图9所示,为最终优化的掩模的图形。
需要说明的是,除了上述提供的优化变量之外,其他的优化变量同样可以。
请再次参阅图1,一种Hessian-Free的光刻掩模优化方法还包括如下步骤:
S4、提供关于优化变量x的目标函数cost,及
S5、利用基于Hessian-Free的共轭梯度方法对所述目标函数cost进行优化,以得到所述待优化掩模的优化结果。
在步骤S4中,定义所述目标函数cost如下:
式中:ci表示第i个曝光条件,pj表示第j个误差监测点,Power为一设定的正偶数值(Power=2、4、6……),Signal(ci,pj)表示在第i个曝光条件下第j个误差监测点处的信号误差值,所述信号误差值包括RI的强度或者EPE值中的一种,所述RI为光刻胶上的图样的强度,EPE为边缘定位误差。
请参阅图8,所述步骤S5具体包括如下步骤:
S51、设定一初始优化变量值x
0;
在本步骤中,比如优化变量为主图形的边时,则对应的初始优化变量值x
0为随机设定的移动距离,可具体为2nm。
S52、计算所述目标函数cost的初始优化变量值x
0的梯度值g
0;
在步骤S52中,计算所述目标函数cost的初始优化变量值x
0的梯度值g
0。以下举例说明对于初始优化变量值x
0为主图形的边时的梯度值g
0。目标函数cost的梯度相对于优化变量值x
0可以基于如下级联关系式计算获得:
1)
在计算1)中的各式子的计算和现有的ILT(Inverse Lithography Technology,反演光刻技术)的过程相同,在此不再赘述。
S53、判定梯度值g
0是否小于设定的阈值,若是;则执行如下步骤:
S54、结束优化流程,得到所述待优化掩模的优化结果;
若否,则执行如下步骤:
S55、基于H·p
k与优化变量x
k的特征向量v
k的关系对所述优化变量x
k进行迭代更新以获得更新变量x
k+1。
在步骤S55中,首先令迭代次数k=0(K=0、1、2、4、5……),请参阅图9,步骤S55具体包括如下步骤:
步骤S551、计算系数α
k,定义α
k可通过如下关系式确定:
步骤S552、计算,
v
k+1=v
k+α
kp
k,
其中,所述v
k为一个多维向量,例如,当优化变量为主图形的边时,其每个分量为优化变量迭代K次的过程中的主图形边的位置变化值,可见其为已知的数值。可以理解,当优化变量为辅助图形采样点时,其每个分量对应为优化变量迭代K次的过程中,辅助图形采样点信号的变化值。
步骤S553、更新优化变量:x
k+1=x
k+v
k+1。
请参阅图10,所述步骤S5还包括步骤:
S56、通过所述H·p
k的计算结果计算迭代优化后的优化变量x
k+1的梯度值r
k+1,在本步骤中,所述r
k+1通过如下公式获得:r
k+1=r
k-α
k(H·p
k)
步骤S57、判定|r
k+1|是否小于设定的阈值,若是则执行步骤S58、终止优化,并将当前的优化变量作为优化结果,否则执行步骤:
S59、计算系数β
k以及p
k+1并返回步骤S55,定义β
k以及p
k+1可分别通过下式计算获得:
1)
2)
p
k+1=r
k+1+β
kp
k;
上述步骤中,H·p
k的获得包括如下步骤:
首先需要说明的是,H·p
k中的p
k代表第k次迭代循环的所有优化变量相关的特征值,因此,在以下步骤中,(H·v)
k中的v代表 任一次循环的p
k,(H·v)
k指的是(H·v)的第k项分量。
T01、定义算符:
T02、计算:(H·v)
k
(H·v)
k可通过如下公式计算获得:
在所述步骤T02中,p为设定的正偶数,如(p=4、6、8……)。当所述Signal(ci,pj)为RI时,所述RI可通过如下步骤获得:
T021、计算:
T022、计算:
T0221、计算交叉传递系数矩阵;
T0222、计算部分相干核函数。
在步骤T0221中,可以通过现有的解析法、积分法以及傅里叶变换的方法计算得出所述交叉传递系数矩阵。其中傅里叶变换的方法能适应不同类型的光源,并且具有较快的计算速率,在本发明中,选用傅里叶变换的方法计算。
在步骤T0222中,首先需要将四维的交叉传递系数矩阵表示成二维矩阵,然后对其做特征值分解以得到其本征系数与特征向量。其中,计算得到的特征向量即对应为部分相干核函数。在本步骤中,主要是基于光学成像模型Hopkins(霍普金斯统计量)将交叉传递系数矩阵进行特征值分解,保留前n项,每一项由本征系数和特征向量表示。因此获得第n项本征系数λ
n和特征向量。EI
n,m由MI与所述特征向量卷积计算获得,具体通过T023计算获得;
T023、计算
其中,所述s
t,o和d
t,l为关于掩模到格点化掩模计算的线性系数,所述E
o表示图形边的位移变量,所述P
l表示辅助图形采样点的信号值,MI
t(0)为初始值,即E
o和P
l均为0时的初始MI。可以理解,上述所述的MI
t只是其中的一个举例,在实际运算中根据具体的优化变量做调整。比如,当所述优化变量为主图形的边时,则
在一些具体的实施方式中,MI
t(0)可通过对E确定的掩模图形进行卷积操作得到,其具体包括如下步骤:
T0231、通过卷积运算获得低通滤波器矩阵(卷积核);
T0232、对所述掩模图形中的每个像素点进行计算,计算每个像素点的邻域像素和所述低通滤波器矩阵对应元素的乘积,并将对应元素的值进行相加,获得代表该像素位置的特征值,从而形成关于所述掩膜图形的特征图。
可见,所述特征图上的特征值即对应为MI
t(0)。需要说明的是,在本步骤中,通过对E确定的掩模图形进行卷积操作为常用的图像滤波卷积操作算法,在此不再做过多的赘述。
T025、计算
其中v
o为v的第o项分量,初始优化的特征向量,v
l为v的第1项分量。
T026、计算所述
Rv(RI),所述Rv(RI)可通过如下步骤计算获得:
T0251、计算
T0262、计算
T0263、计算
T0264、计算
在一些其他实施方式中,当所述Signal(ci,pj)为EPE(边缘定位误差)时,所述EPE可通过如下步骤获得:
T027、计算
T028、计算
T029、计算
T030、计算
其中,RI
i的计算可通过上述的步骤:T021-T023计算获得,在此不再赘述。d
i,j关于掩模到格点化掩模的计算的线性系数。
所述Rv(RI)可通过上述步骤T0261-T0264计算获得,在此不再赘述。
其中每一个曝光条件下的H
j·v计算方法可通过上述提供的计算获得。在本实施例中,采用多个曝光条件进行测试,具体包括标准曝光条件(NC)、曝光剂量+3%(PD3)、曝光剂量-3%(ND3)、离焦+40nm(PF40)、离焦-40nm(NF40)。其中,标准曝光条件是指,光刻机在理想的工作状态下,即曝光值在设置的标准值,镜头聚焦也在设置的标准值上,没有偏移。
请参阅图11,以主图形的边以及辅助图形信号采样点作为优化变量x优化后的掩模版图如图11所示,主图形的边做了相应的移动,并且在基于辅助图形信号采样点的信号值大小放置了辅助图形。
请参阅图12,以主图形的边为优化变量结合辅助图形的边为优化变量对掩模进行优化,如图12中所示为最终优化的掩模的图形。
请参阅图13,对所述最终优化的掩模进行优化计算获得的抗蚀剂图像和放置在初始设计掩模的设计版图的监测点吻合,因此可以说明,本发明提供的Hessian-Free的光刻掩模优化方法具有较好的优化效果。
同时,对EPE(边缘定位误差)和pvhand(某一检测点处于不同的曝光条件下EPE的分布宽度)进行统计分析获得如下数值:
曝光条件 | Maximum EPE(nm) |
NC | 0.378 |
PD3 | 1.476 |
ND3 | 1.542 |
其中,EPE是指通过目标函数计算得到的硅片上的图形和实际所需图形(目标图形)的边缘之间的误差。
Pvband指的是不同曝光条件下EPE分布的宽度。
Maximum Pvband=2.97nm,通过具体的EPE数值和Pvband值进一步说明可本发明提供的Hessian-Free的光刻掩模优化方法具有较好的优化效果。
请参阅图14,本发明的第二实施提供一种Hessian-Free的光刻掩模优化装置200,包括输入模块201、误差监测点放置模块202、优化变量生成模块203、目标函数生成模块204以及优化计算模块205。
输入模块201,配置用于输入待优化掩模的设计版图;
误差监测点放置模块202,配置用于在所述待优化掩模的 设计版图上放置误差监测点;
优化变量生成模块203,配置用于获得所述待优化掩模的优化变量x;
目标函数生成模块204,提供关于优化变量x的目标函数cost;及
优化计算模块205,配置用于基于Hessian-Free的共轭梯度方法对所述目标函数cost进行优化,以得到所述待优化掩模的优化结果。
请参阅图15,本发明的第三实施提供一种电子装置300,其包括一个或多个处理器302;
存储装置301,用于存储一个或多个程序,
当所述一个或多个程序被所述一个或多个处理器302执行,使得所述一个或多个处理器302实现如第一实施提供的基于模型的数据处理方法的任一步骤。
下面参考图16,其示出了适于用来实现本发明实施例的终端设备/服务器的计算机系统800的结构示意图。图16示出的终端设备/服务器仅仅是一个示例,不应对本申请实施例的功能和使用范围带来任何限制。
如图16所示,计算机系统800包括中央处理单元(CPU)801,其可以根据存储在只读存储器(ROM)802中的程序或者从存储部分808加载到随机访问存储器(RAM)803中的程序而执行各种适当的动作和处理。在RAM 803中,还存储有系统800操作所需的各种程序和数据。CPU 801、ROM 802以及RAM 803通过总线804彼此相连。输入/输出(I/O)接口805也连接至总线804。
以下部件连接至I/O接口805:包括键盘、鼠标等的输入部分806;包括诸如阴极射线管(CRT)、液晶显示器(LCD)等以及扬声器等的输出部分807;包括硬盘等的存储部分808;以及包括诸如LAN卡、调制解调器等的网络接口卡的通信部分809。通信部分809经由诸如因特网的网络执行通信处理。驱动器810也根据需要连接至I/O接口805。可拆卸介质811,诸如磁盘、光盘、磁光盘、半导体存储器等等,根据需要安装在驱动器810上,以便于从其上读出的计算机程序根据需要被安装入存储部分808。
根据本公开的实施例,上文参考流程图描述的过程可以被实现为计算机软件程序。例如,本公开的实施例包括一种计算机程序产品,其包括承载在计算机可读介质上的计算机程序,该计算机程序包含用于执行流程图所示的方法的程序代码。在这样的实施例中,该计算机程序可以通过通信部分809从网络上被下载和安装,和/或从可拆卸介质811被安装。在该计算机程序被中央处理单元(CPU)801执行时,执行本发明的方法中限定的上述功能。需要说明的是,本发明所述的计算机可读介质可以是计算机可读信号介质或者计算机可读存储介质或者是上述两者的任意组合。计算机可读存储介质例如可以是-但不限于-电、磁、光、电磁、红外线、或半导体的系统、装 置或器件,或者任意以上的组合。计算机可读存储介质的更具体的例子可以包括但不限于:具有一个或多个导线的电连接、便携式计算机磁盘、硬盘、随机访问存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑磁盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。
可以以一种或多种程序设计语言或其组合来编写用于执行本申请的操作的计算机程序代码,所述程序设计语言包括面向对象的程序设计语言-诸如Java、Smalltalk、C++,还包括常规的过程式程序设计语言-诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算机上执行、部分地在用户计算机上执行、作为一个独立的软件包执行、部分在用户计算机上部分在远程计算机上执行、或者完全在远程计算机或服务器上执行。在涉及远程计算机的情形中,远程计算机可以通过任意种类的网络——包括局域网(LAN)或广域网(WAN)-连接到用户计算机,或者,可以连接到外部计算机(例如利用因特网服务提供商来通过因特网连接)。
附图中的流程图和框图,图示了按照本发明各种实施例的系统、方法和计算机程序产品的可能实现的体系架构、功能和操作。在这点上,流程图或框图中的每个方框可以代表一个模块、程序段、或代码的一部分,该模块、程序段、或代码的一部分包含一个或多个用于实现规定的逻辑功能的可执行指令。也应当注意,在有些作为替换的实现中,方框中所标注的功能也可以以不同于附图中所标注的顺序发生。例如,两个接连地表示的方框实际上可以基本并行地执行,它们有时也可以按相反的顺序执行,这依所涉及的功能而定。也要注意的是,框图和/或流程图中的每个方框、以及框图和/或流程图中的方框的组合,可以用执行规定的功能或操作的专用的基于硬件的系统来实现,或者可以用专用硬件与计算机指令的组合来实现。
描述于本发明实施例中所涉及到的单元可以通过软件的方式实现,也可以通过硬件的方式来实现。所描述的单元也可以设置在处理器中,例如,可以描述为:一种处理器包括输入模块、误差监测点放置模块、优化变量生成模块、目标函数生成模块以及优化计算模块。其中,这些单元的名称在某种情况下并不构成对该单元本身的限定,例如,输入模块还可以被描述为“用于输入待优化掩模的设计版图”。作为另一方面,本发明还提供了一种计算机可读介质,该计算机可读介质可以是上述实施例中描述的装置中所包含的;也可以是单独存在,而未装配入该装置中。上述计算机可读介质承载有一个或者多个程序,当上述一个或者多个程序被该装置执行时,使得该装置:输入待优化掩模的设计版图,在所述待优化掩模的设计版图上放置误差监测点,获得所述待优化掩模的优化变量x,提供关于优化变量x的目标函数coat及基于Hessian-Free的共轭梯度方法对所述目标函数cost进行优化,以得到所述待优化掩模的优化结果。
以上所述仅为本发明较佳实施例而已,并不用以限制本发明,凡在本发明原则之内所作的任何修改,等同替换和改进等均应包含本发明的保护范围之内。
Claims (10)
- 一种Hessian-Free的光刻掩模优化方法,用于对待优化掩模进行优化,其特征在于,包括如下步骤:S1、输入待优化掩模的设计版图;S2、在所述待优化掩模的设计版图上放置误差监测点;S3、获得所述待优化掩模的优化变量x;S4、提供关于优化变量x的目标函数cost;S5、利用基于Hessian-Free的共轭梯度方法对所述目标函数cost进行优化,以得到所述待优化掩模的优化结果。
- 如权利要求1所述的Hessian-Free的光刻掩模优化方法,其特征在于:所述待优化掩模包括主图形,所述步骤S3中,所述待优化掩模的优化变量x包括主图形的边和/或放置在所述主图形的周围的辅助图形采样点;或者根据所述辅助图形采样点的信号值放置的辅助图形的边。
- 如权利要求1所述的Hessian-Free的光刻掩模优化方法,其特征在于:所述步骤S5具体包括如下步骤:S51、设定一初始优化变量值x 0;S52、计算所述目标函数cost的初始优化变量值x 0的梯度值g 0;S53、判定梯度值g 0是否小于设定的阈值,若是;则执行如下步骤:S54、结束优化流程,得到所述待优化掩模的优化结果;若否,则执行如下步骤:S55、基于H·p k与优化变量x k的特征向量v k的关系对所述优化变量x k进行迭代更新以获得更新变量x k+1, 其中H为关于目标函数cost的Hessian矩阵,所述P k=-g k,所述g k为优化变量x k对于目标函数的梯度。
- 如权利要求6所述的Hessian-Free的光刻掩模优化方法,其特征在于:所述H·p k的获得包括如下步骤:T01、定义算符:T02、计算(H·v) k(H·v) k可通过如下公式计算获得:在所述步骤T02中,当所述Signal(ci,pj)为RI时,所述RI可通过如下步骤获得:T021、计算:T022、计算:T023、计算:T024、计算其中,所述s t,o和d t,l为关于掩模到格点化掩模计算的线性系数,所述E o表示图形边的位移变量,所述P l表示辅助图形采样点的信号值,MI t(0)为初始值,即E o和P l均为0时的初始MI。T025、计算其中v o为v的第o项分量,初始优化的特征向量,v l为v的第l项分量;T026、计算所述Rv(RI),所述Rv(RI)可通过如下步骤计算获得:T0261、计算T0262、计算T0263、计算T0264、计算
- 一种Hessian-Free的光刻掩模优化装置,其特征在于:其包括输入模块、误差监测点放置模块、优化变量生成模块、目标函数生成模块以及优化计算模块,所述输入模块,配置用于输入待优化掩模的设计版图;所述误差监测点放置模块,配置用于在所述待优化掩模的设计版图上放置误差监测点;所述优化变量生成模块,配置用于获得所述待优化掩模的优化变量x;所述目标函数生成模块,提供关于优化变量x的目标函数cost;及所述优化计算模块,配置用于基于Hessian-Free的共轭梯度方法对所述目标函数cost进行优化,以得到所述待优化掩模的优化结果。
- 一种电子设备,其特征在于:其包括一个或多个处理器;存储装置,用于存储一个或多个程序,当所述一个或多个程序被所述一个或多个处理器执行,使得所述一个或多个处理器实现如权利要求1-8中任一项所述的方法。
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