WO2020147575A1 - 薄膜晶体管的制备方法及显示装置 - Google Patents

薄膜晶体管的制备方法及显示装置 Download PDF

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WO2020147575A1
WO2020147575A1 PCT/CN2019/130303 CN2019130303W WO2020147575A1 WO 2020147575 A1 WO2020147575 A1 WO 2020147575A1 CN 2019130303 W CN2019130303 W CN 2019130303W WO 2020147575 A1 WO2020147575 A1 WO 2020147575A1
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metal layer
layer
source
drain
thin film
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French (fr)
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何怀亮
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HKC Co Ltd
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HKC Co Ltd
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/10—Etching compositions
    • C23F1/14—Aqueous compositions
    • C23F1/16—Acidic compositions
    • C23F1/20—Acidic compositions for etching aluminium or alloys thereof
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/10—Etching compositions
    • C23F1/14—Aqueous compositions
    • C23F1/16—Acidic compositions
    • C23F1/26—Acidic compositions for etching refractory metals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices

Definitions

  • This application relates to the field of thin film transistor liquid crystal display technology, and in particular to a method for manufacturing a thin film transistor and a display device.
  • TFT Thin Film Transistor
  • LCD Crystal Display
  • the source and drain electrodes are generally obtained by wet etching the source and drain metal layers.
  • the source and drain metal layers usually adopt a molybdenum nitride/aluminum/molybdenum nitride multilayer metal structure.
  • the reaction rate of the etching solution is relatively small, so that molybdenum metal residues easily appear in the source and drain electrodes obtained after wet etching, which affects the performance of the thin film transistor.
  • the main purpose of this application is to provide a method for manufacturing a thin film transistor and a display device, which improves the reaction rate of the molybdenum metal layer and the etching solution, and reduces the residue of metal molybdenum in the source and drain.
  • the present application provides a method for manufacturing a thin film transistor, which includes the following steps:
  • the first molybdenum metal layer, the aluminum metal layer and the second molybdenum metal layer are sequentially deposited on the semiconductor layer of the substrate by physical vapor deposition to obtain a source-drain metal layer, wherein the first molybdenum metal layer and the second molybdenum metal layer are deposited
  • the nitrogen flow rate is 0sccm ⁇ 1000sccm;
  • Etching the source and drain metal layers with an etching solution to obtain source and drain electrodes wherein the etching solution includes a mixed solution of hydrochloric acid and nitric acid;
  • a passivation layer and an electrode layer are sequentially formed on the source electrode and the drain electrode.
  • the nitrogen gas flow rate is 0 sccm to 750 sccm.
  • the flow rate of nitrogen gas introduced is 500 sccm.
  • the material of the electrode layer includes indium tin oxide.
  • the method before the step of sequentially depositing a first molybdenum metal layer, an aluminum metal layer and a second molybdenum metal layer on the semiconductor layer of the substrate by using a physical vapor deposition method to obtain the source and drain metal layers, the method further includes:
  • the method further includes:
  • the substrate is cleaned.
  • the etching temperature in the process of etching the source and drain metal layers with an etching solution is 30°C-40°C.
  • the etching temperature is 32°C to 37°C.
  • the etching temperature is 35°C.
  • the etching solution includes hydrochloric acid and nitric acid, wherein the concentration by weight of the nitric acid is 1.5% to 3.5%.
  • the weight percentage concentration of the nitric acid is 2% to 3%.
  • the concentration by weight of the nitric acid is 2.5%.
  • the step of etching the source and drain metal layers with an etchant to obtain source and drain electrodes includes:
  • the etchant includes a mixture of hydrochloric acid and nitric acid Solution.
  • the material of the gate includes at least one of aluminum, molybdenum and copper.
  • the gate and the electrode layer are prepared by a physical vapor deposition method
  • the gate insulating layer, the semiconductor layer, and the passivation layer are prepared by a chemical vapor deposition method.
  • this application also proposes a method for manufacturing a thin film transistor, which includes the following steps:
  • a first molybdenum metal layer, an aluminum metal layer, and a second molybdenum metal layer are sequentially deposited on the semiconductor layer using a physical vapor deposition method to obtain a source-drain metal layer, wherein the first molybdenum metal layer and the second molybdenum metal layer are deposited
  • the nitrogen flow rate is 0sccm ⁇ 1000sccm;
  • the source and drain metal layers are etched at 30°C to 40°C using an etching solution to obtain source and drain electrodes, wherein the etching solution includes a mixed solution of hydrochloric acid and nitric acid, wherein the nitric acid weight percentage concentration is 1.5% ⁇ 3.5%;
  • a passivation layer and an electrode layer are sequentially formed on the source electrode and the drain electrode.
  • the gate and the electrode layer are prepared by a physical vapor deposition method
  • the gate insulating layer, the semiconductor layer, and the passivation layer are prepared by a chemical vapor deposition method.
  • the present application also proposes a display device, the display device includes a thin film transistor, the thin film transistor includes a gate, a gate insulating layer, a semiconductor layer, a source and a drain, which are sequentially stacked on a substrate.
  • Passivation layer, electrode layer, the thin film transistor is prepared by the following steps:
  • the first molybdenum metal layer, the aluminum metal layer, and the second molybdenum metal layer are sequentially deposited on the semiconductor layer of the substrate by physical vapor deposition to obtain a source-drain metal layer, wherein the first molybdenum metal layer and the second molybdenum metal layer are deposited
  • the nitrogen flow rate is 0sccm ⁇ 1000sccm;
  • Etching the source and drain metal layers with an etching solution to obtain source and drain electrodes wherein the etching solution includes a mixed solution of hydrochloric acid and nitric acid;
  • a passivation layer and an electrode layer are sequentially formed on the source electrode and the drain electrode.
  • the embodiment of the application provides a method for manufacturing a thin film transistor and a display device.
  • a first molybdenum metal layer, an aluminum metal layer, and a second molybdenum metal layer are sequentially deposited on a semiconductor layer of a substrate using a physical vapor deposition method to obtain a source and drain metal layer ,
  • the nitrogen gas flow rate is 0sccm-1000sccm, and then the source and drain metal layers are etched with an etchant to obtain source and drain
  • the etching solution includes a mixed solution of hydrochloric acid and nitric acid, and then a passivation layer and an electrode layer are sequentially formed on the source and drain electrodes.
  • the nitrogen flow rate is controlled below 1000 sccm when depositing the molybdenum metal layer, the nitrogen content of the molybdenum metal layer is reduced, and the reaction rate of the molybdenum metal layer and the etching solution is increased, and the source and drain electrodes obtained by etching have no molybdenum metal residue.
  • FIG. 1 is a schematic diagram of the process flow of an embodiment of a method for manufacturing a thin film transistor according to the present application
  • FIG. 2 is a schematic flow diagram of the steps of another embodiment of the method for manufacturing a thin film transistor of the present application.
  • FIG. 1 is a schematic diagram of a step flow diagram of an embodiment of a method for manufacturing a thin film transistor according to the present application.
  • the method for manufacturing a thin film transistor includes:
  • Step S10 using a physical vapor deposition method to sequentially deposit a first molybdenum metal layer, an aluminum metal layer and a second molybdenum metal layer on the semiconductor layer of the substrate to obtain a source-drain metal layer, wherein the first molybdenum metal layer and the all When the second molybdenum metal layer is described, the nitrogen gas flow rate is 0sccm ⁇ 1000sccm;
  • a substrate on which a semiconductor layer has been deposited clean the substrate, and then deposit a source and drain metal layer on the semiconductor layer by Physical Vapor Deposition (PVD), and perform wet etching on the source and drain metal layer to obtain the source and drain pole.
  • PVD Physical Vapor Deposition
  • the substrate is sent to the vacuum chamber of the PVD device, and the first molybdenum metal layer, the aluminum metal layer and the semiconductor layer are sequentially deposited on the semiconductor layer of the substrate by the physical vapor deposition method.
  • the second molybdenum metal layer obtains a source and drain metal layer, wherein, when the first molybdenum metal layer and the second molybdenum metal layer are deposited, the nitrogen gas flow rate is 0 sccm to 1000 sccm.
  • first pure molybdenum is used as the target material, the nitrogen flow rate is controlled to 0sccm ⁇ 1000sccm, and the first molybdenum metal layer is deposited on the semiconductor layer of the substrate by physical vapor deposition; then pure aluminum is used as the target material, and the first molybdenum metal layer A physical vapor deposition method is used to deposit an aluminum metal layer on the layer; pure molybdenum is used as a target, and the nitrogen flow rate is controlled to be 0 sccm ⁇ 1000 sccm, and a second molybdenum metal layer is deposited on the aluminum metal layer by physical vapor deposition.
  • a source and drain metal layer composed of the first molybdenum metal layer, the aluminum metal layer and the second molybdenum metal layer is obtained.
  • the composition of the molybdenum metal layer in the present application may include pure molybdenum or molybdenum nitride.
  • Step S20 etching the source and drain metal layers with an etchant to obtain source and drain electrodes, wherein the etchant includes a mixed solution of hydrochloric acid and nitric acid;
  • the substrate on which the active drain metal layer is deposited is taken out, and then a layer of photoresist is applied, and the photoresist is exposed by the mask corresponding to the source and drain, and then developed, the etching solution is used to The source and drain metal layers are wet-etched, and then the substrate is put into a stripping solution, and the photoresist is stripped to obtain the source electrode and the drain electrode.
  • the etching solution includes a mixed solution of hydrochloric acid and nitric acid, and the etching solution can be an etching solution composed of hydrochloric acid and nitric acid used in conventional alumina acid etching.
  • the reaction rate of metal and etching solution is mainly related to the concentration of nitric acid in the etching solution.
  • concentration of nitric acid in the etching solution By adjusting the concentration of nitric acid in the etching solution, the reaction rate of the etching solution and the source and drain metal layers can be adjusted to better solve the source and drain metal layers.
  • the residue of metallic molybdenum after etching may be 1.5% to 3.5%.
  • the etching temperature can be the etching temperature used in conventional alumina etching, and there is no specific limitation.
  • the step of etching the source and drain metal layers with an etching solution is performed at 30°C-40°C.
  • step S30 a passivation layer and an electrode layer are sequentially formed on the source electrode and the drain electrode.
  • the passivation layer film can be deposited by a chemical vapor deposition method. Then apply a layer of photoresist, use the mask corresponding to the passivation layer to expose the photoresist, and then develop, dry etching, and then peel off the photoresist to obtain the passivation layer.
  • the passivation layer includes Hole pattern.
  • the material component of the pixel electrode layer film may be indium tin oxide. Then apply a layer of photoresist, use the mask corresponding to the pixel electrode layer to expose the photoresist, and after developing, perform wet etching, then put the substrate in the stripping solution, and peel off the photoresist to obtain the pixel electrode Layer (electrode layer).
  • FIG. 2 is a schematic flow chart of the steps of another embodiment of the method for manufacturing a thin film transistor according to the present application. Before the step S10, it further includes:
  • Step S40 provides a substrate
  • a substrate is provided as a substrate, and before the gate is prepared on the substrate, the substrate needs to be cleaned to prevent dirt on the substrate from affecting the uniformity of deposition or causing pollution in the subsequent deposition process.
  • step S50 a gate electrode, a gate insulating layer and a semiconductor layer which are sequentially stacked on the substrate are formed on the substrate.
  • a first metal layer is deposited on the cleaned substrate.
  • the first metal layer can be deposited by physical vapor deposition; optionally, the material of the first metal layer is at least one of copper, aluminum or molybdenum .
  • coat a layer of photoresist on the first metal layer use the mask corresponding to the gate layer to expose the photoresist, and then develop the exposed photoresist, and then perform wet etching with an etching solution. Then the substrate is put into the stripping solution, and the photoresist is stripped off to obtain the gate.
  • the gate insulating layer film and the semiconductor layer film can be deposited by chemical vapor deposition. Then a layer of photoresist is coated on the semiconductor layer, the photoresist is exposed using the mask corresponding to the semiconductor layer, and the exposed photoresist is developed, and then wet etched with an etching solution, and then the substrate Put it in a stripping solution, strip off the photoresist to obtain a gate.
  • Gate insulating layer and semiconductor layer is used to isolate the gate and the semiconductor layer to prevent the gate and the semiconductor layer from being connected to cause a short circuit.
  • etching is not required, and the source and drain metal layers are deposited directly after cleaning, and then coated with photoresist, and the photolithography is performed using the masks corresponding to the source and drain electrodes.
  • the glue is exposed, and then developed with a developer, and then two dry etching and two wet etching are performed to obtain the source electrode and the drain electrode, and the corresponding pattern of the semiconductor layer is obtained.
  • wet etching can be performed under the above-mentioned conditions.
  • the thin film transistor prepared according to the above solution includes a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode and a drain electrode, a passivation layer, and an electrode layer which are sequentially stacked on a substrate, wherein the source electrode and the drain electrode have no metal residue,
  • the passivation layer deposited on the source and drain has no undesirable conditions such as disconnection.
  • the present application also provides a display device, which includes the thin film transistor prepared by the above solution, and the display device may be a liquid crystal panel, electronic paper, OLED (Organic Light Emitting Diode (Organic Light Emitting Diode) panels, LCD TVs, LCD monitors, digital photo frames, mobile phones, tablet computers and other products or components with display functions.
  • OLED Organic Light Emitting Diode (Organic Light Emitting Diode) panels
  • LCD TVs Organic Light Emitting Diode
  • LCD monitors digital photo frames
  • mobile phones tablet computers and other products or components with display functions.
  • the steps of preparing the source electrode and the drain electrode are as follows: After cleaning the substrate on which the semiconductor layer has been deposited, the substrate Into the vacuum chamber of the PVD equipment, pure molybdenum was used as the target material, the nitrogen flow rate was controlled to 1000sccm, and the first molybdenum metal layer was deposited on the semiconductor layer of the substrate by physical vapor deposition; then pure aluminum was used as the target material.
  • the aluminum metal layer is deposited on the metal layer by physical vapor deposition; pure molybdenum is used as the target, and the nitrogen flow rate is controlled to 1000 sccm, and the second molybdenum metal layer is deposited on the aluminum metal layer by physical vapor deposition to obtain the source and drain metal layer .
  • the substrate on which the active drain metal layer is deposited is taken out, and then a layer of photoresist is coated, and the photoresist is exposed by the mask plate corresponding to the source electrode and the drain electrode, and then developed. Then, an etching solution composed of hydrochloric acid and nitric acid is used to wet-etch the source and drain metal layers at 40° C., wherein the concentration of nitric acid in the etching solution is 1.5% by weight. After the etching is completed, the substrate is put into the stripping solution, and the photoresist is stripped to obtain the source electrode and the drain electrode.
  • the wet-etched substrate was observed under a scanning electron microscope (SEM), and the results showed that the edges of the source and drain were flat without metal residue, and the taper angles on both sides of the source and drain were at Within the range of 40° ⁇ 60°.
  • a passivation layer and an electrode layer are sequentially formed on the source electrode and the drain electrode to obtain a thin film transistor.
  • the steps of preparing the source electrode and the drain electrode are as follows: After cleaning the substrate on which the semiconductor layer has been deposited, the substrate Into the vacuum chamber of the PVD equipment, pure molybdenum was used as the target, and the nitrogen flow rate was controlled to 750sccm. The first molybdenum metal layer was deposited on the semiconductor layer of the substrate by physical vapor deposition; then pure aluminum was used as the target.
  • the aluminum metal layer is deposited on the metal layer by physical vapor deposition; pure molybdenum is used as the target, and the nitrogen flow rate is controlled to 750sccm, and the second molybdenum metal layer is deposited on the aluminum metal layer by physical vapor deposition to obtain the source and drain metal layer .
  • the substrate on which the active drain metal layer is deposited is taken out, and then a layer of photoresist is coated, and the photoresist is exposed by the mask plate corresponding to the source electrode and the drain electrode, and then developed. Then, an etching solution composed of hydrochloric acid and nitric acid is used to wet-etch the source and drain metal layers at 37° C., where the concentration of nitric acid in the etching solution is 2% by weight. After the etching is completed, the substrate is put into the stripping solution, and the photoresist is stripped to obtain the source electrode and the drain electrode.
  • the wet-etched substrate was observed under a scanning electron microscope (SEM), and the results showed that the edges of the source and drain were flat without metal residue, and the taper angles on both sides of the source and drain were at Within the range of 40° ⁇ 60°.
  • a passivation layer and an electrode layer are sequentially formed on the source electrode and the drain electrode to obtain a thin film transistor.
  • the steps of preparing the source electrode and the drain electrode are as follows: After cleaning the substrate on which the semiconductor layer has been deposited, the substrate Into the vacuum chamber of the PVD equipment, pure molybdenum was used as the target material, and the nitrogen flow rate was controlled to 500 sccm. The first molybdenum metal layer was deposited on the semiconductor layer of the substrate by physical vapor deposition; then pure aluminum was used as the target material.
  • the aluminum metal layer is deposited on the metal layer by physical vapor deposition; pure molybdenum is used as the target material, and the nitrogen flow rate is controlled to 500sccm, and the second molybdenum metal layer is deposited on the aluminum metal layer by physical vapor deposition to obtain the source and drain metal layer .
  • the substrate on which the active drain metal layer is deposited is taken out, and then a layer of photoresist is coated, and the photoresist is exposed by the mask plate corresponding to the source electrode and the drain electrode, and then developed. Then, an etching solution composed of hydrochloric acid and nitric acid is used to wet-etch the source and drain metal layers at 35° C., wherein the concentration of nitric acid in the etching solution is 2.5% by weight. After the etching is completed, the substrate is put into the stripping solution, and the photoresist is stripped to obtain the source electrode and the drain electrode.
  • the wet-etched substrate was observed under a scanning electron microscope (SEM), and the results showed that the edges of the source and drain were flat without metal residue, and the taper angles on both sides of the source and drain were at Within the range of 40° ⁇ 60°.
  • a passivation layer and an electrode layer are sequentially formed on the source electrode and the drain electrode to obtain a thin film transistor.
  • the steps of preparing the source electrode and the drain electrode are as follows: After cleaning the substrate on which the semiconductor layer has been deposited, the substrate Into the vacuum chamber of the PVD equipment, pure molybdenum was used as the target material, and the nitrogen flow rate was controlled to 250sccm. The first molybdenum metal layer was deposited on the semiconductor layer of the substrate by physical vapor deposition; then pure aluminum was used as the target material.
  • the aluminum metal layer is deposited on the metal layer by physical vapor deposition; pure molybdenum is used as the target, and the nitrogen flow rate is controlled to 250sccm, and the second molybdenum metal layer is deposited on the aluminum metal layer by physical vapor deposition to obtain the source and drain metal layer .
  • the substrate on which the active drain metal layer is deposited is taken out, and then a layer of photoresist is coated, and the photoresist is exposed by the mask plate corresponding to the source electrode and the drain electrode, and then developed. Then, an etching solution composed of hydrochloric acid and nitric acid is used to wet-etch the source and drain metal layers at 32° C., wherein the concentration of nitric acid in the etching solution is 3% by weight. After the etching is completed, the substrate is put into the stripping solution, and the photoresist is stripped to obtain the source electrode and the drain electrode.
  • the wet-etched substrate was observed under a scanning electron microscope (SEM), and the results showed that the edges of the source and drain were flat without metal residue, and the taper angles on both sides of the source and drain were at Within the range of 40° ⁇ 60°.
  • a passivation layer and an electrode layer are sequentially formed on the source electrode and the drain electrode to obtain a thin film transistor.
  • the steps of preparing the source electrode and the drain electrode are as follows: After cleaning the substrate on which the semiconductor layer has been deposited, the substrate Into the vacuum chamber of the PVD equipment, pure molybdenum was used as the target, the nitrogen flow rate was controlled to 0sccm, and the first molybdenum metal layer was deposited on the semiconductor layer of the substrate by physical vapor deposition; then pure aluminum was used as the target, and the first molybdenum The aluminum metal layer is deposited on the metal layer by physical vapor deposition; pure molybdenum is used as the target, and the nitrogen flow rate is controlled to 0sccm, and the second molybdenum metal layer is deposited on the aluminum metal layer by physical vapor deposition to obtain the source and drain metal layer .
  • the substrate on which the active drain metal layer is deposited is taken out, and then a layer of photoresist is coated, and the photoresist is exposed by the mask plate corresponding to the source electrode and the drain electrode, and then developed. Then, an etching solution composed of hydrochloric acid and nitric acid is used to wet-etch the source and drain metal layers at 30° C., wherein the concentration of nitric acid in the etching solution is 3.5% by weight. After the etching is completed, the substrate is put into the stripping solution, and the photoresist is stripped to obtain the source electrode and the drain electrode.
  • the wet-etched substrate was observed under a scanning electron microscope (SEM), and the results showed that the edges of the source and drain were flat without metal residue, and the taper angles on both sides of the source and drain were at Within the range of 20° ⁇ 40°.
  • a passivation layer and an electrode layer are sequentially formed on the source electrode and the drain electrode to obtain a thin film transistor.
  • the edges of the source electrode and the drain electrode obtained in any of the above embodiments are flat and there is no metal residue, which well solves the problem of molybdenum metal residue that easily occurs after the source electrode and the drain electrode are etched.
  • the molybdenum metal layer (the first molybdenum metal layer and the second molybdenum metal layer) in the source and drain metal layers is prepared, when the nitrogen gas flow rate is 0 sccm, the resulting molybdenum metal layer
  • the material is pure molybdenum, and the taper angle between the source and drain obtained by etching is in the range of 20° ⁇ 40°; when preparing the molybdenum metal layer in the source and drain metal layer (the first molybdenum metal layer and the second molybdenum metal layer)
  • the nitrogen flow rate is not 0sccm (the nitrogen flow rate is 250 sccm, 500 sccm, 750 sccm or 1000 sccm)
  • the material of the obtained molybdenum metal layer is molybdenum nitride, and the taper angles on both sides of the source and drain obtained by etching are in

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Abstract

一种薄膜晶体管的制备方法和一种显示装置。所述薄膜晶体管的制备方法包括：利用物理气相沉积法在基板的半导体层上依次沉积第一钼金属层，铝金属层和第二钼金属层，得到源漏金属层，其中，沉积所述第一钼金属层和所述第二钼金属层时，通入的氮气流量为0sccm～1000sccm（S10）；利用蚀刻液对所述源漏金属层进行蚀刻，得到源极和漏极，其中，所述蚀刻液包括盐酸和硝酸的混合溶液（S20）；在所述源极和漏极上依次形成钝化层和电极层（S30）。

Description

薄膜晶体管的制备方法及显示装置
关于优先权引用的声明：本申请要求于2019年1月18日提交中国专利局，申请号为201910051342.9、发明名称为“薄膜晶体管的制备方法及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请。
技术领域
本申请涉及薄膜晶体管液晶显示技术领域，尤其涉及薄膜晶体管的制备方法及显示装置。
 背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
薄膜晶体管(Thin Film Transistor，TFT)是目前液晶显示装置(Liquid CrystalDisplay，LCD )中的主要驱动元件，TFT的性能直接关系液晶显示装置的显示性能。
TFT阵列的制备过程中，源极和漏极一般通过对源漏金属层进行湿蚀刻得到，源漏金属层通常采用氮化钼/铝/氮化钼的多层金属结构，由于氮化钼与蚀刻液的反应速率较小，从而进行湿蚀刻后得到的源极和漏极容易出现钼金属残留，影响薄膜晶体管的性能。
 技术解决方案
本申请的主要目的在于提供一种薄膜晶体管的制备方法及显示装置，提高了钼金属层与蚀刻液的反应速率，减少了源极和漏极的金属钼残留。
为实现本申请的目的，本申请提供一种薄膜晶体管的制备方法，所述薄膜晶体管的制备方法包括以下步骤：
利用物理气相沉积法在基板的半导体层上依次沉积第一钼金属层，铝金属层和第二钼金属层，得到源漏金属层，其中，沉积所述第一钼金属层和所述第二钼金属层时，通入的氮气流量为0sccm~1000sccm；
利用蚀刻液对所述源漏金属层进行蚀刻，得到源极和漏极，其中，所述蚀刻液包括盐酸和硝酸的混合溶液；
以及，在所述源极和漏极上依次形成钝化层和电极层。
可选地，所述沉积所述第一钼金属层和所述第二钼金属层时，通入的氮气流量为0sccm~750sccm。
可选地，所述沉积所述第一钼金属层和所述第二钼金属层时，通入的氮气流量为500sccm。
可选地，所述电极层的材料包括氧化铟锡。
可选地，所述利用物理气相沉积法在基板的半导体层上依次沉积第一钼金属层，铝金属层和第二钼金属层，得到源漏金属层的步骤之前，还包括：
提供基板；
以及，在所述基板上形成依次层叠于所述基板上的栅极、栅极绝缘层以及半导体层。
可选地，所述提供基板的步骤之后，还包括：
对所述基板进行清洗。
可选地，利用蚀刻液对所述源漏金属层进行蚀刻的过程中蚀刻温度为30℃~40℃。
可选地，所述蚀刻温度为32℃~37℃。
可选地，所述蚀刻温度为35℃。
可选地，所述蚀刻液中包括盐酸和硝酸，其中，所述硝酸重量百分比浓度为1.5%~3.5%。
可选地，所述硝酸的重量百分比浓度为2%~3%。
可选地，所述硝酸的重量百分比浓度为2.5%。
可选地，所述利用蚀刻液对所述源漏金属层进行蚀刻，得到源极和漏极，其中，所述蚀刻液包括盐酸和硝酸的混合溶液的步骤包括：
在所述源漏金属层上涂覆光刻胶，利用掩膜版对所述光刻胶曝光，然后对所述光刻胶进行显影；
以及，利用蚀刻液对涂覆有所述光刻胶的所述源漏金属层进行蚀刻，然后剥离所述光刻胶得到源极和漏极，其中，所述蚀刻液包括盐酸和硝酸的混合溶液。
可选地，所述栅极的材料包括铝、钼和铜中的至少一种。
可选地，其中，所述栅极以及所述电极层采用物理气相沉积法制备，所述栅极绝缘层、所述半导体层以及所述钝化层采用化学气相沉积法制备。
为了实现上述目的，本申请还提出一种薄膜晶体管的制备方法，所述薄膜晶体管的制备方法包括以下步骤：
提供基板；
在所述基板上形成依次层叠于所述基板上的栅极、栅极绝缘层以及半导体层；
利用物理气相沉积法在所述半导体层上依次沉积第一钼金属层，铝金属层和第二钼金属层，得到源漏金属层，其中，沉积所述第一钼金属层和所述第二钼金属层时，通入的氮气流量为0sccm~1000sccm；
利用蚀刻液在30℃~40℃下对所述源漏金属层进行蚀刻，得到源极和漏极，其中，所述蚀刻液包括盐酸和硝酸的混合溶液，其中，所述硝酸重量百分比浓度为1.5%~3.5%；
以及，在所述源极和漏极上依次形成钝化层和电极层。
可选地，所述栅极以及所述电极层采用物理气相沉积法制备，所述栅极绝缘层、所述半导体层以及所述钝化层采用化学气相沉积法制备。
为了实现上述目的，本申请还提出一种显示装置，所述显示装置包括薄膜晶体管，所述薄膜晶体管包括依次层叠于基板上的栅极、栅极绝缘层、半导体层、源极和漏极、钝化层、电极层，所述薄膜晶体管通过如下步骤制备得到：
利用物理气相沉积法在基板的半导体层上依次沉积第一钼金属层，铝金属层和第二钼金属层，得到源漏金属层，其中，沉积所述第一钼金属层和所述第二钼金属层时，通入的氮气流量为0sccm~1000sccm；
利用蚀刻液对所述源漏金属层进行蚀刻，得到源极和漏极，其中，所述蚀刻液包括盐酸和硝酸的混合溶液；
以及，在所述源极和漏极上依次形成钝化层和电极层。
本申请实施例提供一种薄膜晶体管的制备方法及显示装置，利用物理气相沉积法在基板的半导体层上依次沉积第一钼金属层，铝金属层和第二钼金属层，得到源漏金属层，其中，沉积所述第一钼金属层和所述第二钼金属层时，通入的氮气流量为0sccm -1000sccm，然后利用蚀刻液对所述源漏金属层进行蚀刻，得到源极和漏极，其中，所述蚀刻液包括盐酸和硝酸的混合溶液，然后在所述源极和漏极上依次形成钝化层和电极层。由于在沉积钼金属层时将氮气流量控制在1000sccm以下，从而降低了钼金属层的氮含量，提高了钼金属层与蚀刻液的反应速率，蚀刻得到的源极和漏极无钼金属残留。
 附图说明
图1为本申请薄膜晶体管的制备方法一实施例的步骤流程示意图；
图2为本申请薄膜晶体管的制备方法又一实施例的步骤流程示意图。
 本发明的实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
首先，对本申请实施例提供的薄膜晶体管的制备方法进行简要概述。
参照图1，图1为本申请薄膜晶体管的制备方法一实施例的步骤流程示意图，该薄膜晶体管的制备方法包括：
步骤S10，利用物理气相沉积法在基板的半导体层上依次沉积第一钼金属层，铝金属层和第二钼金属层，得到源漏金属层，其中，沉积所述第一钼金属层和所述第二钼金属层时，通入的氮气流量为0sccm~1000sccm；
提供已经沉积有半导体层的基板，对该基板进行清洗，然后在半导体层上物理气相沉积(Physical Vapor Deposition，PVD)法沉积源漏金属层，对源漏金属层进行湿蚀刻得到源极和漏极。具体地，对已经沉积有半体层的基板进行清洗后，将该基板送入PVD设备的真空室，利用物理气相沉积法在基板的半导体层上依次沉积第一钼金属层，铝金属层和第二钼金属层，得到源漏金属层，其中，沉积所述第一钼金属层和所述第二钼金属层时，通入的氮气流量为0sccm~1000sccm。具体地，先以纯钼作为靶材，控制通入的氮气流量为0sccm~1000sccm，利用物理气相沉积法在基板的半导体层上第一钼金属层；然后以纯铝作为靶材，在第一钼金属层上利用物理气相沉积法沉积铝金属层；以纯钼作为靶材，控制通入的氮气流量为0sccm~1000sccm，利用物理气相沉积法在铝金属层上沉积第二钼金属层。从而得到由第一钼金属层、铝金属层和第二钼金属层共同构成的源漏金属层。需要理解的是，本申请中的钼金属层的成分可包括纯钼，也可以包括氮化钼。
步骤S20，利用蚀刻液对所述源漏金属层进行蚀刻，得到源极和漏极，其中，所述蚀刻液包括盐酸和硝酸的混合溶液；
将沉积有源漏金属层的基板取出，在然后涂覆一层光刻胶，利用源极和漏极对应的掩膜版对光刻胶进行曝光，再进行显影后，利用蚀刻液对所述源漏金属层进行湿蚀刻，然后将基板放入剥离液中，剥离光刻胶得到源极和漏极。其中，蚀刻液包括盐酸和硝酸的混合溶液，蚀刻液可以选用常规的铝酸蚀刻所用的盐酸和硝酸组成的蚀刻液。其中，金属与蚀刻液的反应速率主要与蚀刻液中的硝酸浓度有关，通过调节蚀刻液中的硝酸浓度，可调节蚀刻液和源漏金属层的反应速率，以更好地解决源漏金属层蚀刻后金属钼的残留。可选地，蚀刻液中所述硝酸的重量百分比浓度可为1.5%~3.5%。此外，蚀刻的温度可选用常规铝酸蚀刻所用的蚀刻温度，可不做具体限制。可选地，利用蚀刻液对源漏金属层进行蚀刻的步骤在30℃~40℃条件下进行。
步骤S30，在所述源极和漏极上依次形成钝化层和电极层。
得到源极和漏极后，进行清洗，然后在源极和漏极上沉积钝化层薄膜，可选地，钝化层薄膜可利用化学气相沉积法进行沉积。然后涂覆一层光刻胶，利用钝化层对应的掩膜版对光刻胶进行曝光，再进行显影后，进行干蚀刻，然后剥离光刻胶得到钝化层，钝化层中包括过孔图案。
得到钝化层后，进行清洗，然后在钝化层上沉积像素电极层薄膜，可选地，像素电极层薄膜的材料成分可为氧化铟锡。然后涂覆一层光刻胶，利用像素电极层对应的掩膜版对光刻胶进行曝光，再进行显影后，进行湿蚀刻，然后将基板放入剥离液中，剥离光刻胶得到像素电极层（电极层）。
参照图2，图2为本申请薄膜晶体管的制备方法又一实施例的步骤流程示意图，所述步骤S10之前，还包括：
步骤S40提供基板；
提供基板作为衬底，且在基板上制备栅极之前，需要对该基板进行清洁，以避免基板上的脏污物影响沉积的均匀性或在后续沉积过程中造成污染。
步骤S50在所述基板上形成依次层叠于所述基板上的栅极、栅极绝缘层以及半导体层。
在清洗后的基板上沉积第一金属层，可选地，第一金属层可采用物理气相沉积法进行沉积；可选地，第一金属层的材料采用铜、铝或钼中的至少一种。然后在第一金属层上涂覆一层光刻胶，利用栅极层对应的掩膜版对光刻胶进行曝光，再对曝光后的光刻胶进行显影后，利用蚀刻液进行湿蚀刻，然后将基板放入剥离液中，剥离掉光刻胶后得到栅极。
得到栅极后，对包含栅极的基板进行清洗，然后在基板上沉积栅极绝缘层薄膜，然后再次对基板进行清洗后，在基板上沉积半导体层（包括本征层和掺杂层）薄膜。可选地，栅极绝缘层薄膜和半导体层薄膜可采用化学气相沉积法进行沉积。然后在半导体层上涂覆一层光刻胶，利用半导体层对应的掩膜版对光刻胶进行曝光，再对曝光后的光刻胶进行显影后，利用蚀刻液进行湿蚀刻，然后将基板放入剥离液中，剥离掉光刻胶后得到栅极。栅极绝缘层和半导体层。其中，栅极绝缘层用于将栅极和半导体层隔绝，以防止栅极和半导体层连通，而发生短路。
可选地，在沉积栅极绝缘层薄膜和半导体薄膜后，可不进行蚀刻，直接清洗后沉积源漏金属层，然后涂覆光刻胶，利用源极和漏极对应的掩膜版对光刻胶进行曝光，然后利用显影液进行显影后，再进行两次干蚀刻和两次湿蚀刻得到源极和漏极，以及的得到半导体层对应的图形。其中，湿蚀刻可按照上述条件进行。
根据上述方案制备得到的薄膜晶体管包括依次层叠于基板上的栅极、栅极绝缘层、半导体层、源极和漏极、钝化层、电极层，其中，源极和漏极无金属残留，在源极和漏极上沉积的钝化层无断线等不良状况。
进一步地，本申请还提供一种显示装置，该显示装置包括上述方案制备得到的薄膜晶体管，该显示装置可以是液晶面板、电子纸、OLED（Organic Light Emitting Diode，有机发光二极管）面板、液晶电视、液晶显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
在一实施例中，在基板上依次形成栅极、栅极绝缘层、半导体层后，制备源极和漏极的步骤具体如下：对已经沉积有半导体层的基板进行清洗后，将该基板送入PVD设备的真空室，以纯钼作为靶材，控制通入的氮气流量为1000sccm，利用物理气相沉积法在基板的半导体层上第一钼金属层；然后以纯铝作为靶材，在第一钼金属层上利用物理气相沉积法沉积铝金属层；以纯钼作为靶材，控制通入的氮气流量为1000sccm，利用物理气相沉积法在铝金属层上沉积第二钼金属层，得到源漏金属层。
将沉积有源漏金属层的基板取出，然后涂覆一层光刻胶，利用源极和漏极对应的掩膜版对光刻胶进行曝光，再进行显影。然后利用盐酸和硝酸组成的蚀刻液在40℃下对所述源漏金属层进行湿蚀刻，其中，蚀刻液中硝酸的重量百分比浓度为1.5%。蚀刻完成后，将基板放入剥离液中，剥离光刻胶得到源极和漏极。
将湿蚀刻后的基板至于扫描电子显微镜（scanning electron microscope，SEM）下观察，结果显示源极和漏极边缘平整，无金属残留，且源极和漏极两侧的倾斜角（Taper angle）在40°~60°范围内。
然后在所述源极和漏极上依次形成钝化层和电极层，得到薄膜晶体管。
在一实施例中，在基板上依次形成栅极、栅极绝缘层、半导体层后，制备源极和漏极的步骤具体如下：对已经沉积有半导体层的基板进行清洗后，将该基板送入PVD设备的真空室，以纯钼作为靶材，控制通入的氮气流量为750sccm，利用物理气相沉积法在基板的半导体层上第一钼金属层；然后以纯铝作为靶材，在第一钼金属层上利用物理气相沉积法沉积铝金属层；以纯钼作为靶材，控制通入的氮气流量为750sccm，利用物理气相沉积法在铝金属层上沉积第二钼金属层，得到源漏金属层。
将沉积有源漏金属层的基板取出，然后涂覆一层光刻胶，利用源极和漏极对应的掩膜版对光刻胶进行曝光，再进行显影。然后利用盐酸和硝酸组成的蚀刻液在37℃下对所述源漏金属层进行湿蚀刻，其中，蚀刻液中硝酸的重量百分比浓度为2%。蚀刻完成后，将基板放入剥离液中，剥离光刻胶得到源极和漏极。
将湿蚀刻后的基板至于扫描电子显微镜（scanning electron microscope，SEM）下观察，结果显示源极和漏极边缘平整，无金属残留，且源极和漏极两侧的倾斜角（Taper angle）在40°~60°范围内。
然后在所述源极和漏极上依次形成钝化层和电极层，得到薄膜晶体管。
在一实施例中，在基板上依次形成栅极、栅极绝缘层、半导体层后，制备源极和漏极的步骤具体如下：对已经沉积有半导体层的基板进行清洗后，将该基板送入PVD设备的真空室，以纯钼作为靶材，控制通入的氮气流量为500sccm，利用物理气相沉积法在基板的半导体层上第一钼金属层；然后以纯铝作为靶材，在第一钼金属层上利用物理气相沉积法沉积铝金属层；以纯钼作为靶材，控制通入的氮气流量为500sccm，利用物理气相沉积法在铝金属层上沉积第二钼金属层，得到源漏金属层。
将沉积有源漏金属层的基板取出，然后涂覆一层光刻胶，利用源极和漏极对应的掩膜版对光刻胶进行曝光，再进行显影。然后利用盐酸和硝酸组成的蚀刻液在35℃下对所述源漏金属层进行湿蚀刻，其中，蚀刻液中硝酸的重量百分比浓度为2.5%。蚀刻完成后，将基板放入剥离液中，剥离光刻胶得到源极和漏极。
将湿蚀刻后的基板至于扫描电子显微镜（scanning electron microscope，SEM）下观察，结果显示源极和漏极边缘平整，无金属残留，且源极和漏极两侧的倾斜角（Taper angle）在40°~60°范围内。
然后在所述源极和漏极上依次形成钝化层和电极层，得到薄膜晶体管。
在一实施例中，在基板上依次形成栅极、栅极绝缘层、半导体层后，制备源极和漏极的步骤具体如下：对已经沉积有半导体层的基板进行清洗后，将该基板送入PVD设备的真空室，以纯钼作为靶材，控制通入的氮气流量为250sccm，利用物理气相沉积法在基板的半导体层上第一钼金属层；然后以纯铝作为靶材，在第一钼金属层上利用物理气相沉积法沉积铝金属层；以纯钼作为靶材，控制通入的氮气流量为250sccm，利用物理气相沉积法在铝金属层上沉积第二钼金属层，得到源漏金属层。
将沉积有源漏金属层的基板取出，然后涂覆一层光刻胶，利用源极和漏极对应的掩膜版对光刻胶进行曝光，再进行显影。然后利用盐酸和硝酸组成的蚀刻液在32℃下对所述源漏金属层进行湿蚀刻，其中，蚀刻液中硝酸的重量百分比浓度为3%。蚀刻完成后，将基板放入剥离液中，剥离光刻胶得到源极和漏极。
将湿蚀刻后的基板至于扫描电子显微镜（scanning electron microscope，SEM）下观察，结果显示源极和漏极边缘平整，无金属残留，且源极和漏极两侧的倾斜角（Taper angle）在40°~60°范围内。
然后在所述源极和漏极上依次形成钝化层和电极层，得到薄膜晶体管。
在一实施例中，在基板上依次形成栅极、栅极绝缘层、半导体层后，制备源极和漏极的步骤具体如下：对已经沉积有半导体层的基板进行清洗后，将该基板送入PVD设备的真空室，以纯钼作为靶材，控制通入的氮气流量为0sccm，利用物理气相沉积法在基板的半导体层上第一钼金属层；然后以纯铝作为靶材，在第一钼金属层上利用物理气相沉积法沉积铝金属层；以纯钼作为靶材，控制通入的氮气流量为0sccm，利用物理气相沉积法在铝金属层上沉积第二钼金属层，得到源漏金属层。
将沉积有源漏金属层的基板取出，然后涂覆一层光刻胶，利用源极和漏极对应的掩膜版对光刻胶进行曝光，再进行显影。然后利用盐酸和硝酸组成的蚀刻液在30℃下对所述源漏金属层进行湿蚀刻，其中，蚀刻液中硝酸的重量百分比浓度为3.5%。蚀刻完成后，将基板放入剥离液中，剥离光刻胶得到源极和漏极。
将湿蚀刻后的基板至于扫描电子显微镜（scanning electron microscope，SEM）下观察，结果显示源极和漏极边缘平整，无金属残留，且源极和漏极两侧的倾斜角（Taper angle）在20°~40°范围内。
然后在所述源极和漏极上依次形成钝化层和电极层，得到薄膜晶体管。
由以上实施例结果可以看出，上述任一实施例得到的源极和漏极边缘平整，无金属残留，很好的解决了源极和漏极蚀刻后容易出现钼金属残留的问题。此外，上述实施例中，当制备源漏金属层中的钼金属层（第一钼金属层和第二钼金属层）的过程中，通入的氮气流量为0sccm时，得到的钼金属层的材料为纯钼，蚀刻得到的源极和漏极两侧的倾斜角（Taper angle）在20°~40°范围内；当制备源漏金属层中的钼金属层（第一钼金属层和第二钼金属层）的过程中，通入的氮气流量不为0sccm（通入的氮气流量为250 sccm，500 sccm，750 sccm及1000 sccm中的任意一种）时，得到的钼金属层的材料为氮化钼，蚀刻得到的源极和漏极两侧的倾斜角（Taper angle）在40°~60°范围内；由于蚀刻得到的源极和漏极两侧的倾斜角（Taper angle）均在60°以下，使得在源极和漏极上沉积的钝化层不会由于倾斜角过大而产生断线。此外，制备钼金属层时使用较低的氮气流量，还降低了薄膜晶体管的制备成本。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者系统不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者系统所固有的要素。在没有更多限制的情况下，由语句“包括……”限定的要素，并不排除在包括该要素的过程、方法、物品或者系统中还存在另外的相同要素。
另外，在本申请中涉及“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。
以上仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效物品或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (18)

  1. 一种薄膜晶体管的制备方法，其中，所述薄膜晶体管的制备方法包括以下步骤：
    利用物理气相沉积法在基板的半导体层上依次沉积第一钼金属层，铝金属层和第二钼金属层，得到源漏金属层，其中，沉积所述第一钼金属层和所述第二钼金属层时，通入的氮气流量为0sccm~1000sccm；
    利用蚀刻液对所述源漏金属层进行蚀刻，得到源极和漏极，其中，所述蚀刻液包括盐酸和硝酸的混合溶液；
    以及，在所述源极和漏极上依次形成钝化层和电极层。
  2. 如权利要求1所述的薄膜晶体管的制备方法，其中，所述沉积所述第一钼金属层和所述第二钼金属层时，通入的氮气流量为0sccm~750sccm。
  3. 如权利要求1所述的薄膜晶体管的制备方法，其中，所述沉积所述第一钼金属层和所述第二钼金属层时，通入的氮气流量为500sccm。
  4. 如权利要求1所述的薄膜晶体管的制备方法，其中，所述电极层的材料包括氧化铟锡。
  5. 如权利要求1所述的薄膜晶体管的制备方法，其中，所述利用物理气相沉积法在基板的半导体层上依次沉积第一钼金属层，铝金属层和第二钼金属层，得到源漏金属层的步骤之前，还包括：
    提供基板；
    以及，在所述基板上形成依次层叠于所述基板上的栅极、栅极绝缘层以及半导体层。
  6. 如权利要求5所述的薄膜晶体管的制备方法，其中，所述提供基板的步骤之后，还包括：
    对所述基板进行清洗。
  7. 如权利要求1所述的薄膜晶体管的制备方法，其中，利用蚀刻液对所述源漏金属层进行蚀刻的过程中蚀刻温度为30℃~40℃。
  8. 如权利要求7所述的薄膜晶体管的制备方法，其中，所述蚀刻温度为32℃~37℃。
  9. 如权利要求7所述的薄膜晶体管的制备方法，其中，所述蚀刻温度为35℃。
  10. 如权利要求1所述的薄膜晶体管制备方法，其中，所述蚀刻液中包括盐酸和硝酸，其中，所述硝酸的重量百分比浓度为1.5%~3.5%。
  11. 如权利要求10所述的薄膜晶体管制备方法，其中，所述硝酸的重量百分比浓度为2%~3%。
  12. 如权利要求10所述的薄膜晶体管制备方法，其中，所述硝酸的重量百分比浓度为2.5%。
  13. 如权利要求1所述的薄膜晶体管的制备方法，其中，所述利用蚀刻液对所述源漏金属层进行蚀刻，得到源极和漏极，其中，所述蚀刻液包括盐酸和硝酸的混合溶液的步骤包括：
    在所述源漏金属层上涂覆光刻胶，利用掩膜版对所述光刻胶曝光，然后对所述光刻胶进行显影；
    以及，利用蚀刻液对涂覆有所述光刻胶的所述源漏金属层进行蚀刻，然后剥离所述光刻胶得到源极和漏极，其中，所述蚀刻液包括盐酸和硝酸的混合溶液。
  14. 如权利要求5所述的薄膜晶体管的制备方法，其中，所述栅极的材料包括铝、钼和铜中的至少一种。
  15. 如权利要求5所述的薄膜晶体管的制备方法，其中，所述栅极以及所述电极层采用物理气相沉积法制备，所述栅极绝缘层、所述半导体层以及所述钝化层采用化学气相沉积法制备。
  16. 一种薄膜晶体管的制备方法，其中，所述薄膜晶体管的制备方法包括以下步骤：
    提供基板；
    在所述基板上形成依次层叠于所述基板上的栅极、栅极绝缘层以及半导体层；
    利用物理气相沉积法在所述半导体层上依次沉积第一钼金属层，铝金属层和第二钼金属层，得到源漏金属层，其中，沉积所述第一钼金属层和所述第二钼金属层时，通入的氮气流量为0sccm~1000sccm；
    利用蚀刻液在30℃~40℃下对所述源漏金属层进行蚀刻，得到源极和漏极，其中，所述蚀刻液包括盐酸和硝酸的混合溶液，其中，所述硝酸重量百分比浓度为1.5%~3.5%；
    以及，在所述源极和漏极上依次形成钝化层和电极层。
  17. 如权利要求16所述的薄膜晶体管的制备方法，其中，所述栅极以及所述电极层采用物理气相沉积法制备，所述栅极绝缘层、所述半导体层以及所述钝化层采用化学气相沉积法制备。
  18. 一种显示装置，其中，所述显示装置包括薄膜晶体管，所述薄膜晶体管包括依次层叠于基板上的栅极、栅极绝缘层、半导体层、源极和漏极、钝化层、电极层，所述薄膜晶体管通过如下步骤制备得到：
    利用物理气相沉积法在基板的半导体层上依次沉积第一钼金属层，铝金属层和第二钼金属层，得到源漏金属层，其中，沉积所述第一钼金属层和所述第二钼金属层时，通入的氮气流量为0sccm~1000sccm；
    利用蚀刻液对所述源漏金属层进行蚀刻，得到源极和漏极，其中，所述蚀刻液包括盐酸和硝酸的混合溶液；
    以及，在所述源极和漏极上依次形成钝化层和电极层。
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