WO2020147575A1 - Procédé de préparation de transistor à couches minces et appareil d'affichage - Google Patents

Procédé de préparation de transistor à couches minces et appareil d'affichage Download PDF

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Publication number
WO2020147575A1
WO2020147575A1 PCT/CN2019/130303 CN2019130303W WO2020147575A1 WO 2020147575 A1 WO2020147575 A1 WO 2020147575A1 CN 2019130303 W CN2019130303 W CN 2019130303W WO 2020147575 A1 WO2020147575 A1 WO 2020147575A1
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metal layer
layer
source
drain
thin film
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PCT/CN2019/130303
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English (en)
Chinese (zh)
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何怀亮
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惠科股份有限公司
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Publication of WO2020147575A1 publication Critical patent/WO2020147575A1/fr

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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/10—Etching compositions
    • C23F1/14—Aqueous compositions
    • C23F1/16—Acidic compositions
    • C23F1/20—Acidic compositions for etching aluminium or alloys thereof
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/10—Etching compositions
    • C23F1/14—Aqueous compositions
    • C23F1/16—Acidic compositions
    • C23F1/26—Acidic compositions for etching refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

Definitions

  • This application relates to the field of thin film transistor liquid crystal display technology, and in particular to a method for manufacturing a thin film transistor and a display device.
  • TFT Thin Film Transistor
  • LCD Crystal Display
  • the source and drain electrodes are generally obtained by wet etching the source and drain metal layers.
  • the source and drain metal layers usually adopt a molybdenum nitride/aluminum/molybdenum nitride multilayer metal structure.
  • the reaction rate of the etching solution is relatively small, so that molybdenum metal residues easily appear in the source and drain electrodes obtained after wet etching, which affects the performance of the thin film transistor.
  • the main purpose of this application is to provide a method for manufacturing a thin film transistor and a display device, which improves the reaction rate of the molybdenum metal layer and the etching solution, and reduces the residue of metal molybdenum in the source and drain.
  • the present application provides a method for manufacturing a thin film transistor, which includes the following steps:
  • the first molybdenum metal layer, the aluminum metal layer and the second molybdenum metal layer are sequentially deposited on the semiconductor layer of the substrate by physical vapor deposition to obtain a source-drain metal layer, wherein the first molybdenum metal layer and the second molybdenum metal layer are deposited
  • the nitrogen flow rate is 0sccm ⁇ 1000sccm;
  • Etching the source and drain metal layers with an etching solution to obtain source and drain electrodes wherein the etching solution includes a mixed solution of hydrochloric acid and nitric acid;
  • a passivation layer and an electrode layer are sequentially formed on the source electrode and the drain electrode.
  • the nitrogen gas flow rate is 0 sccm to 750 sccm.
  • the flow rate of nitrogen gas introduced is 500 sccm.
  • the material of the electrode layer includes indium tin oxide.
  • the method before the step of sequentially depositing a first molybdenum metal layer, an aluminum metal layer and a second molybdenum metal layer on the semiconductor layer of the substrate by using a physical vapor deposition method to obtain the source and drain metal layers, the method further includes:
  • the method further includes:
  • the substrate is cleaned.
  • the etching temperature in the process of etching the source and drain metal layers with an etching solution is 30°C-40°C.
  • the etching temperature is 32°C to 37°C.
  • the etching temperature is 35°C.
  • the etching solution includes hydrochloric acid and nitric acid, wherein the concentration by weight of the nitric acid is 1.5% to 3.5%.
  • the weight percentage concentration of the nitric acid is 2% to 3%.
  • the concentration by weight of the nitric acid is 2.5%.
  • the step of etching the source and drain metal layers with an etchant to obtain source and drain electrodes includes:
  • the etchant includes a mixture of hydrochloric acid and nitric acid Solution.
  • the material of the gate includes at least one of aluminum, molybdenum and copper.
  • the gate and the electrode layer are prepared by a physical vapor deposition method
  • the gate insulating layer, the semiconductor layer, and the passivation layer are prepared by a chemical vapor deposition method.
  • this application also proposes a method for manufacturing a thin film transistor, which includes the following steps:
  • a first molybdenum metal layer, an aluminum metal layer, and a second molybdenum metal layer are sequentially deposited on the semiconductor layer using a physical vapor deposition method to obtain a source-drain metal layer, wherein the first molybdenum metal layer and the second molybdenum metal layer are deposited
  • the nitrogen flow rate is 0sccm ⁇ 1000sccm;
  • the source and drain metal layers are etched at 30°C to 40°C using an etching solution to obtain source and drain electrodes, wherein the etching solution includes a mixed solution of hydrochloric acid and nitric acid, wherein the nitric acid weight percentage concentration is 1.5% ⁇ 3.5%;
  • a passivation layer and an electrode layer are sequentially formed on the source electrode and the drain electrode.
  • the gate and the electrode layer are prepared by a physical vapor deposition method
  • the gate insulating layer, the semiconductor layer, and the passivation layer are prepared by a chemical vapor deposition method.
  • the present application also proposes a display device, the display device includes a thin film transistor, the thin film transistor includes a gate, a gate insulating layer, a semiconductor layer, a source and a drain, which are sequentially stacked on a substrate.
  • Passivation layer, electrode layer, the thin film transistor is prepared by the following steps:
  • the first molybdenum metal layer, the aluminum metal layer, and the second molybdenum metal layer are sequentially deposited on the semiconductor layer of the substrate by physical vapor deposition to obtain a source-drain metal layer, wherein the first molybdenum metal layer and the second molybdenum metal layer are deposited
  • the nitrogen flow rate is 0sccm ⁇ 1000sccm;
  • Etching the source and drain metal layers with an etching solution to obtain source and drain electrodes wherein the etching solution includes a mixed solution of hydrochloric acid and nitric acid;
  • a passivation layer and an electrode layer are sequentially formed on the source electrode and the drain electrode.
  • the embodiment of the application provides a method for manufacturing a thin film transistor and a display device.
  • a first molybdenum metal layer, an aluminum metal layer, and a second molybdenum metal layer are sequentially deposited on a semiconductor layer of a substrate using a physical vapor deposition method to obtain a source and drain metal layer ,
  • the nitrogen gas flow rate is 0sccm-1000sccm, and then the source and drain metal layers are etched with an etchant to obtain source and drain
  • the etching solution includes a mixed solution of hydrochloric acid and nitric acid, and then a passivation layer and an electrode layer are sequentially formed on the source and drain electrodes.
  • the nitrogen flow rate is controlled below 1000 sccm when depositing the molybdenum metal layer, the nitrogen content of the molybdenum metal layer is reduced, and the reaction rate of the molybdenum metal layer and the etching solution is increased, and the source and drain electrodes obtained by etching have no molybdenum metal residue.
  • FIG. 1 is a schematic diagram of the process flow of an embodiment of a method for manufacturing a thin film transistor according to the present application
  • FIG. 2 is a schematic flow diagram of the steps of another embodiment of the method for manufacturing a thin film transistor of the present application.
  • FIG. 1 is a schematic diagram of a step flow diagram of an embodiment of a method for manufacturing a thin film transistor according to the present application.
  • the method for manufacturing a thin film transistor includes:
  • Step S10 using a physical vapor deposition method to sequentially deposit a first molybdenum metal layer, an aluminum metal layer and a second molybdenum metal layer on the semiconductor layer of the substrate to obtain a source-drain metal layer, wherein the first molybdenum metal layer and the all When the second molybdenum metal layer is described, the nitrogen gas flow rate is 0sccm ⁇ 1000sccm;
  • a substrate on which a semiconductor layer has been deposited clean the substrate, and then deposit a source and drain metal layer on the semiconductor layer by Physical Vapor Deposition (PVD), and perform wet etching on the source and drain metal layer to obtain the source and drain pole.
  • PVD Physical Vapor Deposition
  • the substrate is sent to the vacuum chamber of the PVD device, and the first molybdenum metal layer, the aluminum metal layer and the semiconductor layer are sequentially deposited on the semiconductor layer of the substrate by the physical vapor deposition method.
  • the second molybdenum metal layer obtains a source and drain metal layer, wherein, when the first molybdenum metal layer and the second molybdenum metal layer are deposited, the nitrogen gas flow rate is 0 sccm to 1000 sccm.
  • first pure molybdenum is used as the target material, the nitrogen flow rate is controlled to 0sccm ⁇ 1000sccm, and the first molybdenum metal layer is deposited on the semiconductor layer of the substrate by physical vapor deposition; then pure aluminum is used as the target material, and the first molybdenum metal layer A physical vapor deposition method is used to deposit an aluminum metal layer on the layer; pure molybdenum is used as a target, and the nitrogen flow rate is controlled to be 0 sccm ⁇ 1000 sccm, and a second molybdenum metal layer is deposited on the aluminum metal layer by physical vapor deposition.
  • a source and drain metal layer composed of the first molybdenum metal layer, the aluminum metal layer and the second molybdenum metal layer is obtained.
  • the composition of the molybdenum metal layer in the present application may include pure molybdenum or molybdenum nitride.
  • Step S20 etching the source and drain metal layers with an etchant to obtain source and drain electrodes, wherein the etchant includes a mixed solution of hydrochloric acid and nitric acid;
  • the substrate on which the active drain metal layer is deposited is taken out, and then a layer of photoresist is applied, and the photoresist is exposed by the mask corresponding to the source and drain, and then developed, the etching solution is used to The source and drain metal layers are wet-etched, and then the substrate is put into a stripping solution, and the photoresist is stripped to obtain the source electrode and the drain electrode.
  • the etching solution includes a mixed solution of hydrochloric acid and nitric acid, and the etching solution can be an etching solution composed of hydrochloric acid and nitric acid used in conventional alumina acid etching.
  • the reaction rate of metal and etching solution is mainly related to the concentration of nitric acid in the etching solution.
  • concentration of nitric acid in the etching solution By adjusting the concentration of nitric acid in the etching solution, the reaction rate of the etching solution and the source and drain metal layers can be adjusted to better solve the source and drain metal layers.
  • the residue of metallic molybdenum after etching may be 1.5% to 3.5%.
  • the etching temperature can be the etching temperature used in conventional alumina etching, and there is no specific limitation.
  • the step of etching the source and drain metal layers with an etching solution is performed at 30°C-40°C.
  • step S30 a passivation layer and an electrode layer are sequentially formed on the source electrode and the drain electrode.
  • the passivation layer film can be deposited by a chemical vapor deposition method. Then apply a layer of photoresist, use the mask corresponding to the passivation layer to expose the photoresist, and then develop, dry etching, and then peel off the photoresist to obtain the passivation layer.
  • the passivation layer includes Hole pattern.
  • the material component of the pixel electrode layer film may be indium tin oxide. Then apply a layer of photoresist, use the mask corresponding to the pixel electrode layer to expose the photoresist, and after developing, perform wet etching, then put the substrate in the stripping solution, and peel off the photoresist to obtain the pixel electrode Layer (electrode layer).
  • FIG. 2 is a schematic flow chart of the steps of another embodiment of the method for manufacturing a thin film transistor according to the present application. Before the step S10, it further includes:
  • Step S40 provides a substrate
  • a substrate is provided as a substrate, and before the gate is prepared on the substrate, the substrate needs to be cleaned to prevent dirt on the substrate from affecting the uniformity of deposition or causing pollution in the subsequent deposition process.
  • step S50 a gate electrode, a gate insulating layer and a semiconductor layer which are sequentially stacked on the substrate are formed on the substrate.
  • a first metal layer is deposited on the cleaned substrate.
  • the first metal layer can be deposited by physical vapor deposition; optionally, the material of the first metal layer is at least one of copper, aluminum or molybdenum .
  • coat a layer of photoresist on the first metal layer use the mask corresponding to the gate layer to expose the photoresist, and then develop the exposed photoresist, and then perform wet etching with an etching solution. Then the substrate is put into the stripping solution, and the photoresist is stripped off to obtain the gate.
  • the gate insulating layer film and the semiconductor layer film can be deposited by chemical vapor deposition. Then a layer of photoresist is coated on the semiconductor layer, the photoresist is exposed using the mask corresponding to the semiconductor layer, and the exposed photoresist is developed, and then wet etched with an etching solution, and then the substrate Put it in a stripping solution, strip off the photoresist to obtain a gate.
  • Gate insulating layer and semiconductor layer is used to isolate the gate and the semiconductor layer to prevent the gate and the semiconductor layer from being connected to cause a short circuit.
  • etching is not required, and the source and drain metal layers are deposited directly after cleaning, and then coated with photoresist, and the photolithography is performed using the masks corresponding to the source and drain electrodes.
  • the glue is exposed, and then developed with a developer, and then two dry etching and two wet etching are performed to obtain the source electrode and the drain electrode, and the corresponding pattern of the semiconductor layer is obtained.
  • wet etching can be performed under the above-mentioned conditions.
  • the thin film transistor prepared according to the above solution includes a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode and a drain electrode, a passivation layer, and an electrode layer which are sequentially stacked on a substrate, wherein the source electrode and the drain electrode have no metal residue,
  • the passivation layer deposited on the source and drain has no undesirable conditions such as disconnection.
  • the present application also provides a display device, which includes the thin film transistor prepared by the above solution, and the display device may be a liquid crystal panel, electronic paper, OLED (Organic Light Emitting Diode (Organic Light Emitting Diode) panels, LCD TVs, LCD monitors, digital photo frames, mobile phones, tablet computers and other products or components with display functions.
  • OLED Organic Light Emitting Diode (Organic Light Emitting Diode) panels
  • LCD TVs Organic Light Emitting Diode
  • LCD monitors digital photo frames
  • mobile phones tablet computers and other products or components with display functions.
  • the steps of preparing the source electrode and the drain electrode are as follows: After cleaning the substrate on which the semiconductor layer has been deposited, the substrate Into the vacuum chamber of the PVD equipment, pure molybdenum was used as the target material, the nitrogen flow rate was controlled to 1000sccm, and the first molybdenum metal layer was deposited on the semiconductor layer of the substrate by physical vapor deposition; then pure aluminum was used as the target material.
  • the aluminum metal layer is deposited on the metal layer by physical vapor deposition; pure molybdenum is used as the target, and the nitrogen flow rate is controlled to 1000 sccm, and the second molybdenum metal layer is deposited on the aluminum metal layer by physical vapor deposition to obtain the source and drain metal layer .
  • the substrate on which the active drain metal layer is deposited is taken out, and then a layer of photoresist is coated, and the photoresist is exposed by the mask plate corresponding to the source electrode and the drain electrode, and then developed. Then, an etching solution composed of hydrochloric acid and nitric acid is used to wet-etch the source and drain metal layers at 40° C., wherein the concentration of nitric acid in the etching solution is 1.5% by weight. After the etching is completed, the substrate is put into the stripping solution, and the photoresist is stripped to obtain the source electrode and the drain electrode.
  • the wet-etched substrate was observed under a scanning electron microscope (SEM), and the results showed that the edges of the source and drain were flat without metal residue, and the taper angles on both sides of the source and drain were at Within the range of 40° ⁇ 60°.
  • a passivation layer and an electrode layer are sequentially formed on the source electrode and the drain electrode to obtain a thin film transistor.
  • the steps of preparing the source electrode and the drain electrode are as follows: After cleaning the substrate on which the semiconductor layer has been deposited, the substrate Into the vacuum chamber of the PVD equipment, pure molybdenum was used as the target, and the nitrogen flow rate was controlled to 750sccm. The first molybdenum metal layer was deposited on the semiconductor layer of the substrate by physical vapor deposition; then pure aluminum was used as the target.
  • the aluminum metal layer is deposited on the metal layer by physical vapor deposition; pure molybdenum is used as the target, and the nitrogen flow rate is controlled to 750sccm, and the second molybdenum metal layer is deposited on the aluminum metal layer by physical vapor deposition to obtain the source and drain metal layer .
  • the substrate on which the active drain metal layer is deposited is taken out, and then a layer of photoresist is coated, and the photoresist is exposed by the mask plate corresponding to the source electrode and the drain electrode, and then developed. Then, an etching solution composed of hydrochloric acid and nitric acid is used to wet-etch the source and drain metal layers at 37° C., where the concentration of nitric acid in the etching solution is 2% by weight. After the etching is completed, the substrate is put into the stripping solution, and the photoresist is stripped to obtain the source electrode and the drain electrode.
  • the wet-etched substrate was observed under a scanning electron microscope (SEM), and the results showed that the edges of the source and drain were flat without metal residue, and the taper angles on both sides of the source and drain were at Within the range of 40° ⁇ 60°.
  • a passivation layer and an electrode layer are sequentially formed on the source electrode and the drain electrode to obtain a thin film transistor.
  • the steps of preparing the source electrode and the drain electrode are as follows: After cleaning the substrate on which the semiconductor layer has been deposited, the substrate Into the vacuum chamber of the PVD equipment, pure molybdenum was used as the target material, and the nitrogen flow rate was controlled to 500 sccm. The first molybdenum metal layer was deposited on the semiconductor layer of the substrate by physical vapor deposition; then pure aluminum was used as the target material.
  • the aluminum metal layer is deposited on the metal layer by physical vapor deposition; pure molybdenum is used as the target material, and the nitrogen flow rate is controlled to 500sccm, and the second molybdenum metal layer is deposited on the aluminum metal layer by physical vapor deposition to obtain the source and drain metal layer .
  • the substrate on which the active drain metal layer is deposited is taken out, and then a layer of photoresist is coated, and the photoresist is exposed by the mask plate corresponding to the source electrode and the drain electrode, and then developed. Then, an etching solution composed of hydrochloric acid and nitric acid is used to wet-etch the source and drain metal layers at 35° C., wherein the concentration of nitric acid in the etching solution is 2.5% by weight. After the etching is completed, the substrate is put into the stripping solution, and the photoresist is stripped to obtain the source electrode and the drain electrode.
  • the wet-etched substrate was observed under a scanning electron microscope (SEM), and the results showed that the edges of the source and drain were flat without metal residue, and the taper angles on both sides of the source and drain were at Within the range of 40° ⁇ 60°.
  • a passivation layer and an electrode layer are sequentially formed on the source electrode and the drain electrode to obtain a thin film transistor.
  • the steps of preparing the source electrode and the drain electrode are as follows: After cleaning the substrate on which the semiconductor layer has been deposited, the substrate Into the vacuum chamber of the PVD equipment, pure molybdenum was used as the target material, and the nitrogen flow rate was controlled to 250sccm. The first molybdenum metal layer was deposited on the semiconductor layer of the substrate by physical vapor deposition; then pure aluminum was used as the target material.
  • the aluminum metal layer is deposited on the metal layer by physical vapor deposition; pure molybdenum is used as the target, and the nitrogen flow rate is controlled to 250sccm, and the second molybdenum metal layer is deposited on the aluminum metal layer by physical vapor deposition to obtain the source and drain metal layer .
  • the substrate on which the active drain metal layer is deposited is taken out, and then a layer of photoresist is coated, and the photoresist is exposed by the mask plate corresponding to the source electrode and the drain electrode, and then developed. Then, an etching solution composed of hydrochloric acid and nitric acid is used to wet-etch the source and drain metal layers at 32° C., wherein the concentration of nitric acid in the etching solution is 3% by weight. After the etching is completed, the substrate is put into the stripping solution, and the photoresist is stripped to obtain the source electrode and the drain electrode.
  • the wet-etched substrate was observed under a scanning electron microscope (SEM), and the results showed that the edges of the source and drain were flat without metal residue, and the taper angles on both sides of the source and drain were at Within the range of 40° ⁇ 60°.
  • a passivation layer and an electrode layer are sequentially formed on the source electrode and the drain electrode to obtain a thin film transistor.
  • the steps of preparing the source electrode and the drain electrode are as follows: After cleaning the substrate on which the semiconductor layer has been deposited, the substrate Into the vacuum chamber of the PVD equipment, pure molybdenum was used as the target, the nitrogen flow rate was controlled to 0sccm, and the first molybdenum metal layer was deposited on the semiconductor layer of the substrate by physical vapor deposition; then pure aluminum was used as the target, and the first molybdenum The aluminum metal layer is deposited on the metal layer by physical vapor deposition; pure molybdenum is used as the target, and the nitrogen flow rate is controlled to 0sccm, and the second molybdenum metal layer is deposited on the aluminum metal layer by physical vapor deposition to obtain the source and drain metal layer .
  • the substrate on which the active drain metal layer is deposited is taken out, and then a layer of photoresist is coated, and the photoresist is exposed by the mask plate corresponding to the source electrode and the drain electrode, and then developed. Then, an etching solution composed of hydrochloric acid and nitric acid is used to wet-etch the source and drain metal layers at 30° C., wherein the concentration of nitric acid in the etching solution is 3.5% by weight. After the etching is completed, the substrate is put into the stripping solution, and the photoresist is stripped to obtain the source electrode and the drain electrode.
  • the wet-etched substrate was observed under a scanning electron microscope (SEM), and the results showed that the edges of the source and drain were flat without metal residue, and the taper angles on both sides of the source and drain were at Within the range of 20° ⁇ 40°.
  • a passivation layer and an electrode layer are sequentially formed on the source electrode and the drain electrode to obtain a thin film transistor.
  • the edges of the source electrode and the drain electrode obtained in any of the above embodiments are flat and there is no metal residue, which well solves the problem of molybdenum metal residue that easily occurs after the source electrode and the drain electrode are etched.
  • the molybdenum metal layer (the first molybdenum metal layer and the second molybdenum metal layer) in the source and drain metal layers is prepared, when the nitrogen gas flow rate is 0 sccm, the resulting molybdenum metal layer
  • the material is pure molybdenum, and the taper angle between the source and drain obtained by etching is in the range of 20° ⁇ 40°; when preparing the molybdenum metal layer in the source and drain metal layer (the first molybdenum metal layer and the second molybdenum metal layer)
  • the nitrogen flow rate is not 0sccm (the nitrogen flow rate is 250 sccm, 500 sccm, 750 sccm or 1000 sccm)
  • the material of the obtained molybdenum metal layer is molybdenum nitride, and the taper angles on both sides of the source and drain obtained by etching are in

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Abstract

L'invention concerne un procédé de préparation de transistor à couches minces et un appareil d'affichage. L'invention concerne un procédé de préparation de transistor à couches minces comprenant : l'utilisation d'un procédé de dépôt physique en phase vapeur pour déposer séquentiellement une première couche de métal de molybdène, une couche de métal d'aluminium, et une seconde couche de métal de molybdène sur une couche semi-conductrice d'un substrat pour obtenir une couche métallique de source et de drain, le débit d'azote introduit étant de 0 sccm à 1000 sccm lors du dépôt de la première couche de métal de molybdène et de la seconde couche de métal de molybdène (S10) ; l'utilisation d'une solution de gravure pour graver la source et la couche métallique de drain pour obtenir une électrode de source et une électrode de drain, la solution de gravure comprenant une solution mixte d'acide chlorhydrique et d'acide nitrique (S20) ; et la formation séquentielle d'une couche de passivation et d'une couche d'électrode sur l'électrode de source et l'électrode de drain (S30).
PCT/CN2019/130303 2019-01-18 2019-12-31 Procédé de préparation de transistor à couches minces et appareil d'affichage WO2020147575A1 (fr)

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Application Number Priority Date Filing Date Title
CN201910051342.9 2019-01-18
CN201910051342.9A CN109786258A (zh) 2019-01-18 2019-01-18 薄膜晶体管的制备方法及显示装置

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WO2020147575A1 true WO2020147575A1 (fr) 2020-07-23

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113421916A (zh) * 2021-05-27 2021-09-21 重庆惠科金渝光电科技有限公司 金属导电薄膜的制备方法、薄膜晶体管以及显示装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109786258A (zh) * 2019-01-18 2019-05-21 惠科股份有限公司 薄膜晶体管的制备方法及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040263708A1 (en) * 2003-06-30 2004-12-30 Won-Ho Cho Array substrate for LCD device having metal-diffusion film and manufacturing method thereof
CN1798874A (zh) * 2004-11-09 2006-07-05 先进显示股份有限公司 蚀刻剂和蚀刻方法
CN104241345A (zh) * 2014-07-31 2014-12-24 京东方科技集团股份有限公司 铝电极、形成铝电极的方法及其电子设备
CN105324835A (zh) * 2013-06-28 2016-02-10 株式会社神户制钢所 薄膜晶体管及其制造方法
CN109786258A (zh) * 2019-01-18 2019-05-21 惠科股份有限公司 薄膜晶体管的制备方法及显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3302240B2 (ja) * 1995-11-28 2002-07-15 シャープ株式会社 薄膜トランジスタ及びその製造方法
JP3488681B2 (ja) * 1999-10-26 2004-01-19 シャープ株式会社 液晶表示装置
CN106601689B (zh) * 2016-12-08 2019-04-09 惠科股份有限公司 主动开关阵列基板及其制备方法
CN106601596A (zh) * 2016-12-30 2017-04-26 惠科股份有限公司 一种导线制程阵列蚀刻方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040263708A1 (en) * 2003-06-30 2004-12-30 Won-Ho Cho Array substrate for LCD device having metal-diffusion film and manufacturing method thereof
CN1798874A (zh) * 2004-11-09 2006-07-05 先进显示股份有限公司 蚀刻剂和蚀刻方法
CN105324835A (zh) * 2013-06-28 2016-02-10 株式会社神户制钢所 薄膜晶体管及其制造方法
CN104241345A (zh) * 2014-07-31 2014-12-24 京东方科技集团股份有限公司 铝电极、形成铝电极的方法及其电子设备
CN109786258A (zh) * 2019-01-18 2019-05-21 惠科股份有限公司 薄膜晶体管的制备方法及显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113421916A (zh) * 2021-05-27 2021-09-21 重庆惠科金渝光电科技有限公司 金属导电薄膜的制备方法、薄膜晶体管以及显示装置
CN113421916B (zh) * 2021-05-27 2024-03-01 重庆惠科金渝光电科技有限公司 金属导电薄膜的制备方法、薄膜晶体管以及显示装置

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