WO2020137470A1 - Élément électroluminescent à semi-conducteur - Google Patents

Élément électroluminescent à semi-conducteur Download PDF

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Publication number
WO2020137470A1
WO2020137470A1 PCT/JP2019/047989 JP2019047989W WO2020137470A1 WO 2020137470 A1 WO2020137470 A1 WO 2020137470A1 JP 2019047989 W JP2019047989 W JP 2019047989W WO 2020137470 A1 WO2020137470 A1 WO 2020137470A1
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region
light emitting
layer
area
dot
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PCT/JP2019/047989
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English (en)
Japanese (ja)
Inventor
慎一 松井
良基 鎌田
面家　英樹
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豊田合成株式会社
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Priority claimed from JP2018242168A external-priority patent/JP7056543B2/ja
Priority claimed from JP2019003847A external-priority patent/JP7043014B2/ja
Application filed by 豊田合成株式会社 filed Critical 豊田合成株式会社
Priority to CN201980074061.3A priority Critical patent/CN112997324B/zh
Publication of WO2020137470A1 publication Critical patent/WO2020137470A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape

Definitions

  • the present invention relates to a semiconductor light emitting device that emits ultraviolet light.
  • Ultraviolet rays are applied to biomedical fields such as processing such as photolithography, analysis such as ultraviolet-visible near-infrared spectroscopy, and sterilization.
  • a semiconductor light emitting device that emits ultraviolet light as a light source of ultraviolet light has been researched and developed.
  • Group III nitride semiconductors containing Al as a constituent element are used to emit ultraviolet light.
  • the nitride semiconductor containing Al has a high resistivity, and when it is used for the n-type semiconductor layer, the sheet resistance becomes high, and the current does not flow evenly and uniformly in the light emitting layer.
  • Patent Document 1 discloses a technique in which the area of the n-electrode is 25% or more and 50% or less of the chip area (claim 1 of Patent Document 1).
  • the light emitting layer, the p-type semiconductor layer, and the p-electrode are dot patterns in a honeycomb-like arrangement that is dispersed and projected in a dot shape.
  • the surface of the n-type semiconductor layer having no dot pattern is a continuous plane, and one sheet-shaped n electrode having a hole larger than the dot pattern diameter is formed on the continuous plane (Patent Document 1). 2 and 4).
  • Patent Document 2 discloses various n-electrode patterns (see FIG. 1 of Patent Document 2).
  • Patent Document 2 discloses a technique of forming a p-electrode at a position separated from an end of a mesa structure by a certain distance or more (paragraph [0010] of Patent Document 2). This discloses that the current flowing between the p electrode and the n electrode can be suppressed from being concentrated around the end of the mesa structure (paragraph [0009] of Patent Document 2).
  • the current does not easily diffuse, so that the current cannot be uniformly and uniformly distributed in the active layer and the p-type semiconductor layer, and the light emission is formed by stacking semiconductors that do not contribute to light emission.
  • a semiconductor stack such as a light emitting layer that does not contribute to light emission absorbs light, resulting in a decrease in light emission efficiency.
  • an AlN layer may be formed on a substrate. In that case, a low temperature AlN layer formed at a low temperature and a high temperature AlN layer formed at a high temperature may be formed. In that case, an AlN layer that is formed while increasing the substrate temperature is often formed between the low temperature AlN layer and the high temperature AlN layer.
  • the present inventors have discovered that the light emitting layer emits light at a position close to the n dot electrode, but does not emit light at a position far from the n dot electrode. In this way, the non-light emitting portion where the light emitting layer does not emit light absorbs light.
  • the p-type semiconductor layer has a p-type GaN layer
  • the p-type GaN layer absorbs ultraviolet rays.
  • the inventors of the present invention have found that the AlN layer formed while increasing the substrate temperature has a composition abnormal region, and the composition abnormal region absorbs ultraviolet rays. When ultraviolet rays are absorbed by the AlN layer, the light output of the ultraviolet light emitting semiconductor light emitting element naturally lowers.
  • the purpose of one feature of the present invention is to suppress the absorption of ultraviolet rays in the non-light emitting portion.
  • the purpose of another feature is to suppress the absorption of ultraviolet rays in the abnormal composition region of the AlN layer.
  • a first feature of the present invention is that a substrate having a first surface, an n-type semiconductor layer formed above the first surface of the substrate, a light-emitting layer that emits ultraviolet light, a p-type semiconductor layer, and an n-type semiconductor layer.
  • a semiconductor light emitting device having a plurality of n dot electrodes having a plurality of n dot electrodes each having a dot electrode outer periphery in contact with a dispersed electrode formed surface on which the semiconductor layer does not exist above the semiconductor layer, ultraviolet rays are emitted in the light emitting layer.
  • the structure is characteristic.
  • the boundary side surface between the light emitting region and the non-light emitting region may be perpendicular to the first surface of the substrate or may be tapered.
  • the light emitting region and the non-light emitting region are defined by the positions where the light emitting layer exists. Therefore, the outer peripheral contour line is the side surface contour of the light emitting layer. Further, the arrangement relationship of the n dot electrodes is determined so that the non-light emitting portion does not exist in the light emitting region.
  • the electrode formation surface is the upper surface of the n-type semiconductor layer which is exposed in the manufacturing process without the semiconductor stacking on the n-type semiconductor layer.
  • the n-dot electrode is in contact with this electrode formation surface, and the contour of the contact surface is defined as the dot electrode outer circumference.
  • the outer-peripheral contour line has a distance from the dot-electrode outer circumference of the n-dot electrodes of the array, It is preferably 45 ⁇ m or less. More preferably, it is 40 ⁇ m or less. Further, it is desirable that the distance is larger than 1 ⁇ 2 of the distance between the dot electrodes, which is the shortest distance between the dot electrode outer circumferences of the two closest n dot electrodes.
  • the plurality of n dot electrodes are arranged at the vertices of the equilateral triangle in the projection pattern on the first surface, and the shortest distance from the dot electrode outer circumference of the n dot electrodes located at the vertices of the equilateral triangle to the center of gravity of the equilateral triangle.
  • the distance is preferably smaller than the separation distance.
  • it is desirable that the length of the outer peripheral contour line is 1.05 times or more and 1.15 times or less the length of the rectangular contour line circumscribing the outer peripheral contour line.
  • An AlN layer is provided between the substrate and the n-type semiconductor layer, and the first surface has a first region (light emitting region) covered with the AlN layer and a second region not covered with the AlN layer. It is preferable that the ratio of the area of the first region to the total area of the first surface is 10% or more and 80% or less. In the semiconductor light emitting device of the first feature described above, absorption of ultraviolet rays in the non-light emitting portion is suppressed. Therefore, the external quantum efficiency of ultraviolet rays emitted from the light emitting element is high.
  • the second feature of the invention is a substrate having a first surface, an AlN layer on the first surface of the substrate, an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer on the AlN layer, A plurality of n-dot electrodes that are in contact with the n-type semiconductor layer, the plurality of n-dot electrodes are arranged in a discrete manner, and the substrate is covered with the AlN layer in a first region (light-emitting region). And a second region (non-light emitting region) not covered by the AlN layer, and the ratio of the area of the first region to the area of the first surface of the substrate is 10% or more and 80% or less. It was that.
  • the reflective film has a reflective film
  • the reflective film is disposed in the second region of the substrate, that is, the non-light emitting region.
  • the AlN layer may have a region (intermediate AlN layer) in which the concentration of carbon or oxygen is higher than that of other regions in the stacking direction. The AlN layer is formed by changing from a low temperature to a high temperature in the stacking direction.
  • the positional relationship between the first area and the second area may be the following several relationships.
  • the second region preferably surrounds the periphery of the first region.
  • the second region may surround the periphery of the plurality of first regions.
  • the first region may surround the periphery of the second region.
  • There may be a plurality of second regions, and the first region may surround the periphery of the plurality of second regions.
  • the second region has an inner second region disposed inside and an outer second region disposed outside thereof, and the first region surrounds the inner second region.
  • the outer second region may surround the first region.
  • the AlN layer may have a tapered side surface in a direction in which the area becomes smaller as the distance from the first surface of the substrate increases. In the semiconductor light emitting device having the second characteristic described above, the abnormal composition region in the AlN layer is reduced. That is, the amount of ultraviolet rays absorbed in the composition abnormal region of the AlN layer is smaller than in the conventional case. Therefore, the external quantum efficiency of this semiconductor light emitting device is higher than that of the conventional one.
  • the entire region of the light-emitting surface of the light-emitting layer is any strip-shaped region. It is desirable that the n dot electrodes are arranged so as to belong to the inside. The current flows vertically through the p-type semiconductor layer and the light-emitting layer toward the n-type semiconductor layer, and is distributed in the n-type semiconductor layer toward the adjacent n dot electrodes in the lateral direction and flows into the n dot electrode.
  • the band-shaped region is a dominant region of the n-dot electrode in which a current having a certain density or more flows into each n-dot electrode. If the current flowing through all the light emitting surfaces of the light emitting layer exists in this dominant region, the current density on the light emitting surface of the light emitting layer becomes a certain value or more. As a result, there is no region of the light emitting layer that does not contribute to light emission. Also, the outer contour line may have an arc.
  • the outer peripheral contour line is a waveform that is parallel to a portion of the dot electrode outer periphery of the array of the plurality of n dot electrodes that is closest to the outer peripheral contour line along the outer peripheral contour line and that faces the outer peripheral contour line. It is desirable to have a shape.
  • the p-type semiconductor layer may have a p-type GaN layer.
  • the p-type GaN layer is desirable because it has higher hole conductivity than AlGaN, but it has a drawback of absorbing ultraviolet rays. However, since p-GaN does not exist in the non-light emitting region, light absorption can be suppressed.
  • absorption of ultraviolet rays in the non-light emitting portion is suppressed. Further, according to the second feature, absorption of ultraviolet rays in the composition abnormal region of the AlN layer is suppressed.
  • FIG. 3 is a plan view in which a substrate, an n-type semiconductor layer, and an n dot electrode are extracted and drawn from the light emitting device of the first embodiment. It is the figure which expanded the circumference
  • FIG. 6 is an enlarged view showing the periphery of an AlN layer in the light emitting device of the second embodiment.
  • 6 is a graph showing the relationship between the ratio of the area of the AlN layer to the area of the semiconductor formation surface of the substrate and the amount of increase in drive voltage.
  • 5 is a graph showing the relationship between the light emitting efficiency and the ratio of the area of the AlN layer to the area of the semiconductor formation surface of the substrate.
  • the present invention is not limited to these embodiments.
  • the laminated structure in the drawings does not reflect the actual thickness.
  • the semiconductor light emitting device may have a laminated structure different from that of the embodiment.
  • FIG. 1 is a schematic configuration diagram of a light emitting element 100 according to the first embodiment.
  • the light emitting element 100 emits ultraviolet light.
  • the wavelength of ultraviolet rays is 100 nm or more and 400 nm or less.
  • the light emitting element 100 is a flip chip having a light extraction surface LE1 on the substrate side.
  • the light emitting device 100 includes a substrate 110, an AlN layer 120, an n-type semiconductor layer 130, a light emitting layer 140, a p-type semiconductor layer 150, a transparent electrode 160, and an n dot electrode N1.
  • the substrate 110 supports the semiconductor layer.
  • the substrate 110 has a first surface 110a and a light extraction surface LE1.
  • the first surface 110a is a semiconductor layer formation surface.
  • the light extraction surface LE1 is a surface opposite to the first surface 110a.
  • the substrate 110 is, for example, a sapphire substrate.
  • a growth substrate on which a Group III nitride semiconductor can be formed is preferable.
  • the substrate 110 is a heterogeneous substrate different from AlN.
  • the AlN layer 120 is a layer formed on the first surface 110 a of the substrate 110.
  • the AlN layer 120 is in contact with the first surface 110a.
  • the AlN layer 120 may include a low temperature AlN layer, an intermediate AlN layer, and a high temperature AlN layer from the first surface 110a side.
  • the intermediate AlN layer is an AlN layer formed while increasing the substrate temperature from the film forming temperature of the low temperature AlN layer to the film forming temperature of the high temperature AlN layer. The presence of the low temperature AlN layer, the intermediate AlN layer, and the high temperature AlN layer makes it possible to grow a semiconductor layer having excellent crystallinity.
  • the n-type semiconductor layer 130 is formed on the AlN layer 120.
  • the n-type semiconductor layer 130 is located on the substrate 110 and between the AlN layer 120 and the light emitting layer 140.
  • the n-type semiconductor layer 130 is, for example, an n-AlGaN layer.
  • the n-type semiconductor layer 130 is in contact with the n-dot electrode N1. Therefore, the n-type semiconductor layer 130 is electrically connected to the n-dot electrode N1.
  • the light emitting layer 140 is a layer that emits ultraviolet rays.
  • the light emitting layer 140 is located between the n-type semiconductor layer 130 and the p-type semiconductor layer 150.
  • the light emitting layer 140 has a well layer and a barrier layer.
  • the number of repetitions of the well layer and the barrier layer is, for example, 1 or more and 5 or less.
  • the well layer is, for example, an AlGaN layer.
  • the barrier layer is, for example, an AlGaN layer.
  • the Al composition of the well layer is lower than the Al composition of the barrier layer.
  • the p-type semiconductor layer 150 is located between the light emitting layer 140 and the transparent electrode 160.
  • the p-type semiconductor layer 150 is, for example, a p-AlGaN layer or a p-GaN layer.
  • the p-type semiconductor layer 150 may be a layer in which a p-AlGaN layer and a p-GaN layer are sequentially stacked.
  • the p-type semiconductor layer 150 is electrically connected to the p-dot electrode P1 via the transparent electrode 160.
  • the transparent electrode 160 is located on the p-type semiconductor layer 150.
  • the transparent electrode 160 is for diffusing an electric current in the light emitting surface.
  • the material of the transparent electrode 160 is, for example, IZO or ITO. Alternatively, other conductive transparent oxide may be used.
  • the n dot electrode N1 is for electrically connecting the n-type semiconductor layer 130 and the n pad electrode N3.
  • the n dot electrode N1 is in contact with the n type semiconductor layer 130 on the n type semiconductor layer 130.
  • a plurality of n dot electrodes N1 are arranged discretely with respect to the first surface 110a of the substrate 110.
  • the n wiring electrode N2 is a wiring for electrically connecting the n dot electrode N1 and the n pad electrode N3.
  • the n-pad electrode N3 is an electrode for electrically connecting to a power source outside the element.
  • the p dot electrode P1 is for electrically connecting the p-type semiconductor layer 150 and the p pad electrode P3.
  • the p dot electrode P1 is in contact with the transparent electrode 160.
  • the p dot electrode P1 is electrically connected to the p-type semiconductor layer 150 via the transparent electrode 160.
  • a plurality of p dot electrodes P1 are arranged discretely with respect to the plate surface of the substrate 110.
  • the plurality of p dot electrodes P1 are arranged, for example, in a honeycomb shape.
  • the p wiring electrode P2 is a wiring for electrically connecting the p dot electrode P1 and the p pad electrode P3.
  • the p pad electrode P3 is an electrode for electrically connecting to a power source outside the element.
  • the distributed Bragg reflection film DBR1 is a reflection film for reflecting the light transmitted through the substrate 110 in the direction away from the light extraction surface LE1.
  • the distributed Bragg reflection film DBR1 covers the semiconductor layer and is in contact with part of the substrate 110.
  • the distributed Bragg reflection film DBR1 insulates the p electrode such as the p wiring electrode P2 from the n electrode such as the n wiring electrode N2.
  • the distributed Bragg reflection film DBR1 is formed by alternately stacking SiO 2 and TiO 2 , for example. Of course, materials other than these may be used.
  • the insulating film IF1 insulates the p electrode such as the p wiring electrode P2 from the n electrode such as the n wiring electrode N2.
  • the material of the insulating film IF1 is, for example, SiO 2 . Of course, other materials may be used.
  • FIG. 2 is a plan view of the substrate 110, the n-type semiconductor layer 130, and the n dot electrode N1 extracted from the light emitting device 100 of the first embodiment.
  • the n dot electrode N1 is formed on the surface (electrode formation surface) of the n-type semiconductor layer 130 exposed by removing the light emitting layer 140 and the p-type semiconductor layer 150.
  • the electrode forming surface is arranged in a dispersed manner on a surface parallel to the plate surface (first surface 110a) of the first substrate 110.
  • the plurality of n dot electrodes N1 are arranged in a honeycomb shape.
  • the plurality of n dot electrodes N1 are regularly arranged at the vertices of an equilateral triangle.
  • the pitches of the plurality of n dot electrodes N1 are equidistant.
  • the plurality of n dot electrodes N1 are circular in a cross section parallel to the first surface 110a.
  • the contour of the portion where the n dot electrode N1 contacts the electrode formation surface is the dot electrode outer circumference.
  • FIG. 3 is an enlarged view of the periphery of the outer edge of the light emitting device 100 of the first embodiment.
  • the semiconductor layer has a concave-convex portion U1 on the side surface O1 (the contour of the orthogonal projection of the first surface 110a of the side wall of the light emitting layer 140 of U1 is the outer peripheral contour line).
  • the uneven portion U1 is formed over the side surface O1 of the n-type semiconductor layer 130, the light emitting layer 140, and the p-type semiconductor layer 150.
  • the concavo-convex shape portion U1 has concavities and convexities that face outward from the side surface O1 of the light emitting layer 140.
  • the side surface O1 intersects the first surface 110a of the substrate 110.
  • a region surrounded by the outer peripheral contour line is a light emitting region.
  • the uneven portion U1 has an uneven shape that conforms to the shape of the dot electrode outer circumference of the n dot electrode N1.
  • the distance between the outer circumference of each dot electrode of the array and the outer contour line is within the range of 45 ⁇ m or less.
  • the separation distance between the outer peripheral contour line of the uneven portion U1 and the outer periphery of the n-dot electrode may be in the range of 10 ⁇ m or more and 45 ⁇ m or less. It is preferably 40 ⁇ m or less. More preferably, the separation distance is in the range of 20 ⁇ m or more and 45 ⁇ m or less, and more preferably in the range of 32 ⁇ m or more and 43 ⁇ m or less.
  • the contour line of the uneven portion U1 in the cross section parallel to the first surface 110a partially has an arc.
  • a cross section parallel to the first surface 110a of the substrate 110 is as follows.
  • the distance W1 from the n dot electrode N1 closest to the uneven portion U1 to the uneven portion U1 (outer peripheral contour line) is the dot electrode outer circumference (n dot electrode) of the adjacent n dot electrodes N1. It is greater than half the distance W2 between the N1 n-type semiconductor layer 130 contact surface contour) and the dot electrode outer circumference of the n dot electrode N1. That is, the following formula is established. W2/2 ⁇ W1.........(1)
  • a current preferably reaches from the intermediate point Q1 between the dot electrode outer circumference of the adjacent n dot electrode N1 and the dot electrode outer circumference of the n dot electrode N1 which are adjacent to each other. ..
  • half of the inter-dot electrode distance W2 (W2/2), which is the distance between the dot electrode outer circumferences of the adjacent n dot electrodes N1 and N dot electrodes N1 is the distance from the n dot electrode N1 to the intermediate point Q1. is there.
  • the distance from the n dot electrode N1 is not the distance from the center of the n dot electrode N1 but the shortest distance from the dot electrode outer circumference of the n dot electrode N1.
  • the inter-dot electrode distance W2 between the adjacent n dot electrodes N1 and N dot electrodes N1 is calculated from the arrangement of the plurality of n dot electrodes N1 closest to the concavo-convex shape portion U1 among the plurality of n dot electrodes N1. Is larger than the separation distance W1. That is, the following formula is established. W1 ⁇ W2.........(2)
  • the pitch interval of the n dot electrodes N1 is suitable.
  • the n dot electrodes N1 are arranged in a honeycomb shape (triangular lattice), the three n dot electrodes N1 are arranged at the vertices of an equilateral triangle. Therefore, the center of gravity G1 of the equilateral triangle can be virtually set.
  • the center of gravity G1 is located at the same distance from the three n dot electrodes N1.
  • the distance W3 from the outer circumference of the dot electrode of the n dot electrode N1 located at the apex of the equilateral triangle to the center of gravity G1 of the equilateral triangle is the distance of the n dot electrode N1 closest to the uneven portion U1 among the plurality of n dot electrodes N1.
  • the n dot electrode diameter, pitch, and arrangement are set so that all the light emitting surfaces of the light emitting layer are present in this strip region when a strip region of 40 ⁇ m is drawn from the outer circumference of those dot electrodes. By determining, light can be emitted from all light emitting surfaces.
  • the current flows vertically through the p-type semiconductor layer 150 and the light-emitting layer 140 toward the n-type semiconductor layer 130, and is dispersed in the n-type semiconductor layer 130 toward each adjacent n dot electrode in the lateral direction to be an n dot electrode. Pour in.
  • the band-shaped region is a dominant region of the n-dot electrode in which a current having a certain density or more flows into each n-dot electrode. If the current flowing through all the light emitting surfaces of the light emitting layer 140 exists in this dominant region, the current density on the light emitting surface of the light emitting layer becomes a certain value or more. As a result, there is no region of the light emitting layer that does not contribute to light emission.
  • the outer peripheral contour line of the light emitting region of the light emitting layer 140 changes depending on the diameter and pitch of the n dot electrode N1 and the distance from the n dot electrode N1.
  • the length of the outer peripheral contour line of the uneven shape portion U1 that is the side surface O1 is longer than that of the conventional one.
  • the length of the outer peripheral contour line of the concave-convex shape portion U1 in the cross section parallel to the first surface 110a is the length of the quadrangle contour circumscribing the concave-convex shape portion U1 (peripheral contour line) in the cross section parallel to the first surface 110a. It is 1.05 times or more and 1.15 times or less.
  • FIG. 4 is a diagram for comparing semiconductor layers of the light emitting element 100 of the first embodiment and the conventional light emitting element.
  • a first region R1 and a second region R2 are drawn.
  • the first region R1 is a region where the AlN layer 120 was present.
  • the second region R2 is a region where a laminated structure of the n-type semiconductor layer 130, the light emitting layer 140, and the p-type semiconductor layer 150 is present.
  • the conventional light emitting device has the first region R1 and the second region R2, but does not exist in the light emitting device 100 of the first embodiment. Further, in the conventional light emitting device, there may be a case where only the first region R1 is provided.
  • the first region R1 and the second region R2 are non-light emitting parts. Then, the first region R1 and the second region R2 absorb ultraviolet rays to some extent.
  • the p-type semiconductor layer 150 includes p-GaN, the amount of ultraviolet rays absorbed is large. This is because p-GaN has a small band gap and easily absorbs ultraviolet rays.
  • the first region R1 and the second region R2 in the conventional light emitting element not only contribute to light emission but also absorb ultraviolet rays. Since the light emitting device 100 according to the first embodiment does not have such a non-light emitting portion, the external quantum efficiency is high.
  • the AlN layer 120 is formed on the first surface 110a of the substrate 110.
  • the first surface 110a is a surface opposite to the light extraction surface LE1.
  • a low temperature AlN layer is formed on the first surface 110a while keeping the substrate temperature constant.
  • an intermediate AlN layer is formed on the low temperature AlN layer while increasing the substrate temperature.
  • a high temperature AlN layer is formed on the intermediate AlN layer while keeping the substrate temperature constant.
  • the formation temperature of the high temperature AlN layer is higher than the formation temperature of the low temperature AlN layer.
  • a semiconductor layer is formed on the AlN layer 120.
  • the formation order is the n-type semiconductor layer 130, the light emitting layer 140, and the p-type semiconductor layer 150. As a result, a semiconductor layer is formed on the entire surface of the wafer.
  • Concavo-convex portion forming step Next, a part of the semiconductor layer is removed to form the concavo-convex portion U1.
  • the uneven portion U1 can be formed while partially removing the semiconductor layer by dry etching using a chlorine-based gas such as Cl 2 .
  • the n-type semiconductor layer 130 may be partially exposed in accordance with the formation position of the n-dot electrode N1 arranged in a honeycomb shape.
  • the transparent electrode 160 is formed on the p-type semiconductor layer 150.
  • Step of forming reflective layer Next, the distributed Bragg reflective film DBR1 is formed. At this time, the distributed Bragg reflection film DBR1 covers the semiconductor layer and the outer peripheral surface of the first surface 110a of the substrate 110.
  • part of the distributed Bragg reflective film DBR1 is opened to expose part of the n-type semiconductor layer 130 and the transparent electrode 160 covered with the distributed Bragg reflective film DBR1. Then, the n dot electrode N1 and the p dot electrode P1 are formed. After that, the n wiring electrode N2 and the p wiring electrode P2 may be formed while appropriately forming the insulating film IF1. Then, the n pad electrode N3 and the p pad electrode P3 are formed.
  • the light emitting device 100 of the first embodiment does not have a non-light emitting region unlike the conventional light emitting device.
  • This non-luminous region easily absorbs ultraviolet rays. Therefore, in the light emitting element 100 of the first embodiment, the absorption of light by the non-light emitting region is suppressed. Therefore, the external quantum efficiency of the light emitting device 100 of the first embodiment is sufficiently higher than the external quantum efficiency of the conventional light emitting device.
  • the p-dot electrode P1 may be one in some cases. That is, the p dot electrodes P1 may not be arranged discretely. This is because the current is relatively diffused by the transparent electrode 160.
  • the first surface 110a of the substrate 110 may be covered with the distributed Bragg reflection film DBR1. This is because the light traveling from the light extraction surface LE1 of the substrate 110 toward the first surface 110a can be reflected to the light extraction surface LE1 side.
  • n dot Electrodes N1 are arranged in a honeycomb shape (triangular lattice). However, they may be arranged in a square lattice. Even in this case, the technique of the first embodiment can be applied. Further, the equation (1) holds similarly. Alternatively, it may be another regular array.
  • a metallic reflective film may be used instead of the distributed Bragg reflective film DBR1 of the first embodiment. Even in this case, the metal reflection film can reflect the ultraviolet rays moving away from the light extraction surface LE1. However, it is necessary to separately form an insulating film that insulates the n electrode and the p electrode.
  • the insulating film IF1 may be a distributed Bragg reflection film.
  • the light emitting element of the example is the light emitting element 100 of the first embodiment having an uneven portion.
  • the light emitting element of the comparative example is a conventional light emitting element having no uneven portion.
  • a quadrangle circumscribing the plurality of convex portions of the uneven portion of the light emitting layer of the light emitting element of the example substantially matches the outer shape of the light emitting layer of the light emitting element of the comparative example. Otherwise, the light emitting device of the example and the light emitting device of the comparative example are the same.
  • Table 1 is a table for comparing the lengths of the outer peripheries of the concave-convex shape. Table 1 compares the length of one round of the side surface of the light emitting layer when there is the uneven portion with the length of one round of the side surface of the light emitting layer when there is no uneven portion.
  • the length of the contour line of the light emitting layer when there is no uneven portion is 1.
  • the case where there is no uneven portion is a case where a quadrangle that circumscribes a plurality of convex portions of the uneven portion is set. Therefore, the length of the contour line of the light emitting layer when there is no uneven portion is the total length of the four sides of a quadrangle circumscribing the plurality of convex portions of the uneven portion.
  • the length of the contour line of the light emitting layer in the case where there is the uneven portion is the length of the outer frame of the light emitting layer in a cross section parallel to the first surface 110a.
  • the length of the contour line of the light emitting layer when there is the uneven portion is 1.09 times the length of the contour line of the light emitting layer when there is no uneven portion.
  • the diameter of the n dot electrode P1 is 48 ⁇ m.
  • the pitch of the n dot electrodes N1 is 103 ⁇ m.
  • the separation distance between the uneven portion U1, that is, the outer peripheral contour line of the light emitting region and the n dot electrode N1 is 40 ⁇ m.
  • the length of the contour line of the light emitting layer when there is the uneven portion is preferably 1.05 times or more and 1.15 times or less the length of the contour line of the light emitting layer when there is no uneven portion. In this case, the light output of the light emitting element is high.
  • Light Output Table 2 is a table for comparing the relationship between the uneven portion and the light output. As shown in Table 2, the light output of the light emitting element of the example having the uneven portion is 1.05 times the light output of the light emitting element of the comparative example having no uneven portion. As described above, the non-light emitting portion of the conventional light emitting element is removed by forming the uneven portion. By removing the non-light emitting portion, it is possible to suppress absorption of ultraviolet rays by the non-light emitting portion.
  • FIG. 5 is a schematic configuration diagram of the light-emitting element 101 of the second embodiment.
  • the light emitting element 101 emits ultraviolet light.
  • the wavelength of ultraviolet rays is 100 nm or more and 400 nm or less.
  • the light emitting element 101 is a flip chip having a light extraction surface LE1 on the substrate side.
  • the light emitting device 101 includes a substrate 110, an AlN layer 120, an n-type semiconductor layer 130, a light emitting layer 140, a p-type semiconductor layer 150, a transparent electrode 160, and an n dot electrode N1.
  • DBR distributed Bragg reflection film
  • IF1 insulating film
  • insulating film IF2 insulating film
  • the substrate 110 supports the semiconductor layer.
  • the substrate 110 has a first surface 110a and a light extraction surface LE1.
  • the first surface 110a is a semiconductor layer formation surface.
  • the light extraction surface LE1 is a surface opposite to the first surface 110a.
  • the substrate 110 is, for example, a sapphire substrate.
  • a growth substrate on which a Group III nitride semiconductor can be formed is preferable.
  • the substrate 110 is a heterogeneous substrate different from AlN.
  • the AlN layer 120 is a layer formed on the first surface 110 a of the substrate 110.
  • the AlN layer 120 is in contact with the first surface 110a.
  • the AlN layer 120 will be described later.
  • the n-type semiconductor layer 130 is formed on the AlN layer 120.
  • the n-type semiconductor layer 130 is located between the AlN layer 120 and the light emitting layer 140.
  • the n-type semiconductor layer 130 is, for example, an n-AlGaN layer.
  • the n-type semiconductor layer 130 is in contact with the n-dot electrode N1, and the n-type semiconductor layer 130 is in conduction with the n-dot electrode N1.
  • the light emitting layer 140 is a layer that emits ultraviolet light.
  • the light emitting layer 140 is located between the n-type semiconductor layer 130 and the p-type semiconductor layer 150.
  • the light emitting layer 140 has a well layer and a barrier layer.
  • the number of repetitions of the well layer and the barrier layer is, for example, 1 or more and 5 or less.
  • the well layer is, for example, an AlGaN layer.
  • the barrier layer is, for example, an AlGaN layer.
  • the Al composition of the well layer is lower than the Al composition of the barrier layer.
  • the p-type semiconductor layer 150 is located between the light emitting layer 140 and the transparent electrode 160.
  • the p-type semiconductor layer 150 is, for example, a p-AlGaN layer or a p-GaN layer.
  • the p-type semiconductor layer 150 is electrically connected to the p-dot electrode P1 via the transparent electrode 160.
  • the transparent electrode 160 is located on the p-type semiconductor layer 150.
  • the transparent electrode 160 is for diffusing an electric current in the light emitting surface.
  • the material of the transparent electrode 160 is, for example, IZO or ITO. Alternatively, other conductive transparent oxide may be used.
  • the n dot electrode N1 is for electrically connecting the n-type semiconductor layer 130 and the n pad electrode N3.
  • the n-dot electrode N1 is in contact with the n-type semiconductor layer 130.
  • a plurality of n dot electrodes N1 are arranged discretely on the plate surface of the substrate 110.
  • the plurality of n dot electrodes N1 are arranged, for example, in a honeycomb shape.
  • the n wiring electrode N2 is a wiring for electrically connecting the n dot electrode N1 and the n pad electrode N3.
  • the n-pad electrode N3 is an electrode for electrically connecting to a power source outside the element.
  • the p dot electrode P1 is for electrically connecting the p-type semiconductor layer 150 and the p pad electrode.
  • the p dot electrode P1 is in contact with the transparent electrode 160.
  • the p dot electrode P1 is electrically connected to the p-type semiconductor layer 150 via the transparent electrode 160.
  • a plurality of p dot electrodes P1 are arranged discretely with respect to the plate surface of the substrate 110.
  • the plurality of p dot electrodes P1 are arranged, for example, in a honeycomb shape.
  • the p wiring electrode P2 is a wiring for electrically connecting the p dot electrode P1 and the p pad electrode.
  • the p-pad electrode is an electrode for electrically connecting to a power source outside the device.
  • the distributed Bragg reflection film DBR1 is a reflection film for reflecting the light transmitted through the substrate 110 in the direction away from the light extraction surface LE1.
  • the distributed Bragg reflection film DBR1 covers the semiconductor layer and is in contact with part of the substrate 110.
  • the distributed Bragg reflection film DBR1 is formed by alternately stacking SiO 2 and TiO 2 , for example. Of course, materials other than these may be used.
  • the insulating film IF1 insulates the p electrode such as the p wiring electrode P2 from the n electrode such as the n wiring electrode N2.
  • the material of the insulating film IF1 is, for example, SiO 2 . Of course, other materials may be used.
  • the insulating film IF2 covers the electrodes such as the n-wiring electrode N2 and protects these electrodes.
  • the material of the insulating film IF2 is, for example, SiO 2 . Of course, other materials may be used.
  • FIG. 6 is an enlarged view in which the periphery of the AlN layer 120 in the light emitting device 101 of the second embodiment is enlarged.
  • the AlN layer 120 includes a low temperature AlN layer 121, an intermediate AlN layer 122, and a high temperature AlN layer 123. From the substrate 110 side, a low temperature AlN layer 121, an intermediate AlN layer 122 and a high temperature AlN layer 123 are arranged.
  • the low temperature AlN layer 121 is an AlN layer formed at a relatively low substrate temperature.
  • the low temperature AlN layer 121 is arranged in contact with the substrate 110 and the intermediate AlN layer 122 at a position between them.
  • the substrate temperature when forming the low-temperature AlN layer 121 is, for example, 1000° C. or higher and 1200° C. or lower.
  • the film thickness of the low temperature AlN layer 121 is, for example, 0.1 ⁇ m or more and 1 ⁇ m or less.
  • the intermediate AlN layer 122 is an AlN layer formed while raising the substrate temperature.
  • the intermediate AlN layer 122 is arranged at a position between the low temperature AlN layer 121 and the high temperature AlN layer 123 so as to be in contact with them.
  • the substrate temperature at the time of forming the intermediate AlN layer 122 is from the film forming temperature of the low temperature AlN layer 121 to the film forming temperature of the high temperature AlN layer 123.
  • the film thickness of the intermediate AlN layer 122 is, for example, 0.3 ⁇ m or more and 3 ⁇ m or less.
  • the high temperature AlN layer 123 is an AlN layer formed with a relatively high substrate temperature.
  • the high temperature AlN layer 123 is arranged in contact with the intermediate AlN layer 122 and the n-type semiconductor layer 130 at a position between them.
  • the substrate temperature when forming the high temperature AlN layer 123 is, for example, 1200° C. or higher and 1400° C. or lower.
  • the film thickness of the high temperature AlN layer 123 is, for example, 0.5 ⁇ m or more and 5 ⁇ m or less.
  • the AlN layer 120 has a taper T1 on the side surface.
  • the taper T1 is a surface in which the area of the AlN layer 120 becomes smaller as the distance from the substrate 110 increases.
  • the intermediate AlN layer 122 has a composition abnormal area CA1.
  • the abnormal composition region CA1 is a place where the content of carbon atoms or oxygen atoms is locally high.
  • the transmission electron microscope image of the abnormal composition region CA1 resembles a void.
  • the present inventors have discovered that the abnormal composition region CA1 easily absorbs ultraviolet rays.
  • FIG. 7 is a plan view showing the substrate 110, the n-type semiconductor layer 130, and the n-dot electrode N1 extracted from the light emitting device 101 of the second embodiment.
  • the n dot electrodes N1 are discretely arranged on the plate surface of the substrate 110.
  • the n dot electrodes N1 are arranged in a honeycomb shape.
  • the semiconductor layer such as the light emitting layer 140 is within a range of 45 ⁇ m or less from the end of the n dot electrode N1. Therefore, the outer surface of the light emitting layer 140 has an uneven shape according to the shape of the n dot electrode N1.
  • the light emitting element 101 has a first region R1 (light emitting region) and a second region R2 (non-light emitting region). As shown in FIG. 7, the first region R1 is located near the center of the element, and the second region R2 surrounds the periphery of the first region R1.
  • the first region R1 is a region in which the AlN layer 120 is formed on the substrate 110.
  • the second region R2 is a region where the AlN layer 120 is not formed on the substrate 110. That is, in the first region R1, the substrate 110 is covered with the AlN layer 120, and in the second region R2, the substrate 110 is not covered with the AlN layer 120.
  • the substrate 110 is in contact with the AlN layer 120 in the first region R1. In the second region R2, the substrate 110 is in contact with the distributed Bragg reflection film DBR1.
  • the distributed Bragg reflection film DBR1 covers the semiconductor layer in the first region R1 and covers the exposed surface of the substrate 110 while being in contact with the second region R2 of the substrate 110.
  • the ratio of the area of the first region R1 to the area of the first surface 110a of the substrate 110 is 10% or more and 80% or less.
  • FIG. 8 is a diagram for explaining a light path in the light-emitting element 101 of the second embodiment.
  • FIG. 8 shows a case where the ultraviolet rays UV1a emitted from the light emitting layer 140 are reflected by the light extraction surface LE1, are reflected again by the distributed Bragg reflection film DBR1, and are extracted to the outside of the element.
  • the ultraviolet rays UV1a are reflected by the light extraction surface LE1 in the direction of the ultraviolet rays UV1b.
  • the ultraviolet ray UV1b is reflected in the direction of the ultraviolet ray UV1c by the distributed Bragg reflection film DBR1.
  • the ultraviolet rays UV1a pass through the AlN layer 120, but the ultraviolet rays UV1b and ultraviolet rays UV1c do not pass through the AlN layer 120. In this way, the light from the light emitting layer 140 can be suppressed from passing through the AlN layer 120. That is, the amount of light absorbed by the abnormal composition region CA1 is small.
  • FIG. 9 is a diagram for explaining light paths in a light-emitting element in which area of a semiconductor layer forming surface of a substrate is equal to area of AlN layer. Is.
  • FIG. 9 shows a case where the ultraviolet rays UV2a emitted from the light emitting layer are reflected on the light extraction surface, are reflected again by the distributed Bragg reflection film, and are extracted to the outside of the element. As shown in FIG. 9, the ultraviolet rays UV2a are reflected by the light extraction surface in the direction of the ultraviolet rays UV2b. The ultraviolet ray UVb2 is reflected in the direction of the ultraviolet ray UV2c by the distributed Bragg reflection film.
  • the light emitting area of the light emitting layer is smaller than that of the conventional light emitting element. Instead, the current density of the light emitting element 101 is higher than that of the conventional light emitting element. Although affected by the current resistance value, the current value of the light emitting element 101 is not significantly different from the current value of the conventional light emitting element.
  • Patent Document 1 International Publication 2016/143574.
  • the shape of the n-electrode is devised.
  • the n-electrode is formed on the n-type semiconductor layer, the light-emitting layer is surrounded by the n-type semiconductor layer. That is, the AlN layer, which is a base layer of the n-type semiconductor layer, surrounds the periphery of the light emitting layer.
  • the AlN layer surrounding the light emitting layer absorbs light in the abnormal composition region.
  • a light emitting device 101 according to the second embodiment has a first region R1 in which the AlN layer 120 exists and a second region R2 in which the AlN layer 120 does not exist.
  • the composition abnormal region CA1 is smaller than that of the conventional light emitting element. Therefore, the amount of ultraviolet rays absorbed in the abnormal composition region CA1 of the AlN layer 120 is small. Therefore, the light output of the light emitting device 101 of the second embodiment is sufficiently higher than the light output of the conventional light emitting device.
  • the AlN layer 120 is formed on the first surface 110a of the substrate 110.
  • the first surface 110a is a surface opposite to the light extraction surface LE1.
  • the low temperature AlN layer 121 is formed on the first surface 110a while keeping the substrate temperature constant.
  • the intermediate AlN layer 122 is formed on the low temperature AlN layer 121.
  • the high temperature AlN layer 123 is formed on the intermediate AlN layer 122 while keeping the substrate temperature constant.
  • the formation temperature of the high temperature AlN layer 123 is higher than the formation temperature of the low temperature AlN layer 121.
  • a semiconductor layer is formed on the high temperature AlN layer 123 of the AlN layer 120.
  • the formation order is the n-type semiconductor layer 130, the light emitting layer 140, and the p-type semiconductor layer 150.
  • the semiconductor layer and the AlN layer 120 are removed.
  • the semiconductor layer and the AlN layer 120 in a region corresponding to the second region R2 (non-light emitting region) are removed by leaving the first region R1 (light emitting region) by dry etching using a chlorine-based gas such as Cl 2 .
  • the etching is performed in two steps of etching for exposing the n-type semiconductor layer 130 and etching for removing the AlN layer 120.
  • the n-type semiconductor layer 130 is exposed at the formation position of the n-dot electrode N1 arranged in a honeycomb shape.
  • the transparent electrode 160 is formed on the p-type semiconductor layer 150.
  • Step of forming reflective layer the distributed Bragg reflective film DBR1 is formed. At that time, the distributed Bragg reflection film DBR1 covers the transparent electrode 160 and the semiconductor layer in the first region R1, and covers the first surface 110a of the substrate 110 in the second region R2.
  • part of the distributed Bragg reflective film DBR1 is opened to expose part of the n-type semiconductor layer 130 and the transparent electrode 160 covered with the distributed Bragg reflective film DBR1. Then, the n dot electrode N1 and the p dot electrode P1 are formed. After that, the n wiring electrode N2 and the p wiring electrode P2 may be formed while appropriately forming the insulating film IF1. Then, the insulating film IF2 is formed. Then, the n pad electrode N3 and the p pad electrode are formed.
  • Modification 8-1 Reflective Film
  • a metallic reflective film may be used. Even in this case, the metal reflection film covers the semiconductor layer in the first region R1 and contacts the substrate 110 in the second region R2. Even in this case, the metal reflection film can reflect the ultraviolet rays moving away from the light extraction surface LE1.
  • Insulating Film At least one of the insulating film IF1 and the insulating film IF2 may be a distributed Bragg reflection film.
  • Step of forming AlN layer An insulating film may be formed in advance in the second region R2.
  • the AlN layer 120 may be formed in the first region R1 using the insulating film as a mask. In this case, the step of removing the AlN layer 120 is not necessary.
  • the insulating film used as the mask may be the first layer in the distributed Bragg reflection film DBR1.
  • the first layer is a film formed in contact with the first surface 110a immediately above the substrate 110.
  • the p-dot electrode P1 may be one in some cases. That is, the p dot electrodes P1 may not be arranged discretely. This is because the current is relatively diffused by the transparent electrode 160.
  • a third embodiment will be described.
  • the semiconductor light emitting device of the third embodiment is different from the semiconductor light emitting device of the second embodiment in the formation regions of the first region R1 and the third region R2. Therefore, the difference will be described.
  • FIG. 10 is a plan view showing a first area R1 (light emitting area) and a second area R2 (non-light emitting area) in the light emitting device 200 of the third embodiment. ..
  • the light emitting element 200 has four first regions R1 and second regions R2.
  • the second region R2 surrounds the four first regions R1.
  • the plurality of first regions R1 has a shape close to a square.
  • the number of the first regions R1 may be a plurality other than four.
  • the shape of the first region R1 may be a polygon other than a square or a circle. Alternatively, it may have another shape.
  • a fourth embodiment will be described.
  • the semiconductor light emitting device of the fourth embodiment is different from the semiconductor light emitting device of the second embodiment in the formation regions of the first region R1 and the second region R2. Therefore, the difference will be described.
  • FIG. 11 is a plan view showing a first region R1 and a second region R2 in the light emitting device 300 of the fourth embodiment.
  • the light emitting element 300 has a first region R1 and a second region R2.
  • the second region R2 is located near the center of the element.
  • the first region R1 surrounds the periphery of the second region R2.
  • the first region R1 has a frame shape.
  • the second region R2 has a shape close to a square inside the frame-shaped first region R1.
  • a fifth embodiment will be described.
  • the semiconductor light emitting device of the fifth embodiment is different from the semiconductor light emitting device of the second embodiment in the formation regions of the first region R1 and the second region R2. Therefore, the difference will be described.
  • FIG. 12 is a plan view showing a first region R1 and a second region R2 in the light emitting device 400 of the fifth embodiment.
  • the light emitting element 400 has a first region R1 and four second regions R2.
  • the first region R1 surrounds the four second regions R2.
  • the four second regions R2 have a shape close to a square.
  • the number of the second regions R2 may be plural other than four.
  • the shape of the second region R2 may be a polygon other than a square or a circle. Alternatively, it may have another shape.
  • FIG. 6 A sixth embodiment will be described.
  • the semiconductor light emitting device of the sixth embodiment is different from the semiconductor light emitting device of the second embodiment in the formation regions of the first region R1 and the second region R2. Therefore, the difference will be described.
  • FIG. 13 is a plan view showing a first region R1 and a second region R2 in the light emitting device 500 of the sixth embodiment.
  • the light emitting element 500 has a first region R1, an inner second region R2a, and an outer second region R2b.
  • the inner second region R2a is located near the center of the element.
  • the first region R1 surrounds the inner periphery of the second region R2a.
  • the outer second region R2b surrounds the periphery of the first region R1. That is, the first region R1 is sandwiched between the inner second region R2a and the outer second region R2b.
  • the inner second region R2a has a shape close to a square.
  • the first region R1 has a frame shape.
  • the outer second region R2b has a frame shape.
  • the shape of the inner second region R2a is a shape close to a square. However, it may be a polygon other than a square or a circle.
  • the intermediate AlN layer 122 there is a composition abnormal region where the carbon concentration and the oxygen concentration are high.
  • FIG. 14 is a TEM image around the AlN layer. In the region of the intermediate AlN layer, the abnormal composition region appears as a shadow or a void.
  • FIG. 15 is a graph showing the relationship between the optical output and the ratio of the area of the AlN layer to the area of the semiconductor formation surface of the substrate (AlN area ratio).
  • the horizontal axis of FIG. 15 is the ratio of the area of the AlN layer to the area of the semiconductor formation surface of the substrate. That is, it is the ratio of the area of the first region R1 to the area of the semiconductor formation surface of the substrate.
  • the area of the semiconductor formation surface of the substrate is the sum of the area of the first region R1 and the area of the second region R2.
  • the vertical axis of FIG. 15 represents the light output (au) of the light emitting element.
  • the AlN area ratio is 10% or more and 80% or less, the light output is larger than 1, and the light output is higher than the conventional one (AlN area ratio is 100%).
  • AlN area ratios were 26%, 38%, 50% and 66%, the light outputs were 1.34, 1.27, 1.26 and 1.23, respectively. From this, it can be seen that when the AlN area ratio is 20% or more and 70% or less, the optical output is 20% or more higher than the conventional one, and there is a remarkable effect. Further, in the range of the actually measured value, in the range of the AlN area ratio of 26% or more and 66% or less, the light output was 1.23 or more, which is a remarkable effect compared to the conventional example.
  • the light output changes critically when the AlN area ratio is 26%. In the range where the AlN area ratio is 38% or more and 66% or less, the light output shows a substantially constant value of 1.3 to 1.2, and decreases as the AlN area ratio increases. When the AlN area ratio was 25%, the light output was about 34% higher than the conventional value, and showed the highest value.
  • FIG. 16 is a graph showing the relationship between the ratio of the area of the AlN layer to the area of the semiconductor formation surface of the substrate (AlN area ratio) and the amount of increase in the driving voltage.
  • the amount of increase is the amount of increase with respect to the drive voltage of the element (conventional example) when the AlN layer is not removed.
  • the horizontal axis of FIG. 16 is the AlN area ratio.
  • the vertical axis of FIG. 16 represents the amount of increase (V) in the drive voltage of the light emitting element.
  • the driving voltage tends to increase as the AlN area ratio decreases. Since the current cross section becomes smaller, the drive voltage rises.
  • the increase range of the driving voltage is 3V or less.
  • the increase range of the driving voltage is 2V or less.
  • FIG. 17 is a graph showing the relationship between the luminous efficiency and the ratio of the area of the AlN layer to the area of the semiconductor formation surface of the substrate (AlN area ratio).
  • the horizontal axis of FIG. 17 is the AlN area ratio.
  • the vertical axis of FIG. 17 represents the luminous efficiency (au) of the light emitting element.
  • the optical outputs were 0.91, 0.98, 1.04, and 1.11. From FIG. 17, it can be seen that when the AlN area ratio is 40% or more and 80% or less, the luminous efficiency is higher than that of the conventional element (AlN area ratio 100%). In particular, it is understood that the luminous efficiency can be maintained high if the AlN area ratio is 37% or more.

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Abstract

Le problème décrit par la présente invention est de supprimer l'absorption de rayons UV dans une section non électroluminescente. À cet effet, l'invention concerne un élément électroluminescent à semi-conducteur comprenant : un substrat ayant une première surface; une couche semi-conductrice de type n formée sur la première surface du substrat; une couche électroluminescente qui émet des rayons UV; une couche semi-conductrice de type p; et une pluralité d'électrodes à n points qui entrent en contact avec une surface de formation d'électrode formée de manière dispersée dans laquelle la couche semi-conductrice supérieure de la couche semi-conductrice de type n n'est pas présente, les surfaces de contact de la pluralité d'électrodes à n points comportant la périphérie externe des électrodes à points. Dans la couche électroluminescente, seule une région électroluminescente ayant une ligne de contour de périphérie externe sur le plan parallèle à la première surface est formée, la région électroluminescente restant après la couche semi-conductrice de type p, la couche électroluminescente et la couche semi-conductrice de type n sont retirées, de sorte qu'il n'y ait pas de région où la lumière UV ne soit pas émise.
PCT/JP2019/047989 2018-12-26 2019-12-09 Élément électroluminescent à semi-conducteur WO2020137470A1 (fr)

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JP7177360B2 (ja) 2020-07-22 2022-11-24 日亜化学工業株式会社 発光素子及び発光装置
WO2023015275A1 (fr) * 2021-08-06 2023-02-09 Creeled, Inc. Structures de bord pour la mise en forme de la lumière dans des puces de diodes électroluminescentes
US11870009B2 (en) 2021-08-06 2024-01-09 Creeled, Inc. Edge structures for light shaping in light-emitting diode chips

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