WO2020135049A1 - 显示面板的过流保护方法及显示装置 - Google Patents

显示面板的过流保护方法及显示装置 Download PDF

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Publication number
WO2020135049A1
WO2020135049A1 PCT/CN2019/124553 CN2019124553W WO2020135049A1 WO 2020135049 A1 WO2020135049 A1 WO 2020135049A1 CN 2019124553 W CN2019124553 W CN 2019124553W WO 2020135049 A1 WO2020135049 A1 WO 2020135049A1
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Prior art keywords
level shifter
current
preset
current input
effective
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PCT/CN2019/124553
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English (en)
French (fr)
Inventor
邱彬
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惠科股份有限公司
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Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Priority to US17/264,300 priority Critical patent/US11514869B2/en
Publication of WO2020135049A1 publication Critical patent/WO2020135049A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/025—Reduction of instantaneous peaks of current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • the present application relates to the field of display technology, and in particular, to an overcurrent protection method of a display panel and a display device.
  • the gate driver circuit Gate Driver on Array, GOA
  • GOA Gate Driver on Array
  • the embodiments of the present application provide an over-current protection method and a display device for a display panel, to achieve the purpose of avoiding damage to the chip due to excessive current input by the level shifter.
  • the overcurrent protection method for the display panel includes the following steps:
  • the level shifter When the current input by the level shifter is greater than the first preset current within a first preset time, the level shifter is controlled to stop running.
  • the present application also provides an overcurrent protection method for a display panel, which is applied in a timing controller.
  • the overcurrent protection method for the display panel includes the following steps:
  • the level shifter When the average current input by the level shifter is greater than the first preset current within a first preset time, the level shifter is controlled to stop running.
  • the present application also provides a display device, including a memory, a processor, and an overcurrent protection program for a display panel stored on the memory and operable on the processor.
  • the processor executes the display panel The following steps are implemented during the overcurrent protection program:
  • the level shifter When the current input by the level shifter is greater than the first preset current within a first preset time, the level shifter is controlled to stop running.
  • the level shifter when the first clock signal is received, it is determined whether the current input by the level shifter is greater than the first preset current within the first preset time, and the level shift is performed within the first preset time.
  • the level shifter is controlled to stop running to avoid damage to the chip due to excessive current input by the level shifter.
  • FIG. 1 is a schematic structural diagram of an electronic device in a hardware operating environment involved in an embodiment of the present application
  • FIG. 2 is a schematic flowchart of an embodiment of an overcurrent protection method for a display panel of this application
  • FIG. 3 is a schematic diagram of the distribution of the first preset time and the effective time in an embodiment of the application
  • FIG. 4 is a schematic flowchart of another embodiment of an overcurrent protection method for a display panel of this application.
  • FIG. 5 is a detailed flowchart of step S4 in an embodiment of the present application.
  • FIG. 6 is a detailed flowchart of step S42 in an embodiment of the present application.
  • FIG. 7 is a schematic diagram of the correspondence between current and preset times in an embodiment of the present application.
  • FIG. 8 is another schematic flowchart of step S42 in an embodiment of the present application.
  • the main solution of the embodiment of the present application is: when receiving the first clock signal, calculate the current input by the level shifter in the first preset time in the first clock signal; Whether the current input by the level shifter is greater than the first preset current; when the current input by the level shifter is greater than the first preset current within the first preset time, the level shifter is controlled to stop running .
  • the level shifter when it is detected that the current input by the level shifter in the first preset time in the first clock signal is greater than the first preset current, the level shifter is controlled to stop running to avoid the level The current input by the converter is too large and the chip is damaged.
  • the display device may be as shown in FIG. 1.
  • the embodiment of the present application relates to a display device.
  • the display device includes: a processor 1001, such as a CPU, a communication bus 1002, and a memory 1003.
  • the communication bus 1002 is used to implement connection communication between these components.
  • the memory 1003 may be a high-speed RAM memory, or may be a non-volatile memory (non-volatile memory), such as a disk memory. As shown in FIG. 1, the memory 1003 as a computer storage medium may include an overcurrent protection program of the display panel; and the processor 1001 may be used to call the overcurrent protection program of the display panel stored in the memory 1003 and execute the following operating:
  • the level shifter When the current input by the level shifter is greater than the first preset current within a first preset time, the level shifter is controlled to stop running.
  • the processor 1001 may be used to call an overcurrent protection program of the display panel stored in the memory 1003, and perform the following operations:
  • the level shifter When the current input by the level shifter is greater than the second preset current within a second preset time, the level shifter is controlled to stop running.
  • the processor 1001 may be used to call an overcurrent protection program of the display panel stored in the memory 1003, and perform the following operations:
  • the average current input by the level shifter within the second preset time is calculated according to the effective current input by the level shifter during the effective time of each clock signal.
  • the processor 1001 may be used to call an overcurrent protection program of the display panel stored in the memory 1003, and perform the following operations:
  • the processor 1001 may be used to call an overcurrent protection program of the display panel stored in the memory 1003, and perform the following operations:
  • the ratio of the sum of each effective current and the number of clock signals is calculated to obtain the average current input by the level shifter within the second preset time.
  • the processor 1001 may be used to call an overcurrent protection program of the display panel stored in the memory 1003, and perform the following operations:
  • the first preset current is greater than the second preset current.
  • the processor 1001 may be used to call an overcurrent protection program of the display panel stored in the memory 1003, and perform the following operations:
  • the second preset time is the accumulation of the effective time of each clock signal.
  • the processor 1001 may be used to call an overcurrent protection program of the display panel stored in the memory 1003, and perform the following operations:
  • the effective time is the time during which the level shifter inputs the normal operating current in each clock signal, and the effective current is the average current input by the level shifter during each of the effective times.
  • the processor 1001 may be used to call an overcurrent protection program of the display panel stored in the memory 1003, and perform the following operations:
  • the level shifter When the average current input by the level shifter is greater than the first preset current within a first preset time, the level shifter is controlled to stop running.
  • FIG. 2 is a schematic flowchart of an embodiment of an overcurrent protection method for a display panel of this application
  • the overcurrent protection method of the display panel includes:
  • Step S1 when receiving the first clock signal, calculate the current input by the level shifter in the first preset time in the first clock signal;
  • the first preset time is the time that the level shifter in the first clock signal lasts before the normal operating current is input, that is, the time that the level shifter input current is in a steady state, expressed as T0, for example,
  • T0 the time that the level shifter input current is in a steady state
  • the duration of the high level input by the level shifter in a clock signal period is 14.8us
  • the duration before the input current is the normal operating current is 9us
  • the first preset time T0 is 9us, such as As shown in Fig. 3, the current input by the level shifter in T0 time is detected by the timing controller, and the current can be the average current in T0 time.
  • Step S2 Determine whether the current input by the level shifter is greater than the first preset current within the first preset time
  • the first preset current is preset under a conventional circuit based on the results of multiple experiments as a basis for determining whether it is necessary to control the level shifter to stop working within T0 time. After obtaining the average current input by the level shifter in T0 time, the average current input by the level shifter in T0 time is compared with the first preset current to obtain a comparison result.
  • Step S3 When the current input by the level shifter is greater than the first preset current within a first preset time, control the level shifter to stop running.
  • the timing controller When the timing controller detects that the average current input by the level shifter is greater than the first preset current in T0, it means that the current input by the level shifter is too large at this time, which will cause the chip to be damaged.
  • the chip may be powered.
  • a level shifter chip in which the level shifter is electrically connected to the gate drive circuit. At this time, the timing controller outputs a corresponding control signal, for example, a high-level control signal to the level shifter, to control the level shifter to stop working, thereby avoiding damage to the chip.
  • the level shifter when the first clock signal is received, it is determined whether the current input by the level shifter is greater than the first preset current within the first preset time, and the level is within the first preset time.
  • the level converter is controlled to stop running, to prevent the chip from being damaged due to excessive current input by the level converter, and to avoid excessive current due to excessive current A situation that caused an accidental power failure.
  • FIG. 4 is a schematic flowchart of another embodiment of an overcurrent protection method for a display panel of this application.
  • step S2 it further includes:
  • Step S4 When the current input by the level shifter is less than the first preset current within the first preset time, calculate the current input by the level shifter during the second preset time;
  • the second preset time is the accumulation of the effective time in the multiple clock signals.
  • the effective time represents the time during which the level converter inputs the normal operating current in each clock signal, that is, the current input by the level converter is at The duration of the steady state. For example, in a clock signal period, the duration of the high level input by the level shifter is 14.8us, and the duration of the normal operating current input by the level shifter is 5.8us, then the effective time is 5.8us.
  • the effective time in the first clock signal is represented by T1
  • the effective time in the second clock signal is represented by T2
  • Tnth clock signal is represented by Tn, where T1 to Tn
  • the total time is taken as the second preset time.
  • the current input by the level converter within the first preset time is less than the first preset current
  • the current input by the level converter within the second preset time is calculated by the timing controller, that is, T1, T2...Tn are calculated
  • the effective current input by the level shifter in each effective time calculates the average current input by the level shifter within the second preset time according to the effective current input by the level shifter in each clock signal.
  • step S4 includes:
  • Step S41 calculating the effective current input by the level shifter within the effective time of each clock signal
  • the effective current can be for each effective time The average current within.
  • Step S42 Calculate the average current input by the level shifter within the second preset time according to the effective current input by the level shifter during the effective time of each clock signal.
  • step S42 After obtaining the effective current input by the level shifter in the effective time of each clock signal, the average current input by the level shifter in the second preset time is calculated by each effective current. Specifically, referring to FIG. 6, step S42 includes:
  • Step S421 obtaining a preset number of times corresponding to the effective current input by the level shifter according to the effective current input by the level shifter within the effective time of each clock signal;
  • the preset number of times represents the number of times that the instantaneous current input by the level shifter is greater than the current threshold Iocp within the effective time corresponding to the effective current.
  • the current threshold can be set according to the maximum current that the load can withstand.
  • Step S422 accumulating each preset number of times in sequence to obtain a total preset number of times m;
  • step S42 includes:
  • Step S424 accumulating the effective current input by the level shifter in the effective time of each clock signal in sequence to obtain the sum of the effective currents;
  • the current input by the level shifter within the second preset time can also be calculated by first summing the effective current input by the level shifter within the effective time of each clock signal, that is, the effective current of each clock signal The current is accumulated in sequence to obtain the sum of the effective current within the second preset time.
  • Step S425, calculating the ratio of the sum of each effective current and the number of clock signals to obtain the average current input by the level shifter within the second preset time;
  • the ratio of the sum of the obtained effective current and the number of clock signals is calculated, for example, the effective current of the first clock signal is I1, and the effective of the second clock signal is The current is I2, and so on.
  • the effective current of the nth clock signal is In. I1+I2+, In are obtained as the sum of the effective current in the second preset time, Itotal, and then the ratio of Itotal and n is calculated to obtain the first 2.
  • Step S5 Determine whether the current input by the level shifter is greater than the second preset current within the second preset time
  • the second preset current is preset under a conventional circuit based on the results of multiple experiments as a basis for determining whether it is necessary to control the level shifter to stop working within the second preset time.
  • the current is less than the first preset current.
  • Step S6 When the current input by the level shifter is greater than the second preset current within a second preset time, control the level shifter to stop running.
  • the timing controller When the average current input by the level shifter is greater than the second preset current in the second preset time, it means that the chip may be in danger of being damaged at this time.
  • the timing controller outputs the corresponding control signal, for example, high power Level control signal to level shifter to control the level shifter to stop working, so as to avoid damage to the chip.
  • the control signal output by the timing controller is used to control the level shifter to stop running, So as to avoid damage to the chip due to excessive current.
  • the present application also provides a display device, including: a memory, a processor, and an overcurrent protection program of a display panel stored on the memory and capable of running on the processor, the overcurrent protection program of the display panel is used by the processor The steps of the overcurrent protection method of the display panel as described above are implemented during operation.
  • the display device further includes a display panel and a circuit board, the display panel is connected to the circuit board, and the overcurrent protection program of the display panel is arranged on the circuit board.
  • the display device in this embodiment may be a display device with a display panel, such as a television, a tablet computer, and a mobile phone.
  • the display panel in this embodiment may be any of the following: liquid crystal display panel, OLED display panel, QLED display panel, twisted nematic (Twisted Nematic (TN) or Super Twisted Nematic (STN) type, In-Plane Switching (IPS) type, Vertical Alignment (VA) type, curved type panel, or other display panel.

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Abstract

一种显示面板的过流保护方法及显示装置，显示面板的过流保护方法包括以下步骤：在接收到首个时钟信号时，计算首个时钟信号中的第一预设时间内电平转换器输入的电流（步骤S1）；判断在第一预设时间内电平转换器输入的电流是否大于第一预设电流（步骤S2）；在第一预设时间内电平转换器输入的电流大于第一预设电流时，控制电平转换器停止运行（步骤S3）。

Description

显示面板的过流保护方法及显示装置
相关申请
本申请要求2018年12月25日申请的，申请号201811598783.2，名称为“显示面板的过流保护方法及显示装置”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板的过流保护方法及显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
目前，显示面板中的栅极驱动电路(Gate Driver on Array，GOA)的过流保护机制，是在侦测到开机瞬间电平转换器的输入电流过大时，将栅极驱动电路的电源切断；但是，若外部干扰导致电平转换器的输入电流瞬时变大，该过流保护机制会被误触发，导致显示装置黑屏，若在侦测到开机瞬间电平转换器输入的电流过大，但是不启动过流保护机制的话，若电平转换器输入的电流足够大，会导致芯片被损坏。
发明内容
本申请实施例通过提供一种显示面板的过流保护方法及显示装置，旨在实现避免由于电平转换器输入的电流过大而导致芯片被损坏的目的。
为实现上述目的，本申请提供一种显示面板的过流保护方法，该显示面板的过流保护方法包括以下步骤：
在接收到首个时钟信号时，计算首个时钟信号中的第一预设时间内电平转换器输入的电流；
判断在第一预设时间内所述电平转换器输入的电流是否大于第一预设电流；
在第一预设时间内所述电平转换器输入的电流大于所述第一预设电流时，控制所述电平转换器停止运行。
为实现上述目的，本申请还提供一种显示面板的过流保护方法，应用于时序控制器内，所述显示面板的过流保护方法包括以下步骤：
在接收到首个时钟信号时，计算首个时钟信号中的第一预设时间内电平转换器输入的平均电流；
判断在第一预设时间内所述电平转换器输入的平均电流是否大于第一预设电流；
在第一预设时间内所述电平转换器输入的平均电流大于所述第一预设电流时，控制所述电平转换器停止运行。
为实现上述目的，本申请还提供一种显示装置，包括存储器、处理器及存储在存储器上并可在处理器上运行的显示面板的过流保护程序，所述处理器执行所述显示面板的过流保护程序时实现如下步骤：
在接收到首个时钟信号时，计算首个时钟信号中的第一预设时间内电平转换器输入的电流；
判断在第一预设时间内所述电平转换器输入的电流是否大于第一预设电流；
在第一预设时间内所述电平转换器输入的电流大于所述第一预设电流时，控制所述电平转换器停止运行。
本申请的技术方案，在接收到首个时钟信号时，判断在第一预设时间内电平转换器输入的电流是否大于第一预设电流，在第一预设时间内所述电平转换器输入的电流大于所述第一预设电流时，控制电平转换器停止运行，避免由于电平转换器输入的电流过大而导致芯片被损坏。
附图说明
图1为本申请实施例方案涉及的硬件运行环境的电子设备结构示意图；
图2为本申请显示面板的过流保护方法一实施例的流程示意图；
图3为本申请一实施例中第一预设时间及有效时间的分布示意图；
图4为本申请显示面板的过流保护方法另一实施例的流程示意图；
图5为本申请一实施例中步骤S4的一细化流程示意图；
图6为本申请一实施例中步骤S42的一细化流程示意图；
图7为本申请一实施例中电流与预设次数的对应关系示意图；
图8为本申请一实施例中步骤S42的另一细化流程示意图。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
本申请实施例的主要解决方案是：在接收到首个时钟信号时，计算首个时钟信号中的第一预设时间内电平转换器输入的电流；判断在第一预设时间内所述电平转换器输入的电流是否大于第一预设电流；在第一预设时间内所述电平转换器输入的电流大于所述第一预设电流时，控制所述电平转换器停止运行。
本申请的技术方案，在侦测到首个时钟信号中的第一预设时间内电平转换器输入的电流大于第一预设电流时，控制电平转换器停止运行，以避免由于电平转换器输入的电流过大而导致芯片被损坏。
作为一种实施方案，显示装置可以如图1所示。
本申请实施例方案涉及的是显示装置，显示装置包括：处理器1001，例如CPU，通信总线1002，存储器1003。其中，通信总线1002用于实现这些组件之间的连接通信。
存储器1003可以是高速RAM存储器，也可以是稳定的存储器（non-volatilememory），例如磁盘存储器。如图1所示，作为一种计算机存储介质的存储器1003中可以包括显示面板的过流保护程序；而处理器1001可以用于调用存储器1003中存储的显示面板的过流保护程序，并执行以下操作：
在接收到首个时钟信号时，计算首个时钟信号中的第一预设时间内电平转换器输入的电流；
判断在第一预设时间内所述电平转换器输入的电流是否大于第一预设电流；
在第一预设时间内所述电平转换器输入的电流大于所述第一预设电流时，控制所述电平转换器停止运行。
可选的，处理器1001可以用于调用存储器1003中存储的显示面板的过流保护程序，并执行以下操作：
在第一预设时间内所述电平转换器输入的电流小于所述第一预设电流时，计算在第二预设时间内所述电平转换器输入的电流；
判断在第二预设时间内所述电平转换器输入的电流是否大于第二预设电流；
在第二预设时间内所述电平转换器输入的电流大于所述第二预设电流时，控制所述电平转换器停止运行。
可选的，处理器1001可以用于调用存储器1003中存储的显示面板的过流保护程序，并执行以下操作：
计算各个时钟信号的有效时间内所述电平转换器输入的有效电流；
根据每一时钟信号的有效时间内所述电平转换器输入的有效电流计算在第二预设时间内所述电平转换器输入的平均电流。
可选的，处理器1001可以用于调用存储器1003中存储的显示面板的过流保护程序，并执行以下操作：
根据每一时钟信号的有效时间内所述电平转换器输入的有效电流获得与所述电平转换器输入的有效电流对应的预设次数；
将各个预设次数依次累加，获得总的预设次数m；
根据平均电流计算公式I=m*Iocp/10n计算在第二预设时间内所述电平转换器输入的平均电流，其中，所述Iocp为电流阈值，所述n为时钟信号的数量。
可选的，处理器1001可以用于调用存储器1003中存储的显示面板的过流保护程序，并执行以下操作：
将每一时钟信号的有效时间内所述电平转换器输入的有效电流依次累加，获得各个有效电流之和；
将各个有效电流之和与时钟信号的数量进行比值计算，获得在第二预设时间内所述电平转换器输入的平均电流。
可选的，处理器1001可以用于调用存储器1003中存储的显示面板的过流保护程序，并执行以下操作：
所述第一预设电流大于所述第二预设电流。
可选的，处理器1001可以用于调用存储器1003中存储的显示面板的过流保护程序，并执行以下操作：
所述第二预设时间为各个时钟信号的有效时间的累加。
可选的，处理器1001可以用于调用存储器1003中存储的显示面板的过流保护程序，并执行以下操作：
所述有效时间为电平转换器在每一时钟信号内输入正常工作电流的时间，所述有效电流为电平转换器在每一所述有效时间内输入的平均电流。
可选的，处理器1001可以用于调用存储器1003中存储的显示面板的过流保护程序，并执行以下操作：
在接收到首个时钟信号时，计算首个时钟信号中的第一预设时间内电平转换器输入的平均电流；
判断在第一预设时间内所述电平转换器输入的平均电流是否大于第一预设电流；
在第一预设时间内所述电平转换器输入的平均电流大于所述第一预设电流时，控制所述电平转换器停止运行。
图2为本申请显示面板的过流保护方法一实施例的流程示意图；
该显示面板的过流保护方法包括：
步骤S1，在接收到首个时钟信号时，计算首个时钟信号中的第一预设时间内电平转换器输入的电流；
所述第一预设时间，为首个时钟信号内电平转换器输入正常工作电流之前所持续的时间，即电平转换器输入的电流处于平稳状态之前所持续的时间，以T0表示，例如，在一个时钟信号周期内电平转换器输入的高电平的持续时间为14.8us，在其输入的电流为正常工作电流之前所持续的时间为9us，则第一预设时间T0为9us，如图3所示，通过时序控制器侦测在T0时间内电平转换器输入的电流，该电流可以为T0时间内的平均电流。
步骤S2，判断在第一预设时间内所述电平转换器输入的电流是否大于第一预设电流；
所述第一预设电流，是在常规电路下，根据多次实验结果而预设置的，作为判断在T0时间内是否需要控制电平转换器停止工作的依据。在获得T0时间内电平转换器输入的平均电流后，将T0时间内电平转换器输入的平均电流与第一预设电流比较，获得比较结果。
步骤S3，在第一预设时间内所述电平转换器输入的电流大于所述第一预设电流时，控制所述电平转换器停止运行。
在时序控制器侦测到T0时间内电平转换器输入的平均电流大于第一预设电流时，说明此时电平转换器输入的电流过大，会导致芯片被损坏，该芯片可以为电平转换器芯片，其中，电平转换器与栅极驱动电路电连接。此时，时序控制器输出对应的控制信号，例如，高电平的控制信号至电平转换器，以控制电平转换器停止工作，从而避免芯片被损坏。如此设置，通过求首个时钟信号的T0时间内电平转换器输入的平均电流大小，来判断是否需要控制电平转换器停止工作，其判断结果更为准确，可避免由于误断电而导致显示装置黑屏。
本实施例的技术方案，在接收到首个时钟信号时，判断在第一预设时间内电平转换器输入的电流是否大于第一预设电流，在第一预设时间内所述电平转换器输入的电流大于所述第一预设电流时，控制电平转换器停止运行，避免由于电平转换器输入的电流过大而导致芯片被损坏，还能避免由于瞬间的电流过大而导致误断电的情况出现。
图4为本申请显示面板的过流保护方法另一实施例的流程示意图；
基于上述实施例，所述步骤S2之后，还包括：
步骤S4，在第一预设时间内所述电平转换器输入的电流小于所述第一预设电流时，计算在第二预设时间内所述电平转换器输入的电流；
所述第二预设时间，为多个时钟信号中的有效时间的累加，该有效时间表示在每个时钟信号内电平转换器输入正常工作电流的时间，即电平转换器输入的电流处于平稳状态所持续的时间。例如，在一个时钟信号周期内，电平转换器输入的高电平的持续时间为14.8us，而电平转换器输入正常工作电流的持续时间为5.8us，则该有效时间为5.8us。参照图3，第一个时钟信号内的有效时间以T1表示，第二个时钟信号内的有效时间以T2表示，依次类推，第n个时钟信号内的有效时间以Tn表示，将T1至Tn的总时间作为第二预设时间。在第一预设时间内电平转换器输入的电流小于第一预设电流时，通过时序控制器计算第二预设时间内电平转换器输入的电流，也就是计算T1、T2……Tn各个有效时间内电平转换器输入的有效电流，根据每个时钟信号内电平转换器输入的有效电流计算在第二预设时间内电平转换器输入的平均电流。
具体的，参照图5，步骤S4包括：
步骤S41，计算各个时钟信号的有效时间内所述电平转换器输入的有效电流；
通过时序控制器计算每一个时钟信号的有效时间内电平转换器输入的有效电流，即计算T1、T2……Tn时间内电平转换器输入的有效电流，该有效电流可以为每个有效时间内的平均电流。
步骤S42，根据每一时钟信号的有效时间内所述电平转换器输入的有效电流计算在第二预设时间内所述电平转换器输入的平均电流。
在获得每个时钟信号的有效时间内电平转换器输入的有效电流后，通过各个有效电流计算第二预设时间内电平转换器输入的平均电流。具体的，参照图6，步骤S42包括：
步骤S421，根据每一时钟信号的有效时间内所述电平转换器输入的有效电流获得与所述电平转换器输入的有效电流对应的预设次数；
所述预设次数表示该有效电流所对应的有效时间内，电平转换器输入的瞬间电流大于电流阈值Iocp的次数，该电流阈值可以根据负载所能承受的最大电流设置。在获得每个时钟信号的有效电流后，通过预先设置的电流与预设次数的关系，获得每个有效电流所对应的预设次数。如图7所示，通过判断每个时钟信号所对应的有效电流所属的范围，根据电流与预设次数的一一对应关系，从而得到每个时钟信号的有效电流所对应的预设次数。
步骤S422，将各个预设次数依次累加，获得总的预设次数m；
将每个有效电流所对应的预设次数依次累加，获得一帧时间内的总的预设次数，将总的预设次数以m表示，例如，若第一个时钟信号的有效电流对应的预设次数为1，第二个时钟信号的有效电流对应的预设次数为2，依次类推，第n个时钟信号的有效电流所对应的预设次数为a，则m=1+2+……+a。
步骤S423，根据平均电流计算公式I=m*Iocp/10n计算在第二预设时间内所述电平转换器输入的平均电流；
在获得第二预设时间内的总预设次数m之后，利用公式I=m*Iocp/10n计算在第二预设时间内的平均电流，所述n为时钟信号的数量。
可选的，参照图8，步骤S42包括：
步骤S424，将每一时钟信号的有效时间内所述电平转换器输入的有效电流依次累加，获得各个有效电流之和；
在一实施例中，第二预设时间内电平转换器输入的电流还可以通过先计算每个时钟信号的有效时间内电平转换器输入的有效电流之和，即将每个时钟信号的有效电流依次累加，获得第二预设时间内的有效电流之和。
步骤S425，将各个有效电流之和与时钟信号的数量进行比值计算，获得在第二预设时间内所述电平转换器输入的平均电流；
在获得各个时钟信号的有效电流之和后，将所获得的有效电流之和与时钟信号的个数进行比值计算，例如，第一个时钟信号的有效电流为I1，第二个时钟信号的有效电流为I2，依次类推，第n个时钟信号的有效电流为In，将I1+I2+、、In获得第二预设时间内的有效电流之和Itotal，再将Itotal与n进行比值计算，获得第二预设时间内的平均电流。
步骤S5，判断在第二预设时间内所述电平转换器输入的电流是否大于第二预设电流；
所述第二预设电流，是在常规电路下，根据多次实验结果而预设置的，作为判断在第二预设时间内是否需要控制电平转换器停止工作的依据，该第二预设电流小于第一预设电流。在获得第二预设时间内电平转换器输入的平均电流后，将所获得的平均电流与第二预设电流进行比较，获得比较结果。
步骤S6，在第二预设时间内所述电平转换器输入的电流大于所述第二预设电流时，控制所述电平转换器停止运行。
在第二预设时间内电平转换器输入的平均电流大于第二预设电流时，说明此时芯片可能存在被损坏的危险，此时，时序控制器输出对应的控制信号，例如，高电平的控制信号至电平转换器，以控制电平转换器停止工作，从而避免芯片被损坏。通过计算第二预设时间内电平转换器输入的平均电流以判断在稳定状态下电平转换器输入的电流是否满足所需的电流大小，从而判断是否需要控制电平转换器停止工作，如此设置，能够提高对是否需要切断栅极驱动电路的电源的判断的准确性。
本实施例的技术方案，在检测到第二预设时间内电平转换器输入的平均电流大于第二预设电流时，通过时序控制器输出的控制信号，以控制电平转换器停止运行，从而避免由于电流过大而导致芯片被损坏。
本申请还提供一种显示装置，包括：存储器、处理器及存储在存储器上并可在处理器上运行的显示面板的过流保护程序，所述显示面板的过流保护程序被所述处理器运行时实现如上所述的显示面板的过流保护方法的步骤。该显示装置还包括显示面板及电路板，所述显示面板与所述电路板连接，所述显示面板的过流保护程序布置在所述电路板上。
本实施例的显示装置可以是电视机、平板电脑、手机等具有显示面板的显示装置。本实施例的显示面板可以为以下任一种：液晶显示面板、OLED显示面板、QLED显示面板、扭曲向列(Twisted Nematic，TN)或超扭曲向列(Super Twisted Nematic，STN)型，平面转换(In-Plane Switching，IPS)型、垂直配向(Vertical Alignment，VA)型、曲面型面板、或其他显示面板。
以上所述仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是在本申请的发明构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (17)

  1. 一种显示面板的过流保护方法，其中，所述显示面板的过流保护方法包括以下步骤：
    在接收到首个时钟信号时，计算首个时钟信号中的第一预设时间内电平转换器输入的电流；
    判断在第一预设时间内所述电平转换器输入的电流是否大于第一预设电流；以及
    在第一预设时间内所述电平转换器输入的电流大于所述第一预设电流时，控制所述电平转换器停止运行。
  2. 如权利要求1所述的显示面板的过流保护方法，其中，所述判断在第一预设时间内所述电平转换器输入的电流是否大于第一预设电流的步骤之后，还包括；
    在第一预设时间内所述电平转换器输入的电流小于所述第一预设电流时，计算在第二预设时间内所述电平转换器输入的电流；
    判断在第二预设时间内所述电平转换器输入的电流是否大于第二预设电流；以及
    在第二预设时间内所述电平转换器输入的电流大于所述第二预设电流时，控制所述电平转换器停止运行。
  3. 如权利要求2所述的显示面板的过流保护方法，其中，所述在第一预设时间内所述电平转换器输入的电流小于所述第一预设电流时，计算在第二预设时间内所述电平转换器输入的电流的步骤包括：
    计算各个时钟信号的有效时间内所述电平转换器输入的有效电流；以及
    根据每一时钟信号的有效时间内所述电平转换器输入的有效电流计算在第二预设时间内所述电平转换器输入的平均电流。
  4. 如权利要求3所述的显示面板的过流保护方法，其中，所述根据每一时钟信号的有效时间内所述电平转换器输入的有效电流计算在第二预设时间内所述电平转换器输入的平均电流的步骤包括：
    根据每一时钟信号的有效时间内所述电平转换器输入的有效电流获得与所述电平转换器输入的有效电流对应的预设次数；
    将各个预设次数依次累加，获得总的预设次数m；以及
    根据平均电流计算公式I=m*Iocp/10n计算在第二预设时间内所述电平转换器输入的平均电流，其中，所述Iocp为电流阈值，所述n为时钟信号的数量。
  5. 如权利要求4所述的显示面板的过流保护方法，其中，所述预设次数，为每一时钟信号的有效时间内，所述电平转换器输入的瞬间电流大于电流阈值的次数。
  6. 如权利要求3所述的显示面板的过流保护方法，其中，所述根据每一所述时钟信号的有效时间内所述电平转换器输入的平均电流计算在第二预设时间内所述电平转换器输入的平均电流的步骤包括：
    将每一时钟信号的有效时间内所述电平转换器输入的有效电流依次累加，获得各个有效电流之和；以及
    将各个有效电流之和与时钟信号的数量进行比值计算，获得在第二预设时间内所述电平转换器输入的平均电流。
  7. 如权利要求2所述的显示面板的过流保护方法，其中，所述第一预设电流大于所述第二预设电流。
  8. 如权利要求4所述的显示面板的过流保护方法，其中，所述第二预设时间为各个时钟信号的有效时间的累加。
  9. 如权利要求4所述的显示面板的过流保护方法，其中，所述有效时间为电平转换器在每一时钟信号内输入正常工作电流的时间，所述有效电流为电平转换器在每一所述有效时间内输入的平均电流。
  10. 如权利要求1所述的显示面板的过流保护方法，其中，所述第一预设时间，为首个时钟信号内所述电平转换器输入正常工作电流之前所持续的时间。
  11. 一种显示面板的过流保护方法，应用于时序控制器内，其中，所述显示面板的过流保护方法包括以下步骤：
    在接收到首个时钟信号时，计算首个时钟信号中的第一预设时间内电平转换器输入的平均电流；
    判断在第一预设时间内所述电平转换器输入的平均电流是否大于第一预设电流；以及
    在第一预设时间内所述电平转换器输入的平均电流大于所述第一预设电流时，控制所述电平转换器停止运行。
  12. 一种显示装置，其中，包括存储器、处理器及存储在存储器上并可在处理器上运行的显示面板的过流保护程序，所述处理器执行所述显示面板的过流保护程序时实现如下步骤：
    在接收到首个时钟信号时，计算首个时钟信号中的第一预设时间内电平转换器输入的电流；
    判断在第一预设时间内所述电平转换器输入的电流是否大于第一预设电流；以及
    在第一预设时间内所述电平转换器输入的电流大于所述第一预设电流时，控制所述电平转换器停止运行。
  13. 如权利要求12所述的显示装置，其中，所述判断在第一预设时间内所述电平转换器输入的电流是否大于第一预设电流的步骤之后，还包括；
    在第一预设时间内所述电平转换器输入的电流小于所述第一预设电流时，计算在第二预设时间内所述电平转换器输入的电流；
    判断在第二预设时间内所述电平转换器输入的电流是否大于第二预设电流；以及
    在第二预设时间内所述电平转换器输入的电流大于所述第二预设电流时，控制所述电平转换器停止运行。
  14. 如权利要求13所述的显示装置，其中，所述在第一预设时间内所述电平转换器输入的电流小于所述第一预设电流时，计算在第二预设时间内所述电平转换器输入的电流的步骤包括：
    计算各个时钟信号的有效时间内所述电平转换器输入的有效电流；以及
    根据每一时钟信号的有效时间内所述电平转换器输入的有效电流计算在第二预设时间内所述电平转换器输入的平均电流。
  15. 如权利要求14所述的显示装置，其中，所述根据每一时钟信号的有效时间内所述电平转换器输入的有效电流计算在第二预设时间内所述电平转换器输入的平均电流的步骤包括：
    根据每一时钟信号的有效时间内所述电平转换器输入的有效电流获得与所述电平转换器输入的有效电流对应的预设次数；
    将各个预设次数依次累加，获得总的预设次数m；以及
    根据平均电流计算公式I=m*Iocp/10n计算在第二预设时间内所述电平转换器输入的平均电流，其中，所述Iocp为电流阈值，所述n为时钟信号的数量。
  16. 如权利要求12所述的显示装置，其中，所述显示装置还包括显示面板以及电路板，所述显示面板与所述电路板连接，所述显示面板的过流保护程序布置在所述电路板上。
  17. 如权利要求16所述的显示装置，其中，所述显示装置为电视机，所述显示面板为液晶显示面板。
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