WO2020134429A1 - 同质集成红外光子芯片及其制备方法 - Google Patents

同质集成红外光子芯片及其制备方法 Download PDF

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WO2020134429A1
WO2020134429A1 PCT/CN2019/112932 CN2019112932W WO2020134429A1 WO 2020134429 A1 WO2020134429 A1 WO 2020134429A1 CN 2019112932 W CN2019112932 W CN 2019112932W WO 2020134429 A1 WO2020134429 A1 WO 2020134429A1
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layer
waveguide
contact layer
iii
lower contact
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PCT/CN2019/112932
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English (en)
French (fr)
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王永进
倪曙煜
李欣
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南京邮电大学
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Priority to JP2021537056A priority Critical patent/JP7182814B2/ja
Publication of WO2020134429A1 publication Critical patent/WO2020134429A1/zh
Priority to US17/360,942 priority patent/US20210325601A1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/102—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type for infrared and ultraviolet radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/12004—Combinations of two or more optical elements
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13—Integrated optical circuits characterised by the manufacturing method
    • G02B6/132—Integrated optical circuits characterised by the manufacturing method by deposition of thin films
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13—Integrated optical circuits characterised by the manufacturing method
    • G02B6/136—Integrated optical circuits characterised by the manufacturing method by etching
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/0304—Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L31/03046—Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds including ternary or quaternary compounds, e.g. GaAlAs, InGaAs, InGaAsP
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    • H01L31/035281—Shape of the body
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    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0392—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
    • H01L31/1844—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP comprising ternary or quaternary compounds, e.g. Ga Al As, In Ga As P
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
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    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
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    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
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    • H01L33/58—Optical field-shaping elements
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    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12083—Constructional arrangements
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    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer

Definitions

  • the invention relates to the technical field of information materials and devices, in particular to a homogeneous integrated infrared photonic chip and a preparation method thereof.
  • Infrared light-emitting diode is a diode that can emit infrared rays, which is used in the fields of safety monitoring, wearable devices, infrared communication, infrared remote control devices, light sources for sensors and night lighting, especially in the field of gas detection.
  • infrared light emitting diodes or infrared receiving diodes currently there are only independent infrared light emitting diodes or infrared receiving diodes on the market. Therefore, when manufacturing infrared optical communication devices, it is necessary to separately manufacture diode devices and waveguide devices on different materials, that is, the infrared optical communication devices in the prior art are all heterogeneous integrated devices, which greatly increases the infrared optical communication device. Manufacturing difficulty and manufacturing cost.
  • the invention provides a homogeneous integrated infrared photonic chip and a preparation method thereof, which are used to solve the problems of high difficulty and high manufacturing cost of existing infrared optical communication devices.
  • the present invention provides a homogeneous integrated infrared photonic chip, including a substrate layer, and a device structure and a waveguide structure both located on the surface of the substrate layer;
  • the device structure includes a lower contact layer, a quantum well layer, and an upper contact layer sequentially stacked in a direction perpendicular to the substrate layer, and the substrate layer, the lower contact layer, the quantum well layer, and the The materials of the upper contact layer are all III-V materials;
  • the waveguide structure includes a waveguide layer made of III-V group materials, and the waveguide layer and the lower contact layer are arranged in the same layer.
  • it further includes a buffer layer on the surface of the substrate layer and made of III-V materials, and both the lower contact layer and the waveguide layer are on the surface of the buffer layer.
  • the lower contact layer has a step shape
  • the stepped lower contact layer includes a lower mesa and an upper mesa protruding on the surface of the lower mesa; the quantum well layer and the upper contact layer are sequentially stacked On the upper mesa; the material of the waveguide layer and the lower contact layer are the same.
  • the substrate layer is an InP substrate layer
  • the lower contact layer and the waveguide layer are both n-InP layers
  • the upper contact layer is a p-InGaAs layer
  • the device structure includes a quantum well layer, a p-InP spacer layer, an etch blocking layer, a p-InP cladding layer, and a p that are sequentially stacked on the upper mesa surface along the direction of the substrate layer toward the device structure -PQ gap buffer layer, p-InGaAs layer.
  • the surface of the substrate layer has two device structures and a waveguide isolation groove between the two device structures; the waveguide structure is located at the bottom of the waveguide isolation groove for Optical signals are transmitted between device structures.
  • the present invention also provides a method for preparing a homogeneous integrated infrared photonic chip, including the following steps:
  • the device structure includes a lower contact layer, a quantum well layer, and an upper contact layer sequentially stacked in a direction perpendicular to the substrate layer, and the lower contact layer,
  • the materials of the quantum well layer and the upper contact layer are III-V materials;
  • the waveguide structure includes a waveguide layer made of III-V materials, the waveguide layer is the same as the lower contact layer Layer settings.
  • forming the device structure and the waveguide structure before the surface of the substrate layer further includes the following steps:
  • a first III-V material is deposited on the surface of the substrate layer to form a buffer layer.
  • the specific steps of forming the device structure and the waveguide structure on the surface of the substrate layer include:
  • the waveguide structure includes the waveguide layer made of part of the second group III-V material.
  • the specific steps of etching the stacked structure include:
  • the second III-V material layer includes a lower mesa and an upper mesa protruding from the lower mesa, the quantum well layer Sequentially stacked on the upper mesa with the upper contact layer, the upper mesa and the lower mesa located in the device area constitute the lower contact layer, and the lower mesa extends to the waveguide area to form the waveguide layer .
  • the surface of the substrate layer has two device structures and a waveguide isolation groove between the two device structures; the waveguide structure is located at the bottom of the waveguide isolation groove for Optical signals are transmitted between device structures.
  • the homogeneous integrated infrared photonic chip and its preparation method provided by the present invention by integrating the waveguide structure and the device structure on the substrate composed of the III-V group material, also using the III-V group material to manufacture the waveguide structure and the device
  • the device structure is described, and the lower contact layer in the device structure and the waveguide layer in the waveguide structure are arranged in the same layer, so as to achieve the purpose of homogenous integration of the waveguide structure and the device structure, and thereby realize the invisible light in the infrared band On-chip transmission reduces the manufacturing difficulty and manufacturing cost of infrared optical communication devices.
  • FIG. 1A is a schematic structural plan view of a homogeneous integrated infrared photonic chip in a specific embodiment of the present invention
  • FIG. 1B is a schematic structural plan view of another homogeneous integrated infrared photonic chip in a specific embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view of FIG. 1A along the X-axis direction;
  • Figure 3 is a schematic cross-sectional view of Figure 1A along the Y-axis direction;
  • FIG. 4 is a schematic cross-sectional view of FIG. 1B along the Y-axis direction;
  • FIG. 5 is a flowchart of a method for preparing a homogeneous integrated infrared photonic chip in a specific embodiment of the present invention
  • 6A-6L are schematic cross-sectional views of main processes in the process of manufacturing a homogeneous integrated infrared photonic chip according to a specific embodiment of the present invention.
  • FIG. 1A is a top schematic structural view of a homogeneous integrated infrared photonic chip in a specific embodiment of the present invention
  • FIG. 1B is another homogeneous integrated in the specific embodiment of the present invention.
  • the top schematic view of the infrared photonic chip FIG. 2 is a schematic cross-sectional view along the X-axis direction of FIG. 1A
  • FIG. 3 is a cross-sectional schematic view along the Y-axis direction of FIG. 1A
  • FIG. 4 is a Y-axis along the FIG. 1B A schematic cross-section of the direction.
  • the homogeneous integrated infrared photonic chip provided in this embodiment includes a substrate layer 20 and a device structure and a waveguide structure both located on the surface of the substrate layer 20;
  • the device structure includes a lower contact layer 22, a quantum well layer 23, and an upper contact layer 13 sequentially stacked in a direction perpendicular to the substrate layer 20, and the substrate layer 20, the lower contact layer 22, the The materials of the quantum well layer 23 and the upper contact layer 13 are all III-V materials;
  • the waveguide structure includes a waveguide layer 10 made of III-V materials, and the waveguide layer 10 and the lower contact layer 22 are arranged in the same layer.
  • the device structure and the waveguide structure are integrated on the surface of the substrate layer 20.
  • the lower contact layer 22, the The quantum well layer 23 and the upper contact layer 13 are sequentially stacked in a direction perpendicular to the substrate layer 20; in a cross-sectional view along the X-axis direction in FIG. 1, the device structure and the waveguide of the waveguide structure
  • the layers 10 are arranged in a direction parallel to the substrate layer 20, and infrared light signals are transmitted between the device structure and the waveguide structure.
  • This specific embodiment realizes the transmission of invisible light in the infrared band within the chip, reducing the manufacturing difficulty and manufacturing cost of the infrared optical communication device; at the same time, the homogeneous integrated structure improves the utilization efficiency of the on-chip light-emitting diode light source, and is oriented for development Photonic devices for optical communication and optical sensing provide new directions.
  • the homogeneous integrated infrared photonic chip further includes a buffer layer 21 located on the surface of the substrate layer 20 and made of III-V materials, the lower contact layer 22 and the waveguide layer 10 are both located The surface of the buffer layer 21.
  • the buffer layer 21 is epitaxially grown on the surface of the substrate layer 20.
  • the material of the buffer layer 21 and the material of the substrate layer 20 may be the same or different. Stress between the device structures.
  • the waveguide layer 10 and a portion of the buffer layer 21 located in a region directly below the waveguide layer 10 together constitute the waveguide structure.
  • the lower contact layer 22 has a stepped shape, and the stepped lower contact layer 22 includes a lower mesa and an upper mesa projecting on the surface of the lower mesa; the quantum well layer 23 and the upper contact layer 13 is sequentially stacked on the upper mesa; the material of the waveguide layer 10 and the lower contact layer 22 is the same.
  • the substrate layer 20 is an InP substrate layer
  • the lower contact layer 22 and the waveguide layer 10 are both n-InP layers
  • the upper contact layer 13 is a p-InGaAs layer
  • the device structure includes a quantum well layer 23, a p-InP spacer layer 24, an etch blocking layer 25, and a p-InP overlay that are sequentially stacked on the surface of the upper mesa along the direction of the substrate layer toward the device structure Layer 26, p-PQ gap buffer layer 27, p-InGaAs layer.
  • PQ in the p-PQ gap buffer layer 27 represents a compound composed of four elements of In, P, Ga, and As.
  • the device structure can generate light with a wavelength of 1550 nm, which belongs to invisible light in the infrared band.
  • those skilled in the art can also select other III-V materials to manufacture the device structure as long as they can generate infrared light signals.
  • the buffer layer 21 may be an InP layer or a GaAs layer.
  • the surface of the buffer layer 21 includes a device region having the device structure and a waveguide region having the waveguide layer 10.
  • the n-InP layer located in the device region constitutes the lower contact layer 22, and the lower contact layer 22 has a stepped shape, the quantum well layer 23, the p-InP spacer layer 24, the inscribed An etch stop layer 25, the p-InP cladding layer 26, the p-PQ gap buffer layer 27, and the p-InGaAs layer are sequentially stacked on the upper mesa in a direction perpendicular to the substrate layer 20.
  • the n-InP layer located in the waveguide region constitutes the waveguide layer 10.
  • the thickness of the waveguide layer 10 and the lower mesa are the same.
  • FIGS. 1A and 3 there is a layer extending through the n-InP layer in a direction perpendicular to the substrate layer 20 between the waveguide layer 10 and the lower contact layer 22 Opening.
  • the waveguide layer 10 is connected to the lower mesa of the lower contact layer 22, that is, the lower mesa of the lower contact layer 22 extends to The waveguide region 10 forms the waveguide layer 10.
  • the p-electrode 12 is located on the surface of the p-InGaAs layer, and the n-electrode 11 is located on the surface of the lower mesa of the lower contact layer 22.
  • the materials of the p-electrode 12 and the n-electrode 11 may be titanium, platinum or gold.
  • the surface of the substrate layer 20 has two device structures and a waveguide isolation groove between the two device structures; the waveguide structure is located at the bottom of the waveguide isolation groove and is used for Optical signals are transmitted between the device structures.
  • the waveguide isolation groove is used to electrically isolate the two device structures.
  • the waveguide structure is located between two identical device structures, and one of the two device structures serves as a transmitting end of an optical signal and the other serves as a receiving end of an optical signal, so that an infrared optical signal passes through the
  • the waveguide structure transmits between the transmitting end and the receiving end.
  • the two device structures and the waveguide structure between the two device structures constitute a pair of photonic communication devices.
  • the homogeneous integrated infrared photonic chip provided in this specific embodiment, it may include only one pair of photonic communication devices, or multiple pairs of photonic communication devices, and those skilled in the art may choose according to actual needs.
  • both of the device structures can pass through the waveguide layer
  • the waveguide isolation groove above 10 is electrically isolated, so as to realize the homogeneous integration of the infrared photonic chip and the transmission in the non-visible light sheet, and can simplify the preparation process of the homogeneous integrated infrared photonic chip.
  • the two device structures can be better electrically isolated; when the lower contact layer 22 is connected to the waveguide layer 10, it can greatly Simplify the manufacturing process.
  • FIG. 5 is a flowchart of a method for preparing a homogeneous integrated infrared photonic chip in the embodiment of the present invention.
  • FIGS. 6A-6L are A schematic cross-sectional view of main processes in the process of manufacturing a homogeneous integrated infrared photonic chip according to a specific embodiment of the present invention.
  • the structure of the homogeneous integrated infrared photonic chip manufactured in this embodiment can be seen in FIG. 1A, FIG. 1B, and FIG. 2 to FIG. 4.
  • a method for preparing a homogeneous integrated infrared photonic chip provided by this embodiment includes the following steps:
  • Step S41 providing a substrate layer 20 made of group III-V materials
  • Step S42 forming a device structure and a waveguide structure on the surface of the substrate layer 20, the device structure includes a lower contact layer 22, a quantum well layer 23, and an upper contact layer 13 sequentially stacked in a direction perpendicular to the substrate layer, And the materials of the lower contact layer 22, the quantum well layer 23 and the upper contact layer 13 are all III-V materials; the waveguide structure includes a waveguide layer 10 made of III-V materials, The waveguide layer 10 and the lower contact layer 22 are disposed in the same layer.
  • forming the device structure and the waveguide structure before the surface of the substrate layer 20 further includes the following steps:
  • a first group III-V material is deposited on the surface of the substrate layer 20 to form a buffer layer 21.
  • the specific steps of forming the device structure and the waveguide structure on the surface of the substrate layer 20 include:
  • the waveguide structure includes the waveguide layer 10 made of part of the second III-V group material.
  • the specific steps of etching the stacked structure include:
  • the second III-V material layer includes a lower mesa and an upper mesa protruding from the lower mesa, the quantum well layer 23 and the upper contact layer 13 are sequentially stacked on the upper mesa, the upper mesa and the lower mesa located in the device region constitute the lower contact layer 22, and the lower mesa extends to the waveguide region Described waveguide layer 10.
  • FIG. 1A the structure of the formed homogeneous integrated infrared photonic chip is shown in FIG. 1A, FIG. 2, and FIG. 3, that is, the lower contact layer 22 is connected to the waveguide layer 10.
  • the method further includes the steps of: etching the lower mesa between the waveguide region and the device region , An opening penetrating the buffer layer is formed, and the waveguide layer 10 made up of part of the lower mesa is formed at the same time.
  • the first III-V group material is InP material
  • the second III-V group material is n-InP material
  • the third III-V group material is p-InGaAs
  • the material of the substrate layer 20 is InP material.
  • the structure shown in FIGS. 1B and 4 will be described as an example.
  • the specific steps of forming the device structure and the waveguide structure on the surface of the substrate layer 20 include:
  • a layer of first photoresist layer 501 is uniformly coated on the surface of the stacked structure, as shown in FIG. 6B, and a device region and a waveguide region are defined in the first photoresist layer 501.
  • the stacked structure is etched by reactive ion beam to form a stepped structure as shown in FIG. 6C, and after removing the residual first photoresist layer 501, the structure as shown in FIG. 6D is finally obtained.
  • the n-InP layer in a step shape is formed by etching, wherein the n-InP layer located in the device region includes a lower mesa and an upper mesa convexly provided on the surface of the lower mesa, and The lower mesa of the n-InP layer extends to the waveguide region.
  • the p-InP cladding layer 26, the p-PQ gap buffer layer 27, the upper contact layer 13, and the stepped n-InP material layer located in the device region constitute the lower contact layer 22.
  • a second photoresist layer 502 is uniformly coated on the surface of the structure shown in FIG. 6D, as shown in FIG. 6E; the p-electrode window area 121 and the p-electrode window area 121 are defined in the second photoresist layer 502 n-electrode window area 111, as shown in FIG. 6F; in the p-electrode window area 121 and the n-electrode window area 111, titanium, platinum or gold are vapor-deposited respectively to form an ohmic contact to obtain the p-electrode 12 and n-electrode 11, as shown in FIG. 6G; removing the remaining second photoresist layer 502, and finally obtaining the light emitting diode structure shown in FIG. 6H.
  • a third photoresist layer 503 is coated on the uniform surface of the substrate layer 20 formed with the light emitting diode structure shown in FIG. 6H, as shown in FIG. 6I; and the third photoresist
  • the waveguide area, the device area, and the space area 51 between the waveguide area and the device area are again defined in the layer, as shown in FIG. 6J; then, the reactive ion beam etching process is used to etch the From the lower mesa of the n-InP material layer of the spacer region 51 to the buffer layer 21, an opening is formed through the lower mesa, as shown in FIG. 6K; after removing the remaining third photoresist layer 503, Finally, the structure shown in FIG. 6L is obtained.
  • the surface of the substrate layer 20 has two of the device structures and a waveguide isolation groove between the two device structures; the waveguide structure is located at the bottom of the waveguide isolation groove for Optical signals are transmitted between device structures.
  • the two device structures are completely the same, so the two device structures and the waveguide structure can be manufactured simultaneously, thereby further simplifying the manufacturing process of the homogeneous integrated infrared photonic chip and reducing the manufacturing cost .
  • the homogeneous integrated infrared photonic chip and the preparation method thereof provided by the specific embodiment, by integrating the waveguide structure and the device structure on a substrate composed of III-V materials, the same III-V materials are used to manufacture the waveguide structure And the device structure, and a gap is formed between the waveguide structure and the device structure, which achieves the goal of homogenous integration of the waveguide structure and the device structure, and further realizes the transmission of invisible light in the infrared band in the chip , Which reduces the difficulty and cost of manufacturing infrared communication devices.

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Abstract

一种同质集成红外光子芯片及其制备方法，涉及信息材料与器件技术领域。所述同质集成红外光子芯片包括衬底层（20）以及均位于所述衬底层（20）表面的器件结构和波导结构；所述器件结构包括沿垂直于所述衬底层（20）的方向依次叠置的下接触层（22）、量子阱层（23）和上接触层（13），且所述衬底层（20）、所述下接触层（22）、所述量子阱层（23）与所述上接触层（13）的材料均为III-V族材料；所述波导结构包括采用III-V族材料制造而成的波导层（10），所述波导层（10）与所述下接触层（22）同层设置。该同质集成红外光子芯片实现了红外波段的非可见光在片内的传输，降低了红外光通信器件的制造难度及制造成本。

Description

同质集成红外光子芯片及其制备方法 技术领域
本发明涉及信息材料与器件技术领域，尤其涉及一种同质集成红外光子芯片及其制备方法。
背景技术
红外发光二极管是一种能发出红外线的二极管，应用于安全监控、穿戴式装置、红外线通信、红外线遥控装置、传感器用光源及夜间照明等领域，特别是气体检测领域。然而，目前市场上仅有独立的红外发光二极管或红外接收二极管。因此，在制造红外光通信器件时，需要在不同材料上分别制造二极管器件和波导器件，即现有技术中的红外光通信器件均为异质集成器件，极大的增加了红外光通信器件的制造难度以及制造成本。
因此，如何降低红外光通信器件的制造难度以及制造成本，是目前亟待解决的技术问题。
发明内容
本发明提供了一种同质集成红外光子芯片及其制备方法，用于解决现有的红外光通信器件制造难度大、制造成本高的问题。
为了解决上述问题，本发明提供了一种同质集成红外光子芯片，包括衬底层以及均位于所述衬底层表面的器件结构和波导结构；
所述器件结构包括沿垂直于所述衬底层的方向依次叠置的下接触层、量子阱层和上接触层，且所述衬底层、所述下接触层、所述量子阱层与所述上接触层的材料均为Ⅲ-Ⅴ族材料；
所述波导结构包括采用Ⅲ-Ⅴ族材料制造而成的波导层，所述波导层与所述下接触层同层设置。
优选的，还包括位于所述衬底层表面、且采用Ⅲ-Ⅴ族材料制造而成的缓冲层，所述下接触层与所述波导层均位于所述缓冲层表面。
优选的，所述下接触层呈台阶状，台阶状的所述下接触层包括下台面以及凸设于所述下台面表面的上台面；所述量子阱层与所述上接触层依次叠置于所述上台面；所述波导层与所述下接触层的材料相同。
优选的，所述衬底层为InP衬底层，所述下接触层与所述波导层均为n-InP层，所述上接触层为p-InGaAs层；
所述器件结构包括在所述上台面表面沿所述衬底层指向所述器件结构的方向依次叠置的量子阱层、p-InP间隔层、刻蚀阻断层、p-InP覆盖层、p-PQ间隙缓冲层、p-InGaAs层。
优选的，所述衬底层表面具有两个所述器件结构以及位于两个所述器件结构之间的波导隔离槽；所述波导结构位于所述波导隔离槽的底部，用于在两个所述器件结构之间传输光信号。
为了解决上述问题，本发明还提供了一种同质集成红外光子芯片的制备方法，包括如下步骤：
提供一采用Ⅲ-Ⅴ族材料制造而成的衬底层；
形成器件结构与波导结构于所述衬底层表面，所述器件结构包括沿垂直于所述衬底层的方向依次叠置的下接触层、量子阱层和上接触层，且所述下接触层、所述量子阱层与所述上接触层的材料均为Ⅲ-Ⅴ族材料；所述波导结构包括采用Ⅲ-Ⅴ族材料制造而成的波导层，所述波导层与所述下接触层同层设置。
优选的，形成器件结构与波导结构于所述衬底层表面之前还包括如下步骤：
沉积第一Ⅲ-Ⅴ族材料于所述衬底层表面，形成缓冲层。
优选的，形成器件结构与波导结构于所述衬底层表面的具体步骤包括：
依次沉积第二Ⅲ-Ⅴ族材料、量子阱材料、第三Ⅲ-Ⅴ族材料于所述缓冲层表面，形成堆叠结构；
刻蚀所述堆叠结构，形成所述器件结构和所述波导结构，所述器件结构包括由部分所述第二Ⅲ-Ⅴ族材料构成的所述下接触层、由所述量子阱材料构成的量子阱层以及由所述第三Ⅲ-Ⅴ族材料构成的上接触层，所述波导结构包括由部分所述第二Ⅲ-Ⅴ族材料构成的所述波导层。
优选的，刻蚀所述堆叠结构的具体步骤包括：
于所述堆叠结构中定义器件区域和波导区域；
刻蚀所述堆叠结构，形成台阶状的第二Ⅲ-Ⅴ族材料层；所述第二Ⅲ-Ⅴ族 材料层包括下台面以及凸设于所述下台面的上台面，所述量子阱层与所述上接触层依次叠置于所述上台面，所述上台面与位于所述器件区域的下台面构成所述下接触层，所述下台面延伸至所述波导区域形成所述波导层。
优选的，所述衬底层表面具有两个所述器件结构以及位于两个所述器件结构之间的波导隔离槽；所述波导结构位于所述波导隔离槽的底部，用于在两个所述器件结构之间传输光信号。
本发明提供的同质集成红外光子芯片及其制备方法，通过将波导结构与器件结构集成于由Ⅲ-Ⅴ族材料构成的衬底上，同样采用Ⅲ-Ⅴ族材料制造所述波导结构与所述器件结构，且将所述器件结构中的下接触层与所述波导结构中的波导层同层设置，达到了波导结构与器件结构同质集成的目的，进而实现了红外波段的非可见光在片内的传输，降低了红外光通信器件的制造难度及制造成本。
附图说明
附图1A是本发明具体实施方式中一同质集成红外光子芯片的俯视结构示意图；
附图1B是本发明具体实施方式中另一同质集成红外光子芯片的俯视结构示意图；
附图2是附图1A沿X轴方向的一截面示意图；
附图3是附图1A沿Y轴方向的一截面示意图；
附图4是附图1B沿Y轴方向的一截面示意图；
附图5是本发明具体实施方式中同质集成红外光子芯片的制备方法流程图；
附图6A-6L是本发明具体实施方式在制造同质集成红外光子芯片过程中的主要工艺截面示意图。
具体实施方式
下面结合附图对本发明提供的同质集成红外光子芯片及其制备方法的具体实施方式做详细说明。
本具体实施方式提供了一种同质集成红外光子芯片，附图1A是本发明具 体实施方式中一同质集成红外光子芯片的俯视结构示意图，附图1B是本发明具体实施方式中另一同质集成红外光子芯片的俯视结构示意图，附图2是附图1A沿X轴方向的一截面示意图，附图3是附图1A沿Y轴方向的一截面示意图，附图4是附图1B沿Y轴方向的一截面示意图。
如图1A-1B、图2-图4所示，本具体实施方式提供的同质集成红外光子芯片，包括衬底层20以及均位于所述衬底层20表面的器件结构和波导结构；
所述器件结构包括沿垂直于所述衬底层20的方向依次叠置的下接触层22、量子阱层23和上接触层13，且所述衬底层20、所述下接触层22、所述量子阱层23与所述上接触层13的材料均为Ⅲ-Ⅴ族材料；
所述波导结构包括采用Ⅲ-Ⅴ族材料制造而成的波导层10，所述波导层10与所述下接触层22同层设置。
本具体实施方式在所述衬底层20表面同时集成有所述器件结构与所述波导结构，在沿图1中的Y轴方向的截面图中，器件结构中的所述下接触层22、所述量子阱层23与所述上接触层13沿垂直于所述衬底层20的方向依次堆叠；在沿图1中的X轴方向的截面图中，所述器件结构与所述波导结构的波导层10沿平行于所述衬底层20的方向排布，红外光信号在所述器件结构与所述波导结构之间进行传输。本具体实施方式实现了红外波段的非可见光在片内的传输，降低了红外光通信器件的制造难度及制造成本；同时，同质集成结构提高了片内发光二极管光源的利用效率，为发展面向光通信、光传感的光子器件提供了新的方向。
优选的，所述同质集成红外光子芯片还包括位于所述衬底层20表面、且采用Ⅲ-Ⅴ族材料制造而成的缓冲层21，所述下接触层22与所述波导层10均位于所述缓冲层21表面。
具体来说，所述缓冲层21外延生长于所述衬底层20表面，所述缓冲层21的材料与所述衬底层20的材料可以相同，也可以不同，用于调整所述衬底层20与所述器件结构之间的应力。所述波导层10与位于所述波导层10正下方区域的部分所述缓冲层21共同构成所述波导结构。
优选的，所述下接触层22呈台阶状，台阶状的所述下接触层22包括下台 面以及凸设于所述下台面表面的上台面；所述量子阱层23与所述上接触层13依次叠置于所述上台面；所述波导层10与所述下接触层22的材料相同。
优选的，所述衬底层20为InP衬底层，所述下接触层22与所述波导层10均为n-InP层，所述上接触层13为p-InGaAs层；
所述器件结构包括在所述上台面表面沿所述衬底层指向所述器件结构的方向依次叠置的量子阱层23、p-InP间隔层24、刻蚀阻断层25、p-InP覆盖层26、p-PQ间隙缓冲层27、p-InGaAs层。
其中，p-PQ间隙缓冲层27中的PQ表示由In、P、Ga、As四种元素组成的化合物。在采用上述各种材料的组合制造而成的所述同质集成红外光子芯片中，所述器件结构能够产生的光波长为1550nm，属于红外波段的非可见光。当然，本领域技术人员还可以根据需要选择其他Ⅲ-Ⅴ族材料制造所述器件结构，只要能产生红外光信号即可。
具体来说，所述缓冲层21可以为InP层或GaAs层。所述缓冲层21表面包括具有所述器件结构的器件区域和具有所述波导层10的波导区域。位于所述器件区域的所述n-InP层构成所述下接触层22，且所述下接触层22呈台阶状，所述量子阱层23、所述p-InP间隔层24、所述刻蚀阻断层25、所述p-InP覆盖层26、所述p-PQ间隙缓冲层27、所述p-InGaAs层沿垂直于所述衬底层20的方向依次叠置于所述上台面。位于所述波导区域的所述n-InP层构成所述波导层10。为了简化制造工艺，所述波导层10与所述下台面的厚度相同。
在本具体实施方式中，如图1A、图3所示，所述波导层10与所述下接触层22之间具有一沿垂直于所述衬底层20的方向贯穿所述n-InP层的开口。
在其他具体实施方式中，如图1B、图4所述，所述波导层10与所述下接触层22的所述下台面连接，即所述下接触层22的所述下台面延伸至所述波导区域，形成所述波导层10。
p-电极12位于所述p-InGaAs层表面，n-电极11位于所述下接触层22的所述下台面的表面。所述p-电极12与所述n-电极11的材料可以均为钛、铂或金。
优选的，所述衬底层20表面具有两个所述器件结构以及位于两个所述器 件结构之间的波导隔离槽；所述波导结构位于所述波导隔离槽的底部，用于在两个所述器件结构之间传输光信号。
具体来说，所述波导隔离槽用于电性隔离两个所述器件结构。所述波导结构位于两个完全相同的所述器件结构之间，两个所述器件结构的其中之一作为光信号的发射端、另一作为光信号的接收端，使得红外光信号通过所述波导结构在所述发射端与所述接收端之间进行传输。两个所述器件结构与位于两个所述器件结构之间的所述波导结构构成一对光子通信器件。在本具体实施方式提供的所述同质集成红外光子芯片中，可以仅包括一对光子通信器件，也可以包括多对光子通信器件，本领域技术人员可以根据实际需要进行选择。
在本具体实施方式中，无论所述器件结构中的所述下接触层22与所述波导结构中的所述波导层10连接或者不连接，两个所述器件结构都能通过所述波导层10上方的所述波导隔离槽电性隔离，从而在实现红外光子芯片同质集成、非可见光片内传输的同时，能够简化所述同质集成红外光子芯片的制备工艺。当所述下接触层22与所述波导层10不连接时，能够更好的电性隔离两个所述器件结构；当所述下接触层22与所述波导层10连接时，则可以大大简化制造工艺。
不仅如此，本具体实施方式还提供了一种同质集成红外光子芯片的制备方法，附图5是本发明具体实施方式中同质集成红外光子芯片的制备方法流程图，附图6A-6L是本发明具体实施方式在制造同质集成红外光子芯片过程中的主要工艺截面示意图。本具体实施方式制造的同质集成红外光子芯片的结构可参见图1A、图1B、图2-图4。如图1A、图1B、图2-图5、图6A-图6L所示，本具体实施方式提供的同质集成红外光子芯片的制备方法，包括如下步骤：
步骤S41，提供一采用Ⅲ-Ⅴ族材料制造而成的衬底层20；
步骤S42，形成器件结构与波导结构于所述衬底层20表面，所述器件结构包括沿垂直于所述衬底层的方向依次叠置的下接触层22、量子阱层23和上接触层13，且所述下接触层22、所述量子阱层23与所述上接触层13的材料均为Ⅲ-Ⅴ族材料；所述波导结构包括采用Ⅲ-Ⅴ族材料制造而成的波导层10，所述波导层10与所述下接触层22同层设置。
优选的，形成器件结构与波导结构于所述衬底层20表面之前还包括如下步骤：
沉积第一Ⅲ-Ⅴ族材料于所述衬底层20表面，形成缓冲层21。
优选的，形成器件结构与波导结构于所述衬底层20表面的具体步骤包括：
依次沉积第二Ⅲ-Ⅴ族材料、量子阱材料、第三Ⅲ-Ⅴ族材料于所述缓冲层21表面，形成堆叠结构，如图6A所示；
刻蚀所述堆叠结构，形成所述器件结构和所述波导结构，所述器件结构包括由部分所述第二Ⅲ-Ⅴ族材料构成的所述下接触层22、由所述量子阱材料构成的量子阱层23以及由所述第三Ⅲ-Ⅴ族材料构成的上接触层13，所述波导结构包括由部分所述第二Ⅲ-Ⅴ族材料构成的所述波导层10。
优选的，刻蚀所述堆叠结构的具体步骤包括：
于所述堆叠结构中定义器件区域和波导区域；
刻蚀所述堆叠结构，形成台阶状的第二Ⅲ-Ⅴ族材料层；所述第二Ⅲ-Ⅴ族材料层包括下台面以及凸设于所述下台面的上台面，所述量子阱层23与所述上接触层13依次叠置于所述上台面，所述上台面与位于所述器件区域的下台面构成所述下接触层22，所述下台面延伸至所述波导区域形成所述波导层10。
此时，形成的同质集成红外光子芯片的结构如图1A、图2、图3所示，即所述下接触层22与所述波导层10连接。
在其他具体实施方式中，为了得到如图1B、图4所示的结构，刻蚀所述堆叠结构之后还包括如下步骤：刻蚀所述波导区域与所述器件区域之间的所述下台面，形成贯穿至所述缓冲层的开口、并同时形成由部分所述下台面构成的所述波导层10。
所述第一Ⅲ-Ⅴ族材料为InP材料，所述第二Ⅲ-Ⅴ族材料为n-InP材料，所述第三Ⅲ-Ⅴ族材料为p-InGaAs，所述衬底层20的材料为InP材料。以下以形成如图1B、图4所示的结构为例进行说明。形成器件结构与波导结构于所述衬底层20表面的具体步骤包括：
(1)依次沉积InP层、n-InP层、量子阱层、p-InP间隔层、刻蚀阻断层、p-InP覆盖层、p-PQ间隙缓冲层、p-InGaAs层于所述衬底层20表面，形成堆 叠结构，如图6A所示。
(2)于所述堆叠结构表面均匀涂布一层第一光刻胶层501，如图6B所示，并于所述第一光刻胶层501中定义器件区域和波导区域。
(3)采用反应离子束刻蚀所述堆叠结构，形成如图6C所示的台阶状结构，去除残余的所述第一光刻胶层501之后，最终得到如图6D所示的结构。具体来说，通过刻蚀，形成台阶状的所述n-InP层，其中位于所述器件区域的所述n-InP层包括下台面以及凸设于所述下台面表面的上台面，且所述n-InP层的下台面延伸至所述波导区域。同时，仅保留位于所述上台面的所述量子阱层、所述p-InP间隔层、所述刻蚀阻断层、所述p-InP覆盖层、所述p-PQ间隙缓冲层、所述p-InGaAs层，位于所述下台面上的所述量子阱层、所述p-InP间隔层、所述刻蚀阻断层、所述p-InP覆盖层、所述p-PQ间隙缓冲层、所述p-InGaAs层均去除，在形成波导隔离槽的同时形成位于所述上台面的所述量子阱层23、所述p-InP间隔层24、所述刻蚀阻断层25、所述p-InP覆盖层26、所述p-PQ间隙缓冲层27、所述上接触层13，位于所述器件区域的台阶状的所述n-InP材料层构成所述下接触层22。
(4)在如图6D所示的结构表面均匀涂布一层第二光刻胶层502，如图6E所示；在所述第二光刻胶层502中定义p-电极窗口区域121和n-电极窗口区域111，如图6F所示；在所述p-电极窗口区域121和所述n-电极窗口区域111分别蒸镀钛、铂或金，形成欧姆接触，得到p-电极12与n-电极11，如图6G所示；除去残余的所述第二光刻胶层502，最终得到如图6H所示的发光二极管结构。
(5)在形成有如图6H所示的发光二极管结构的所述衬底层20的均匀表面涂布一层第三光刻胶层503，如图6I所示；并在所述第三光刻胶层中再次定义所述波导区域、所述器件区域以及所述波导区域与所述器件区域之间的间隔区域51，如图6J所述；接着，采用反应离子束刻蚀工艺刻蚀位于所述间隔区域51的所述n-InP材料层的下台面至所述缓冲层21，形成贯穿所述下台面的开口，如图6K所示；去除残余的所述第三光刻胶层503之后，最终得到如图6L所示的结构。
优选的，所述衬底层20表面具有两个所述器件结构以及位于两个所述器件结构之间的波导隔离槽；所述波导结构位于所述波导隔离槽底部，用于在两个所述器件结构之间传输光信号。
具体来说，两个所述器件结构完全相同，因此，两个所述器件结构与所述波导结构可以同步制作，从而进一步简化了所述同质集成红外光子芯片的制备工艺，降低了制备成本。
本具体实施方式提供的同质集成红外光子芯片及其制备方法，通过将波导结构与器件结构集成于由Ⅲ-Ⅴ族材料构成的衬底上，同样采用Ⅲ-Ⅴ族材料制造所述波导结构与所述器件结构，且在所述波导结构与所述器件结构之间形成一间隙，达到了波导结构与器件结构的同质集成的目的，进而实现了红外波段的非可见光在片内的传输，降低了红外光通信器件的制造难度及制造成本。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种同质集成红外光子芯片，其特征在于，包括衬底层以及均位于所述衬底层表面的器件结构和波导结构；
    所述器件结构包括沿垂直于所述衬底层的方向依次叠置的下接触层、量子阱层和上接触层，且所述衬底层、所述下接触层、所述量子阱层与所述上接触层的材料均为Ⅲ-Ⅴ族材料；
    所述波导结构包括采用Ⅲ-Ⅴ族材料制造而成的波导层，所述波导层与所述下接触层同层设置。
  2. 根据权利要求1所述的同质集成红外光子芯片，其特征在于，还包括位于所述衬底层表面、且采用Ⅲ-Ⅴ族材料制造而成的缓冲层，所述下接触层与所述波导层均位于所述缓冲层表面。
  3. 根据权利要求1所述的同质集成红外光子芯片，其特征在于，所述下接触层呈台阶状，台阶状的所述下接触层包括下台面以及凸设于所述下台面表面的上台面；所述量子阱层与所述上接触层依次叠置于所述上台面；所述波导层与所述下接触层的材料相同。
  4. 根据权利要求3所述的同质集成红外光子芯片，其特征在于，所述衬底层为InP衬底层，所述下接触层与所述波导层均为n-InP层，所述上接触层的为p-InGaAs层；
    所述器件结构包括在所述上台面表面沿所述衬底层指向所述器件结构的方向依次叠置的量子阱层、p-InP间隔层、刻蚀阻断层、p-InP覆盖层、p-PQ间隙缓冲层、p-InGaAs层。
  5. 根据权利要求1所述的同质集成红外光子芯片，其特征在于，所述衬底层表面具有两个所述器件结构以及位于两个所述器件结构之间的波导隔离槽；所述波导结构位于所述波导隔离槽的底部，用于在两个所述器件结构之间传输光信号。
  6. 一种同质集成红外光子芯片的制备方法，其特征在于，包括如下步骤：
    提供一采用Ⅲ-Ⅴ族材料制造而成的衬底层；
    形成器件结构与波导结构于所述衬底层表面，所述器件结构包括沿垂直于 所述衬底层的方向依次叠置的下接触层、量子阱层和上接触层，且所述下接触层、所述量子阱层与所述上接触层的材料均为Ⅲ-Ⅴ族材料；所述波导结构包括采用Ⅲ-Ⅴ族材料制造而成的波导层，所述波导层与所述下接触层同层设置。
  7. 根据权利要求6所述的同质集成红外光子芯片的制备方法，其特征在于，形成器件结构与波导结构于所述衬底层表面之前还包括如下步骤：
    沉积第一Ⅲ-Ⅴ族材料于所述衬底层表面，形成缓冲层。
  8. 根据权利要求7所述的同质集成红外光子芯片的制备方法，其特征在于，形成器件结构与波导结构于所述衬底层表面的具体步骤包括：
    依次沉积第二Ⅲ-Ⅴ族材料、量子阱材料、第三Ⅲ-Ⅴ族材料于所述缓冲层表面，形成堆叠结构；
    刻蚀所述堆叠结构，形成所述器件结构和所述波导结构，所述器件结构包括由部分所述第二Ⅲ-Ⅴ族材料构成的所述下接触层、由所述量子阱材料构成的量子阱层以及由所述第三Ⅲ-Ⅴ族材料构成的上接触层，所述波导结构包括由部分所述第二Ⅲ-Ⅴ族材料构成的所述波导层。
  9. 根据权利要求8所述的同质集成红外光子芯片的制备方法，其特征在于，刻蚀所述堆叠结构的具体步骤包括：
    于所述堆叠结构中定义器件区域和波导区域；
    刻蚀所述堆叠结构，形成台阶状的第二Ⅲ-Ⅴ族材料层；所述第二Ⅲ-Ⅴ族材料层包括下台面以及凸设于所述下台面的上台面，所述量子阱层与所述上接触层依次叠置于所述上台面，所述上台面与位于所述器件区域的下台面构成所述下接触层，所述下台面延伸至所述波导区域形成所述波导层。
  10. 根据权利要求6所述的同质集成红外光子芯片的制备方法，其特征在于，所述衬底层表面具有两个所述器件结构以及位于两个所述器件结构之间的波导隔离槽；所述波导结构位于所述波导隔离槽的底部，用于在两个所述器件结构之间传输光信号。
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