WO2020133623A1 - 显示面板驱动电路及显示装置 - Google Patents

显示面板驱动电路及显示装置 Download PDF

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Publication number
WO2020133623A1
WO2020133623A1 PCT/CN2019/073132 CN2019073132W WO2020133623A1 WO 2020133623 A1 WO2020133623 A1 WO 2020133623A1 CN 2019073132 W CN2019073132 W CN 2019073132W WO 2020133623 A1 WO2020133623 A1 WO 2020133623A1
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WIPO (PCT)
Prior art keywords
timing controller
display panel
driving circuit
data
branch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/073132
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English (en)
French (fr)
Inventor
黄笑宇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
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HKC Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HKC Co Ltd filed Critical HKC Co Ltd
Publication of WO2020133623A1 publication Critical patent/WO2020133623A1/zh
Priority to US17/060,281 priority Critical patent/US11114012B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/04—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/04—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
    • G09G2370/042—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller for monitor identification
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/06—Consumer Electronics Control, i.e. control of another device by a display or vice versa
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit

Definitions

  • the present application relates to the field of display driving technology, in particular to a display panel driving circuit and a display device.
  • the timing controller TCON The data in the internal static read-only memory SROM of the IC cannot generally be saved after power-off, while the EEPROM (Electrically Erasable Programmable read only memory, erasable memory) or the data stored in the flash memory Flash can be saved even after power off, so the control program of the timing controller is stored in the external memory EEPROM or Flash.
  • the timing controller After power-on, the timing controller will initialize and read the timing control data from the external memory through the bus. Then connect to the control chip through the bus.
  • the memory and the timing controller are connected to the timing controller through the communication bus, when the timing control data is read from the external memory through the bus, the control signal of the control chip may interfere with the timing controller and the memory. Data read, causing data read failure.
  • the main purpose of the present application is to propose a display panel driving circuit and a display device, aiming to solve the problem of timing controller software reading errors and improve the reliability of the display device.
  • the display panel driving circuit includes:
  • a control chip, the control chip is connected to a serial communication bus
  • the communication switching circuit includes a controlled terminal, a control signal input terminal and a control signal output terminal, and the control signal input terminal is communicatively connected to the control chip via the serial communication bus;
  • the timing controller includes a data transmission terminal and a control terminal.
  • the data transmission terminal is connected to the control signal output terminal of the communication switching circuit and the data output terminal of the memory.
  • the control terminal is connected to the communication switching circuit. Console connection; where,
  • the timing controller is configured to receive the control signal output by the control chip when the communication switching circuit is turned on, and read the software data of the memory when the communication switching circuit is turned off.
  • the display panel driving circuit further includes a communication isolation circuit, the communication isolation circuit is disposed in series between the communication switching circuit and the timing controller, and the communication isolation circuit is configured to When the timing controller controls the communication switching circuit to be turned on, the control signal output by the control chip is isolated and output.
  • the communication isolation circuit includes a first unidirectional conducting element and a second unidirectional conducting element.
  • the input end of the first unidirectional conducting element is connected to the output end of the first strobe branch.
  • the input end of the second unidirectional conduction element is connected to the output end of the second gating branch, and the output end of the second unidirectional conduction element is connected to the data transmission end of the timing controller.
  • the serial communication bus includes a data line and a clock line
  • the communication switching circuit includes a first gating branch, a second gating branch, and a D flip-flop, and a clock signal input of the D flip-flop
  • the terminal is connected to the control terminal of the timing controller
  • the data input terminal of the D flip-flop is connected to the first DC power supply
  • the data output terminal of the D flip-flop is connected to the first strobe branch and the
  • the controlled end of the second gating branch is connected
  • the first gating branch is connected in series between the data line and a data transmission end of the timing controller
  • the second gating branch is connected in series It is arranged between the clock line and another data transmission end of the timing controller.
  • the first gating branch includes a first electronic switch and a first resistor, the controlled end of the first electronic switch is the controlled end of the first gating branch, and passes through the The first resistor is grounded, the input end of the first electronic switch is connected to the data line, and the output end of the first electronic switch is connected to the second data transmission end of the book sequence controller.
  • the first gating branch includes a second electronic switch and a second resistor
  • the controlled end of the second electronic switch is the controlled end of the second gating branch, and passes through the The second resistor is grounded, the input end of the second electronic switch is connected to the data line, and the output end of the second electronic switch is connected to the data transmission end of the timing controller.
  • the display panel driving circuit further includes a third unidirectional conducting element, an input end of the third unidirectional conducting element is connected to the memory, and an output end of the third unidirectional conducting element is connected to the Timing controller connection.
  • the display panel driving circuit further includes a gate driving circuit and a source driving circuit, the controlled ends of the gate driving circuit and the source driving circuit are respectively connected to the output ends of the timing controller .
  • This application also proposes a display panel driving circuit, including:
  • the communication switching circuit includes a controlled terminal, a control signal input terminal and a control signal output terminal, the communication switching circuit, the control signal input terminal is in communication connection with each of the control chips via the serial communication bus;
  • a unidirectional conduction element the input end of the unidirectional conduction element is connected to the control signal output end of the communication switching circuit;
  • the timing controller includes a data transmission end and a control end, the data transmission end is connected to the output end of the unidirectional conduction element and the data output end of the memory, and the control end is controlled by the communication switching circuit End connection;
  • the timing controller is configured to receive the control signal output by the control chip when the communication switching circuit is turned on, and read the software data of the memory when the communication switching circuit is turned off.
  • the present application also proposes a display device, which includes a display panel and the display panel drive circuit as described above, and the gate drive circuit and the source drive circuit of the display panel are electrically connected to the display panel, respectively .
  • a control chip, a timing controller and a memory are provided, and a communication connection is performed through a serial communication bus, and a communication switching circuit is provided in series between the control chip and the timing controller.
  • the communication switching circuit is based on the control of the timing control circuit And, when the timing controller controls the communication switching circuit to be closed, the communication connection between the timing controller and the memory is realized, so that the timing controller reads the software data of the memory, and then the initial setting of the timing controller is completed.
  • the timing controller controls the communication switching circuit to be turned on, the timing controller communicates with the control chip so as to receive the control signal output by the control chip, convert it to the corresponding driving signal, and output it to complete the image display of the display panel.
  • the present application solves that when the timing controller reads the data of the memory, the data of the memory may sneak into the control chip, causing the work of the control chip to be disordered, or the data signal of the control chip is output to the timing controller or the memory, resulting in the timing The controller failed to read the memory data.
  • This application effectively solves the problem of timing controller software reading errors and improves the reliability of the display device.
  • FIG. 1 is a schematic diagram of functional modules of an embodiment of a display panel driving circuit of the present application
  • FIG. 2 is a schematic diagram of functional modules of another embodiment of the display panel driving circuit of the present application.
  • FIG. 3 is a schematic diagram of a circuit structure of an embodiment of a display panel driving circuit of the present application.
  • Label Name Label Name 10 Memory 31 First gate branch 20 Control chip 32 Second gate branch 30 Communication switching circuit 33 D trigger 40 Timing controller Q1 The first electronic switch 50 Communication isolation circuit R1 First resistance SCL Clock line Q2 Second electronic switch SDA Data cable R2 Second resistance VDD First DC power supply C Clock signal input D1 The first unidirectional element D Data input D2 The second unidirectional element Q Data output
  • This application proposes a display panel driving circuit.
  • the display panel driving circuit includes:
  • a control chip 20 which is connected to a serial communication bus
  • the communication switching circuit 30 includes a controlled terminal, a control signal input terminal and a control signal output terminal, and the control signal input terminal is communicatively connected to the control chip 20 via the serial communication bus;
  • the timing controller 40 includes a data transmission end and a control end, the data transmission end is connected to the control signal output end of the communication switching circuit 30 and the data output end of the memory 10, and the control end is switched to the communication The controlled end of the circuit 30 is connected; wherein,
  • the timing controller 40 is configured to receive the control signal output by the control chip 20 when the communication switching circuit 30 is turned on, and read the software data of the memory 10 when the communication switching circuit 30 is turned off.
  • the display panel driving circuit further includes a gate driving circuit and a source driving circuit, the controlled ends of the gate driving circuit and the source driving circuit are respectively output from the timing controller 40 ⁇ End connection.
  • Both the memory 10 and the timing controller 40 can be set on a timing controller (TCON) PCB board.
  • the memory 10 can store control signals for driving the gate driving integrated circuit and the source driving integrated circuit, and through the serial
  • the communication bus is communicatively connected to the timing controller 40.
  • the timing controller 40 reads the control signals in the memory 10 and other setting data for initial setting to generate corresponding timing control signals to drive
  • the source driving integrated circuit and the gate driving integrated circuit of the display panel in the display device work.
  • the data of the memory 10 cannot be modified when the display device is working normally. Once modified, the setting data is wrong, which will cause the display device to display abnormally.
  • the memory 10 is mostly provided with a write protection pin (WP pin), and when the high level is input, the memory 10 can be controlled to write data, and when the level is low, the data cannot be written. At this time, the memory 10 is only for the timing controller 40 Read the data.
  • the timing control board is also provided with a power processing circuit, and the output end of the power processing circuit is connected to the memory 10 and the timing controller 40 respectively.
  • the serial communication bus may use the (I 2 Cnter-Integrated Circuit) communication bus, and of course, it may also be implemented using other communication lines, which is not limited herein.
  • the control chip 20 may be provided on the main control board of the display device, and the number of the control chip 20 may be one or more, which may be set according to the function of the display device, and may be the main controller of the display device or For the video processing chip, when the number of control chips 20 is set to multiple, each control chip 20 is connected to the timing controller 40 through a serial communication bus.
  • the control chip 20 outputs the R/G/B compressed signal and the control signal to the timing controller 40 via the serial communication bus when the display device is working, and the power source passes through the power line and the power processing circuit.
  • the power processing circuit converts the received power into the corresponding driving power and outputs it to the circuit module on the timing control board.
  • the timing controller 40 converts the received R/G/B compressed signals and control signals into data signals, control signals, and clocks suitable for the source driving circuit and the gate driving circuit in the display device Signal to realize the image display of the display panel.
  • control chip 20, the timing controller 40 and the memory 10 are all connected by a serial communication bus, and the timing controller 40 needs to read the data of the memory 10 and the control chip 20 to realize the driving of the display panel . Therefore, when the timing controller 40 reads the data, it may affect other chips. For example, when the timing controller 40 reads the data of the memory 10, the data of the memory 10 may sneak into the control chip 20, resulting in control The operation of the chip 20 is disordered, or when the timing controller 40 reads the data of the memory 10, the data signal of the control chip 20 is output to the timing controller 40 or the memory 10, which causes the timing controller 40 to fail to read the data of the memory 10.
  • the display panel driving circuit of this embodiment may be provided with a communication switching circuit 30 to realize the switching of the communication circuit.
  • the communication switching circuit 30 receives the control signal output by the timing controller 40 and turns on/off.
  • the timing controller 40 controls the communication switching circuit 30 to close.
  • the timing controller 40 communicates through serial communication
  • the bus is in communication with the memory 10 to read the software data of the memory 10 to realize the initial setting of the timing controller 40.
  • the communication switching circuit 30 is in an off state, so the data of the control chip 20 will not Output to the memory 10 or the timing controller 40 via the serial communication bus, and interfere with the timing controller 40 reading the data of the memory 10, and at the same time, the data of the memory 10 will not enter the control chip 20, resulting in the control chip 20 Dysfunction.
  • the timing controller 40 controls the communication switching circuit 30 to turn on, and at this time the timing controller 40 communicates with the control chip 20 through the serial communication bus, thereby receiving the control signal output by the control chip 20 , Data signal and clock signal, and converted to the corresponding drive signal and output, complete the image display of the display panel.
  • control chip 20, the timing controller 40 and the memory 10 are provided, and the communication connection is performed through a serial communication bus, and the communication switching circuit 30 is provided in series between the control chip 20 and the timing controller 40 in series.
  • 30 is based on the control of the timing control circuit, and when the timing controller 40 controls the communication switching circuit 30 to be closed, the communication connection between the timing controller 40 and the memory 10 is realized, so that the timing controller 40 reads the software data of the memory 10, and then completes the timing The initial setting of the controller 40.
  • the timing controller 40 controls the communication switching circuit 30 to turn on, the timing controller 40 communicates with the control chip 20 so as to receive the control signal output from the control chip 20 and convert it into a corresponding driving signal and then output it to complete the display panel. Image display.
  • the present application solves that when the timing controller 40 reads the data of the memory 10, the data of the memory 10 may sneak into the control chip 20, causing the control chip 20 to work disorderly, or the data signal of the control chip 20 is output to the timing controller 40 or the memory 10, which causes the timing controller 40 to fail to read the data of the memory 10.
  • the present application effectively solves the problem of the software read error of the timing controller 40 and improves the reliability of the display device.
  • the display panel driving circuit further includes a communication isolation circuit 50, and the communication isolation circuit 50 is disposed in series with the communication switching circuit 30 and the timing controller 40 In between, the communication isolation circuit 50 is configured to isolate and output the control signal output by the control chip 20 when the timing controller 40 controls the communication switching circuit 30 to turn on.
  • the communication isolation circuit 50 of this embodiment can output the communication signal of the control chip 20 after the communication between the control chip 20 and the timing controller 40 is communication isolated, so as to isolate the I 2 C bus of the memory 10 and the timing controller 40 Interfering signals generated.
  • the communication isolation circuit 50 includes a first unidirectional conduction element D1 and a second unidirectional conduction element D2, the input end of the first unidirectional conduction element D1 and the first strobe The output end of the branch 31 is connected, and the output end of the first unidirectional conduction element D1 is connected to the second data transmission end of the timing controller 40;
  • the input terminal of the second unidirectional conduction element D2 is connected to the output terminal of the second gating branch 32, and the output terminal of the second unidirectional conduction element D2 is connected to the second data of the timing controller 40 Transmission side.
  • the first unidirectional conduction element D1 and/or the second unidirectional conduction element D2 may be implemented by using a unidirectional diode with isolation characteristics such as a photocoupler and a diode.
  • a diode may be used for implementation.
  • the unidirectional conduction element can also avoid the I 2 C bus used to connect the memory 10 and the timing controller 40 when the communication strobe circuit is turned on, that is, when the timing controller 40 receives the control signal of the control chip 20
  • the interference signal generated by the parasitic capacitance and impedance on the control channel enters the control chip 20, and the problem of disordered operation of the control chip 20 occurs, so that the communication between the timing controller 40 and the memory chip affects other external I 2 C bus
  • the chip works normally.
  • the serial communication bus includes a data line SDA and a clock line SCL
  • the communication switching circuit 30 includes a first gate branch 31, a second gate branch Road 32 and D flip-flop 33
  • the clock signal input terminal C of the D flip-flop 33 is connected to the control terminal of the timing controller 40
  • the data input terminal D of the D flip-flop 33 is connected to the first DC
  • the power supply VDD is connected
  • the data output terminal Q of the D flip-flop 33 is connected to the controlled ends of the first gating branch 31 and the second gating branch 32
  • the first gating branch 31 is arranged in series
  • the second strobe branch 32 is connected in series to the clock line SCL and another data transmission of the timing controller 40 Between the ends.
  • the first DC power supply VDD may be the power supply of the timing controller.
  • the D flip-flop 33 is based on the control of the timing controller 40, and is used to assign the logic level of the data input terminal D when the rising edge trigger signal output by the timing controller 40 is received, that is, high power
  • the flat first DC power supply VDD is provided to the data output terminal, so that the data output terminal Q outputs a high-level control signal to the first gate branch 31 and the second gate branch 32, thereby controlling the first gate branch
  • the path 31 and the second gate branch 32 are opened, and the communication connection between the control chip 20 and the timing controller 40 is realized.
  • the D flip-flop 33 When the falling edge trigger signal output by the timing controller 40 is received, the D flip-flop 33 does not operate, thereby controlling the first strobe branch 31 and the second strobe branch 32 to be disconnected, so as to disconnect the control chip 20 from The communication connection of the timing controller 40.
  • the first gate branch 31 includes a first electronic switch Q1 and a first resistor R1, the controlled end of the first electronic switch Q1 is the The controlled end of the first gate branch 31 is grounded via the first resistor R1, the input end of the first electronic switch Q1 is connected to the data line SDA, and the output end of the first electronic switch Q1 It is connected to the second data transmission end of the book sequence controller.
  • the first electronic switch Q1 may be implemented using a switching transistor such as a triode, a MOS transistor, etc.
  • a switching transistor such as a triode, a MOS transistor, etc.
  • an N-MOS transistor may optionally be used.
  • the first resistor R1 is a pull-down resistor, which is used to output a low-level control signal to the gate of the N-MOS tube, so that the N-MOS tube is in an off state.
  • the timing controller 40 outputs a falling edge trigger signal, and the D flip-flop 33 does not operate, thereby keeping the N-MOS tube off.
  • the timing controller 40 communicates with the memory 10 to realize timing control The initial setting of the device 40.
  • the timing controller 40 outputs a rising edge trigger signal, which triggers the D flip-flop 33 to output a high-level control signal to control the N-MOS tube to turn on.
  • the timing controller 40 and the control chip 20 Communication connection to complete the image display of the display panel.
  • the second gate branch 32 includes a second electronic switch Q2 and a second resistor R2, the controlled end of the second electronic switch Q2 is the The controlled end of the second gate branch 32 is grounded via the second resistor R2, the input end of the second electronic switch Q2 is connected to the data line SDA, and the output end of the second electronic switch Q2 It is connected to the second data transmission end of the timing controller 40.
  • the second electronic switch Q2 may be implemented using a switching transistor such as a triode, a MOS transistor, etc.
  • an N-MOS transistor may optionally be used.
  • the second resistor R2 is a pull-down resistor, which is used to output a low-level control signal to the gate of the N-MOS tube, so that the N-MOS tube is in an off state.
  • the timing controller 40 outputs a falling edge trigger signal, and the D flip-flop 33 does not operate, thereby keeping the N-MOS tube off.
  • the timing controller 40 communicates with the memory 10 to realize timing control The initial setting of the device 40.
  • the timing controller 40 outputs a rising edge trigger signal, which triggers the D flip-flop 33 to output a high-level control signal to control the N-MOS tube to turn on.
  • the timing controller 40 and the control chip 20 Communication connection to complete the image display of the display panel.
  • the display panel driving circuit further includes a third unidirectional conducting element (not shown), and an input end of the third unidirectional conducting element is connected to the The memory 10 is connected, and the output end of the third conducting element is connected to the timing controller 40.
  • the data of the memory 10 cannot be modified during the normal operation of the display device. Once modified, the setting data is wrong, which will cause the display device to display abnormalities. Therefore, the memory 10 is mostly provided with a write protection pin (WP pin), and when the high level is input, the memory 10 can be controlled to write data, while at the low level, the data cannot be written, and the memory 10 is write protected.
  • WP pin write protection pin
  • the third unidirectional conducting element may be implemented by a unidirectional diode with isolation characteristics such as an optical coupler and a diode.
  • a diode may be used for implementation.
  • the third unidirectional conducting element is used to prevent the timing controller 40 from reading the data of the control chip 20, the data of the control chip 20 stolen into the memory 10, and causing the data of the memory 10 to be rewritten.
  • the present application also proposes a display device including a display panel and the display panel driving circuit as described above.
  • the gate driving circuit and the source driving circuit of the display panel are electrically connected to the display panel, respectively.
  • the display panel driving circuit For the detailed structure of the display panel driving circuit, reference may be made to the above embodiment, which will not be repeated here; it can be understood that, since the above display panel driving circuit is used in the display device of the present application, embodiments of the display device of the present application include All the technical solutions of all the embodiments of the display panel driving circuit described above, and the technical effects achieved are also the same, which will not be repeated here.
  • the display device may be a display device having a display panel, such as a television, a tablet computer, and a mobile phone.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本申请公开一种显示面板驱动电路及显示装置，该显示面板驱动电路包括存储器；控制芯片；时序控制器，包括数据传输端及控制端，数据传输端与通讯切换电路的控制信号输出端及存储器的数据输出端连接，控制端与通讯切换电路的受控端连接；其中，时序控制器被配置为，控制通讯切换电路开启时，接收控制芯片输出的控制信号，控制通讯切换电路关闭时，读取存储器的软体数据。

Description

显示面板驱动电路及显示装置
相关专利
本申请要求2018年12月27日，申请号为201811617081.4，申请名称为“显示面板驱动电路及显示装置”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及显示驱动技术领域，特别涉及一种显示面板驱动电路及显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
显示装置中，时序控制器TCON IC内部静态只读存储器SROM里的数据一般在掉电之后不能保存，而EEPROM(Electrically Erasable Programmable read only memory，可擦除存储器）或闪存器Flash里存储的数据即使掉电之后也能保存，所以会将时序控制器的控制程序储存在外部存储器EEPROM或Flash中。上电之后，时序控制器会进行初始化，通过总线从外部存储器中读取时序控制数据。随后再通过总线与控制芯片连接。
由于存储器和时序控制器均是通过通讯总线与时序控制器连接的，因此，在通过总线从外部存储器中读取时序控制数据时，控制芯片的控制信号可能会干扰时序控制器与存储器之间的数据读取，导致数据读取失败。
申请内容
本申请的主要目的是提出一种显示面板驱动电路及显示装置，旨在解决时序控制器软件读取错误的问题，提高了显示装置的可靠性。
为实现上述目的，本申请提出一种显示面板驱动电路，所述显示面板驱动电路包括：
存储器；
控制芯片，所述控制芯片连接至串行通讯总线；
通讯切换电路，包括受控端、控制信号输入端及控制信号输出端，所述控制信号输入端经所述串行通讯总线与所述控制芯片通讯连接；
时序控制器，包括数据传输端及控制端，所述数据传输端与所述通讯切换电路的控制信号输出端及所述存储器的数据输出端连接，所述控制端与所述通讯切换电路的受控端连接；其中，
所述时序控制器被配置为，控制所述通讯切换电路开启时，接收所述控制芯片输出的控制信号，控制通讯切换电路关闭时，读取所述存储器的软体数据。
可选地，所述显示面板驱动电路还包括通讯隔离电路，所述通讯隔离电路串联设置于所述通讯切换电路与所述时序控制器之间，所述通讯隔离电路被配置为，在所述时序控制器控制所述通讯切换电路开启时，将所述控制芯片输出的控制信号进行隔离后输出。
可选地，所述通讯隔离电路包括第一单向导通元件及第二单向导通元件，所述第一单向导通元件的输入端与所述第一选通支路的输出端连接，所述第一单向导通元件的输出端与所述时序控制器的数据传输端；
所述第二单向导通元件的输入端与所述第二选通支路的输出端连接，所述第二单向导通元件的输出端与所述时序控制器的数据传输端。
可选地，所述串行通讯总线包括数据线和时钟线，所述通讯切换电路包括第一选通支路、第二选通支路及D触发器，所述D触发器的时钟信号输入端与所述时序控制器的控制端连接，所述D触发器的数据输入端与第一直流电源连接，所述D触发器的数据输出端与所述第一选通支路和所述第二选通支路的受控端连接，所述第一选通支路串联设置于所述数据线与所述时序控制器的一数据传输端之间，所述第二选通支路串联设置于所述时钟线与所述时序控制器的另一数据传输端之间。
可选地，所述第一选通支路包括第一电子开关和第一电阻，所述第一电子开关的受控端为所述第一选通支路的受控端，并经所述第一电阻的接地，所述第一电子开关的输入端与所数据线连接，所述第一电子开关的输出端与所述书序控制器的第二数据传输端连接。
可选地，所述第一选通支路包括第二电子开关和第二电阻，所述第二电子开关的受控端为所述第二选通支路的受控端，并经所述第二电阻的接地，所述第二电子开关的输入端与所数据线连接，所述第二电子开关的输出端与所述时序控制器的数据传输端连接。
可选地，所述显示面板驱动电路还包括第三单向导通元件，所述第三单向导通元件的输入端与所述存储器连接，所述第三导向导通元件的输出端与所述时序控制器连接。
可选地，所述显示面板驱动电路还包括栅极驱动电路及源极驱动电路，所述栅极驱动电路和所述源极驱动电路的受控端分别与所述时序控制器的输出端连接。
本申请还提出一种显示面板驱动电路，包括：
存储器；
多个控制芯片，各所述控制芯片连接至串行通讯总线；
通讯切换电路，包括受控端、控制信号输入端及控制信号输出端，所述通讯切换电路，所述控制信号输入端经所述串行通讯总线与各所述控制芯片通讯连接；
单向导通元件，所述单向导通元件的输入端与所述通讯切换电路的控制信号输出端连接；
时序控制器，包括数据传输端及控制端，所述数据传输端与所述单向导通元件的输出端及所述存储器的数据输出端连接，所述控制端与所述通讯切换电路的受控端连接；其中，
所述时序控制器被配置为，控制所述通讯切换电路开启时，接收所述控制芯片输出的控制信号，控制通讯切换电路关闭时，读取所述存储器的软体数据。
本申请还提出一种显示装置，其特征在于，包括显示面板及如上所述的显示面板驱动电路，所述显示面板的栅极驱动电路和所述源极驱动电路分别与所述显示面板电连接。
本申请通过设置控制芯片、时序控制器及存储器，并通过串行通讯总线进行通讯连接，并通过设置通讯切换电路串联设置于控制芯片与时序控制器之间，通讯切换电路基于时序控制电路的控制，并在时序控制器控制通讯切换电路关闭时，实现时序控制器与存储器通讯连接，以使时序控制器读取存储器的软体数据，进而完成时序控制器的初始设置。而在时序控制器控制通讯切换电路开启时，实现时序控制器与控制芯片通讯连接，从而接收控制芯片输出的控制信号，并转换为对应的驱动信号后输出，完成显示面板的图像显示。本申请解决了在时序控制器读取存储器的数据时，存储器的数据可能窜入至控制芯片，而导致控制芯片的工作紊乱，或者控制芯片的数据信号输出至时序控制器或者存储器，而导致时序控制器读取存储器数据失败的问题。本申请有效的解决了时序控制器软件读取错误的问题，提高了显示装置的可靠性。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请显示面板驱动电路一实施例的功能模块示意图；
图2为本申请显示面板驱动电路另一实施例的功能模块示意图；
图3为本申请显示面板驱动电路一实施例的电路结构示意图。
附图标号说明：
标号 名称 标号 名称
10 存储器 31 第一选通支路
20 控制芯片 32 第二选通支路
30 通讯切换电路 33 D触发器
40 时序控制器 Q1 第一电子开关
50 通讯隔离电路 R1 第一电阻
SCL 时钟线 Q2 第二电子开关
SDA 数据线 R2 第二电阻
VDD 第一直流电源 C 时钟信号输入端
D1 第一单向导通元件 D 数据输入端
D2 第二单向导通元件 Q 数据输出端
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，若本申请实施例中有涉及方向性指示（诸如上、下、左、右、前、后……），则该方向性指示仅用于解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，若本申请实施例中有涉及“第一”、“第二”等的描述，则该“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
本申请提出一种显示面板驱动电路。
参照图1至图3，在本申请一实施例中，该显示面板驱动电路包括：
存储器10；
控制芯片20，所述控制芯片20连接至串行通讯总线；
通讯切换电路30，包括受控端、控制信号输入端及控制信号输出端，所述控制信号输入端经所述串行通讯总线与所述控制芯片20通讯连接；
时序控制器40，包括数据传输端及控制端，所述数据传输端与所述通讯切换电路30的控制信号输出端及所述存储器10的数据输出端连接，所述控制端与所述通讯切换电路30的受控端连接；其中，
所述时序控制器40被配置为，控制所述通讯切换电路30开启时，接收所述控制芯片20输出的控制信号，控制通讯切换电路30关闭时，读取所述存储器10的软体数据。
本实施例中，所述显示面板驱动电路还包括栅极驱动电路及源极驱动电路，所述栅极驱动电路和所述源极驱动电路的受控端分别与所述时序控制器40的输出端连接。
存储器10和时序控制器40均可以设置于时序控制（Timing Controller，TCON）PCB板上，存储器10可以存储用于驱动栅极驱动集成电路和源极驱动集成电路工作的控制信号，并通过串行通讯总线与时序控制器40通讯连接，在显示装置上电工作时，时序控制器40读取存储器10里的控制信号，及其他设定数据进行初始设置，以产生对应的时序控制信号，从而驱动显示装置中的显示面板的源极驱动集成电路及栅极驱动集成电路工作。存储器10的数据在显示装置正常工作时是不能被修改的，一旦被修改，使得设定数据出错，将导致显示装置显示异常。因此，存储器10大多设置写保护引脚（WP pin），并在输入高电平时，可以控制存储器10写入数据，而在低电平时，不能写入数据，此时存储器10仅供时序控制器40读取数据。时序控制板上还设置有电源处理电路，电源处理电路的输出端分别与存储器10及时序控制器40连接。上述实施例中，串行通讯总线可以采用（I2Cnter-Integrated Circuit）通讯总线，当然也可以采用其他的通讯线路来实现，此处不做限制。
该控制芯片20可以设置于显示装置的主控板上，控制芯片20的数量可以是一个，也可以是多个，具体可以根据显示装置的功能进行设定，可以是显示装置的主控制器或者视频处理芯片，当控制芯片20的数量设置为多个时每一控制芯片20均通过串行通讯总线与时序控制器40连接。控制芯片20在显示装置工作时，将R/G/B压缩信号、控制信号经串行通讯总线输出至时序控制器40，电源则通过电源线及电源处理电路。电源处理电路将接收到的电源转换成对应的驱动电源后输出至时序控制板上的电路模块。在显示装置正常工作后，时序控制器40将接收到的R/G/B压缩信号、控制信号转换成适于显示装置中的源极驱动电路和栅极驱动电路的数据信号、控制信号及时钟信号，实现显示面板的图像显示。
需要说明的是，控制芯片20、时序控制器40及存储器10之间均通过串行通讯总线进行通讯连接，并且时序控制器40需要读取存储器10及控制芯片20的数据来实现显示面板的驱动。因此，在时序控制器40读取数据的过程中，可能对其他芯片产生影响，例如在时序控制器40读取存储器10的数据时，存储器10的数据可能窜入至控制芯片20，而导致控制芯片20的工作紊乱，或者在时序控制器40读取存储器10的数据时，控制芯片20的数据信号输出至时序控制器40或者存储器10，而导致时序控制器40读取存储器10数据失败。
为了解决上述问题，本实施例显示面板驱动电路可以设置通讯切换电路30来实现通讯电路的切换。具体地，通讯切换电路30接收时序控制器40输出的控制信号而开启/断开，在显示装置上电时，时序控制器40控制通讯切换电路30关闭，此时时序控制器40通过串行通讯总线与存储器10通讯连接，以读取所述存储器10的软体数据，实现对时序控制器40的初始设置，在这个过程中，通讯切换电路30处于断开状态，因此控制芯片20的数据不会经串行通讯总线输出至存储器10或者时序控制器40，而对时序控制器40读取存储器10数据产生干扰，同时，存储器10的数据也不会窜入至控制芯片20，而导致控制芯片20的功能紊乱。在初始化结束，显示装置进入正常工作状态时，时序控制器40控制通讯切换电路30开启，此时时序控制器40通过串行通讯总线与控制芯片20通讯连接，从而接收控制芯片20输出的控制信号、数据信号及时钟信号，并转换为对应的驱动信号后输出，完成显示面板的图像显示。
本申请通过设置控制芯片20、时序控制器40及存储器10，并通过串行通讯总线进行通讯连接，并通过设置通讯切换电路30串联设置于控制芯片20与时序控制器40之间，通讯切换电路30基于时序控制电路的控制，并在时序控制器40控制通讯切换电路30关闭时，实现时序控制器40与存储器10通讯连接，以使时序控制器40读取存储器10的软体数据，进而完成时序控制器40的初始设置。而在时序控制器40控制通讯切换电路30开启时，实现时序控制器40与控制芯片20通讯连接，从而接收控制芯片20输出的控制信号，并转换为对应的驱动信号后输出，完成显示面板的图像显示。本申请解决了在时序控制器40读取存储器10的数据时，存储器10的数据可能窜入至控制芯片20，而导致控制芯片20的工作紊乱，或者控制芯片20的数据信号输出至时序控制器40或者存储器10，而导致时序控制器40读取存储器10数据失败的问题。本申请有效的解决了时序控制器40软件读取错误的问题，提高了显示装置的可靠性。
参照图1至图3，在一可选实施例中，所述显示面板驱动电路还包括通讯隔离电路50，所述通讯隔离电路50串联设置于所述通讯切换电路30与所述时序控制器40之间，所述通讯隔离电路50被配置为，在所述时序控制器40控制所述通讯切换电路30开启时，将所述控制芯片20输出的控制信号进行隔离后输出。
需要说明的是，在存储器10与时序控制器40的I2C总线上，一般产生有寄生电容、阻抗，而这些电阻及寄生电容会在显示装置上电工作后，产生电磁干扰，这些干扰信号在控制芯片20与时序控制器40通讯连接时，容易通过窜入I2 C总线至控制芯片20。本实施例的通讯隔离电路50可以在控制芯片20与时序控制器40通讯连接时，对控制芯片20输出的控制信号进行通讯隔离后输出，以隔离存储器10与时序控制器40的I2 C总线产生的干扰信号。
进一步地，上述实施例中，所述通讯隔离电路50包括第一单向导通元件D1及第二单向导通元件D2，所述第一单向导通元件D1的输入端与所述第一选通支路31的输出端连接，所述第一单向导通元件D1的输出端与所述时序控制器40的第二数据传输端；
所述第二单向导通元件D2的输入端与所述第二选通支路32的输出端连接，所述第二单向导通元件D2的输出端与所述时序控制器40的第二数据传输端。本实施例中，第一单向导通元件D1和/或第二单向导通元件D2可以采用光耦、二极管等具有隔离特性的单向二极管来实现，本实施例可选采用二极管实现。利用单向导通特性，可以避免在时序控制器40读取存储器10的数据时，存储器10的数据窜入至控制芯片20，而导致控制芯片20的工作紊乱的问题发生，使得时序控制器40与存储芯片之间的通讯影响外部I2 C总线上的其他芯片正常工作。
本实施例通过单向导通元件，还可以避免在通讯选通电路开启时，也即时序控制器40接收控制芯片20的控制信号时，用于连接存储器10与时序控制器40的I2 C总线上的寄生电容、阻抗产生的干扰信号窜入至控制芯片20，而导致控制芯片20的工作紊乱的问题发生，使得时序控制器40与存储芯片之间的通讯影响外部I2 C总线上的其他芯片正常工作。
参照图1至图3，在一可选实施例中，所述串行通讯总线包括数据线SDA和时钟线SCL，所述通讯切换电路30包括第一选通支路31、第二选通支路32及D触发器33，所述D触发器33的时钟信号输入端C与所述时序控制器40的控制端连接，所述D触发器33的数据输入端D与所述第一直流电源VDD连接，所述D触发器33的数据输出端Q与所述第一选通支路31和第二选通支路32的受控端连接，所述第一选通支路31串联设置于所述数据线SDA与所述时序控制器40的一数据传输端之间，所述第二选通支路32串联设置于所述时钟线SCL与所述时序控制器40的另一数据传输端之间。其中，第一直流电源VDD可以是时序控制器的供电电源。
本实施例中，D触发器33基于时序控制器40的控制，用于在接收到时序控制器40输出的上升沿触发信号的时候，将数据输入端D的逻辑准位赋值，也即高电平的第一直流电源VDD给数据输出端，以使数据输出端Q输出高电平的控制信号至第一选通支路31和第二选通支路32，从而控制第一选通支路31和第二选通支路32开启，并实现控制芯片20与时序控制器40的通讯连接。在接收到时序控制器40输出的下降沿触发信号的时候，D触发器33不动作，从而控制第一选通支路31和第二选通支路32断开，以断开控制芯片20与时序控制器40的通讯连接。
参照图1至图3，在一可选实施例中，所述第一选通支路31包括第一电子开关Q1和第一电阻R1，所述第一电子开关Q1的受控端为所述第一选通支路31的受控端，并经所述第一电阻R1的接地，所述第一电子开关Q1的输入端与所数据线SDA连接，所述第一电子开关Q1的输出端与所述书序控制器的第二数据传输端连接。
本实施例中，第一电子开关Q1可以采用三极管、MOS管等开关管来实现，本实施例可选采用N-MOS管来实现。第一电阻R1为下拉电阻，用于输出低电平的控制信号至N-MOS管的栅极，从而使N-MOS管处于截止状态。在显示装置上电时，时序控制器40输出下降沿触发信号，D触发器33不动作，从而使N-MOS管保持截止状态，此时时序控制器40与存储器10通讯连接，实现对时序控制器40的初始设置。在初始化结束，显示装置进入正常工作状态时，时序控制器40输出上升沿触发信号，从而触发D触发器33输出高电平的控制信号控制N-MOS管导通，时序控制器40与控制芯片20通讯连接，完成显示面板的图像显示。
参照图1至图3，在一可选实施例中，所述第二选通支路32包括第二电子开关Q2和第二电阻R2，所述第二电子开关Q2的受控端为所述第二选通支路32的受控端，并经所述第二电阻R2的接地，所述第二电子开关Q2的输入端与所数据线SDA连接，所述第二电子开关Q2的输出端与所述时序控制器40的第二数据传输端连接。
本实施例中，第二电子开关Q2可以采用三极管、MOS管等开关管来实现，本实施例可选采用N-MOS管来实现。第二电阻R2为下拉电阻，用于输出低电平的控制信号至N-MOS管的栅极，从而使N-MOS管处于截止状态。在显示装置上电时，时序控制器40输出下降沿触发信号，D触发器33不动作，从而使N-MOS管保持截止状态，此时时序控制器40与存储器10通讯连接，实现对时序控制器40的初始设置。在初始化结束，显示装置进入正常工作状态时，时序控制器40输出上升沿触发信号，从而触发D触发器33输出高电平的控制信号控制N-MOS管导通，时序控制器40与控制芯片20通讯连接，完成显示面板的图像显示。
参照图1至图3，在一可选实施例中，所述显示面板驱动电路还包括第三单向导通元件（图未示出），所述第三单向导通元件的输入端与所述存储器10连接，所述第三导向导通元件的输出端与所述时序控制器40连接。
需要说明的是，存储器10的数据在显示装置正常工作时是不能被修改的，一旦被修改，使得设定数据出错，将导致显示装置显示异常。因此，存储器10大多设置写保护引脚（WP pin），并在输入高电平时，可以控制存储器10写入数据，而在低电平时，不能写入数据，而对存储器10进行写保护。而在时序控制板与外部的串行通讯总线上存在的寄生电容及阻抗，这样容易导致串行通讯总线上产生杂波串到写保护脚，而出现高电平，从而使存储器10进入写保护状态，此时，若通讯切换电路30接收时序控制器40输出的控制信号而开启，该控制信号将进入至存储器10，导致存储器10的数据被改写。
为了解决上述问题，第三单向导通元件可以采用光耦、二极管等具有隔离特性的单向二极管来实现，本实施例可选采用二极管实现。第三单向导通元件用于防止时序控制器40读取控制芯片20的数据时，控制芯片20的数据窜入至存储器10，而导致存储器10的数据被改写。
本申请还提出一种显示装置，包括显示面板及如上所述的显示面板驱动电路，所述显示面板的栅极驱动电路和所述源极驱动电路分别与所述显示面板电连接。该显示面板驱动电路的详细结构可参照上述实施例，此处不再赘述；可以理解的是，由于在本申请显示装置中使用了上述显示面板驱动电路，因此，本申请显示装置的实施例包括上述显示面板驱动电路全部实施例的全部技术方案，且所达到的技术效果也完全相同，在此不再赘述。
本实施例中，显示装置可以是电视机、平板电脑、手机等具有显示面板的显示装置。
以上所述仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是在本申请的申请构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (20)

  1. 一种显示面板驱动电路，其特征在于，所述显示面板驱动电路包括：
    存储器；
    控制芯片，所述控制芯片连接至串行通讯总线；
    通讯切换电路，包括受控端、控制信号输入端及控制信号输出端，所述控制信号输入端经所述串行通讯总线与所述控制芯片通讯连接；
    时序控制器，包括数据传输端及控制端，所述数据传输端与所述通讯切换电路的控制信号输出端及所述存储器的数据输出端连接，所述控制端与所述通讯切换电路的受控端连接；其中，
    所述时序控制器被配置为，控制所述通讯切换电路开启时，接收所述控制芯片输出的控制信号，控制通讯切换电路关闭时，读取所述存储器的软体数据。
  2. 如权利要求1所述的显示面板驱动电路，其特征在于，所述显示面板驱动电路还包括通讯隔离电路，所述通讯隔离电路串联设置于所述通讯切换电路与所述时序控制器之间，所述通讯隔离电路被配置为，在所述时序控制器控制所述通讯切换电路开启时，将所述控制芯片输出的控制信号进行隔离后输出。
  3. 如权利要求2所述的显示面板驱动电路，其特征在于，所述通讯隔离电路包括第一单向导通元件及第二单向导通元件，所述第一单向导通元件的输入端与所述第一选通支路的输出端连接，所述第一单向导通元件的输出端与所述时序控制器的数据传输端；
    所述第二单向导通元件的输入端与所述第二选通支路的输出端连接，所述第二单向导通元件的输出端与所述时序控制器的数据传输端。
  4. 如权利要求3所述的显示面板驱动电路，其特征在于，所述第一单向导通元件和/或所述第二单向导通元件为二极管。
  5. 如权利要求1所述的显示面板驱动电路，其特征在于，所述串行通讯总线包括数据线和时钟线，所述通讯切换电路包括第一选通支路、第二选通支路及D触发器，所述D触发器的时钟信号输入端与所述时序控制器的控制端连接，所述D触发器的数据输入端与第一直流电源连接，所述D触发器的数据输出端与所述第一选通支路和所述第二选通支路的受控端连接，所述第一选通支路串联设置于所述数据线与所述时序控制器的一数据传输端之间，所述第二选通支路串联设置于所述时钟线与所述时序控制器的另一数据传输端之间。
  6. 如权利要求5所述的显示面板驱动电路，其特征在于，所述第一选通支路包括第一电子开关和第一电阻，所述第一电子开关的受控端为所述第一选通支路的受控端，并经所述第一电阻的接地，所述第一电子开关的输入端与所数据线连接，所述第一电子开关的输出端与所述书序控制器的第二数据传输端连接。
  7. 如权利要求6所述的显示面板驱动电路，其特征在于，所述第一电子开关为三极管或MOS管。
  8. 如权利要求5所述的显示面板驱动电路，其特征在于，所述第一选通支路包括第二电子开关和第二电阻，所述第二电子开关的受控端为所述第二选通支路的受控端，并经所述第二电阻的接地，所述第二电子开关的输入端与所数据线连接，所述第二电子开关的输出端与所述时序控制器的数据传输端连接。
  9. 如权利要求8所述的显示面板驱动电路，其特征在于，所述第二电子开关为三极管或MOS管。
  10. 如权利要求1所述的显示面板驱动电路，其特征在于，所述显示面板驱动电路还包括第三单向导通元件，所述第三单向导通元件的输入端与所述存储器连接，所述第三导向导通元件的输出端与所述时序控制器连接。
  11. 如权利要求1所述的显示面板驱动电路，其特征在于，所述显示面板驱动电路还包括栅极驱动电路及源极驱动电路，所述栅极驱动电路和所述源极驱动电路的受控端分别与所述时序控制器的输出端连接。
  12. 一种显示面板驱动电路，其特征在于，包括：
    存储器；
    多个控制芯片，各所述控制芯片连接至串行通讯总线；
    通讯切换电路，包括受控端、控制信号输入端及控制信号输出端，所述通讯切换电路，所述控制信号输入端经所述串行通讯总线与各所述控制芯片通讯连接；
    单向导通元件，所述单向导通元件的输入端与所述通讯切换电路的控制信号输出端连接；
    时序控制器，包括数据传输端及控制端，所述数据传输端与所述单向导通元件的输出端及所述存储器的数据输出端连接，所述控制端与所述通讯切换电路的受控端连接；其中，
    所述时序控制器被配置为，控制所述通讯切换电路开启时，接收所述控制芯片输出的控制信号，控制通讯切换电路关闭时，读取所述存储器的软体数据。
  13. 一种显示装置，其特征在于，包括显示面板及如权利要求1所述的显示面板驱动电路，所述显示面板的栅极驱动电路和所述源极驱动电路分别与所述显示面板电连接；所述显示面板驱动电路包括：
    存储器；
    控制芯片，所述控制芯片连接至串行通讯总线；
    通讯切换电路，包括受控端、控制信号输入端及控制信号输出端，所述控制信号输入端经所述串行通讯总线与所述控制芯片通讯连接；
    时序控制器，包括数据传输端及控制端，所述数据传输端与所述通讯切换电路的控制信号输出端及所述存储器的数据输出端连接，所述控制端与所述通讯切换电路的受控端连接；其中，
    所述时序控制器被配置为，控制所述通讯切换电路开启时，接收所述控制芯片输出的控制信号，控制通讯切换电路关闭时，读取所述存储器的软体数据。
  14. 如权利要求13所述的显示装置，其特征在于，所述显示装置还包括通讯隔离电路，所述通讯隔离电路串联设置于所述通讯切换电路与所述时序控制器之间，所述通讯隔离电路被配置为，在所述时序控制器控制所述通讯切换电路开启时，将所述控制芯片输出的控制信号进行隔离后输出。
  15. 如权利要求14所述的显示装置，其特征在于，所述通讯隔离电路包括第一单向导通元件及第二单向导通元件，所述第一单向导通元件的输入端与所述第一选通支路的输出端连接，所述第一单向导通元件的输出端与所述时序控制器的数据传输端；
    所述第二单向导通元件的输入端与所述第二选通支路的输出端连接，所述第二单向导通元件的输出端与所述时序控制器的数据传输端。
  16. 如权利要求14所述的显示装置，其特征在于，所述串行通讯总线包括数据线和时钟线，所述通讯切换电路包括第一选通支路、第二选通支路及D触发器，所述D触发器的时钟信号输入端与所述时序控制器的控制端连接，所述D触发器的数据输入端与第一直流电源连接，所述D触发器的数据输出端与所述第一选通支路和所述第二选通支路的受控端连接，所述第一选通支路串联设置于所述数据线与所述时序控制器的一数据传输端之间，所述第二选通支路串联设置于所述时钟线与所述时序控制器的另一数据传输端之间。
  17. 如权利要求16所述的显示装置，其特征在于，所述第一选通支路包括第一电子开关和第一电阻，所述第一电子开关的受控端为所述第一选通支路的受控端，并经所述第一电阻的接地，所述第一电子开关的输入端与所数据线连接，所述第一电子开关的输出端与所述书序控制器的第二数据传输端连接。
  18. 如权利要求16所述的显示装置，其特征在于，所述第二选通支路包括第二电子开关和第二电阻，所述第二电子开关的受控端为所述第二选通支路的受控端，并经所述第二电阻的接地，所述第二电子开关的输入端与所数据线连接，所述第二电子开关的输出端与所述时序控制器的数据传输端连接。
  19. 如权利要求13所述的显示装置，其特征在于，所述显示面板驱动电路还包括第三单向导通元件，所述第三单向导通元件的输入端与所述存储器连接，所述第三导向导通元件的输出端与所述时序控制器连接。
  20. 如权利要求13所述的显示装置，其特征在于，所述显示面板驱动电路还包括栅极驱动电路及源极驱动电路，所述栅极驱动电路和所述源极驱动电路的受控端分别与所述时序控制器的输出端连接。
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