WO2018103417A1 - 终端设备、读写设备、数据传输系统和硬件初始化方法 - Google Patents

终端设备、读写设备、数据传输系统和硬件初始化方法 Download PDF

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Publication number
WO2018103417A1
WO2018103417A1 PCT/CN2017/103290 CN2017103290W WO2018103417A1 WO 2018103417 A1 WO2018103417 A1 WO 2018103417A1 CN 2017103290 W CN2017103290 W CN 2017103290W WO 2018103417 A1 WO2018103417 A1 WO 2018103417A1
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WIPO (PCT)
Prior art keywords
resistor
serial bus
universal serial
bus interface
switch
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PCT/CN2017/103290
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English (en)
French (fr)
Inventor
刘伟
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广州视源电子科技股份有限公司
广州视睿电子科技有限公司
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Publication of WO2018103417A1 publication Critical patent/WO2018103417A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0042—Universal serial bus [USB]

Definitions

  • Embodiments of the present invention relate to data transmission technologies, and in particular, to a terminal device, a read/write device, a data transmission system, and a hardware initialization method.
  • USB Universal Serial Bus
  • USB is an external bus standard that regulates the connection and communication between a computer and an external device. Since its introduction in 1996, USB has successfully replaced serial and parallel ports, and has become one of the must-have interfaces for personal computers and a large number of smart devices in the 21st century.
  • USB interface With the popularity of the USB interface, more and more devices (such as smart phones, tablets, etc.) will be equipped with a USB interface and transmit data through the USB interface.
  • it When transferring data through the USB interface, it is generally a device configured with a USB female port to control the entire data transmission process.
  • the external device connected to the device configured with the USB female port through the USB male port is only configured according to the USB.
  • the command of the device of the female port to complete the related operations of data transmission does not have any leading role.
  • the embodiments of the present invention provide a terminal device, a read/write device, a data transmission system, and a hardware initialization method, to solve the problem in the prior art that no device is equipped with a universal serial bus interface. The data cannot be read through the universal serial bus interface connection. question.
  • an embodiment of the present invention provides a terminal device, including:
  • a first universal serial bus interface an uplink port, a downlink port, a switch, a first controller, and a first switch circuit
  • the first universal serial bus interface is configured to be connected to a second universal serial bus interface of the external device, and the signal pin thereof is grounded; the uplink port and the downlink port both pass the switch and the a data transmission end of the first universal serial bus interface is connected, and the on-off state is switched by the switch; the first end of the first switch circuit is connected to a power pin of the first universal serial bus interface, The second end of the first switch circuit is connected to a power source;
  • the first control end of the first controller is connected to the controlled end of the switch, and sends a signal to control the switch to switch between the uplink port and the downlink port;
  • the second control end is connected to the controlled end of the first switch circuit, and the transmit signal controls the on and off of the first switch circuit;
  • the signal input end of the first controller is connected to the first universal serial bus
  • the voltage detection data of the power pin of the interface transmits a signal to the switch and the first switch circuit according to the voltage detection data.
  • the method further includes:
  • the first end of the current limiting circuit is connected to a power pin of the first universal serial bus interface, and the third end of the current limiting circuit is connected to a signal input end of the first controller The second end of the current limiting circuit is coupled to the first end of the first switching circuit.
  • the current limiting circuit includes: a current limiting switch, a resistor R1 and a resistor R2; a first end of the current limiting switch and a first end of the resistor R1 and the first universal a power pin of the serial bus interface is connected, and the second end of the current limiting switch is opposite to the first end of the first switch circuit
  • the second end of the resistor R1 is connected to the first end of the resistor R2 and the signal input end of the first controller; the second end of the resistor R2 is grounded.
  • the first switch circuit includes: a resistor R3, a resistor R4, a resistor R5, a transistor Q2, and a MOS transistor Q1; a first end of the resistor R3 and a first controller
  • the second end of the resistor R3 is connected to the base of the transistor Q2; the emitter of the transistor Q2 is grounded, the collector of the transistor Q2 and the first end of the resistor R4
  • the first end of the resistor R5 is connected;
  • the second end of the resistor R4 is connected to the source of the MOS transistor Q1 and is connected to the power source;
  • the second end of the resistor R5 is connected to the gate of the MOS transistor Q1.
  • the drain of the MOS transistor Q1 is connected to the second end of the current limiting circuit.
  • an embodiment of the present invention provides a reading and writing device, including:
  • a second universal serial bus interface a second controller, a trigger circuit, a second switch circuit, and a third switch circuit;
  • a signal pin of the second universal serial bus interface is connected to a detection end of the trigger circuit,
  • the signal input end of the second controller is connected to the feedback end of the trigger circuit, and sends a signal to the third switch circuit according to the change of the feedback terminal voltage of the trigger circuit;
  • a signal pin of the second universal serial bus interface is connected to a signal pin of the first universal serial bus interface; and a data processing end of the second controller is interfaced with the second universal serial bus
  • the data transmission end is connected to read and write data through the second universal serial bus interface;
  • the first control end of the second controller is connected to the controlled end of the second switch circuit, and sends a signal to control the first a second switch circuit is connected to the controlled end of the third switch circuit, and sends a signal to control the on/off of the third switch circuit;
  • the second switch a first end of the circuit is connected to the power source, a second end of the second switch circuit is connected to a power pin of the second universal serial bus interface; and the first end of the third switch circuit is opposite to the second The universal serial bus interface power supply pin is connected, and the second end of the third switching circuit is grounded.
  • the trigger circuit includes a transistor Q3, a resistor R6, a resistor R7 and a resistor R8, and the first end of the resistor R6 is connected to a signal pin of the second universal serial bus interface;
  • the second end of the resistor R6 is connected to the base of the transistor Q3 and the first end of the resistor R7;
  • the second end of the resistor R7 is connected to the first end of the resistor R8 and is connected to +5V a voltage;
  • a second end of the resistor R8 is coupled to a collector of the transistor Q3 and a signal input of the second controller; an emitter of the transistor Q3 is grounded.
  • the second switch circuit includes a resistor R9, a resistor R10, a resistor R11, a transistor Q4, and a MOS transistor Q5; the first end of the resistor R9 and the first end of the second controller a control terminal is connected; a second end of the resistor R9 is connected to a base of the transistor Q4; an emitter of the transistor Q4 is grounded, a collector of the transistor Q4 is connected to a first end of the resistor R10, and a first end of the resistor R11 is connected; a second end of the resistor R10 is connected to a source of the MOS transistor Q5 and is connected to a power source; a second end of the resistor R11 is connected to a gate of the MOS transistor Q5; The drain of the MOS transistor Q5 is connected to a power supply pin of the second universal serial bus interface.
  • the third switch circuit includes a resistor R13, a resistor R12, and a transistor Q6; a first end of the resistor R13 is connected to a second control end of the second controller, the resistor a second end of the R13 is connected to a base of the transistor Q6; an emitter of the transistor Q6 is grounded, a collector of the transistor Q6 is connected to a first end of the resistor R12, and a second end of the resistor R12 Connected to a power pin of the second universal serial bus interface.
  • an embodiment of the present invention provides a data transmission system, including the foregoing terminal device and the read/write device.
  • an embodiment of the present invention provides a hardware initialization method, which is used in the foregoing data transmission system, and includes:
  • the first controller turns on the first switch circuit, switches the switch to turn on the downlink port, and the second controller turns off the second switch circuit and the third switch circuit ;
  • the second controller When the second controller receives the valid signal detected by the trigger circuit indicating that the second universal serial bus interface is inserted into the first universal serial bus interface, the second controller turns on the The third switching circuit starts counting;
  • the signal input end of the first controller detects that the input is 0, switches the switch to turn on the uplink port, and disconnects The first switching circuit
  • the second controller When the timing reaches a preset duration, the second controller turns on the second switching circuit and turns off the third switching circuit.
  • the method further includes:
  • the second controller When the second controller receives a valid signal detected by the trigger circuit indicating that the second universal serial bus interface is disconnected from the first universal serial bus interface, the second controller is off The second switch circuit and the third switch circuit are turned on.
  • the terminal device, the read/write device, the data transmission system, and the hardware initialization method provided by the embodiment of the present invention by configuring a first universal serial bus interface, an uplink port, a downlink port, a switch, a first controller, and a a circuit device such as a switch circuit, wherein a second universal serial bus interface, a second controller, a trigger circuit, a second switch circuit, and a third switch circuit are disposed in the read/write device, so that the terminal device and the read/write device After being connected, the terminal device can be controlled by the first universal serial bus interface and the second universal serial bus interface, and the terminal device is sent according to the read/write device.
  • the transmitted command transmits data, which solves the technical problem that the internal data of the device in the prior art is not read by the universal serial bus interface connection, and the technical problem is solved.
  • a device configured with a universal serial bus interface is connected to an external device through a universal serial bus interface, the external device can actively read internal data of a device configured with a universal serial bus interface.
  • FIG. 1 is a structural diagram of a terminal device according to Embodiment 1 of the present invention.
  • FIG. 1b is a structural diagram of a first switch circuit according to Embodiment 1 of the present invention.
  • 1c is a connection diagram of a device for using a universal serial bus interface as an uplink port and a universal serial bus interface according to Embodiment 1 of the present invention
  • FIG. 2 is a structural diagram of another terminal device according to Embodiment 2 of the present invention.
  • FIG. 3 is a structural diagram of a reading and writing device according to Embodiment 3 of the present invention.
  • FIG. 3b is a structural diagram of a second switch device according to Embodiment 3 of the present invention.
  • Embodiment 4 is a flowchart of a hardware initialization method according to Embodiment 5 of the present invention.
  • FIG. 1 is a structural diagram of a terminal device according to Embodiment 1 of the present invention.
  • the structure of the terminal device in this embodiment specifically includes:
  • a first universal serial bus interface 110 an uplink port 150, a downlink port 160, a switch 170, a first controller 140 and a first switch circuit 130;
  • the first universal serial bus interface 110 is configured to be connected to a universal serial bus interface of an external device, and its signal pin is grounded; the upstream port 150 and the downstream port 160 are both connected to the first universal serial bus interface 110 through the switch 170.
  • the data transmission end is connected, and the on-off state is switched by the switch 170; the first end of the first switch circuit 130 is connected to the power pin of the first universal serial bus interface 110, and the second end of the first switch circuit 130 is connected.
  • 5V system power supply namely System 5V;
  • the first control end of the first controller 140 is connected to the controlled end of the switch 170, and the transmit signal Switch CTL controls the switch 170 to switch between the uplink port and the downlink port; the second control end of the first controller 140
  • the controlled end of a switching circuit 130 is connected, and the transmitting signal 5V_CTL controls the first
  • the switching circuit 130 is turned on and off; the signal input end of the first controller 140 is connected to the voltage detection data of the power pin of the first universal serial bus interface 110, and is switched to the switch 170 and the first switch circuit 130 according to the voltage detection data.
  • Send signals Switch CTL and 5V_CTL Send signals Switch CTL and 5V_CTL.
  • the first switch circuit 130 is optimized to include a resistor R3, a resistor R4, a resistor R5, a transistor Q2, and a MOS transistor Q1; a first end of the resistor R3 and a second end of the first controller 140
  • the control terminal is connected to receive the signal 5V_CTL; the second end of the resistor R3 is connected to the base of the transistor Q2; the emitter of the transistor Q2 is grounded, the collector of the transistor Q2 and the first end of the resistor R4 and the first end of the resistor R5 Connected; the second end of the resistor R4 is connected to the source of the MOS transistor Q1 and connected to the power supply System 5V; the second end of the resistor R5 is connected to the gate of the MOS transistor Q1; the drain of the MOS transistor Q1 is connected to the current limiting circuit 120 The second end is connected to receive the power source VCC_out.
  • the second control terminal output signal 5V_CTL of the first controller 140 is at a high level, so that the controlled terminal input of the first switch circuit 130 is at a high level. That is, the first terminal input of the resistor R3 is at a high level, so that the transistor Q2 is turned on, and the second end of the resistor R4 is connected to the power supply System 5V, so that the MOS transistor Q1 is turned on, thereby allowing the connected power supply System 5V to pass.
  • the MOS transistor Q1 is output from the drain of Q1 to the power supply pin of the first universal serial bus interface 110.
  • the voltage detection data of the power pin of the first universal serial bus interface 110 is defined as 5V Det, and therefore, the signal 5V Det input by the signal input end of the first controller 140 is at a high level, when the first controller 140 detects When the input signal 5V Det is at a high level, the first controller 140 controls the switching switch 170 to switch to the downstream port 160 through the first control terminal output control signal Switch CTL, so that the data transmission end of the first universal serial bus interface 110 is connected to Downstream port 160.
  • Figure 1c shows a device 310 with a universal serial bus interface as an upstream port, where the outer serial port and signal pins of the universal serial bus interface are grounded.
  • the terminal device in FIG. 1a does not change internally, and continues to maintain the initial state, and may be the same as that in FIG. 1c.
  • the universal serial bus interface communicates as a device on the uplink port for data transmission.
  • the terminal device in this embodiment needs to be read by other devices, after the first universal serial bus interface 110 in FIG. 1a is inserted into the universal serial bus interface of the dedicated reading device, The power supply pin of a universal serial bus interface 110 is grounded, so that the input signal 5V Det of the first controller 140 is 0.
  • the first controller 140 detects that the input signal 5V Det becomes 0, the first controller 140
  • the output signal 5V_CTL is changed to 0, and the input of the controlled terminal of the first switching circuit 130 becomes 0, which causes the transistor Q2 to be turned off, and the MOS transistor Q1 is turned off, and the power supply System 5V to which the resistor R4 is connected cannot be output to the first through the MOS transistor Q1.
  • the power supply pin of the universal serial bus interface 110 After detecting that the input signal 5V Det becomes 0, the first controller 140 also controls the switch 170 to switch to the uplink port 150, thereby completing the first universal serial bus interface 110 from the downlink port to the uplink port. change.
  • the downlink port specifically refers to another universal serial port that is connected to the data transmission process through the universal serial bus interface.
  • the bus interface provides power and a universal serial bus interface that plays a leading role in the data transfer process.
  • the above “another universal serial bus interface” is the uplink port. That is to say, the so-called “upstream” and “downstream” herein do not refer to the flow of data during data transmission, but to the difference in the master-slave status of the two universal serial bus interfaces docked during data transmission. Name it.
  • the terminal device configureds the circuit components such as the first universal serial bus interface 110, the uplink port 150, the downlink port 160, the switch 170, the first controller 140, and the first switch circuit 130 in the terminal device. Therefore, the first universal serial bus interface 110 can be multiplexed into the downlink port 160 or the uplink port 150, which solves the problem in the prior art that no device is configured with the universal serial bus interface, and the internal data cannot pass through.
  • a technical problem in which a universal serial bus interface connection is read, and when a device configured with a universal serial bus interface is connected to an external device through a universal serial bus interface, the external device can actively read and configure a universal serial bus. The internal data of the device of the interface.
  • Embodiment 2 of the present invention provides a structural diagram of a terminal device.
  • the embodiment is optimized based on the above embodiment.
  • the method further includes: a current limiting circuit 120, the first end of the current limiting circuit 120 and the first universal serial bus interface 110.
  • the power pin ie, the output or the +5V pin
  • the third end of the current limiting circuit 120 is connected to the signal input end of the first controller 140 for outputting the signal 5V Det, and the current limiting circuit 120
  • the two ends are connected to the first end of the first switch circuit 130;
  • the current limiting circuit 120 is optimized to include a current limiting switch 180, a resistor R1 and a resistor R2; a first end of the current limiting switch 180 and a first end of the resistor R1 and a power supply of the first universal serial bus interface 110
  • the pin is connected to output a power supply voltage USB5V to the power pin of the first universal serial bus interface 110, and the second end of the current limiting switch 180 is connected to the first end of the first switch circuit 130; the second end of the resistor R1 is The first end of the resistor R2 is connected to the signal input end of the first controller 140; the second end of the resistor R2 is grounded.
  • the second control terminal output signal 5V_CTL of the first controller 140 is at a high level, so that the controlled terminal input of the first switch circuit 130 is high.
  • the level, that is, the input of the first end of the resistor R3 is a high level, so that the transistor Q2 is turned on, and at the same time, the second end of the resistor R4 is connected to the power system 5V, so that the MOS transistor Q1 is turned on, thereby making the power supply system 5V is output from the drain of Q1 through the MOS transistor Q1 to the second end of the current limiting circuit 120, that is, the second end of the current limiting switch 180.
  • the System 5V is output to the power supply pin of the first universal serial bus interface 110 through the current limiting switch 180, and at the same time, the System 5V Grounding through the resistor R1 and the resistor R2, so that the second end of the resistor R1 (connected to the first end of the resistor R2) assumes a high level, and therefore, the input signal 5V Det of the first controller 140 is at a high level.
  • the first controller 140 When the first controller 140 detects that the input signal 5V Det is at a high level, the first controller 140 controls the switch 170 to switch to the downstream port 160 through the first control end output control signal Switch CTL, so that the first universal serial bus interface 110 The data transmission end is connected to the downstream port 160.
  • the terminal device in FIG. 2 When the device 310 of the universal serial bus interface as the uplink port in FIG. 1c is inserted into the first universal serial bus interface 110 in FIG. 2, the terminal device in FIG. 2 does not change internally, and continues to maintain the initial state, and Data can be transmitted normally with the device of Figure 1c, which uses the universal serial bus interface as the uplink port.
  • the first universal serial bus interface 110 in FIG. 2 is inserted into the universal serial bus interface of the dedicated reading device.
  • the power pin of a universal serial bus interface 110 is grounded, thereby triggering the current limiting switch 180 of FIG. 2, so that the output of the first terminal of the current limiting switch 180 is 0, that is, the input of the first end of the resistor R1 is 0, therefore,
  • the input signal 5V Det of the first controller 140 is 0.
  • the first controller 140 When the first controller 140 detects that the input signal 5V Det becomes 0, the first controller 140 changes the output signal 5V_CTL to 0, and thus the first switch circuit 130 The input of the controlled terminal becomes 0, which causes the transistor Q2 to be turned off, and then the MOS transistor Q1 is turned off, and the power supply system 5V to which the resistor R4 is connected cannot be output to the second end of the current limiting circuit 120 through the MOS transistor Q1. After detecting that the input signal 5V Det becomes 0, the first controller 140 also controls the switch 170 to switch to the uplink port 150, thereby completing the first universal serial bus interface 110 from the downlink port to the uplink port. change.
  • the function of the current limiting switch 180 is that when the current passing through the current limiting switch is greater than a preset threshold, the current limiting switch is automatically turned off, so that the circuit at both ends of the current limiting switch is broken. Since the current limiting switch belongs to the prior art, it will not be elaborated here.
  • the terminal device configureds the first universal serial bus interface 110, the uplink port 150, the downlink port 160, the switch 170, the first controller 140, the current limiting circuit 120, and the first switch in the terminal device.
  • the circuit device such as the circuit 130 enables the first universal serial bus interface 110 to be multiplexed into the downlink port 160 or the uplink port 150, which solves the problem in the prior art that no device is equipped with the universal serial bus interface, and the internal The data cannot be read through the universal serial bus interface connection.
  • the external device can actively read the configuration. Internal data for devices with a universal serial bus interface.
  • FIG. 3 is a structural diagram of a reading and writing device according to Embodiment 3 of the present invention, which specifically includes:
  • a second universal serial bus interface 230 a second controller 250, a trigger circuit 240, a second switch circuit 210, and a third switch circuit 220; a signal pin Signal_GND of the second universal serial bus interface 230 and the trigger
  • the detecting end of the circuit 240 is connected to the signal input end of the second controller 250.
  • the signal transmitted between the two is defined as Insert Det, which is specifically used for Describe a voltage state at which the second universal serial bus interface 230 is connected;
  • the signal pin of the second universal serial bus interface 230 is used to connect to the signal pin of the first universal serial bus interface 110; the data processing end of the second controller 250 and the second universal serial bus interface 230 The data transmission end is connected to read and write data through the second universal serial bus interface 230; the first control end of the second controller 250 is connected to the controlled end of the second switch circuit 210, and the signal ON/OFF_CTL is controlled to control the second switch.
  • the second control terminal of the second controller 250 is connected to the controlled end of the third switch circuit 220, and the transmit signal CTL controls the on and off of the third switch circuit 220, and the second controller 250 according to the signal Insert Det determines the specific control content of the ON/OFF_CTL and the CTL; the first end of the second switch circuit 210 is connected to the +5V power supply, and the second end of the second switch circuit 210 and the power pin of the second universal serial bus interface 230 ( That is, the output or the +5V pin is connected, and the power supply VCC_out' is output to the power pin of the second universal serial bus interface 230; the first end of the third switch circuit 220 and the second universal serial bus interface 230 The power pins are connected, and the second end of the third switch circuit 220 is grounded.
  • the trigger circuit 240 is optimized to include a transistor Q3, a resistor R6, a resistor R7 and a resistor R8.
  • the first end of the resistor R6 is connected to the signal pin of the second universal serial bus interface 230; the second end of the resistor R6 Connected to the base of the transistor Q3 and the first end of the resistor R7; the second end of the resistor R7 is connected to the first end of the resistor R8 and is connected to the +5V voltage; the second end of the resistor R8 is connected to the collector of the transistor Q3 and
  • the signal input end of the second controller 250 is connected, and the output signal Insert Det; the emitter of the transistor Q3 is grounded.
  • the second switch circuit 210 is optimized to include a resistor R9, a resistor R10, a resistor R11, a transistor Q4, and a MOS transistor Q5.
  • the first end of the resistor R9 is connected to the first control terminal of the second controller 250 for Receiving ON/OFF_CTL; the second end of the resistor R9 is connected to the base of the transistor Q4; the emitter of the transistor Q4 is grounded, the collector of the transistor Q4 is connected to the first end of the resistor R10 and the first end of the resistor R11;
  • the second end is connected to the source of the MOS transistor Q5 and connected to the power supply; the second end of the resistor R11 is connected to the gate of the MOS transistor Q5; the drain of the MOS transistor Q5 is connected to the power pin of the USB male port 230, and the power is turned on.
  • VCC_out' is output to the power supply pin.
  • the third switch circuit 220 is optimized to include a resistor R13, a resistor R12 and a transistor Q6; a first end of the resistor R13 is connected to the second control terminal of the second controller 250 for outputting the CTL to the resistor R13.
  • the first end of the resistor R13 is connected to the base of the transistor Q6; the emitter of the transistor Q6 is grounded, the collector of the transistor Q6 is connected to the first end of the resistor R12, and the second end of the resistor R12 is connected to the second universal string.
  • the power pins of the row bus interface 230 are connected.
  • the initial state of the read/write device in FIG. 3a is that the ON/OFF_CTL and CTL output by the first control terminal and the second control terminal of the second controller 250 are both low.
  • the first control terminal output ON/OFF_CTL of the second controller 250 is at a low level
  • the first terminal input of the resistor R9 is at a low level
  • the transistor Q4 is turned off
  • the MOS transistor Q5 is also turned off. That is, the drain of Q5 has no voltage output, so the power supply pin of the second universal serial bus interface 230 has no voltage input.
  • the CTL outputted by the second control terminal of the second controller 250 is at a low level.
  • the first terminal input of the resistor R13 is at a low level, and the transistor Q6 is turned off.
  • the +5V power supply is connected to the trigger circuit 240, thereby turning on the transistor Q3, and the collector of Q3 exhibits a low level. Therefore, the second controller 250 inputs the Insert Det to a low level.
  • the read/write device in this embodiment uses the second universal serial bus interface 230 as an external port, and the trigger circuit 240 is disposed in the second universal serial bus interface 230, when a universal serial bus interface is required from an unconventional setting.
  • the trigger circuit 240 and the plurality of switch circuits inside the read/write device realize the establishment of the data channel based on the universal serial bus interface, and the universal serial bus interface is provided. Read data from the storage device.
  • the fourth embodiment of the present invention further provides a data transmission system, which may specifically include the terminal device in FIG. 2 and the read/write device in FIG. 3a.
  • the structure in FIG. 2 and FIG. 3a can already reflect the basic architecture of the data transmission system. No further illustration is given here.
  • the second universal serial bus interface 230 of the read/write device in FIG. 3a When the second universal serial bus interface 230 of the read/write device in FIG. 3a is inserted into the first universal serial bus interface 110 of the terminal device in FIG. 2 (generally the terminal device in FIG. 2 fails, the data cannot be controlled.
  • the internal device and the read/write device may undergo corresponding changes, and the specific process is as follows:
  • the second universal serial bus interface 230 is coupled to the first universal serial bus interface 110.
  • the signal pin of the second universal serial bus interface 230 is also grounded, causing the first end of the resistor R6 to be grounded, because the ratio of the resistor R6 and the resistor R7 satisfies the relationship of the following formula [5/(R6+R7)] ⁇ R6 ⁇ 0.5, therefore, the transistor Q3 is turned off, the collector of Q3 outputs a high level, and the second controller 250 inputs Insert Det to a high level.
  • the second controller 250 When the second controller 250 detects that the input Insert Det changes from a low level to a high level, the second controller 250 starts timing while causing the output CTL to become a high level. At this time, the first end of the resistor R13 is input. The high level, the transistor Q6 is turned on. Since the power pin of the second universal serial bus interface 230 is connected to the power pin of the first universal serial bus interface 110, the second universal serial bus interface is connected. The power supply pin of 230 is connected to the power supply system 5V, causing the power supply system 5V to be grounded through the resistor R12 and the transistor Q6, so that the current flowing through the current limiting switch 180 in the current limiting circuit 120 is greater than a preset current threshold, thereby triggering the current limiting switch 180. The current limiting switch 180 is turned off, and the third terminal output of the current limiting circuit 120 is 0. Therefore, the first controller 140 inputs 5V Det is also 0.
  • the first controller 140 When the first controller 140 detects that the voltage of the input 5V Det changes as described above, it will output 5V_CTL goes low, and at the same time, by switching the command Switch CTL to the switch 170, the switch 170 is connected to the uplink port 150, thereby connecting the first universal serial bus interface 110 to the uplink port 150. After the first controller 140 outputs 5V_CTL to a low level, the transistor Q2 is turned off, and the MOS transistor Q1 is turned off. Therefore, the power supply Systme 5V cannot be transmitted to the second end of the current limiting circuit 120 through Q2.
  • the second controller 250 when the second controller 250 detects that the input Insert Det changes from low level to high level, the second controller 250 starts timing, and when the second controller 250 reaches the preset duration, the output CTL is output. It goes low and the output ON/OFF_CTL goes high.
  • the preset duration specifically refers to the time required to connect the collector of the above Q3 to the high level to the switch 170 and the uplink port 150. The specific value of the preset duration can be tested by the actual debugging process. Of course, the preset duration may also be greater than the time required to change from the collector of the above Q3 to the high level to the connection of the switch 170 to the upstream port 150.
  • the universal serial bus interface serving as the downlink port supplies power to the universal serial bus interface as the uplink port, so the above switching must be waited for.
  • the power pin of the second universal serial bus interface 230 in the read/write device can be connected to the +5V power supply of the first end of the second switch circuit 210.
  • the second controller 250 After the second controller 250 counts the preset time length, the second controller 250 outputs CTL to a low level, and the second controller 250 outputs ON/OFF_CTL to a high level.
  • the transistor Q6 when the second controller 250 outputs CTL to a low level, the transistor Q6 is turned off, and the power pins of the second universal serial bus interface 230 and the first universal serial bus interface 110 no longer pass through the resistor R12 and the transistor Q6. Ground.
  • the output of the second controller 250 turns ON/OFF_CTL to a high level, the transistor Q4 and the MOS transistor Q5 are both turned on, and the power supply +5V of the second end of the resistor R10 is output to the second universal through the MOS transistor Q5.
  • the power pin is connected to the power supply +5V through the second universal serial bus interface 230, and the power source connected to the first universal serial bus interface 110 is grounded through the resistor R1 and the resistor R2, so that the second end of the resistor R1 is high. Therefore, the input 5V Det of the signal input end of the first controller 140 is converted from a low level to a high level. At this point, the data transmission system composed of the terminal device and the read/write device completes the terminal device through the hardware initialization method.
  • the internal first universal serial bus interface 110 is transitioned from the downstream port 160 to the upstream port 150.
  • the power pin of the first universal serial bus interface 110 can no longer be connected to the +5V power supply through the second universal serial bus interface 230. Therefore, the first controller The 140 input 5V Det is again converted from a high level to a low level. When the first control 140 detects that the input 5V Det is converted from a high level to a low level, the first controller 140 sends a command Switch to the switch 170.
  • the CTL causes the switch 170 to switch to the downstream port 160, so that the first universal serial bus interface 110 is connected to the downstream port 160, and at the same time, the first control terminal 140 also changes the output 5V_CTL to a high level, so that the first switch
  • the circuit 130 is turned on, and the power system 5V is transmitted to the power pin of the first universal serial bus interface 110 through the first switch circuit 130 and the current limiting circuit 120, and at the same time, the first controller 140 inputs 5V Det and is low level. It is converted to a high level, and the terminal device returns to the initial state.
  • the signal pin of the second universal serial bus interface 230 of the read/write device is no longer grounded, and the +5V power supply in the trigger circuit 240 re-energizes the transistor Q3, and then the transistor Q3
  • the collector output is high, so that the second controller 250 inputs Insert Det from low level to high level, and when the second controller 250 detects the above change of the input Insert Det, the second controller 250 outputs ON/OFF_CTL is set to low level and returns to the initial state.
  • the terminal device, the read/write device, the data transmission system, and the hardware initialization method provided by the embodiment of the present invention by configuring the first universal serial bus interface 110, the uplink port 150, and the downlink end in the terminal device a circuit device such as a port 160, a switch 170, a first controller 140, a current limiting circuit 120, and a first switch circuit 130, and a second universal serial bus interface 230, a second controller 250, and a trigger circuit are disposed in the read/write device.
  • circuit devices such as the second switch circuit 210 and the third switch circuit 220, so that when the terminal device is connected to the read/write device to form a data transmission system, the terminal device can pass the first universal serial bus interface through a hardware initialization method.
  • the terminal device 110 and the second universal serial bus interface 230 are controlled by the read/write device, and the terminal device performs data transmission according to the command sent by the read/write device, which solves the problem in the prior art that no device is equipped with the universal serial bus interface.
  • the fifth embodiment of the present invention further provides a hardware initialization method for the above data transmission system, so that the above data transmission system completes the designed universal serial bus interface connection to realize data reading in an abnormal state, and the specific process It has been described in the embodiments of the data transmission system and is only briefly described herein.
  • the hardware initialization method includes:
  • Step 410 the first controller 140 turns on the first switch circuit 130, switches the switch 170 to turn on the downstream port 160, and the second controller 250 turns off the second switch circuit 210 and the third switch circuit 220;
  • Step 420 When the second controller 250 receives the valid signal that is detected by the trigger circuit and indicates that the second universal serial bus interface 230 is inserted into the first universal serial bus interface 110, the second controller 250 turns on the third switch circuit 220. And start timing;
  • Step 430 When the power pin of the first universal serial bus interface 110 is grounded, the signal input end of the first controller 140 detects that the input is 0, switches the switch 170 to turn on the uplink port 150, and disconnects the first a switching circuit 130;
  • Step 440 when the timing reaches a preset duration, the second controller 250 turns on the second switch circuit 210, and turns off the third switch circuit 220;
  • Step 450 when the signal input end of the first controller 140 detects that the third end of the current limiting circuit 120 changes from a high level to a low level, the switching switch 170 is switched to be turned on the downlink port;
  • Step 460 when the second controller 250 receives the valid signal detected by the trigger circuit indicating that the second universal serial bus interface 230 is pulled out from the first universal serial bus interface 110, the second controller 250 disconnects the second The switch circuit 210 and the third switch circuit 220.
  • the hardware initialization method provided by the embodiment of the present invention controls the on and off of the first to third switch circuits and the switch-on of the switch 170 by the first controller 140 and the second controller 250 before the terminal device and the read/write device are connected.
  • the internal data of the device of the interface is read, and when a device configured with a universal serial bus interface is connected to an external device through a universal serial bus interface, the external device can actively read and configure a universal serial bus. The internal data of the device of the interface.
  • embodiments of the invention may be executable by a computer device
  • the programs are implemented such that they can be stored in a storage device for execution by a processor, and the programs can be stored in a computer readable storage medium, which can be a read only memory, a magnetic disk or a magnetic disk. Etc.; or make them separately into individual integrated circuit modules, or make multiple modules or steps of them into a single integrated circuit module.
  • the invention is not limited to any specific combination of hardware and software.

Abstract

一种终端设备、读写设备、数据传输系统和硬件初始化方法，通过在终端设备中配置第一通用串行总线接口（110）、上行端口（150）、下行端口（160）、切换开关（170）、第一控制器（140）和第一开关电路（130）等电路器件，在读写设备中配置第二通用串行总线接口（230）、第二控制器（250）、触发电路（240）、第二开关电路（210）和第三开关电路（220）等电路器件，使得终端设备与读写设备相连后，终端设备可以通过第一通用串行总线接口（110）和第二通用串行总线接口（230）受控于读写设备，终端设备根据读写设备发送的命令进行数据传输。实现了配置有通用串行总线接口的设备通过通用串行总线接口与外部设备相连接时，该外部设备可以主动读取配置有通用串行总线接口的设备的内部数据。

Description

终端设备、读写设备、数据传输系统和硬件初始化方法 技术领域
本发明实施例涉及数据传输技术，尤其涉及一种终端设备、读写设备、数据传输系统和硬件初始化方法。
背景技术
USB(Universal Serial Bus，通用串行总线)是一个外部总线标准，用于规范电脑与外部设备的连接和通讯。USB自从1996年推出后，已成功替代串口和并口，并成为二十一世纪个人电脑和大量智能设备必配的接口之一。
随着USB接口的普及，越来越多的设备(例如：智能手机、平板等)会配置有USB接口，并通过USB接口来传输数据。在通过USB接口传输数据时，一般来说是配置有USB母口的设备来控制整个数据的传输过程，通过USB公口与配置有USB母口的设备相连接的外接设备仅是按照配置有USB母口的设备的命令来完成数据传输的相关操作，不起任何的主导作用。
无论配置有USB母口的设备发生任何故障，其内部存储的数据都不能被其他设备通过USB连接进行读取。
发明内容
有鉴于此，本发明实施例提供了一种终端设备、读写设备、数据传输系统和硬件初始化方法，以解决现有技术中无论配置有通用串行总线接口的设备出现何种故障，其内部的数据都无法通过通用串行总线接口连接被读取的技术问 题。
在第一方面，本发明实施例提供了一种终端设备，包括：
第一通用串行总线接口、上行端口、下行端口、切换开关、第一控制器和第一开关电路；
所述第一通用串行总线接口，用于与外部设备的第二通用串行总线接口连接，并且其信号引脚接地；所述上行端口和所述下行端口均通过所述切换开关与所述第一通用串行总线接口的数据传输端相连，并通过所述切换开关切换通断状态；所述第一开关电路的第一端与所述第一通用串行总线接口的电源引脚相连，所述第一开关电路的第二端接入电源；
所述第一控制器的第一控制端与所述切换开关的受控端相连，发送信号控制所述切换开关在所述上行端口和所述下行端口之间切换；所述第一控制器的第二控制端与所述第一开关电路的受控端相连，发送信号控制所述第一开关电路的通断；所述第一控制器的信号输入端接入所述第一通用串行总线接口的电源引脚的电压检测数据，并根据所述电压检测数据向所述切换开关和所述第一开关电路发送信号。
在上述设备中，优选的是，还包括：
限流电路，所述限流电路的第一端与所述第一通用串行总线接口的电源引脚相连，所述限流电路的第三端与所述第一控制器的信号输入端相连，所述限流电路的第二端与所述第一开关电路的第一端相连。
在上述设备中，优选的是，所述限流电路包括：限流开关、电阻R1和电阻R2；所述限流开关的第一端和所述电阻R1的第一端以及所述第一通用串行总线接口的电源引脚相连，所述限流开关的第二端与所述第一开关电路的第一端相 连；所述电阻R1的第二端与所述电阻R2的第一端以及所述第一控制器的信号输入端相连；所述电阻R2的第二端接地。
在上述设备中，优选的是，所述第一开关电路包括：电阻R3、电阻R4、电阻R5、三极管Q2和MOS管Q1；所述电阻R3的第一端与所述第一控制器的第二控制端相连；所述电阻R3的第二端与所述三极管Q2的基极相连；所述三极管Q2的发射极接地，所述三极管Q2的集电极与所述电阻R4的第一端以及所述电阻R5的第一端相连；所述电阻R4的第二端与所述MOS管Q1的源极相连并接入电源；所述电阻R5的第二端与所述MOS管Q1的栅极相连；所述MOS管Q1的漏极与所述限流电路的第二端相连。
在第二方面，本发明实施例提供了一种读写设备，包括：
第二通用串行总线接口、第二控制器、触发电路、第二开关电路和第三开关电路；所述第二通用串行总线接口的信号引脚与所述触发电路的检测端相连，所述第二控制器的信号输入端与所述触发电路的反馈端相连，并根据所述触发电路的反馈端电压的变化向所述第三开关电路发送信号；
所述第二通用串行总线接口的信号引脚用于与第一通用串行总线接口的信号引脚相连；所述第二控制器的数据处理端与所述第二通用串行总线接口的数据传输端相连以通过所述第二通用串行总线接口读写数据；所述第二控制器的第一控制端与所述第二开关电路的受控端相连，并发送信号控制所述第二开关电路的通断；所述第二控制器的第二控制端与所述第三开关电路的受控端相连，并发送信号控制所述第三开关电路的通断；所述第二开关电路的第一端接入电源，所述第二开关电路的第二端与所述第二通用串行总线接口的电源引脚相连；所述第三开关电路的第一端与所述第二通用串行总线接口电源引脚相连，所述第三开关电路的第二端接地。
在上述设备中，优选的是，所述触发电路包括三极管Q3、电阻R6、电阻R7和电阻R8，所述电阻R6的第一端和所述第二通用串行总线接口的信号引脚相连；所述电阻R6的第二端与所述三极管Q3的基极以及所述电阻R7的第一端相连；所述电阻R7的第二端与所述电阻R8的第一端相连并接入+5V电压；所述电阻R8的第二端与所述三极管Q3的集电极以及所述第二控制器的信号输入端相连；所述三极管Q3的发射极接地。
在上述设备中，优选的是，所述第二开关电路包括电阻R9、电阻R10、电阻R11、三极管Q4和MOS管Q5；所述电阻R9的第一端与所述第二控制器的第一控制端相连；所述电阻R9的第二端与所述三极管Q4的基极相连；所述三极管Q4的发射极接地，所述三极管Q4的集电极与所述电阻R10的第一端以及所述电阻R11的第一端相连；所述电阻R10的第二端与所述MOS管Q5的源极相连并接入电源；所述电阻R11的第二端与所述MOS管Q5的栅极相连；所述MOS管Q5的漏极与所述第二通用串行总线接口的电源引脚相连。
在上述设备中，优选的是，所述第三开关电路包括电阻R13、电阻R12和三极管Q6；所述电阻R13的第一端与所述第二控制器的第二控制端相连，所述电阻R13的第二端与所述三极管Q6的基极相连；所述三极管Q6的发射极接地，所述三极管Q6的集电极与所述电阻R12的第一端相连，所述电阻R12的第二端与所述第二通用串行总线接口的电源引脚相连。
在第三方面，本发明实施例提供了一种数据传输系统，包括前文所述的终端设备和所述的读写设备。
在第四方面，本发明实施例提供了一种硬件初始化方法，用于前文所述的数据传输系统，包括：
所述第一控制器导通所述第一开关电路，将所述切换开关切换为导通所述下行端口；所述第二控制器断开所述第二开关电路和所述第三开关电路；
所述第二控制器接收到所述触发电路检测到的表示所述第二通用串行总线接口插入所述第一通用串行总线接口的有效信号时，所述第二控制器导通所述第三开关电路并开始计时；
当所述第一通用串行总线接口的电源引脚接地时，所述第一控制器的信号输入端检测到输入为0，将所述切换开关切换为导通所述上行端口，并断开所述第一开关电路；
当计时达到预设时长，所述第二控制器导通所述第二开关电路，断开所述第三开关电路。
在上述方法中，优选的是，所述当计时达到预设时长，所述第二控制器导通所述第二开关电路，断开所述第三开关电路之后，还包括：
当所述第一控制器的信号输入端检测到输入从高电平变为低电平时，将所述切换开关切换为导通所述下行端口；
当所述第二控制器接收到所述触发电路检测到的表示所述第二通用串行总线接口从所述第一通用串行总线接口断开的有效信号时，所述第二控制器断开所述第二开关电路和所述第三开关电路。
本发明实施例提供的终端设备、读写设备、数据传输系统和硬件初始化方法，通过在终端设备中配置第一通用串行总线接口、上行端口、下行端口、切换开关、第一控制器和第一开关电路等电路器件，在读写设备中配置第二通用串行总线接口、第二控制器、触发电路、第二开关电路和第三开关电路等电路器件，使得当终端设备与读写设备相连接后，终端设备可以通过第一通用串行总线接口和第二通用串行总线接口受控于读写设备，终端设备根据读写设备发 送的命令进行数据传输，解决了现有技术中无论配置有通用串行总线接口的设备出现何种故障，其内部的数据都无法通过通用串行总线接口连接被读取的技术问题，实现了配置有通用串行总线接口的设备通过通用串行总线接口与外部设备相连接时，该外部设备可以主动读取配置有通用串行总线接口的设备的内部数据。
附图说明
图1a是本发明实施例一提供的一种终端设备的结构图；
图1b是本发明实施例一提供的第一开关电路的结构图；
图1c是本发明实施例一提供的将通用串行总线接口作为上行端口的设备与通用串行总线接口的连接图；
图2是本发明实施例二提供的另外一种终端设备的结构图；
图3a是本发明实施例三提供的一种读写设备的结构图；
图3b是本发明实施例三提供的第二开关设备的结构图；
图4是本发明实施例五提供的一种硬件初始化方法的流程图。
具体实施方式
为了使本发明的目的、技术方案和优点更加清楚，下面结合附图对本发明具体实施例作进一步的详细描述。可以理解的是，此处所描述的具体实施例仅仅用于解释本发明，而非对本发明的限定。
另外还需要说明的是，为了便于描述，附图中仅示出了与本发明相关的部分而非全部内容。在更加详细地讨论示例性实施例之前应当提到的是，一些示例性实施例被描述成作为流程图描绘的处理或方法。虽然流程图将各项操作(或 步骤)描述成顺序的处理，但是其中的许多操作可以被并行地、并发地或者同时实施。此外，各项操作的顺序可以被重新安排。当其操作完成时所述处理可以被终止，但是还可以具有未包括在附图中的附加步骤。所述处理可以对应于方法、函数、规程、子例程、子程序等等。
在本发明中，“连接”、“相连”、“连”、“接”等表示电性相连的词语，如无特别说明，则表示直接或间接的电性连接。
需要指出的是，熟悉该领域的技术人员对木发明的具体实施方式所做的任何改动均不脱离本发明的权利要求书的范围。相应地，本发明的权利要的范围也井不仅仅局限于前述具体实施方式。
实施例一
图1a为本发明实施例一提供的一种终端设备的结构图，本实施例中终端设备的结构具体包括：
第一通用串行总线接口110、上行端口150、下行端口160、切换开关170、第一控制器140和第一开关电路130；
第一通用串行总线接口110，用于与外部设备的通用串行总线接口连接，并且其信号引脚接地；上行端口150和下行端口160均通过切换开关170与第一通用串行总线接口110的数据传输端相连，并通过切换开关170切换通断状态；第一开关电路130的第一端与第一通用串行总线接口110的电源引脚相连，第一开关电路130的第二端接入电源，一般是5V的系统电源，即System 5V；
第一控制器140的第一控制端与切换开关170的受控端相连，发送信号Switch CTL控制切换开关170在上行端口和下行端口之间切换；第一控制器140的第二控制端与第一开关电路130的受控端相连，发送信号5V_CTL控制第一 开关电路130的通断；第一控制器140的信号输入端接入第一通用串行总线接口110的电源引脚的电压检测数据，并根据电压检测数据向切换开关170和第一开关电路130发送信号Switch CTL和5V_CTL。
进一步的，如图1b所示，将第一开关电路130优化为：包括电阻R3、电阻R4、电阻R5、三极管Q2和MOS管Q1；电阻R3的第一端与第一控制器140的第二控制端相连，用于接收信号5V_CTL；电阻R3的第二端与三极管Q2的基极相连；三极管Q2的发射极接地，三极管Q2的集电极与电阻R4的第一端以及电阻R5的第一端相连；电阻R4的第二端与MOS管Q1的源极相连并接入电源System 5V；电阻R5的第二端与MOS管Q1的栅极相连；MOS管Q1的漏极与限流电路120的第二端相连，用于接收电源VCC_out。
如图1a和图1b所示，当终端设备处于初始状态时，第一控制器140的第二控制端输出信号5V_CTL为高电平，使得第一开关电路130的受控端输入为高电平，即电阻R3的第一端输入为高电平，使得三极管Q2导通，同时，电阻R4的第二端接入电源System 5V，使得MOS管Q1导通，进而使得接入的电源System 5V通过MOS管Q1从Q1的漏极输出到第一通用串行总线接口110的电源引脚。
由于第一通用串行总线接口110的电源引脚的输入为高电平System 5V，即第一通用串行总线接口110的电源引脚的电压检测数据为高电平，在本实施例中，将第一通用串行总线接口110的电源引脚的电压检测数据定义为5V Det，因此，第一控制器140的信号输入端输入的信号5V Det为高电平，当第一控制器140检测到输入信号5V Det为高电平时，第一控制器140通过第一控制端输出控制信号Switch CTL控制切换开关170切换至下行端口160，使得第一通用串行总线接口110的数据传输端连接至下行端口160。
图1c所示为将通用串行总线接口作为上行端口的设备310，其中，通用串行总线接口的外壳和信号引脚接地。当图1c中的通用串行总线接口插入图1a中的第一通用串行总线接口110后，图1a中的终端设备内部不会发生变化，继续保持初始状态，并可以与图1c中的将通用串行总线接口作为上行端口的设备正常通讯，进行数据传输。
另外还有一种情况，当本实施例中的终端设备需要被其它设备读取数据时，图1a中的第一通用串行总线接口110插入专用的读取设备的通用串行总线接口后，第一通用串行总线接口110的电源引脚接地，进而使得第一控制器140的输入信号5V Det为0，当第一控制器140检测到输入信号5V Det变为0后，第一控制器140将输出信号5V_CTL变为0，进而第一开关电路130的受控端的输入变为0，导致三极管Q2截止，进而MOS管Q1截止，电阻R4接入的电源System5V无法通过MOS管Q1输出至第一通用串行总线接口110的电源引脚。第一控制器140检测到输入信号5V Det变为0后，同时还会控制切换开关170，使其切换至上行端口150，至此完成了第一通用串行总线接口110由下行端口至上行端口的转变。
在此需要说明的是，在本实施例以及之后的所有实施例中，所述下行端口具体是指在通过通用串行总线接口进行数据传输的过程中，给跟其对接的另外一个通用串行总线接口提供电源，在数据传输的过程中起主导作用的通用串行总线接口。相应地，上述“另外一个通用串行总线接口”即为所述的上行端口。也就是说，此处所谓的“上行”和“下行”不是指数据传输过程中数据的流向，而是针对数据传输过程中对接的两个通用串行总线接口所起的主从地位的差异来给其命名的。
本发明实施例提供的终端设备，通过在终端设备中配置第一通用串行总线接口110、上行端口150、下行端口160、切换开关170、第一控制器140和第一开关电路130等电路器件，使得第一通用串行总线接口110可以复用为下行端口160或上行端口150，解决了现有技术中无论配置有通用串行总线接口的设备出现何种故障，其内部的数据都无法通过通用串行总线接口连接被读取的技术问题，实现了配置有通用串行总线接口的设备通过通用串行总线接口与外部设备相连接时，该外部设备可以主动读取配置有通用串行总线接口的设备的内部数据。
实施例二
本发明实施例二提供了一种终端设备的结构图。本实施例以上述实施例为基础进行优化，在本实施例中，如图2所示，还包括：限流电路120，限流电路120的第一端与第一通用串行总线接口110的电源引脚(即输出或接入+5V的引脚)相连，限流电路120的第三端与第一控制器140的信号输入端相连，用于输出信号5V Det，限流电路120的第二端与第一开关电路130的第一端相连；
进一步地，将限流电路120优化为：包括限流开关180、电阻R1和电阻R2；限流开关180的第一端和电阻R1的第一端以及第一通用串行总线接口110的电源引脚相连，用于向第一通用串行总线接口110的电源引脚输出供电电压USB5V，限流开关180的第二端与第一开关电路130的第一端相连；电阻R1的第二端与电阻R2的第一端以及第一控制器140的信号输入端相连；电阻R2的第二端接地。
如图2所示，同样，当终端设备处于初始状态时，第一控制器140的第二控制端输出信号5V_CTL为高电平，使得第一开关电路130的受控端输入为高 电平，即电阻R3的第一端输入为高电平，使得三极管Q2导通，同时，电阻R4的第二端接入电源System 5V，使得MOS管Q1导通，进而使得接入的电源System 5V通过MOS管Q1从Q1的漏极输出到限流电路120的第二端，即限流开关180的第二端。
限流开关180的第二端接入MOS管Q1的漏极输出的电源System 5V后，System 5V通过限流开关180，输出到第一通用串行总线接口110的电源引脚，同时，System 5V通过电阻R1和电阻R2接地，进而使得电阻R1的第二端(与电阻R2的第一端相连接)呈现高电平，因此，第一控制器140的输入信号5V Det为高电平，当第一控制器140检测到输入信号5V Det为高电平时，第一控制器140通过第一控制端输出控制信号Switch CTL控制切换开关170切换至下行端口160，使得第一通用串行总线接口110的数据传输端连接至下行端口160。
当图1c中的将通用串行总线接口作为上行端口的设备310插入图2中的第一通用串行总线接口110后，图2中的终端设备内部不会发生变化，继续保持初始状态，并可以与图1c中的将通用串行总线接口作为上行端口的设备正常通讯，进行数据传输。
另外还有一种情况，当本实施例中的终端设备需要被其它设备读取数据时，图2中的第一通用串行总线接口110插入专用的读取设备的通用串行总线接口后，第一通用串行总线接口110的电源引脚接地，进而触发图2中的限流开关180，使得限流开关180的第一端输出为0，即电阻R1的第一端输入为0，因此，第一控制器140的输入信号5V Det为0，当第一控制器140检测到输入信号5V Det变为0后，第一控制器140将输出信号5V_CTL变为0，进而第一开关电路130的受控端的输入变为0，导致三极管Q2截止，进而MOS管Q1截止，电阻R4接入的电源System 5V无法通过MOS管Q1输出至限流电路120的第二端。 第一控制器140检测到输入信号5V Det变为0后，同时还会控制切换开关170，使其切换至上行端口150，至此完成了第一通用串行总线接口110由下行端口至上行端口的转变。其中，限流开关180的作用是当通过限流开关的电流大于预设阈值时，限流开关自动关断，使得限流开关两端的电路断路。由于限流开关属于现有技术，此处不再进行详细阐述。
本发明实施例提供的终端设备，通过在终端设备中配置第一通用串行总线接口110、上行端口150、下行端口160、切换开关170、第一控制器140、限流电路120和第一开关电路130等电路器件，使得第一通用串行总线接口110可以复用为下行端口160或上行端口150，解决了现有技术中无论配置有通用串行总线接口的设备出现何种故障，其内部的数据都无法通过通用串行总线接口连接被读取的技术问题，实现了配置有通用串行总线接口的设备通过通用串行总线接口与外部设备相连接时，该外部设备可以主动读取配置有通用串行总线接口的设备的内部数据。
实施例三
图3a为本发明实施例三提供的一种读写设备的结构图，具体包括：
第二通用串行总线接口230、第二控制器250、触发电路240、第二开关电路210和第三开关电路220；所述第二通用串行总线接口230的信号引脚Signal_GND与所述触发电路240的检测端相连，所述触发电路240的反馈端与所述第二控制器250的信号输入端相连，本实施例中将此二者之间传输的信号定义为Insert Det，具体用于描述第二通用串行总线接口230接入的电压状态；
第二通用串行总线接口230的信号引脚用于与第一通用串行总线接口110的信号引脚相连；第二控制器250的数据处理端与第二通用串行总线接口230 的数据传输端相连以通过第二通用串行总线接口230读写数据；第二控制器250的第一控制端与第二开关电路210的受控端相连，发送信号ON/OFF_CTL控制第二开关电路210的通断；第二控制器250的第二控制端与第三开关电路220的受控端相连，并发送信号CTL控制第三开关电路220的通断，第二控制器250根据信号Insert Det决定ON/OFF_CTL和CTL的具体控制内容；第二开关电路210的第一端接入+5V电源，第二开关电路210的第二端与第二通用串行总线接口230的电源引脚(即输出或接入+5V的引脚)相连，将电源VCC_out’输出至第二通用串行总线接口230的电源引脚；第三开关电路220的第一端与第二通用串行总线接口230的电源引脚相连，第三开关电路220的第二端接地。
进一步的，将触发电路240优化为：包括三极管Q3、电阻R6、电阻R7和电阻R8，电阻R6的第一端和第二通用串行总线接口230的信号引脚相连；电阻R6的第二端与三极管Q3的基极以及电阻R7的第一端相连；电阻R7的第二端与电阻R8的第一端相连并接入+5V电压；电阻R8的第二端与三极管Q3的集电极以及第二控制器250的信号输入端相连，输出信号Insert Det；三极管Q3的发射极接地。
进一步地，将第二开关电路210优化为：包括电阻R9、电阻R10、电阻R11、三极管Q4和MOS管Q5；电阻R9的第一端与第二控制器250的第一控制端相连，用于接收ON/OFF_CTL；电阻R9的第二端与三极管Q4的基极相连；三极管Q4的发射极接地，三极管Q4的集电极与电阻R10的第一端以及电阻R11的第一端相连；电阻R10的第二端与MOS管Q5的源极相连并接入电源；电阻R11的第二端与MOS管Q5的栅极相连；MOS管Q5的漏极与USB公口230的电源引脚相连，将电源VCC_out’输出至所述电源引脚。
进一步地，将第三开关电路220优化为：包括电阻R13、电阻R12和三极管Q6；电阻R13的第一端与第二控制器250的第二控制端相连，用于将CTL输出至电阻R13的第一端，电阻R13的第二端与三极管Q6的基极相连；三极管Q6的发射极接地，三极管Q6的集电极与电阻R12的第一端相连，电阻R12的第二端与第二通用串行总线接口230的电源引脚相连。
在本实施例中，图3a中的读写设备的初始状态为，第二控制器250的第一控制端和第二控制端输出的ON/OFF_CTL和CTL均为低电平。如图3b所示，由于第二控制器250的第一控制端输出ON/OFF_CTL为低电平，因此，电阻R9的第一端输入为低电平，进而三极管Q4截止，MOS管Q5也截止，即Q5的漏极无电压输出，所以第二通用串行总线接口230的电源引脚无电压输入。如图3a所示，第二控制器250的第二控制端输出的CTL为低电平，因此，电阻R13的第一端输入为低电平，进而三极管Q6截止。如图3a所示，触发电路240中接入了+5V电源，进而使得三极管Q3导通，Q3的集电极呈现低电平，因此，第二控制器250输入Insert Det为低电平。
本实施例中的读写设备以第二通用串行总线接口230作为外接端口，并在第二通用串行总线接口230中设置触发电路240，当需要从非常规的设置有通用串行总线接口的存储设备(例如终端设备)中读取数据时，通过读写设备内部的触发电路240和多个开关电路实现基于通用串行总线接口的数据通道的建立，从设置有通用串行总线接口的存储设备中读取数据。
实施例四
本发明实施例四还提供一种数据传输系统，具体可以包括图2中的终端设备和图3a中的读写设备，图2和图3a中的结构已经能够体现该数据传输系统的基本架构，在此不另行作图说明。
当图3a中的读写设备的第二通用串行总线接口230插入图2中的终端设备的第一通用串行总线接口110时(一般是在图2中的终端设备发生故障，无法控制数据传输的情况下)，图2中的终端设备和图3a中的读写设备作为一个数据传输系统相连接后，终端设备和读写设备的内部会发生相应的变化，具体过程如下所述：
当图3a中的读写设备插入图2中的终端设备之后，由于第一通用串行总线接口110的信号引脚接地，第二通用串行总线接口230与第一通用串行总线接口110相连接后，第二通用串行总线接口230的信号引脚也会接地，导致电阻R6的第一端接地，由于电阻R6和电阻R7的比值满足下式的关系[5/(R6+R7)]×R6＜0.5，因此，三极管Q3截止，Q3的集电极输出高电平，第二控制器250输入Insert Det变为高电平。
当第二控制器250检测到输入Insert Det由低电平变为高电平后，第二控制器250开始计时，同时使输出CTL变为高电平，此时，电阻R13的第一端输入高电平，三极管Q6导通，由于此时第二通用串行总线接口230的电源引脚已与第一通用串行总线接口110的电源引脚相连接，因此，第二通用串行总线接口230的电源引脚接入电源System 5V，导致电源System 5V通过电阻R12和三极管Q6接地，使得流经限流电路120中的限流开关180的电流大于预设电流阈值，进而触发限流开关180，使得限流开关180关断输入，限流电路120的第三端输出为0，因此第一控制器140输入5V Det也为0。
当第一控制器140检测到输入5V Det的电压发生上述变化后，将输出 5V_CTL变为低电平，同时，通过向切换开关170发送命令Switch CTL，使得切换开关170与上行端口150相连接，进而使得第一通用串行总线接口110与上行端口150相连接。其中，第一控制器140输出5V_CTL变为低电平之后，三极管Q2截止，进而MOS管Q1截止，因此，电源Systme 5V无法通过Q2传输到限流电路120的第二端。
上面提到过，当第二控制器250检测到输入Insert Det由低电平变为高电平后，第二控制器250开始计时，当第二控制器250计时到达预设时长后，输出CTL变为低电平，输出ON/OFF_CTL变为高电平。其中，预设时长具体是指从上述Q3的集电极变为高电平至上述切换开关170与上行端口150相连接所需的时间，预设时长的具体数值可以通过实际的调试过程测试得到，当然，预设时长也可以大于从上述Q3的集电极变为高电平至上述切换开关170与上行端口150相连接所需的时间。本领域的技术人员可以理解的是，通过通用串行总线接口进行数据通信时，都是作为下行端口的通用串行总线接口给作为上行端口的通用串行总线接口供电的，所以必须等到上述切换开关170与上行端口150相连接后，才可使读写设备中的第二通用串行总线接口230的电源引脚接入第二开关电路210的第一端接入的+5V电源。
上述当第二控制器250计时到达预设时长后，第二控制器250输出CTL变为低电平，第二控制器250输出ON/OFF_CTL变为高电平。其中，当第二控制器250输出CTL变为低电平后，三极管Q6截止，第二通用串行总线接口230以及第一通用串行总线接口110的电源引脚不再通过电阻R12和三极管Q6接地。其中，当第二控制器250输出ON/OFF_CTL变为高电平后，三极管Q4以及MOS管Q5均导通，电阻R10的第二端接入的电源+5V通过MOS管Q5输出到第二通用串行总线接口230的电源引脚，从而第一通用串行总线接口110 的电源引脚通过第二通用串行总线接口230接入电源+5V，第一通用串行总线接口110所接入的电源通过电阻R1和电阻R2接地，使得电阻R1的第二端呈现高电平，因此，第一控制器140的信号输入端的输入5V Det由低电平转换为高电平，至此，终端设备与读写设备所组成的数据传输系统，通过硬件初始化方法，完成了终端设备内部的第一通用串行总线接口110由下行端口160向上行端口150的转变。
接下来，当读写设备与终端设备断开连接后，第一通用串行总线接口110的电源引脚无法再通过第二通用串行总线接口230接入+5V电源，因此，第一控制器140输入5V Det又由高电平转换为低电平，当第一控制140器再次检测到输入5V Det由高电平转换为低电平后，第一控制器140向切换开关170发送命令Switch CTL，使得切换开关170切换至下行端口160，从而第一通用串行总线接口110与下行端口160相连接，同时，第一控制端140还会将输出5V_CTL变为高电平，使得第一开关电路130导通，电源System 5V通过第一开关电路130和限流电路120传输至第一通用串行总线接口110的电源引脚，同时，使得第一控制器140输入5V Det又由低电平转换为高电平，至此，终端设备恢复至初始状态。
当读写设备与终端设备断开连接后，读写设备的第二通用串行总线接口230的信号引脚不再接地，触发电路240中的+5V电源重新使得三极管Q3导通，进而三极管Q3的集电极输出高电平，使得第二控制器250输入Insert Det由低电平转换为高电平，当第二控制器250检测到输入Insert Det的上述变化后，第二控制器250将输出ON/OFF_CTL设置为低电平，恢复至初始状态。
本发明实施例提供的终端设备、读写设备、数据传输系统和硬件初始化方法，通过在终端设备中配置第一通用串行总线接口110、上行端口150、下行端 口160、切换开关170、第一控制器140、限流电路120和第一开关电路130等电路器件，在读写设备中配置第二通用串行总线接口230、第二控制器250、触发电路240和第二开关电路210和第三开关电路220等电路器件，使得当终端设备与读写设备相连接组成数据传输系统后，通过硬件的初始化方法使得终端设备可以通过第一通用串行总线接口110和第二通用串行总线接口230受控于读写设备，终端设备根据读写设备发送的命令进行数据传输，解决了现有技术中无论配置有通用串行总线接口的设备出现何种故障，其内部的数据都无法通过通用串行总线接口连接被读取的技术问题，实现了配置有通用串行总线接口的设备通过通用串行总线接口与外部设备相连接时，该外部设备可以主动读取配置有通用串行总线接口的设备的内部数据。
实施例五
本发明实施例五还提供一种硬件初始化方法，用于上述的一种数据传输系统，使得上述的数据传输系统完成设计的通用串行总线接口连接以实现异常状态下的数据读取，具体过程在数据传输系统的实施例中已有阐述，在此仅作概括说明。如图4所示，该硬件初始化方法，包括：
步骤410、第一控制器140导通第一开关电路130，将切换开关170切换为导通下行端口160，第二控制器250断开第二开关电路210和第三开关电路220；
步骤420、第二控制器250接收到触发电路检测到的表示第二通用串行总线接口230插入第一通用串行总线接口110的有效信号时，第二控制器250导通第三开关电路220并开始计时；
步骤430、当第一通用串行总线接口110的电源引脚接地时，第一控制器140的信号输入端检测到输入为0，将切换开关170切换为导通上行端口150，并断开第一开关电路130；
步骤440、当计时达到预设时长，第二控制器250导通第二开关电路210，断开第三开关电路220；
步骤450、当第一控制器140的信号输入端检测限流电路120的第三端从高电平变为低电平时，将切换开关170切换为导通下行端口；
步骤460、当第二控制器250接收到触发电路检测到的表示第二通用串行总线接口230从第一通用串行总线接口110拔出的有效信号时，第二控制器250断开第二开关电路210和第三开关电路220。
本发明实施例提供的硬件初始化方法，在终端设备和读写设备相连之前，通过第一控制器140和第二控制器250控制第一至第三开关电路的通断以及切换开关170的接通对象，在终端设备和读写设备相连之后以及断开之后，第一控制器140和第二控制器250根据各自信号输入端输入信号的变化情况，控制各自控制信号输出端输出信号的变化，以此来控制第一至第三开关电路的通断以及切换开关170的接通对象，解决了现有技术中无论配置有通用串行总线接口的设备出现何种故障，其内部的数据都无法通过通用串行总线接口连接被读取的技术问题，实现了配置有通用串行总线接口的设备通过通用串行总线接口与外部设备相连接时，该外部设备可以主动读取配置有通用串行总线接口的设备的内部数据。
显然，本领域技术人员应该明白，上述的本发明的各模块或各步骤可以通过如上所述的服务器实施。可选地，本发明实施例可以用计算机装置可执行的 程序来实现，从而可以将它们存储在存储装置中由处理器来执行，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等；或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本发明不限制于任何特定的硬件和软件的结合。
以上所述仅为本发明的优选实施例，并不用于限制本发明，对于本领域技术人员而言，本发明可以有各种改动和变化。凡在本发明的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (11)

  1. 一种终端设备，其特征在于，包括：第一通用串行总线接口、上行端口、下行端口、切换开关、第一控制器和第一开关电路；
    所述第一通用串行总线接口，用于与外部设备的第二通用串行总线接口连接，并且其信号引脚接地；所述上行端口和所述下行端口均通过所述切换开关与所述第一通用串行总线接口的数据传输端相连，并通过所述切换开关切换通断状态；所述第一开关电路的第一端与所述第一通用串行总线接口的电源引脚相连，所述第一开关电路的第二端接入电源；
    所述第一控制器的第一控制端与所述切换开关的受控端相连，发送信号控制所述切换开关在所述上行端口和所述下行端口之间切换；所述第一控制器的第二控制端与所述第一开关电路的受控端相连，发送信号控制所述第一开关电路的通断；所述第一控制器的信号输入端接入所述第一通用串行总线接口的电源引脚的电压检测数据，并根据所述电压检测数据向所述切换开关和所述第一开关电路发送信号。
  2. 根据权利要求1所述的终端设备，其特征在于，还包括：
    限流电路，所述限流电路的第一端与所述第一通用串行总线接口的电源引脚相连，所述限流电路的第三端与所述第一控制器的信号输入端相连，所述限流电路的第二端与所述第一开关电路的第一端相连。
  3. 根据权利要求2所述的终端设备，其特征在于，所述限流电路包括限流开关、电阻R1和电阻R2；所述限流开关的第一端和所述电阻R1的第一端以及所述第一通用串行总线接口的电源引脚相连，所述限流开关的第二端与所述第一开关电路的第一端相连；所述电阻R1的第二端与所述电阻R2的第一端以及所述第一控制器的信号输入端相连；所述电阻R2的第二端接地。
  4. 根据权利要求2所述的终端设备，其特征在于，所述第一开关电路包括电阻R3、电阻R4、电阻R5、三极管Q2和MOS管Q1；所述电阻R3的第一端与所述第一控制器的第二控制端相连；所述电阻R3的第二端与所述三极管Q2的基极相连；所述三极管Q2的发射极接地，所述三极管Q2的集电极与所述电阻R4的第一端以及所述电阻R5的第一端相连；所述电阻R4的第二端与所述MOS管Q1的源极相连并接入电源；所述电阻R5的第二端与所述MOS管Q1的栅极相连；所述MOS管Q1的漏极与所述限流电路的第二端相连。
  5. 一种读写设备，其特征在于，包括：第二通用串行总线接口、第二控制器、触发电路、第二开关电路和第三开关电路；所述第二通用串行总线接口的信号引脚与所述触发电路的检测端相连，所述第二控制器的信号输入端与所述触发电路的反馈端相连，并根据所述触发电路的反馈端电压的变化向所述第三开关电路发送信号；
    所述第二通用串行总线接口的信号引脚用于与第一通用串行总线接口的信号引脚相连；所述第二控制器的数据处理端与所述第二通用串行总线接口的数据传输端相连以通过所述第二通用串行总线接口读写数据；所述第二控制器的第一控制端与所述第二开关电路的受控端相连，并发送信号控制所述第二开关电路的通断；所述第二控制器的第二控制端与所述第三开关电路的受控端相连，并发送信号控制所述第三开关电路的通断；所述第二开关电路的第一端接入电源，所述第二开关电路的第二端与所述第二通用串行总线接口的电源引脚相连；所述第三开关电路的第一端与所述第二通用串行总线接口电源引脚相连，所述第三开关电路的第二端接地。
  6. 根据权利要求5所述的读写设备，其特征在于，所述触发电路包括三极管Q3、电阻R6、电阻R7和电阻R8，所述电阻R6的第一端和所述第二通用串 行总线接口的信号引脚相连；所述电阻R6的第二端与所述三极管Q3的基极以及所述电阻R7的第一端相连；所述电阻R7的第二端与所述电阻R8的第一端相连并接入+5V电压；所述电阻R8的第二端与所述三极管Q3的集电极以及所述第二控制器的信号输入端相连；所述三极管Q3的发射极接地。
  7. 根据权利要求5所述的读写设备，其特征在于，所述第二开关电路包括电阻R9、电阻R10、电阻R11、三极管Q4和MOS管Q5；所述电阻R9的第一端与所述第二控制器的第一控制端相连；所述电阻R9的第二端与所述三极管Q4的基极相连；所述三极管Q4的发射极接地，所述三极管Q4的集电极与所述电阻R10的第一端以及所述电阻R11的第一端相连；所述电阻R10的第二端与所述MOS管Q5的源极相连并接入电源；所述电阻R11的第二端与所述MOS管Q5的栅极相连；所述MOS管Q5的漏极与所述第二通用串行总线接口的电源引脚相连。
  8. 根据权利要求5所述的读写设备，其特征在于，所述第三开关电路包括电阻R13、电阻R12和三极管Q6；所述电阻R13的第一端与所述第二控制器的第二控制端相连，所述电阻R13的第二端与所述三极管Q6的基极相连；所述三极管Q6的发射极接地，所述三极管Q6的集电极与所述电阻R12的第一端相连，所述电阻R12的第二端与所述第二通用串行总线接口的电源引脚相连。
  9. 一种数据传输系统，其特征在于，包括权利要求1-4任一项所述的终端设备和权利要求5-8任一项所述的读写设备。
  10. 一种硬件初始化方法，用于权利要求9所述的数据传输系统，其特征在于，包括：
    所述第一控制器导通所述第一开关电路，将所述切换开关切换为导通所述下行端口，所述第二控制器断开所述第二开关电路和所述第三开关电路；
    所述第二控制器接收到所述触发电路检测到的表示所述第二通用串行总线接口插入所述第一通用串行总线接口的有效信号时，所述第二控制器导通所述第三开关电路并开始计时；
    当所述第一通用串行总线接口的电源引脚接地时，所述第一控制器的信号输入端检测到输入为0，将所述切换开关切换为导通所述上行端口，并断开所述第一开关电路；
    当计时达到预设时长，所述第二控制器导通所述第二开关电路，断开所述第三开关电路。
  11. 根据权利要求10所述的方法，其特征在于，所述当计时达到预设时长，所述第二控制器导通所述第二开关电路，断开所述第三开关电路之后，还包括：
    当所述第一控制器的信号输入端检测到输入从高电平变为低电平时，将所述切换开关切换为导通所述下行端口；
    当所述第二控制器接收到所述触发电路检测到的表示所述第二通用串行总线接口从所述第一通用串行总线接口断开的有效信号时，所述第二控制器断开所述第二开关电路和所述第三开关电路。
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