WO2020125072A1 - 单相电机无级调速电路及调速方法 - Google Patents

单相电机无级调速电路及调速方法 Download PDF

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Publication number
WO2020125072A1
WO2020125072A1 PCT/CN2019/104700 CN2019104700W WO2020125072A1 WO 2020125072 A1 WO2020125072 A1 WO 2020125072A1 CN 2019104700 W CN2019104700 W CN 2019104700W WO 2020125072 A1 WO2020125072 A1 WO 2020125072A1
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Prior art keywords
switch
signal
circuit
terminal
output terminal
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PCT/CN2019/104700
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English (en)
French (fr)
Inventor
喻辉洁
李干富
周卓源
王曙光
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厦门市必易微电子技术有限公司
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Priority to EP19897682.1A priority Critical patent/EP3820044A4/en
Publication of WO2020125072A1 publication Critical patent/WO2020125072A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
    • H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
    • H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters
    • H02P27/08—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P25/00—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details
    • H02P25/02—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details characterised by the kind of motor
    • H02P25/04—Single phase motors, e.g. capacitor motors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P23/00—Arrangements or methods for the control of AC motors characterised by a control method other than vector control
    • H02P23/0004—Control strategies in general, e.g. linear type, e.g. P, PI, PID, using robust control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P2201/00—Indexing scheme relating to controlling arrangements characterised by the converter used
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P23/00—Arrangements or methods for the control of AC motors characterised by a control method other than vector control
    • H02P23/26—Power factor control [PFC]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P80/00—Climate change mitigation technologies for sector-wide applications
    • Y02P80/10—Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

Definitions

  • This application relates to the field of electronics, and in particular to a stepless speed regulation circuit and speed regulation method for driving a single-phase motor.
  • Single-phase motors generally refer to asynchronous motors powered by single-phase AC power provided by commercial AC power. Because the mains power supply is very convenient and economic, and uses electricity for family life, single-phase motors are not only used in large quantities in production, but also closely related to people's daily lives. Especially with the increasing living standards of the people, the amount of single-phase motors used in household appliances such as electric fans is also increasing. The single-phase motor adjusts the speed of the motor through the speed control circuit.
  • the first single-phase motor speed regulation method is the inductive mechanical switch speed regulation.
  • the speed regulation scheme is realized by adjusting the inductance of the series connection to adjust the mechanical ratio of the auxiliary winding and the main winding inductance, but the speed regulation range of this scheme is limited and it is difficult Actual low speed start or adjustment.
  • the second single-phase motor speed regulation method is series reactance stepless speed regulation, which can realize smooth speed regulation, but the speed regulation range is limited, and the reactance size is large, and the system efficiency is low.
  • the third method is the thyristor speed regulation.
  • the bidirectional thyristor switch is used to complete the chopping control of the motor terminal voltage to realize the voltage regulation.
  • This method has low cost and simple implementation, so it is widely used at present.
  • the thyristor adjusts the speed at low speed, the waveform is chopped more and the deformation is larger, so the power factor (PF) is too low, which does not meet the power supply requirements. And the torque ripple is large and the noise is large.
  • the fourth method is AC chopper speed regulation.
  • This type of speed regulation circuit often requires multiple auxiliary power sources that are isolated from each other, and uses a large number of high-voltage components, such as usually requiring 8 high-voltage diodes and 2 high-voltage bidirectional switches, and The high-voltage devices do not share a common ground, so the circuit design is complicated.
  • the high-voltage devices and the control unit need to be isolated from each other, and multiple isolated power supplies are required, which makes it difficult to achieve system integration. Because the overall system is complex and the cost is relatively high, it is difficult to be practically applied.
  • Another control method is frequency conversion inverter speed regulation, which includes AC-DC conversion circuit that rectifies and filters the AC power to obtain a DC stabilized power supply and a chopping circuit that performs frequency conversion and chopping on the square wave signal, although it has simultaneous amplitude modulation It has the advantages of frequency modulation and flexible application, but it needs to use a large capacitor or an AC-DC switching converter circuit to obtain a DC voltage stabilization source after the input rectifier circuit, and a complex frequency conversion inverter circuit to generate an AC frequency conversion voltage source. Its large size, high cost and complicated system operation. And because of the presence of the input rectifier filter capacitor, its power factor is low, such as half-load power factor is often between 0.5 and 0.6. Therefore, for high-power inverters, it is often necessary to add additional front-end power factor correction (PFC) circuits. But this also increases the system cost and introduces additional losses.
  • PFC front-end power factor correction
  • an object of the present application is to provide a stepless speed regulation circuit and speed regulation method for driving a single-phase motor for solving at least part of the above defects.
  • a stepless speed regulation circuit for driving a motor including: a switching circuit having an input terminal, a ground potential terminal, a first output terminal and a second output terminal, wherein the input terminal is used for Receiving a one-way pulsating steamed bun wave signal, in which the one-way pulsating steamed bun wave signal is a full-wave rectified signal of sinusoidal alternating current signal.
  • the first output terminal and the second output terminal of the switch circuit are used to couple the motor.
  • the switch circuit includes the first A switch, a second switch, a third switch and a fourth switch, wherein the first switch is coupled between the input terminal and the first output terminal, the second switch is coupled between the input terminal and the second output terminal, the third The switch is coupled between the second output terminal and the ground potential terminal, and the fourth switch is coupled between the first output terminal and the ground potential terminal; a synchronization signal generating circuit is used to generate a synchronization signal, in which the sinusoidal alternating current signal In the first half of the cycle, the synchronization signal is in the first state, and in the second half of the sinusoidal alternating current signal, the synchronization signal is in the second state, which is different from the first state; the switch drive circuit is used according to the state of the synchronization signal.
  • At least one of the first switch, the second switch, the third switch, and the fourth switch is selected to chopp at the second frequency for forming a sinusoidal envelope between the first output and the second output
  • the chopping signal wherein the envelope of the sine envelope chopping signal is synchronized with the waveform of the sinusoidal alternating current signal, and the second frequency is more than 10 times the frequency of the sinusoidal alternating current signal.
  • the switch driving circuit when the synchronization signal is in the first state, the switch driving circuit turns on the first switch, chops the third switch, and turns off the second switch and the fourth switch at the same time; when the synchronization signal is in the second state At this time, the switch driving circuit turns on the second switch, chops the fourth switch, and turns off the first switch and the third switch at the same time.
  • the switch driving circuit when the synchronization signal is in the first state, the switch driving circuit turns on the first switch, turns off the fourth switch, and performs reverse phase synchronous chopping on the second switch and the third switch; when the synchronization signal is the first In the second state, the switch driving circuit turns on the second switch, turns off the third switch, and performs synchronous chopping of the first switch and the fourth switch in reverse phase.
  • the switch driving circuit further selects at least one switch among the first switch, the second switch, the third switch, and the fourth switch to turn on in at least one of the states of the synchronization signal according to the state of the synchronization signal and at least A switch is turned off to form a sinusoidal envelope chopping signal between the first output terminal and the second output terminal.
  • the switch driving circuit chops the switch by outputting a pulse width modulation signal.
  • the stepless speed regulation circuit further includes a rectifier circuit, which is used to convert the sinusoidal alternating current signal of the commercial power into a one-way pulsating bun wave signal.
  • the synchronization signal is generated based on a sinusoidal alternating current signal, wherein when the sinusoidal alternating current signal is greater than zero, the synchronization signal is in the first state; when the sinusoidal alternating current signal is less than zero, the synchronization signal is different from the first state The second state.
  • the stepless speed regulation circuit further includes a capacitor coupled between the input terminal and the ground potential terminal.
  • the effective capacitance value between the input terminal and the ground potential terminal is lower than 4.7 microfarads.
  • the first switch, the second switch, the third switch, and the fourth switch are high-voltage power switches, the drains or collectors of the first switch and the second switch are coupled to the input terminal, and the source of the first switch
  • the emitter or emitter is coupled to the first output, the source or emitter of the second switch is coupled to the second output; the source or emitter of the third and fourth switches is coupled to the ground potential, and the drain of the third switch
  • the electrode or collector is coupled to the second output terminal, and the drain or collector of the fourth switch is coupled to the first output terminal.
  • the switch driving circuit includes: a logic circuit having an input terminal, a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal, wherein the input terminal of the logic circuit is coupled to the synchronization signal generation circuit
  • the output of the first half-bridge driving circuit has two input terminals and two output terminals, wherein the two input terminals of the first half-bridge driving circuit are respectively coupled to the first output terminal and the second output terminal of the logic circuit, The two output terminals of the first half-bridge driving circuit are respectively coupled to the control terminal of the first switch and the control terminal of the fourth switch; and the second half-bridge driving circuit has two input terminals and two output terminals, of which the second The two input terminals of the half-bridge drive circuit are respectively coupled to the third output terminal and the fourth output terminal of the logic circuit, and the two output terminals of the second half-bridge drive circuit are respectively coupled to the control terminal of the second switch and the third switch Control terminal.
  • the motor includes a single-phase asynchronous motor.
  • a stepless speed regulation method for driving a motor which includes: full-wave rectification of a sinusoidal alternating current signal into a one-way pulsating bun wave signal; and inputting the one-way pulsating bun wave signal to H
  • the input of the bridge switch circuit provides a synchronization signal, where the synchronization signal is in the first state during the first half cycle of the sinusoidal AC electrical signal, and the second state is during the second half cycle of the sinusoidal AC electrical signal; depending on the state of the synchronization signal
  • drive the motor with a sinusoidal envelope chopping signal and adjust the motor speed by adjusting the duty cycle of the chopping signal that chops the switch.
  • the method for selecting at least one switch in the H-bridge switch circuit for chopping according to the state of the synchronization signal includes: providing a first drive signal synchronized with the synchronization signal for driving the first switch in the H-bridge switch circuit ; Provide a second drive signal inverse to the synchronization signal, used to drive the second switch in the H-bridge switch circuit; the first drive signal and the pulse width modulation signal and the operation to form a first chopping signal, used to drive H The third switch in the bridge switch circuit; and the second drive signal and the pulse width modulation signal are ANDed to form a second chopping signal for driving the fourth switch in the H bridge switch circuit.
  • the method for selecting at least one switch in the H-bridge switching circuit for chopping according to the state of the synchronization signal includes: performing an OR operation on the synchronization signal and the pulse width modulation signal to form a first driving signal for driving the first switch ; Invert the synchronization signal and OR operation with the pulse width modulation signal to form a second drive signal for driving the second switch; Invert the second drive signal for driving the third switch; and the first drive The signal is inverted and used to drive the fourth switch.
  • a speed regulating circuit for driving a motor including: a switching circuit having an input terminal, a ground potential terminal, a first output terminal and a second output terminal, wherein the input terminal is used for receiving The unidirectional pulsating steamed bun wave signal after the full-wave rectification of the sinusoidal alternating current signal is used to couple the motor between the first output terminal and the second output terminal.
  • the switch circuit includes a first switch, a second switch, a third switch and a Four switches, wherein the first switch is coupled between the input terminal and the first output terminal, the second switch is coupled between the input terminal and the second output terminal, and the third switch is coupled between the second output terminal and the ground potential terminal Between, the fourth switch is coupled between the first output terminal and the ground potential terminal; a synchronization signal generating circuit whose output terminal is used to provide a synchronization signal associated with a sinusoidal alternating current signal; and a switch driving circuit used to synchronize
  • the signal turns on the first switch and chops the third switch during the first half cycle of the sinusoidal AC signal, and turns off the second and fourth switches at the same time; turns on the second switch during the second half cycle of the sinusoidal AC signal , Chopper the fourth switch, and turn off the first switch and the third switch at the same time.
  • the switch driving circuit includes: a logic circuit having an input terminal and at least two output terminals, wherein the input terminal of the logic circuit is coupled to the output terminal of the synchronization signal generation circuit, and the output terminal of the logic circuit provides at least two logics Signals; and a driver stage circuit having at least two input terminals and at least two output terminals, wherein at least two input terminals of the driver stage circuit are used to receive at least two logic signals of the logic circuit, and at least two outputs of the driver stage circuit The terminal is used to control the first switch, the second switch, the third switch and the fourth switch.
  • the synchronization signal is in a first state during the first half cycle of the sinusoidal AC electrical signal, and is in a second state different from the first state during the second half cycle of the sinusoidal AC electrical signal;
  • the signal at the first switch control terminal is synchronized with the synchronization signal waveform ;
  • the signal of the second switch control terminal is the inverse signal of the synchronization signal;
  • the signal of the fourth switch control terminal is the AND signal of the signal of the second switch control terminal and the pulse width modulation signal;
  • the signal of the third switch control terminal is the signal of the first switch control terminal AND signal with PWM signal.
  • a speed regulating circuit for driving a motor including: a switching circuit having an input terminal, a ground potential terminal, a first output terminal and a second output terminal, wherein the input terminal is used for receiving The unidirectional pulsating steamed bun wave signal after the full-wave rectification of the sinusoidal alternating current signal is used to couple the motor between the first output terminal and the second output terminal.
  • the switch circuit includes a first switch, a second switch, a third switch and a Four switches, wherein the first switch is coupled between the input terminal and the first output terminal, the second switch is coupled between the input terminal and the second output terminal, and the third switch is coupled between the second output terminal and the ground potential terminal Between, the fourth switch is coupled between the first output terminal and the ground potential terminal; a synchronization signal generating circuit whose output terminal is used to provide a synchronization signal associated with a sinusoidal alternating current signal; and a switch driving circuit used to synchronize In the first half of the sinusoidal AC signal, the signal turns on the first switch, the fourth switch is turned off, and the second switch and the third switch are synchronously chopped in reverse phase; in the second half of the sinusoidal AC signal, the first The second switch turns off the third switch, and performs reverse phase synchronous chopping on the first switch and the fourth switch.
  • a speed regulating circuit for driving a motor including: an H-bridge switching circuit having an input terminal, a ground potential terminal, a first output terminal, and a second output terminal, wherein the input terminal is used For receiving the one-way pulsating bun wave signal, the one-way pulsating bun wave signal is a full-wave rectified signal of the sinusoidal alternating current signal of the commercial power, and the first output terminal and the second output terminal are used to couple the motor; and the switch driving circuit, In the first half cycle of the mains sinusoidal AC signal, chopping at least one switch in the H-bridge switching circuit, and in the second half cycle of the mains sinusoidal AC signal, chopping at least one other switch in the H-bridge switching circuit The wave is used to generate a sinusoidal envelope chopping signal between the first output terminal and the second output terminal, wherein the half-load power factor of the speed regulating circuit is greater than 0.9.
  • the stepless speed regulation circuit and speed regulation method of the motor provided by the present application has a small circuit volume, effectively reduces the system complexity and cost, and has a high power factor, and can greatly improve the efficiency of the motor at low speed, and its specific advantages It will be shown in conjunction with the following specific embodiments.
  • FIG. 1 shows a schematic diagram of a stepless speed regulation circuit for driving a motor according to an embodiment of the present application
  • FIG. 2 shows a schematic diagram of signal waveforms corresponding to the circuit in FIG. 1 according to an embodiment of the present application
  • FIG. 3 shows a schematic diagram of a single-phase motor stepless speed regulation circuit system according to an embodiment of the present application
  • FIG. 4 shows a schematic diagram of signal waveforms for stepless speed control of a single-phase motor corresponding to the signals in the circuit of FIG. 3 according to an embodiment of the present application;
  • FIG. 5 shows a schematic diagram of a signal waveform corresponding to each signal in the circuit of FIG. 3 for performing stepless speed control of a single-phase motor according to another embodiment of the present application;
  • FIG. 6 shows a block diagram of a stepless speed regulation method for driving a motor according to an embodiment of the present application
  • FIG. 7 shows a schematic diagram of a synchronization signal generating circuit according to an embodiment of the present application.
  • FIG. 8 shows a schematic diagram of a sinusoidal envelope chopping signal, its envelope and a sinusoidal alternating current signal Vsin according to an embodiment of the present application
  • FIG. 9 shows a schematic waveform diagram of a prototype test experiment according to an embodiment of the present application.
  • FIG. 10 shows a comparison test schematic diagram of the input power of the prototype motor speed control circuit according to an embodiment of the present application and the input power of the prior art solution at different motor speeds;
  • FIG. 11 shows a comparison test diagram of the input power factor of the prototype motor speed control circuit according to an embodiment of the present application and the input power factor of the prior art solution at different motor speeds.
  • Coupling in the specification includes direct connection and indirect connection, such as connection through an electrically conductive medium such as a conductor, where the electrically conductive medium may contain parasitic inductance or parasitic capacitance. It may also include connections known to those skilled in the art through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as connection of circuits or components such as switches, follower circuits, and the like.
  • FIG. 1 shows a stepless speed regulation circuit for driving a motor according to an embodiment of the present application.
  • the stepless speed regulation circuit is used to drive the single-phase asynchronous motor M.
  • the stepless speed regulation circuit includes a rectifier circuit 10, a switch circuit 11, a synchronization signal generation circuit 12, and a switch drive circuit 13.
  • the rectifying circuit 10 is used for full-wave rectification of the sinusoidal alternating current signal Vsin to generate a one-way pulsating steamed bun wave signal Vin.
  • the sinusoidal alternating current signal Vsin is a commercial alternating current and has a power frequency, such as 50 Hz.
  • the stepless speed regulation circuit may not include the rectifier circuit 10, that is, the rectifier circuit is placed outside the stepless speed regulation circuit.
  • the motor M can also be other types of motors.
  • the switch circuit 11 has an input terminal IN, a ground potential terminal GND, a first output terminal Vo1 and a second output terminal Vo2, wherein the input terminal IN is used to receive the unidirectional pulsating steamed bun wave signal Vin, the first output terminal Vo1 and the second output The terminal Vo2 is used to couple the motor M, and the ground potential terminal GND is used to couple to the reference ground.
  • the one-way pulsating steamed bun wave signal Vin is the full-wave rectified signal of the sinusoidal alternating current signal Vsin.
  • the switch circuit 11 includes a first switch Q1, a second switch Q2, a third switch Q3, and a fourth switch Q4.
  • the first switch Q1 is coupled between the input terminal Vin and the first output terminal Vo1
  • the second switch Q2 is coupled between the input terminal Vin and the second output terminal Vo2
  • the third switch Q3 is coupled to the second output terminal Vo2
  • the fourth switch Q4 is coupled between the first output terminal Vo1 and the ground potential terminal GND.
  • This switching circuit 11 may also be referred to as an H-bridge switching circuit.
  • the synchronization signal generating circuit 12 is used to generate a synchronization signal SYN associated with the sinusoidal alternating current signal Vsin or the unidirectional pulsating steamed bun wave signal Vin.
  • the synchronization signal SYN exhibits a first state S1 having a first level (such as a high level) and a second level (such as a low level) different from the first level ), the second state S2, the first state S1 and the second state S2 alternate, wherein the period of the first state S1 and the period of the second state S2 correspond one-to-one to the period of the one-way pulsating bun wave signal Vin.
  • the synchronization signal SYN is the first state S1, such as high level
  • the synchronization signal SYN is a second state S2 different from the first state , Such as low level.
  • the synchronization signal generating circuit 12 generates a synchronization signal SYN based on the sinusoidal alternating current signal Vsin before rectification, as shown in FIG. 1.
  • the synchronization signal SYN is generated according to the alternating current of the commercial power, and its frequency corresponds to the frequency of the alternating current of the commercial power, for example, it is high level during each first half cycle of the commercial power alternating current, and is low level during each second half cycle of the commercial power alternating current .
  • the synchronization signal generating circuit 12 generates a synchronization signal SYN based on the one-way pulsating bun wave signal Vin, as shown by the dotted line in FIG. 1, if the period corresponding to the odd number of one-way pulsating bun wave signals is high, The period of the even-numbered one-way pulsating steamed bun wave signal is low.
  • the switch drive circuit 13 is used to output drive signals PWMA, PWMB, PWM2, and PWM1 according to the state of the synchronization signal SYN, for controlling the switch states of the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4, respectively, Select at least one of the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4 to chopp at the second frequency by controlling the states of the drive signals PWMA, PWM1, PWM2 and PWMB
  • the envelope of the sinusoidal envelope chopping signal Vo is synchronized with the sinusoidal alternating current signal Vsin and is a power frequency sinusoidal waveform.
  • the switch driving circuit 13 chops the switch by outputting a pulse width modulation (PWM) signal, so that the chopping frequency of the sinusoidal envelope chopping signal is the second frequency, where the second frequency is the frequency of the PWM signal.
  • PWM pulse width modulation
  • the effective value of the output voltage Vo is used to adjust the speed of the motor.
  • the synchronization signal SYN in the first half cycle of the sinusoidal alternating current signal Vsin, the synchronization signal SYN is in the first state (S1), and the switch driving circuit 13 chops the third switch Q3 at the second frequency; In the second half period of the alternating current signal Vsin, the synchronization signal SYN is in the second state (S2), and the switch driving circuit 13 chops the fourth switch Q4 at the second frequency for use at the first output terminal Vo1 and the second output terminal A sine envelope chopping signal is formed between Vo2.
  • the switch driving circuit 13 chops the fourth switch Q4 at the second frequency for use at the first output terminal Vo1 and the second output terminal
  • a sine envelope chopping signal is formed between Vo2.
  • the full-chopped sinusoidal envelope chopping signal Vo is shown.
  • the second switch Q2 and the third switch Q3 are chopped at the PWM frequency (second frequency) (the chopped signals are mutually inverted)
  • the first switch Q1 and the fourth switch Q4 are chopped at a second frequency (the chopping signals are mutually inverted), which are used for the first output terminal Vo1 and the second output
  • a sinusoidal envelope chopping signal is formed between the terminals Vo2.
  • FIG. 2 shows a signal waveform diagram corresponding to the circuit in FIG. 1 according to an embodiment of the present application.
  • the sinusoidal envelope chopping signal formed between the first output terminal Vo1 and the second output terminal Vo2 of the switching circuit 11 in FIG. 1, that is, the difference signal between the voltages Vo1 and Vo2 is the chopping signal Vo as shown in FIG. 2,
  • the envelope of the sinusoidal envelope chopping signal Vo is synchronized with the sinusoidal alternating current signal Vsin, preferably, in the shape of a sine wave.
  • the chopping frequency of the sinusoidal envelope chopping signal Vo that is, the second frequency is greater than 10 times the frequency of the sinusoidal alternating current signal Vsin.
  • the second frequency may be a non-fixed frequency.
  • the one-way pulsating steamed bun wave signal Vin is the waveform of the mains alternating current after full-wave rectification, and the period T of the sinusoidal envelope chopping signal Vo is equal to the period of the mains sinusoidal alternating current signal.
  • the frequency of the one-way pulsating steamed bun wave signal Vin is 2 times the power frequency.
  • the stepless speed regulation of the single-phase motor can be realized by adjusting the duty ratio of the chopping signal Vo.
  • the system input current waveform at the AC input terminal is also consistent with the mains alternating current waveform.
  • This stepless adjustment Speed circuits can have a very high power factor (PF).
  • FIG. 3 shows a schematic diagram of a single-phase motor stepless speed regulation circuit system according to an embodiment of the present application.
  • the motor stepless speed regulation circuit includes a rectifier circuit 10, a switch circuit 11, a synchronization signal generating circuit 12, and a switch drive circuit.
  • the rectifier circuit 10 is used to convert the sinusoidal alternating current signal Vsin into a one-way pulsating bun wave signal Vin.
  • the sinusoidal alternating current signal Vsin is a mains sinusoidal alternating current signal.
  • the sinusoidal alternating current signal of the commercial power may be affected by other factors such as electromagnetic interference, the sinusoidal alternating current signal Vsin is distorted, and its waveform may not be a strict sine wave shape.
  • the synchronization signal generating circuit 12 generates a synchronization signal SYN based on the sinusoidal alternating current signal Vsin.
  • the synchronization signal generation circuit 12 includes a zero-crossing detection circuit, and whenever the sinusoidal alternating current signal Vsin crosses zero, the state of the synchronization signal SYN reverses.
  • FIG. 7 shows a schematic diagram of a synchronization signal generating circuit according to an embodiment of the present application, which will be described in detail below. In this way (see FIG.
  • the synchronization signal SYN when the sinusoidal alternating current signal Vsin is greater than zero, the synchronization signal SYN is in the first state (such as a high level state); when the sinusoidal alternating current signal Vsin is less than zero, the synchronization signal SYN is different from the first The second state of the state (low level).
  • the synchronization signal SYN is the first state S1 in the first half cycle of the sinusoidal alternating current signal Vsin, and is in the second state (S2) different from the first state in the second half period of the sinusoidal alternating current signal Vsin.
  • the switch driving circuit includes a logic circuit 32, a first half-bridge driving circuit 331 and a second half-bridge driving circuit 332.
  • the switch drive circuit chops at least one of the switches Q1-Q4 by outputting a pulse width modulation (PWM) signal according to the state of the synchronization signal SYN.
  • PWM pulse width modulation
  • the logic circuit 32 is used to output the driving signals PWMA, PWM1, PWMB and PWM2 of the four control switches Q1-Q4 according to the synchronization signal SYN.
  • the logic circuit 32 has an input terminal, a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal, wherein the input terminal of the logic circuit 32 is coupled to the output terminal of the synchronization signal generation circuit 12 for receiving Synchronization signal SYN.
  • the first output terminal, the second output terminal, the third output terminal, and the fourth output terminal of the logic circuit 32 are used to output four drive signals PWMA, PWM1, PWMB, and PWM2, respectively.
  • the signal PMMA output from the first output terminal of the logic circuit 32 is synchronized with the synchronization signal SYN, so that the signal at the control terminal of the first switch Q is synchronized with the synchronization signal waveform.
  • the signal PWMB output from the third output terminal of the logic circuit 32 is an inverted signal of the synchronization signal SYN, so that the signal at the control terminal of the second switch Q2 is an inverted signal of the synchronization signal.
  • the signal PWM1 at the second output of the logic circuit 32 is the sum of the signal PWMB and the pulse width modulation (PWM) signal at the third output of the logic circuit, so that the signal at the control terminal of the fourth switch Q4 is the signal and the pulse width at the control terminal of the second switch AND signal of modulated signal.
  • the signal PWM2 of the fourth output terminal of the logic circuit 32 is the AND signal of the signal PWMA and the pulse width modulation (PWM) signal of the first output terminal of the logic circuit, so that the signal of the third switch Q3 control terminal is the signal and pulse width of the first switch control terminal AND signal of modulated signal.
  • the signal PMMA output from the first output terminal of the logic circuit 32 is the OR signal of the synchronization signal SYN and the pulse width modulation signal.
  • the signal PWMB output from the third output terminal of the logic circuit 32 is the OR signal of the inverted signal of the synchronization signal SYN and the pulse width modulation signal.
  • the signal PWM1 of the second output terminal of the logic circuit 32 is an inverted signal of the signal PMMA output from the first output terminal.
  • the signal PWM2 of the fourth output terminal of the logic circuit 32 is an inverted signal of the signal PWMB output from the third output terminal.
  • each driving signal PWMA, PWM1, PWMB and PWM2 sets a dead time to prevent the switch from being turned on at the same time by mistake.
  • the driving stage circuit includes a first half-bridge driving circuit 331 and a second half-bridge driving circuit 332.
  • the first half-bridge driving circuit 331 has two input terminals and two output terminals, wherein the two input terminals are respectively coupled to the first output terminal and the second output terminal of the logic circuit 32 for receiving the driving signals PWMA and PWM1.
  • the two output ends of the half-bridge driving circuit 331 are respectively coupled to the control end of the first switch Q1 and the control end of the fourth switch Q4 for controlling the turning on or off of the switches Q1 and Q4.
  • the first driving signal PWMA signal controls the first switch Q1
  • the second driving signal PWM1 controls the fourth switch Q4.
  • the second half-bridge driving circuit 332 has two input terminals and two output terminals, wherein the two input terminals of the second half-bridge driving circuit 332 are respectively coupled to the third output terminal and the fourth output terminal of the logic circuit 32 for receiving
  • the driving signals PWMB and PWM2 the two output ends of the second half-bridge driving circuit 332 are respectively coupled to the control end of the second switch Q2 and the control end of the third switch Q3 to control the turning on or off of the switches Q2 and Q3.
  • the third drive signal PWMB signal controls the second switch Q2
  • the fourth drive signal PWM2 controls the third switch Q3.
  • the switch driving circuit may have a different structure.
  • the logic circuit has two output terminals, which are used to provide the signals PWMA and PWMB as shown in FIG. 5, or provide PWM1 and PWM2 as shown in FIG. 5, which are amplified by the driver stage circuit to provide two drives
  • the signal is used to drive four switching tubes respectively, where switching tubes Q1 and Q4 have opposite doping types controlled by PWMA or PWM1 signals, Q2 and Q3 have opposite semiconductor doping types and are controlled by PWMB or PWM2 signals, opposite doping
  • the switch state of the type of switch is opposite under the same switch signal.
  • the driving stage circuit can also output four driving signals as shown in the waveform of FIG. 5 based on two input signals to control the four switching tubes.
  • the logic circuit may have three output terminals, which are used to provide PWMA, PWM1, and PWM2 as shown in FIG. 4, and are amplified by the driver stage circuit to output three driving signals to drive Q1 and Q2, Q3, respectively. And Q4, where the doping types of Q1 and Q2 are opposite. Or the driving stage circuit can also provide four driving signals for driving four switches of the same doping type.
  • the logic circuit provides four logic signals PWMA, PWMB, PWM1, and PWM2.
  • the driver stage circuit includes a full-bridge drive circuit for receiving four logic signals, and provides four drive signals to drive four switch tubes, respectively. Q1, Q2, Q3 and Q4.
  • the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4 are metal oxide semiconductor field effect transistors (MOSFETs), and the first switch Q1 and the second switch Q2
  • MOSFETs metal oxide semiconductor field effect transistors
  • the drain of is coupled to the input terminal IN, the source of the first switch Q1 is coupled to the first output terminal Vo1, the source of the second switch Q2 is coupled to the second output terminal Vo2; the sources of the third switch Q3 and the fourth switch Q4
  • the pole is coupled to the ground potential terminal GND, the drain of the third switch Q3 is coupled to the second output terminal Vo2, and the drain of the fourth switch Q4 is coupled to the first output terminal Vo1.
  • the switches Q1-Q4 can also be other types of high-voltage power switches, such as junction field effect transistors (JFET) or bipolar junction transistors (BJT).
  • JFET junction field effect transistors
  • BJT bipolar junction transistors
  • the switches Q1, Q2, Q3, and Q4 are BJT transistors
  • the collectors of the first switch Q1 and the second switch Q2 are coupled to the input terminal IN, and the emitter of the first switch Q1 is coupled to the first output At the terminal Vo1
  • the emitter of the second switch Q2 is coupled to the second output terminal Vo2
  • the emitters of the third switch Q3 and the fourth switch Q4 are coupled to the ground potential terminal GND
  • the collector of the third switch Q3 is coupled to the second output terminal Vo2
  • the collector of the fourth switch Q4 is coupled to the first output terminal Vo1.
  • switches Q1, Q2, Q3, and Q4 are BJT tubes, a diode is connected in parallel between the emitter and collector of each switch to provide a freewheeling path.
  • the switches Q1 and Q2 are the first type of switch, and the switches Q3 and Q4 can be another type of switch.
  • the single-phase motor stepless speed regulation circuit further includes a capacitor Cf, coupled between the input terminal IN of the switch circuit 11 and the ground potential terminal GND, for turning off the switch Q1 or Q2 To provide a freewheeling path for the parasitic diode to prevent sudden changes in the Vo1 or Vo2 voltage at the output.
  • the capacitor Cf is only used to provide a freewheeling path, so the capacitor Cf does not need to have a large capacitance value, and only a small capacitor is needed.
  • the capacitor Cf is a thin film capacitor. This solution does not require the use of large-capacity capacitors such as electrolytic capacitors for providing stable DC power in other technologies, or the need for additional sampling AC-DC conversion circuits, etc., thus greatly reducing the cost and volume of the system.
  • the capacitance of the capacitor Cf is selected to be 0.47 microfarads. In one embodiment, the capacitance of the capacitor Cf is selected to be 0.33 microfarads.
  • the capacitance of the switch circuit 11 when the capacitance of the switch circuit 11 is not considered, if the parasitic capacitance or equivalent working capacitance of the switch circuit 11 is not considered, such as when the switch circuit 11 is removed, the input terminal IN and the ground potential terminal GND The effective capacitance between is below 1 microfarad.
  • the capacitance value of the switching circuit 11 when the capacitance value of the switching circuit 11 is not considered, the effective capacitance value between the input terminal IN and the ground potential terminal GND can also be lower than 4.7 microfarads, which is far lower than the tens to Hundreds of microfarads.
  • the signals from top to bottom are sinusoidal alternating current signal Vsin, unidirectional pulsating bun wave signal Vin, synchronization signal SYN, switch drive signal PWMA for driving the first switch Q1, and switch drive signal for driving the third switch Q3 PWM2, a switch drive signal PWMB for driving the second switch Q2, and a switch drive signal PWM1 for driving the fourth switch Q4.
  • the one-way pulsating steamed bun wave signal Vin is the full-wave rectified signal of the sinusoidal alternating current signal Vsin.
  • the synchronization signal SYN is associated with the one-way pulsating bun wave signal Vin of the bun waveform or the sinusoidal alternating current signal Vsin before rectification. Among them, in the first half period of the sinusoidal alternating current signal Vsin, the synchronization signal SYN is high level, and in the latter half period of the sinusoidal alternating current signal Vsin, the synchronization signal SYN is low level. Of course, the high and low levels of the synchronization signal SYN can also be swapped.
  • the synchronization signal SYN is high (first state S1)
  • the drive signal PWMA is high
  • the drive signal PWM2 is a high-frequency chopping signal
  • the drive signals PWMB and PWM1 are low level.
  • the switch driving circuit turns on the first switch Q1, chops the third switch Q3, and turns off the second switch Q2 and the fourth switch Q4.
  • the synchronization signal SYN is low (second state S2)
  • the drive signal PWMB is high
  • the drive signal PWM1 is a high-frequency chopping signal
  • the drive signals PWMA and PWM2 are low Level.
  • the switch driving circuit turns on the second switch Q2, chops the fourth switch Q4, and turns off the first switch Q1 and the third switch Q3 at the same time.
  • the chopping frequency (second frequency) of the high-frequency chopping signal is more than 10 times the frequency of the sinusoidal alternating current signal Vsin.
  • the first drive signal PWMA driving the first switch Q1 in the H-bridge switching circuit is synchronized with the synchronization signal SYN
  • the envelope of the chopping signal PWM2 driving the third switch Q3 in the H-bridge switching circuit is
  • the driving signal PWMA has the same shape
  • the second driving signal PWMB driving the second switch in the H-bridge switching circuit is inverse to the synchronization signal SYN
  • the envelope of the chopping signal PWM1 driving the fourth switch Q4 in the H-bridge switching circuit is the same as the second
  • the driving signal PWMB has the same shape.
  • the chopping signal is a pulse width modulated signal where each pulse is completely turned on.
  • FIG. 5 shows a signal waveform diagram for performing stepless speed control of a single-phase motor corresponding to each signal in the circuit of FIG. 3 according to another embodiment of the present application.
  • the signals from top to bottom are sinusoidal alternating current signal Vsin, unidirectional pulsating bun wave signal Vin, synchronization signal SYN, switch drive signal PWMA for driving switch Q1, switch drive signal PWM2 for driving switch Q3, and The switch drive signal PWMB driving the switch Q2 and the switch drive signal PWM1 driving the switch Q4.
  • the one-way pulsating steamed bun wave signal Vin is the full-wave rectified signal of the sinusoidal alternating current signal Vsin.
  • the synchronization signal SYN is in the first state (high level)
  • the driving signal PWMA for driving the first switch Q1 is a high level signal
  • the driving signal PWMB for driving the second switch Q2 It is a PWM chopping signal.
  • the driving signal PWM2 for driving the third switch Q3 is a PWM chopping signal of the same frequency that is inverse to the driving signal PWMB.
  • the driving signal PWM1 for driving the fourth switch Q4 is a low-level signal.
  • the switch drive circuit turns on the first switch Q1, turns off the fourth switch Q2, and performs synchronous chopping of the second switch Q2 and the third switch Q3 in reverse phase with each other.
  • the second switch Q2 and the third switch Q3 are turned on and off at a chopping frequency (or second frequency) higher than the frequency of the one-way pulsating bun wave signal Vin, when the second switch Q2 is turned on ,
  • the third switch Q3 is turned off; when the second switch Q2 is turned off, the third switch Q3 is turned on.
  • the synchronization signal SYN is in the second state (low level)
  • the driving signal PWMA for driving the first switch Q1 is the PWM chopping signal of the second frequency for driving the second
  • the drive signal PWMB of the switch Q2 is a high-level signal
  • the drive signal PWM2 for driving the third switch Q3 is a low-level signal
  • the drive signal PWM1 for driving the fourth switch Q4 is the same frequency as the inverted phase of the drive signal PWMA Chopping the signal.
  • the switch driving circuit turns on the second switch Q2, turns off the third switch Q3, and synchronously chops the first switch Q1 and the fourth switch Q4 in reverse phase with each other, that is, the first switch Q1 at the second frequency Turning on and off with the fourth switch Q4, when the first switch Q1 is turned on, the fourth switch Q4 is turned off; when the first switch Q1 is turned off, the fourth switch Q4 is turned on.
  • the second frequency is more than 10 times the frequency of the sinusoidal alternating current signal Vsin.
  • At least one of the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4 is selected to perform at the second frequency according to the state of the synchronization signal SYN Chopping is used to form a sinusoidal envelope chopping signal Vo between the first output Vo1 and the second output Vo2.
  • the third switch Q3 is chopped at the second frequency
  • S2 the third switch Q3
  • S2 the second state
  • the second switch Q2 and the third switch Q3 are chopped at the second frequency, where the second switch Q2 and the third switch Q3
  • the chopping signals are opposite to each other.
  • the first switch Q1 and the fourth switch Q4 are chopped at a second frequency, wherein the chopping signals of the first switch Q1 and the fourth switch Q4 are mutually
  • the reverse phase is used to form a sinusoidal envelope chopping signal between the first output terminal Vo1 and the second output terminal Vo2.
  • the first switch Q1, the second switch Q2, the third switch Q3 and the third switch At least one switch of the four switches Q4 is chopped at the second frequency, and at least one switch is turned on and at least one switch is turned off for use at the first output terminal Vo1 and the second output terminal Vo2 Form a sinusoidal envelope chopping signal Vo.
  • the third switch Q3 is chopped at the second frequency, the first switch Q1 is turned on, and the second The switch Q2 and the fourth switch Q4 are turned off.
  • the fourth switch Q4 When the synchronization signal SYN is in the second state (S2), the fourth switch Q4 is chopped at the second frequency, the second switch Q2 is turned on, and the first The switch Q1 and the third switch Q3 are turned off, and through such control, it is used to form a sinusoidal envelope chopping signal between the first output terminal Vo1 and the second output terminal Vo2.
  • S2 the second state
  • S3 the first The switch Q1 and the third switch Q3 are turned off, and through such control, it is used to form a sinusoidal envelope chopping signal between the first output terminal Vo1 and the second output terminal Vo2.
  • the stepless speed regulation circuit generates a sinusoidal envelope chopping signal as indicated by the signal Vo in FIG. 2 between the output terminals Vo1 and Vo2 of the switching circuit.
  • Vo Vo1-Vo2
  • the envelope waveform of the sinusoidal envelope chopping signal Vo is synchronized with the waveform of the sinusoidal alternating current signal Vsin, and has the same frequency (same period T) and approximate waveform, see FIG. 8.
  • step 601 shows a block diagram of a stepless speed regulation method for driving a single-phase motor according to an embodiment of the present application.
  • the method includes steps 601-605.
  • step 601 the full-wave rectification of the sinusoidal alternating current signal Vsin is converted into a one-way pulsating bun wave signal Vin.
  • the sinusoidal alternating current signal is mains alternating current.
  • step 602 the one-way pulsating steamed bun wave signal Vin is input to the input terminal of the H-bridge switching circuit.
  • a synchronization signal SYN is provided based on the sinusoidal alternating current signal Vsin, wherein in the first half period of the sinusoidal alternating current signal Vsin, the synchronization signal SYN is in a first state, such as a high level, in the latter half period of the sinusoidal alternating current signal Vsin, The synchronization signal SYN is in the second state, such as low level.
  • the synchronization signal SYN is generated by detecting the zero-crossing signal of the sinusoidal alternating current signal Vsin, and when the sinusoidal alternating current signal Vsin crosses the zero value, the state of the synchronization signal SYN is switched.
  • the synchronization signal SYN is generated according to the one-way pulsating steamed bun wave signal Vin.
  • the state of the synchronization signal SYN changes so that the synchronization signal SYN is at the odd number
  • the period of the pulsating steamed bun wave signal is the first state
  • the period of the even-numbered one-way pulsating steamed bun wave signal is the second state.
  • step 604 at least one switch in the H-bridge switching circuit is selectively chopped according to the state of the synchronization signal SYN, for providing a sinusoidal envelope chopping signal Vo at the output of the H-bridge switching circuit, wherein the sinusoidal envelope is chopped
  • the envelope of the wave signal is synchronized with the waveform of the sinusoidal alternating current signal.
  • a method for selectively chopping at least one switch in the H-bridge switching circuit according to the state of the synchronization signal SYN includes: providing a first drive signal PWMA synchronized with the synchronization signal SYN for driving the H-bridge switch The first switch Q1 in the circuit; provides a second drive signal PWMB inverted with the synchronization signal SYN, for driving the second switch Q2 in the H-bridge switch circuit; provides an envelope with the same shape as the first drive signal PWMA
  • the first chopping signal PWM2, that is, the first driving signal PWMA and the pulse width modulation (PWM) signal are combined to form the first chopping signal PWM2, which is used to drive the third switch Q3 in the H-bridge switching circuit;
  • the two driving signals PWMB have a second chopping signal PWM1 with an envelope of the same shape, that is, the second driving signal PWMB and a pulse width modulation (PWM) signal are AND-operated to form a second chopping signal PWM1 for
  • the chopping frequency of the chopping signal PWM1 or PWM2 is more than 10 times the frequency of the sinusoidal alternating current signal.
  • each switch control mode of the H-bridge switch circuit may also be as shown in FIG. 5, and the method of selectively chopping at least one switch in the H-bridge switch circuit according to the state of the synchronization signal SYN includes: The synchronizing signal SYN and the pulse width modulation PWM chopping signal are ORed to form a first driving signal PWMA, which is used to drive the first switch Q1; the synchronizing signal SYN is inverted and the ORing with the PWM chopping signal is formed to form a second driving signal PWMB, used to drive the second switch Q2; inverting the second drive signal PWMB to form the signal PWM2, used to drive the third switch Q3; and inverting the first drive signal PWMA to form the signal PWM1, used to drive the fourth Switch Q4.
  • step 605 the sinusoidal envelope chopping signal Vo is used to drive a single-phase motor, and the motor speed is adjusted according to the duty ratio of the chopping signal that chops the switch.
  • the synchronization signal generating circuit includes two parallel rectifier tubes D1 and D2 coupled in opposite directions to the two input terminals of the sinusoidal alternating current signal Vsin, two series-connected resistors with the same resistance, and a comparison circuit CMP.
  • the rectifiers D1 and D2 are respectively coupled between the two input terminals of the AC input power supply Vsin for rectifying the input sinusoidal AC electric signal Vsin.
  • the connection node of the resistor is coupled to the reference ground.
  • the two input terminals of the comparison circuit CMP are respectively coupled to the two input terminals of the sinusoidal alternating current signal Vsin, and are biased by a stable power supply relative to the reference ground.
  • the output of the comparison circuit provides the synchronization signal SYN as shown in FIG. 2.
  • the synchronization signal SYN is a high-value signal.
  • the synchronization signal SYN is Low value signal (zero value).
  • FIG. 8 shows a schematic diagram of a sinusoidal envelope chopping signal Vo, Vo envelope and a sinusoidal alternating current signal Vsin according to an embodiment of the present application. It can be seen that the envelope of the sinusoidal envelope chopping signal Vo is synchronized with the shape of the sinusoidal alternating current signal Vsin, and both have the same period and similar waveforms.
  • the sinusoidal alternating current signal Vsin In the first half period of the sinusoidal alternating current signal Vsin, the sinusoidal alternating current signal Vsin is greater than zero, and the envelope of the sinusoidal envelope chopping signal Vo is also a half-sine wave greater than zero value; in the latter half period of the sinusoidal alternating current signal Vsin, The sinusoidal alternating current signal Vsin is less than zero, and the envelope of the sinusoidal envelope chopping signal Vo is also a half-sine wave less than zero.
  • FIG. 9 shows a schematic waveform diagram of a prototype test experiment according to an embodiment of the present application.
  • the first signal is the one-way pulsating steamed bun wave signal Vin. It is a rectified signal after the full-wave rectification of the sinusoidal alternating current signal of the commercial power.
  • the third signal is the input current signal at the input end, that is, the front end of the rectifier circuit, and its envelope shape is also a sine wave signal with the same frequency as the input end sinusoidal AC electrical signal. Therefore, the input voltage and input current of the AC signal input terminal are in good agreement, and the power factor of the system is high.
  • the sinusoidal envelope chopping signal for driving a single-phase motor provided in the implementation of the present application, the envelope of which can basically correspond to the signal waveform of the commercial alternating current, and a high power factor can be obtained.
  • the H-bridge switching circuit by chopping at least one switch in the H-bridge switching circuit during the first half cycle of the sinusoidal AC signal of the commercial power supply, such as the third switch Q3 of FIG. 4 or the second switch of FIG. 5 Q2 and the third switch Q3 chopping, in the second half cycle of the mains sinusoidal AC signal, chopping at least one other switch in the H-bridge switching circuit, as shown in the fourth switch Q4 in FIG. 4, or
  • the first switch Q1 and the fourth switch Q4 in 5 perform chopping, which is used to generate a difference signal of a sinusoidal envelope chopping signal between the two output terminals of the H-bridge, and its half-load power factor is greater than 0.9.
  • Half load is 50% of full-scale output current.
  • the H-bridge circuit structure is shown in the switch circuit shown in FIG. 1 or FIG. 3.
  • the stepless speed regulation circuit of the motor in the embodiment of the present application can obtain a large power factor without a power factor correction circuit in front of the front end.
  • FIG. 10 shows a comparison test diagram of the input power of a motor speed control circuit prototype according to an embodiment of the present application and an input power of a prior art solution (multi-tap motor solution) on the market at different motor speeds.
  • the abscissa is the rotation speed of the fan (rpm, revolutions per minute), and the ordinate is the input power (W) at the input of the commercial power supply.
  • the curve 1001 is the input power of the solution of the embodiment of the present application, and the curve 1002 is the input power of the prior art solution. It can be seen that at the same fan speed, the input power of the technical solution of the present application is significantly reduced and has higher efficiency, especially when the speed is lower, the efficiency increase is more obvious. In a test case, when the rotational speed is low, the input efficiency of the speed regulation circuit of this scheme can be increased by more than 25%.
  • FIG. 11 shows a comparison test between the input power factor of a motor speed control circuit prototype according to an embodiment of the present application and the input power factor of a prior art solution (motor multi-speed tap and capacitor adjustment solution) at different motor speeds Schematic.
  • the abscissa is the speed of the fan (rpm, revolutions per minute), and the ordinate is the input power factor of the sinusoidal AC electrical signal input terminal.
  • the curve 1101 is the input power factor of the solution of the embodiment of the present application, and the curve 1102 is the input power factor of the prior art solution. It can be seen that at the same speed, the input power factor of the technical solution of the present application is significantly higher than that of the prior art.

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Abstract

一种无级调速电路及无级调速方法。用于驱动电机的无级调速电路，包括：开关电路（11），输入端用于接收正弦交流电信号经全波整流后的单向脉动馒头波信号，第一输出端和第二输出端之间用于耦接电机；同步信号发生电路（12），用于根据正弦交流电信号产生同步信号；开关驱动电路（13），用于根据同步信号的状态选择开关电路中至少一个开关以第二频率进行斩波，用于在第一输出端和第二输出端之间形成正弦包络斩波信号，其中正弦包络斩波信号的包络线与正弦交流电信号的波形同步。该电机无级调速电路及调速方法，电路体积小，且具有较高的功率因数，并可大大提高低速下电机的效率。

Description

单相电机无级调速电路及调速方法 技术领域
本申请涉及电子领域，具体涉及用于驱动单相电机的无级调速电路及调速方法。
背景技术
单相电机，一般是指由市电交流电提供的单相交流电源进行供电的异步电动机。因为市电电源供电非常方便经济，为家庭生活用电，所以单相电机不但在生产上用量大，而且也与人们日常生活密切相关。尤其是随着人民生活水平的日益提高，用于家用电器设备如电风扇等的单相电机的用量，也越来越大。单相电机通过调速电路来调节电机的转速。
第一种单相电机的调速方法为电感机械开关调速，通过调节串接的电感大小来调节辅助绕组与主绕组电感机械配比来实现调速方案，但是该方案调速范围有限，难以实际低速启动或调节。
第二种单相电机的调速方法为串电抗无级调速，能实现平滑调速，但是调速范围有限，且电抗尺寸大，系统效率低。
第三种方法为可控硅调速，通过双向可控硅开关来完成对电机端电压的斩波控制而实现调压。该方法成本低、实现简单，因而目前被广泛应用。然而，可控硅在低速调速时由于波形被斩波较多，变形较大，因而功率因数(PF)过低，不符合电源要求。且转矩脉动大，噪音大。
第四种方法为交流斩波器调速，该类调速电路往往需要多路相互隔离的辅助电源，且采用大量的高压元器件，如通常需要8个高压二极管和2个高压双向开关，且高压器件不共地，因此电路设计复杂，高压器件和控制单元之间需要相互隔离，且需要多个隔离电源，很难实现系统集成。因为整体系统复杂，成本偏高，很难被实际应用。
另有一种控制方法是变频逆变器调速，包括将交流电源进行整流滤波以获得直流稳压电源的交流-直流变换电路和对方波信号进行变频斩波的斩波电路等，虽然具有同时调幅调频、灵活应用的优势，但是需要在输入整流电路后采用大电容或交流-直流开关变换电路来获取直流稳压源，且采用复杂的变频逆变电路来产生交流变频电压源。其体积大，成本高,系统操作复杂。且因为输入整流滤波电容的存在，其功率因数较低，如半载功率因数经常为0.5至0.6之间。因此对于大功率逆变器往往需要增加额外的前级功率因数校正(PFC)电路。但这也增加了系统成本和引入额外的损耗。
发明内容
针对现有技术中的一个或多个问题，本申请的一个目的在于提供用于解决上述至少部分缺陷的驱动单相电机的无级调速电路及调速方法。
根据本申请的一个方面，提供了一种用于驱动电机的无级调速电路，包括：开关电路，具有输入端、地电位端、第一输出端和第二输出端，其中输入端用于接收单向脉动馒头波信号，其中单向脉动馒头波信号为正弦交流电信号的全波整流信号，开关电路的第一输出端和第二输出端之间用于耦接电机，开关电路包括第一开关、第二开关、第三开关和第四开关，其中第一开关耦接在输入端和第一输出端之间，第二开关耦接在输入端和第二输出端之间，第三开关耦接在第二输出端和地电位端之间，第四开关耦接在第一输出端和地电位端之间；同步信号发生电路，用于产生同步信号，其中在正弦交流电信号的前半周期，同步信号为第一状态，在正弦交流电信号的后半周期，同步信号为不同于第一状态的第二状态；开关驱动电路，用于根据同步信号的状态，在同步信号的任一状态下选择第一开关、第二开关、第三开关和第四开关中的至少一个开关以第二频率进行斩波，用于在第一输出端和第二输出端之间形成正弦包络斩波信号，其中正弦包络斩波信号的包络线与正弦交流电信号的波形同步，第二频率为正弦交流电信号的频率的10倍以上。
在一个实施例中，当同步信号为第一状态时，开关驱动电路导通第一开关，对第三开关进行斩波，同时关断第二开关和第四开关；当同步信号为第二状态时，开关驱动电路导通第二开关，对第四开关进行斩波，同时关断第一开关和第三开关。
在一个实施例中，当同步信号为第一状态时，开关驱动电路导通第一开关，关断第四开关，对第二开关和第三开关进行反相同步斩波；当同步信号为第二状态时，开关驱动电路导通第二开关，关断第三开关，对第一开关和第四开关进行反相同步斩波。
在一个实施例中，开关驱动电路进一步根据同步信号的状态，在同步信号的任一状态下选择第一开关、第二开关、第三开关和第四开关中的至少一个开关进行导通以及至少一个开关进行关断，用于在第一输出端和第二输出端之间形成正弦包络斩波信号。
在一个实施例中，开关驱动电路通过输出脉宽调制信号对开关进行斩波。
在一个实施例中，无级调速电路进一步包括整流电路，整流电路用于将市电正弦交流电信号转换成单向脉动馒头波信号。
在一个实施例中，同步信号基于正弦交流电信号产生，其中当正弦交流电信号大于零时，同步信号为第一状态；当正弦交流电信号小于零时，同步信号为不同于第一状态的第二状态。
在一个实施例中，无级调速电路进一步包括电容，耦接在输入端和地电位端之间。
在一个实施例中，当不考虑开关电路的容值时，输入端和地电位端之间的有效容值低于 4.7微法。
在一个实施例中，第一开关、第二开关、第三开关和第四开关为高压功率开关管，第一开关和第二开关的漏极或集电极耦接输入端，第一开关的源极或发射极耦接第一输出端，第二开关的源极或发射极耦接第二输出端；第三开关和第四开关的源极或发射极耦接地电位端，第三开关的漏极或集电极耦接第二输出端，第四开关的漏极或集电极耦接第一输出端。
在一个实施例中，开关驱动电路包括：逻辑电路，具有输入端、第一输出端、第二输出端、第三输出端和第四输出端，其中逻辑电路的输入端耦接同步信号发生电路的输出端；第一半桥驱动电路，具有两个输入端和两个输出端，其中第一半桥驱动电路的两个输入端分别耦接逻辑电路的第一输出端和第二输出端，第一半桥驱动电路的两个输出端分别耦接第一开关的控制端和第四开关的控制端；以及第二半桥驱动电路，具有两个输入端和两个输出端，其中第二半桥驱动电路的两个输入端分别耦接逻辑电路的第三输出端和第四输出端，第二半桥驱动电路的两个输出端分别耦接第二开关的控制端和第三开关的控制端。
在一个实施例中，电机包括单相异步电机。
根据本申请的另一个方面，提供了一种用于驱动电机的无级调速方法，包括：将正弦交流电信号全波整流成单向脉动馒头波信号；将单向脉动馒头波信号输入H桥开关电路的输入端；提供同步信号，其中在正弦交流电信号的前半周期，同步信号为第一状态，在正弦交流电信号的后半周期，同步信号为第二状态；根据同步信号的状态选择H桥开关电路中至少一个开关进行斩波，用于在H桥开关电路的输出端提供正弦包络斩波信号，其中正弦包络斩波信号的包络线与正弦交流电信号的波形同步；以及采用正弦包络斩波信号驱动电机，并通过调节对开关进行斩波的斩波信号的占空比调节电机转速。
在一个实施例中，根据同步信号的状态选择H桥开关电路中至少一个开关进行斩波的方法包括：提供与同步信号同步的第一驱动信号，用于驱动H桥开关电路中的第一开关；提供与同步信号反相的第二驱动信号，用于驱动H桥开关电路中的第二开关；将第一驱动信号与脉宽调制信号进行与运算形成第一斩波信号，用于驱动H桥开关电路中的第三开关；以及将第二驱动信号与脉宽调制信号进行与运算形成第二斩波信号，用于驱动H桥开关电路中的第四开关。
在一个实施例中，根据同步信号的状态选择H桥开关电路中至少一个开关进行斩波的方法包括：将同步信号与脉宽调制信号进行或运算形成第一驱动信号，用于驱动第一开关；将同步信号进行反相再与脉宽调制信号进行或运算形成第二驱动信号，用于驱动第二开关；将第二驱动信号进行反相，用于驱动第三开关；以及将第一驱动信号进行反相，用于驱动第四 开关。
根据本申请的又一个方面，提供了一种用于驱动电机的调速电路，包括：开关电路，具有输入端、地电位端、第一输出端和第二输出端，其中输入端用于接收正弦交流电信号经全波整流后的单向脉动馒头波信号，第一输出端和第二输出端之间用于耦接电机，开关电路包括第一开关、第二开关、第三开关和第四开关，其中第一开关耦接在输入端和第一输出端之间，第二开关耦接在输入端和第二输出端之间，第三开关耦接在第二输出端和地电位端之间，第四开关耦接在第一输出端和地电位端之间；同步信号发生电路，其输出端用于提供与正弦交流电信号关联的同步信号；以及开关驱动电路，用于根据同步信号在正弦交流电信号的前半周期，导通第一开关，对第三开关进行斩波，同时关断第二开关和第四开关；在正弦交流电信号的后半周期，导通第二开关，对第四开关进行斩波，同时关断第一开关和第三开关。
在一个实施例中，开关驱动电路包括：逻辑电路，具有输入端和至少两个输出端，其中逻辑电路的输入端耦接同步信号发生电路的输出端，逻辑电路的输出端提供至少两个逻辑信号；以及驱动级电路，具有至少两个输入端和至少两个输出端，其中驱动级电路的至少两个输入端用于接收逻辑电路的至少两个逻辑信号，驱动级电路的至少两个输出端用于控制第一开关、第二开关、第三开关和第四开关。
在一个实施例中，同步信号在正弦交流电信号前半周期为第一状态，在正弦交流电信号后半周期为不同于第一状态的第二状态；第一开关控制端的信号与同步信号波形同步；第二开关控制端的信号为同步信号的反相信号；第四开关控制端的信号为第二开关控制端的信号与脉宽调制信号的与信号；第三开关控制端信号为第一开关控制端信号与脉宽调制信号的与信号。
根据本申请的再一个方面，提供了一种用于驱动电机的调速电路，包括：开关电路，具有输入端、地电位端、第一输出端和第二输出端，其中输入端用于接收正弦交流电信号经全波整流后的单向脉动馒头波信号，第一输出端和第二输出端之间用于耦接电机，开关电路包括第一开关、第二开关、第三开关和第四开关，其中第一开关耦接在输入端和第一输出端之间，第二开关耦接在输入端和第二输出端之间，第三开关耦接在第二输出端和地电位端之间，第四开关耦接在第一输出端和地电位端之间；同步信号发生电路，其输出端用于提供与正弦交流电信号关联的同步信号；以及开关驱动电路，用于根据同步信号在正弦交流电信号的前半周期，导通第一开关，关断第四开关，对第二开关和第三开关进行反相同步斩波；在正弦交流电信号的后半周期，导通第二开关，关断第三开关，对第一开关和第四开关进行反相同步斩波。
根据本申请的又一个方面，提供了一种用于驱动电机的调速电路，包括：H桥开关电路，具有输入端、地电位端、第一输出端和第二输出端，其中输入端用于接收单向脉动馒头波信号，单向脉动馒头波信号为市电正弦交流电信号的全波整流信号，第一输出端和第二输出端之间用于耦接电机；以及开关驱动电路，在市电正弦交流电信号的前半周期，对H桥开关电路中的至少一个开关进行斩波，在市电正弦交流电信号的后半周期，对H桥开关电路中的另外至少一个开关进行斩波，用于在第一输出端和第二输出端之间产生正弦包络斩波信号，其中调速电路的半载功率因数大于0.9。
本申请提供的电机无级调速电路及调速方法，电路体积较小，有效降低了系统复杂度和成本，且具有较高的功率因数，并可大大提高低速下电机的效率，其具体优点将结合下述具体实施例予以展现。
附图说明
图1示出了根据本申请一实施例的用于驱动电机的无级调速电路示意图；
图2示出了根据本申请一实施例的对应图1中电路的信号波形示意图；
图3示出了根据本申请一实施例的单相电机无级调速电路系统示意图；
图4示出了根据本申请一实施例的对应图3电路中各信号的用于进行单相电机无级调速控制的信号波形示意图；
图5示出了根据本申请另一实施例的对应图3电路中各信号的用于进行单相电机无级调速控制的信号波形示意图；
图6示出了根据本申请一实施例的用于驱动电机的无级调速方法框图示意图；
图7示出了根据本申请一实施例的同步信号发生电路示意图；
图8示出了根据本申请一实施例的正弦包络斩波信号、其包络线和正弦交流电信号Vsin的示意图；
图9示出了根据本申请一实施例的样机测试实验波形示意图；
图10示出了根据本申请一实施例方案的电机调速电路样机的输入功率与现有技术方案的输入功率在不同电机转速下的对比测试示意图；
图11示出了根据本申请一实施例方案的电机调速电路样机的输入功率因数与现有技术方案的输入功率因数在不同电机转速下的对比测试示意图。
不同示意图中相同的标号代表相同或相似的部件或组成。
具体实施方式
为了进一步理解本申请，下面结合实施例对本申请优选实施方案进行描述，但是应当理解，这些描述只是为进一步说明本申请的特征和优点，而不是对本申请权利要求的限制。
该部分的描述只针对几个典型的实施例，本申请并不仅局限于实施例描述的范围。不同实施例的组合、不同实施例中的一些技术特征进行相互替换，相同或相近的现有技术手段与实施例中的一些技术特征进行相互替换也在本申请描述和保护的范围内。
说明书中的“耦接”包含直接连接，也包含间接连接，如通过电传导媒介如导体的连接，其中该电传导媒介可含有寄生电感或寄生电容。还可包括本领域技术人员公知的在可实现相同或相似功能目的的基础上通过其他有源器件或无源器件的连接，如通过开关、跟随电路等电路或部件的连接。
图1示出了根据本申请一实施例的用于驱动电机的无级调速电路。优选地，无级调速电路用于驱动单相异步电机M。无级调速电路包括整流电路10，开关电路11，同步信号发生电路12和开关驱动电路13。其中整流电路10用于将正弦交流电信号Vsin进行全波整流生成单向脉动馒头波信号Vin。优选地，正弦交流电信号Vsin为市电交流电，具有工频频率，如50赫兹。在一些实施例中，无级调速电路也可不包括整流电路10，即将整流电路置于无级调速电路之外。电机M也可以为其它类型的电机。
其中开关电路11具有输入端IN、地电位端GND、第一输出端Vo1和第二输出端Vo2，其中输入端IN用于接收单向脉动馒头波信号Vin，第一输出端Vo1和第二输出端Vo2之间用于耦接电机M，地电位端GND用于耦接参考地。其中单向脉动馒头波信号Vin为正弦交流电信号Vsin的全波整流信号。
开关电路11包括第一开关Q1、第二开关Q2、第三开关Q3和第四开关Q4。第一开关Q1耦接在输入端Vin和第一输出端Vo1之间，第二开关Q2耦接在输入端Vin和第二输出端Vo2之间，第三开关Q3耦接在第二输出端Vo2和地电位端GND之间，第四开关Q4耦接在第一输出端Vo1和地电位端GND之间。该开关电路11也可称为H桥开关电路。
同步信号发生电路12用于产生与正弦交流电信号Vsin或单向脉动馒头波信号Vin关联的同步信号SYN。在一个实施例中，如图2所示，同步信号SYN呈现具有第一电平(如高电平)的第一状态S1和具有不同于第一电平的第二电平(如低电平)的第二状态S2，第一状态S1和第二状态S2交替，其中第一状态S1的周期和第二状态S2的周期与单向脉动馒头波信号Vin的周期一一对应。其中在正弦交流电信号Vsin的前半周期，同步信号SYN为第一状态S1，如高电平，在正弦交流电信号Vsin的后半周期，同步信号SYN为不同于第一状态的第二状态S2，如低电平。在一个实施例中，同步信号发生电路12基于整流前的正弦交流电信号Vsin 产生同步信号SYN，如图1所示。优选地，同步信号SYN根据市电交流电产生，其频率与市电交流电频率对应，如在市电交流电的每个前半周期为高电平，在市电交流电的每个后半周期为低电平。在另一个实施例中，同步信号发生电路12基于单向脉动馒头波信号Vin产生同步信号SYN，如图1的虚线所示，如对应第奇数个单向脉动馒头波信号周期为高电平，对应第偶数个单向脉动馒头波信号周期为低电平。
开关驱动电路13用于根据同步信号SYN的状态输出驱动信号PWMA、PWMB、PWM2和PWM1，用于分别控制第一开关Q1、第二开关Q2、第三开关Q3和第四开关Q4的开关状态，通过控制驱动信号PWMA、PWM1、PWM2和PWMB的状态来分时段选择第一开关Q1、第二开关Q2、第三开关Q3和第四开关Q4中的至少一个开关以第二频率进行斩波，用于在第一输出端Vo1和第二输出端Vo2之间形成正弦包络斩波信号Vo，Vo＝Vo1-Vo2，其中正弦包络斩波信号Vo的包络线与正弦交流电信号Vsin的波形同步，即具有相同的频率(相同周期T)和近似的外形，参见图8。优选地，正弦包络斩波信号Vo的包络线与正弦交流电信号Vsin同步，为工频正弦波形。优选地，开关驱动电路13通过输出脉宽调制(PWM)信号对开关进行斩波，使得正弦包络斩波信号的斩波频率为第二频率，其中第二频率即为PWM信号的频率。通过调节PWM信号的占空比，可实现对电机M的无级调速。其中输出电压Vo的有效值Voe为输入电压Vin的有效值Vine与占空比Duty的乘积：Voe＝Vine*Duty。输出电压Vo的有效值用于调节电机的转速。
在图4所示的实施例中，在正弦交流电信号Vsin的前半周期，同步信号SYN为第一状态(S1)，开关驱动电路13对第三开关Q3以第二频率进行斩波；在正弦交流电信号Vsin的后半周期，同步信号SYN为第二状态(S2)，开关驱动电路13对第四开关Q4以第二频率进行斩波，用于在第一输出端Vo1和第二输出端Vo2之间形成正弦包络斩波信号。这样，在图4所示的实施例中，无论处于什么时段(同步信号SYN为第一状态或第二状态)，均有一个开关被以第二频率进行斩波，用于输出如图2所示的全程斩波的正弦包络斩波信号Vo。在图5所示的实施例中，在同步信号SYN为第一状态的时段，对第二开关Q2和第三开关Q3以PWM频率(第二频率)进行斩波(斩波信号相互反相)，在同步信号SYN为第二状态的时段，对第一开关Q1和第四开关Q4以第二频率进行斩波(斩波信号相互反相)，用于在第一输出端Vo1和第二输出端Vo2之间形成正弦包络斩波信号。在图5所示的实施例中，无论处于什么时段(同步信号SYN为第一状态或第二状态)，均有两个开关被以第二频率进行斩波，用于输出如图2所示的全程斩波的正弦包络斩波信号Vo。具体控制方式可参看图4和图5所示的实施例，将在下面进行详细描述。
图2示出了根据本申请一实施例的对应图1中电路的信号波形图。图1中开关电路11的第一输出端Vo1和第二输出端Vo2之间形成的正弦包络斩波信号，即电压Vo1与Vo2的差值信号为如图2所示的斩波信号Vo，其中正弦包络斩波信号Vo的包络线与正弦交流电信号Vsin同步，优选地，为正弦波形状。优选的，正弦包络斩波信号Vo的斩波频率即第二频率大为正弦交流电信号Vsin频率的10倍以上。第二频率可以为非固定的频率。
在一个实施例中，单向脉动馒头波信号Vin为市电交流电经过全波整流的波形，正弦包络斩波信号Vo的周期T等于市电正弦交流电信号的周期。单向脉动馒头波信号Vin的频率为2倍工频。
通过正弦包络斩波信号Vo驱动单相电机，可实现通过调节斩波信号Vo的占空比来实现单相电机的无级调速。同时，由于输出的正弦包络斩波信号Vo的包络线形状和市电交流电波形一致性很高，使得交流输入端的系统输入电流波形与市电交流电波形也一致性很高，该无级调速电路可具有很高的功率因数(PF)。
图3示出了根据本申请一实施例的单相电机无级调速电路系统示意图。电机无级调速电路包括整流电路10、开关电路11、同步信号发生电路12和开关驱动电路。整流电路10用于将正弦交流电信号Vsin转换成单向脉动馒头波信号Vin。优选地，正弦交流电信号Vsin为市电正弦交流电信号。当然，由于市电正弦交流电信号可能受其它电磁干扰等因素影响，使得正弦交流电信号Vsin存在畸变，其波形可以不为严格的正弦波形状。
同步信号发生电路12基于正弦交流电信号Vsin产生同步信号SYN。在图示实施例中，同步信号发生电路12包括过零检测电路，每当正弦交流电信号Vsin过零时，同步信号SYN状态发生翻转。图7示出了根据本申请一实施例的同步信号发生电路示意图，具体将在下面描述。这样(参看图4)，当正弦交流电信号Vsin大于零时，同步信号SYN为第一状态(如高电平状态)；当正弦交流电信号Vsin小于零时，同步信号SYN为不同于第一状态的第二状态(低电平)。或者说同步信号SYN在正弦交流电信号Vsin的前半周期为第一状态S1，在正弦交流电信号Vsin后半周期为不同于第一状态的第二状态(S2)。
继续参看图3，开关驱动电路包括逻辑电路32、第一半桥驱动电路331和第二半桥驱动电路332。开关驱动电路根据同步信号SYN的状态通过输出脉宽调制(PWM)信号分时段地对开关Q1-Q4中至少一个开关进行斩波。其中逻辑电路32用于根据同步信号SYN输出四个控制开关Q1-Q4的驱动信号PWMA、PWM1、PWMB和PWM2。具体的，逻辑电路32具有输入端、第一输出端、第二输出端、第三输出端和第四输出端，其中逻辑电路32的输入端耦接同步信号发生电路12的输出端用于接收同步信号SYN。逻辑电路32的第一输出端、第二 输出端、第三输出端和第四输出端用于分别输出四个驱动信号PWMA、PWM1、PWMB和PWM2。在一个实施例中，参看图4，逻辑电路32的第一输出端输出的信号PMMA与同步信号SYN同步，使得第一开关Q控制端的信号与同步信号波形同步。逻辑电路32的第三输出端输出的信号PWMB为同步信号SYN的反相信号，使得第二开关Q2控制端的信号为同步信号的反相信号。逻辑电路32的第二输出端的信号PWM1为逻辑电路的第三输出端的信号PWMB与脉宽调制(PWM)信号的与信号，使得第四开关Q4控制端的信号为第二开关控制端的信号与脉宽调制信号的与信号。逻辑电路32的第四输出端的信号PWM2为逻辑电路的第一输出端的信号PWMA与脉宽调制(PWM)信号的与信号，使得第三开关Q3控制端信号为第一开关控制端信号与脉宽调制信号的与信号。在另一个实施例中，参看图5，逻辑电路32的第一输出端输出的信号PMMA为同步信号SYN与脉宽调制信号的或信号。逻辑电路32的第三输出端输出的信号PWMB为同步信号SYN的反相信号与脉宽调制信号的或信号。逻辑电路32的第二输出端的信号PWM1为第一输出端输出的信号PMMA的反相信号。逻辑电路32的第四输出端的信号PWM2为第三输出端输出的信号PWMB的反相信号。在一个实施例中，各驱动信号PWMA、PWM1、PWMB和PWM2设置死区时间，防止开关管错误地同时导通。
驱动级电路包括第一半桥驱动电路331和第二半桥驱动电路332。
其中第一半桥驱动电路331具有两个输入端和两个输出端，其中两个输入端分别耦接逻辑电路32的第一输出端和第二输出端用于接收驱动信号PWMA和PWM1，第一半桥驱动电路331的两个输出端分别耦接第一开关Q1的控制端和第四开关Q4的控制端用于控制开关Q1和Q4的导通或关断。在一个具体的实施例中，第一驱动信号PWMA信号控制第一开关Q1，第二驱动信号PWM1控制第四开关Q4。
第二半桥驱动电路332具有两个输入端和两个输出端，其中第二半桥驱动电路332的两个输入端分别耦接逻辑电路32的第三输出端和第四输出端用于接收驱动信号PWMB和PWM2，第二半桥驱动电路332的两个输出端分别耦接第二开关Q2的控制端和第三开关Q3的控制端用于控制开关Q2和Q3的导通或关断。在一个具体的实施例中，第三驱动信号PWMB信号控制第二开关Q2，第四驱动信号PWM2控制第三开关Q3。
在其它的实施例中，开关驱动电路可具有不同的结构。在一个实施例中，逻辑电路具有两个输出端，分别用于提供如图5所示的信号PWMA和PWMB，或者提供如图5所示的PWM1和PWM2，经驱动级电路放大提供两个驱动信号用于分别驱动四个开关管，其中开关管Q1和Q4具有相反的掺杂类型受PWMA或PWM1信号控制，Q2和Q3具有相反的半导体掺杂 类型并受PWMB或PWM2信号控制，相反掺杂类型的开关管在相同开关信号的作用下开关状态相反。当然，驱动级电路也可基于两个输入信号输出四个如图5波形所示的驱动信号控制四个开关管。在一个实施例中，逻辑电路可具有三个输出端，分别用于提供如图4所示的PWMA，PWM1和PWM2，经驱动级电路放大分别用于输出三个驱动信号驱动Q1和Q2，Q3以及Q4，其中Q1和Q2的掺杂类型相反。或者驱动级电路也可提供四个驱动信号用于驱动四个相同掺杂类型的开关。在一个实施例中，逻辑电路提供四个逻辑信号PWMA、PWMB、PWM1和PWM2，驱动级电路包括一个全桥驱动电路，用于接收四个逻辑信号，提供四个驱动信号分别驱动四个开关管Q1、Q2、Q3和Q4。
在图3所示的实施例中，第一开关Q1、第二开关Q2、第三开关Q3和第四开关Q4为金属氧化物半导体场效应管(MOSFET)，第一开关Q1和第二开关Q2的漏极耦接输入端IN，第一开关Q1的源极耦接第一输出端Vo1，第二开关Q2的源极耦接第二输出端Vo2；第三开关Q3和第四开关Q4的源极耦接地电位端GND，第三开关Q3的漏极耦接第二输出端Vo2，第四开关Q4的漏极耦接第一输出端Vo1。当然，开关Q1-Q4也可以为其他类型的高压功率开关管，如结型场效应管(JFET)或双极结型晶体管(BJT)。在一个实施例中，当开关Q1、Q2、Q3和Q4为BJT管时，第一开关Q1和第二开关Q2的集电极耦接输入端IN，第一开关Q1的发射极耦接第一输出端Vo1，第二开关Q2的发射极耦接第二输出端Vo2；第三开关Q3和第四开关Q4的发射极耦接地电位端GND，第三开关Q3的集电极耦接第二输出端Vo2，第四开关Q4的集电极耦接第一输出端Vo1。当开关Q1、Q2、Q3和Q4为BJT管时，在各开关的发射极和集电极之间各并联一二极管，用于提供续流通路。在一实施例中，开关Q1和Q2为第一类型的开关管，开关Q3和Q4可为另一类型的开关管。
在图3所示的实施例中，开关管的源-漏端之间存在着寄生二极管，当开关Q1或Q2关断时，电流将流过开关Q1或Q2的寄生二极管。因此，在图示的实施例中，单相电机无级调速电路进一步包括电容Cf，耦接在开关电路11的输入端IN和地电位端GND之间，用于在开关Q1或Q2关断时为寄生二极管提供续流通路，防止输出端Vo1或Vo2电压的突变。但是，该电容Cf仅用于提供续流通路，因此电容Cf无需具有大容值，仅需采用小电容即可。在一个实施例中，电容Cf为薄膜电容。该方案无需采用其它技术中的用于提供平稳直流电源的大容值的电容如电解电容，或需要额外采样交流-直流变换电路等，因此大大降低了系统的成本和体积。在一个实施例中，电容Cf的容值选取为0.47微法。在一个实施例中，电容Cf的容值选取为0.33微法。在一个实施例中，当不考虑开关电路11的容值时，如不考虑开关电路11的寄生电容或等效工作电容时，如将开关电路11移除时，输入端IN和地电位端GND之 间的有效容值低于1微法。当不考虑开关电路11的容值时，输入端IN和地电位端GND之间的有效容值也可低于4.7微法，亦远低于对比技术中因采用电解电容而具有的数十至数百微法容值。
图4示出了根据本申请一实施例的对应图3电路中各信号的用于进行单相电机无级调速控制的信号波形图。从上至下的信号分别为正弦交流电信号Vsin、单向脉动馒头波信号Vin、同步信号SYN、用于驱动第一开关Q1的开关驱动信号PWMA、用于驱动第三开关Q3的开关驱动信号PWM2、用于驱动第二开关Q2的开关驱动信号PWMB和用于驱动开关第四Q4的开关驱动信号PWM1。单向脉动馒头波信号Vin为正弦交流电信号Vsin的全波整流信号。同步信号SYN与馒头波形的单向脉动馒头波信号Vin或整流前的正弦交流电信号Vsin关联。其中在正弦交流电信号Vsin的前半周期，同步信号SYN为高电平，在正弦交流电信号Vsin的后半周期，同步信号SYN为低电平。当然，同步信号SYN的高电平和低电平也可以调换。
在正弦交流电信号Vsin的前半周期，同步信号SYN为高电平(第一状态S1)，驱动信号PWMA为高电平，驱动信号PWM2为高频斩波信号，驱动信号PWMB和PWM1为低电平。此时开关驱动电路导通第一开关Q1，对第三开关Q3进行斩波，同时关断第二开关Q2和第四开关Q4。在正弦交流电信号Vsin的后半周期，同步信号SYN为低电平(第二状态S2)，驱动信号PWMB为高电平，驱动信号PWM1为高频斩波信号，驱动信号PWMA和PWM2为低电平。此时开关驱动电路导通第二开关Q2，对第四开关Q4进行斩波，同时关断第一开关Q1和第三开关Q3。在一个实施例中，上述高频斩波信号的斩波频率(第二频率)为正弦交流电信号Vsin频率的10倍以上。从波形可以看到，驱动H桥开关电路中第一开关Q1的第一驱动信号PWMA与同步信号SYN同步，驱动H桥开关电路中第三开关Q3的斩波信号PWM2的包络线与第一驱动信号PWMA形状相同，驱动H桥开关电路中第二开关的第二驱动信号PWMB与同步信号SYN反相，驱动H桥开关电路中第四开关Q4的斩波信号PWM1的包络线与第二驱动信号PWMB形状相同。在一个实施例中，优选的，斩波信号为各脉冲完整导通的脉宽调制信号。
图5示出了根据本申请另一实施例的对应图3电路中各信号的用于进行单相电机无级调速控制的信号波形图。从上至下的信号分别为正弦交流电信号Vsin、单向脉动馒头波信号Vin、同步信号SYN、用于驱动开关Q1的开关驱动信号PWMA、用于驱动开关Q3的开关驱动信号PWM2、用于驱动开关Q2的开关驱动信号PWMB和用于驱动开关Q4的开关驱动信号PWM1。单向脉动馒头波信号Vin为正弦交流电信号Vsin的全波整流信号。
正弦交流电信号Vsin的前半周期，同步信号SYN为第一状态(高电平)，用于驱动第一 开关Q1的驱动信号PWMA为高电平信号，用于驱动第二开关Q2的驱动信号PWMB为PWM斩波信号，用于驱动第三开关Q3的驱动信号PWM2为与驱动信号PWMB反相的同频率PWM斩波信号，用于驱动第四开关Q4的驱动信号PWM1为低电平信号。这时，开关驱动电路导通第一开关Q1，关断第四开关Q2，对第二开关Q2和第三开关Q3进行相互反相地反相同步斩波。即此时以高于单向脉动馒头波信号Vin频率的斩波频率(或称第二频率)对第二开关Q2和第三开关Q3进行导通和关断，当第二开关Q2导通时，第三开关Q3关断；当第二开关Q2关断时，第三开关Q3导通。
在正弦交流电信号Vsin的后半周期，同步信号SYN为第二状态(低电平)，用于驱动第一开关Q1的驱动信号PWMA为第二频率的PWM斩波信号，用于驱动第二开关Q2的驱动信号PWMB为高电平信号，用于驱动第三开关Q3的驱动信号PWM2为低电平信号，用于驱动第四开关Q4的驱动信号PWM1为与驱动信号PWMA反相的同频率斩波信号。这样，开关驱动电路导通第二开关Q2，关断第三开关Q3，对第一开关Q1和第四开关Q4进行相互反相地反相同步斩波，即以第二频率对第一开关Q1和第四开关Q4进行导通和关断，当第一开关Q1导通时，第四开关Q4关断；当第一开关Q1关断时，第四开关Q4导通。在一个实施例中，第二频率为正弦交流电信号Vsin频率的10倍以上。
结合图3至图5所描述的多个实施例，根据同步信号SYN的状态选择第一开关Q1、第二开关Q2、第三开关Q3和第四开关Q4中的至少一个开关以第二频率进行斩波，用于在第一输出端Vo1和第二输出端Vo2之间形成正弦包络斩波信号Vo。在图4所示的实施例中，在同步信号SYN为第一状态(S1)的时段，对第三开关Q3以第二频率进行斩波，在同步信号SYN为第二状态(S2)的时段，对第四开关Q4以第二频率进行斩波，用于在第一输出端Vo1和第二输出端Vo2之间形成正弦包络斩波信号。在图5所示的实施例中，在同步信号SYN为第一状态的时段，对第二开关Q2和第三开关Q3以第二频率进行斩波，其中第二开关Q2和第三开关Q3的斩波信号相互反相，在同步信号SYN为第二状态时，对第一开关Q1和第四开关Q4以第二频率进行斩波，其中第一开关Q1和第四开关Q4的斩波信号相互反相，用于在第一输出端Vo1和第二输出端Vo2之间形成正弦包络斩波信号。
进一步地，在图4和图5所示的控制实施例中，根据同步信号SYN的状态通过在同步信号SYN的任一状态下对第一开关Q1、第二开关Q2、第三开关Q3和第四开关Q4中的至少一个开关以第二频率进行斩波，同时对至少一个开关进行导通和至少一个开关进行关断的控制，来用于在第一输出端Vo1和第二输出端Vo2之间形成正弦包络斩波信号Vo。例如在图4所示的实施例中，在同步信号SYN为第一状态(S1)的时段，对第三开关Q3以第二频率进行斩 波、对第一开关Q1进行导通、对第二开关Q2和第四开关Q4进行关断，在同步信号SYN为第二状态(S2)的时段，对第四开关Q4以第二频率进行斩波、对第二开关Q2进行导通、对第一开关Q1和第三开关Q3进行关断，通过这样的控制，用于在第一输出端Vo1和第二输出端Vo2之间形成正弦包络斩波信号。在图5所示的实施例中，在同步信号SYN为第一状态时，对第二开关Q2和第三开关Q3以第二频率进行斩波(斩波信号相互反相)、对第一开关Q1进行导通、对第四开关Q4进行关断；在同步信号SYN为第二状态时，对第一开关Q1和第四开关Q4以第二频率进行斩波(斩波信号相互反相)、对第二开关Q2进行导通、对第三开关Q3进行关断，通过这样分时段选择性的控制，用于在第一输出端Vo1和第二输出端Vo2之间形成正弦包络斩波信号。
结合图3至图5所描述的多个实施例，无级调速电路在开关电路输出端Vo1和Vo2之间产生如图2中信号Vo所示意的正弦包络斩波信号。其中Vo＝Vo1-Vo2，正弦包络斩波信号Vo的包络线波形与正弦交流电信号Vsin的波形同步，具有相同的频率(相同周期T)和近似的波形，参见图8。
图6示出了根据本申请一实施例的用于驱动单相电机的无级调速方法框图示意图。该方法包括步骤601-605。在步骤601，将正弦交流电信号Vsin全波整流成单向脉动馒头波信号Vin。优选地，正弦交流电信号为市电交流电。
在步骤602，将单向脉动馒头波信号Vin输入H桥开关电路的输入端。
在步骤603，基于正弦交流电信号Vsin提供同步信号SYN，其中在正弦交流电信号Vsin的前半周期，同步信号SYN为第一状态，如高电平，在正弦交流电信号Vsin的后半周期，同步信号SYN为第二状态，如低电平。在一个实施例中，同步信号SYN通过检测正弦交流电信号Vsin的过零信号产生，当正弦交流电信号Vsin过零值时，同步信号SYN状态进行切换。在另一个实施例中，同步信号SYN根据单向脉动馒头波信号Vin产生，在每个单向脉动馒头波信号Vin周期结束时，同步信号SYN状态发生变化，使得同步信号SYN在第奇数个单向脉动馒头波信号周期为第一状态，在第偶数个单向脉动馒头波信号周期为第二状态。
在步骤604，根据同步信号SYN的状态选择性地对H桥开关电路中至少一个开关进行斩波，用于在H桥开关电路的输出端提供正弦包络斩波信号Vo，其中正弦包络斩波信号的包络线与正弦交流电信号的波形同步。在一个实施例中，根据同步信号SYN的状态选择性地对H桥开关电路中至少一个开关进行斩波的方法包括：提供与同步信号SYN同步的第一驱动信号PWMA，用于驱动H桥开关电路中的第一开关Q1；提供与同步信号SYN反相的第二驱动信号PWMB，用于驱动H桥开关电路中的第二开关Q2；提供与第一驱动信号PWMA具有相同 形状包络线的第一斩波信号PWM2，即将第一驱动信号PWMA与脉宽调制(PWM)信号进行与运算形成第一斩波信号PWM2，用于驱动H桥开关电路中的第三开关Q3；以及提供与第二驱动信号PWMB具有相同形状包络线的第二斩波信号PWM1，即将第二驱动信号PWMB与脉宽调制(PWM)信号进行与运算形成第二斩波信号PWM1，用于驱动H桥开关电路中的第四开关Q4。在一个实施例中，斩波信号PWM1或PWM2的斩波频率为正弦交流电信号频率的10倍以上。在另一个实施例中，H桥开关电路的各开关控制方式也可如图5所示，根据同步信号SYN的状态选择性地对H桥开关电路中至少一个开关进行斩波的方法包括：将同步信号SYN与脉宽调制PWM斩波信号进行或运算形成第一驱动信号PWMA，用于驱动第一开关Q1；将同步信号SYN进行反相再与PWM斩波信号进行或运算形成第二驱动信号PWMB，用于驱动第二开关Q2；将第二驱动信号PWMB进行反相形成信号PWM2，用于驱动第三开关Q3；以及将第一驱动信号PWMA进行反相形成信号PWM1，用于驱动第四开关Q4。
在步骤605，采用正弦包络斩波信号Vo驱动单相电机，并且根据对开关进行斩波的斩波信号的占空比调节电机转速。
图7示出了根据本实用新型一实施例的同步信号发生电路示意图。同步信号发生电路包括分别与正弦交流电信号Vsin的两个输入端耦接的两个并联的方向相反的整流管D1和D2，串联的两个阻值相同的电阻以及比较电路CMP。其中整流管D1和D2分别耦接在交流输入电源Vsin的两个输入端之间用于对输入正弦交流电信号Vsin进行整流。电阻的连接节点耦接参考地。比较电路CMP的两个输入端分别和正弦交流电信号Vsin的两个输入端耦接，并由一相对于参考地的稳定电源提供偏置。比较电路的输出端提供如图2所示的同步信号SYN，当正弦交流电信号Vsin大于零值时，同步信号SYN为高值信号，当正弦交流电信号Vsin小于零值时，同步信号SYN为低值信号(零值)。
图8示出了根据本申请一实施例的正弦包络斩波信号Vo、Vo包络线和正弦交流电信号Vsin的示意图。可见，正弦包络斩波信号Vo的包络线与正弦交流电信号Vsin形状同步，两者具有相同的周期和相似的波形。在正弦交流电信号Vsin的前半周期，正弦交流电信号Vsin大于零，正弦包络斩波信号Vo的包络线亦为大于零值的半正弦波；在正弦交流电信号Vsin的后半周期，正弦交流电信号Vsin小于零，正弦包络斩波信号Vo的包络线亦为小于零值的半正弦波。
图9示出了根据本申请一实施例的样机测试实验波形示意图。其中第一个信号为单向脉动馒头波信号Vin。其为市电正弦交流电信号经全波整流后的整流信号。第二个信号为电机端电压信号Vo(Vo＝Vo1-Vo2)，其包络线为与整流前的正弦交流电信号具有相同频率的同步的 正弦波信号。第三个信号为输入端即整流电路前端的输入电流信号，其包络线形状也是与输入端正弦交流电信号同频率的正弦波信号。因此，交流信号输入端的输入电压和输入电流一致性很好，该系统的功率因数较高。
本申请的实施中提供的用于驱动单相电机的正弦包络斩波信号，其包络线可与市电交流电的信号波形基本完全对应，可获得很高的功率因数。
在一个实施方式中，通过在市电正弦交流电信号的前半周期，对H桥开关电路中的至少一个开关进行斩波，如对图4的第三开关Q3，或图5中的第二开关Q2和第三开关Q3进行斩波，在市电正弦交流电信号的后半周期，对H桥开关电路中的另外至少一个开关进行斩波，如对图4中的第四开关Q4，或图5中的第一开关Q1和第四开关Q4进行斩波，用于在H桥的两个输出端之间产生正弦包络斩波信号的差值信号，且其半载功率因数大于0.9。半载为输出电流占满幅输出电流的50％。其中H桥电路结构如图1或图3所示的开关电路。
本申请实施例中的电机无级调速电路无需在前端前置功率因数校正电路即可获得较大的功率因数。另外无需在前级采用交流-直流变换电路或大电解电容，使得系统体积较小且易于集成，且电路效率较高。
图10示出了根据本申请一实施例方案的电机调速电路样机的输入功率与一市场上现有技术方案(电机多档抽头方案)的输入功率在不同电机转速下的对比测试示意图。其中横坐标为风扇的转速(rpm，每分钟转数)，纵坐标为市电输入端的输入功率(W)。其中曲线1001为本申请实施例方案的输入功率，曲线1002为现有技术方案的输入功率。可以看到，在相同的风扇转速下，本申请技术方案的输入功率显著减少，具有更高的效率，特别当转速较低时，效率提高更为明显。在一个测试案例中，当转速较低时，本方案的调速电路的输入效率可以提高25％以上。
图11示出了根据本申请一实施例方案的电机调速电路样机的输入功率因数与一个现有技术方案(电机多档抽头及电容调节方案)的输入功率因数在不同电机转速下的对比测试示意图。其中横坐标为风扇的转速(rpm，每分钟转数)，纵坐标为正弦交流电信号输入端的输入功率因数。其中曲线1101为本申请实施例方案的输入功率因数，曲线1102为现有技术方案的输入功率因数。可以看到，在相同转速下，本申请技术方案的输入功率因数明显高于现有技术的输入功率因数。
这里本申请的描述和应用是说明性的，并非想将本申请的范围限制在上述实施例中。这里所披露的实施例的变形和改变是可能的，对于那些本领域的普通技术人员来说实施例的替换和等效的各种部件是公知的。本领域技术人员应该清楚的是，在不脱离本申请的精神或本 质特征的情况下，本申请可以以其它形式、结构、布置、比例，以及用其它组件、材料和部件来实现。在不脱离本申请范围和精神的情况下，可以对这里所披露的实施例进行其它变形和改变。

Claims (20)

  1. 一种用于驱动电机的无级调速电路，包括：
    开关电路，具有输入端、地电位端、第一输出端和第二输出端，其中输入端用于接收单向脉动馒头波信号，其中单向脉动馒头波信号为正弦交流电信号的全波整流信号，开关电路的第一输出端和第二输出端之间用于耦接电机，开关电路包括第一开关、第二开关、第三开关和第四开关，其中第一开关耦接在输入端和第一输出端之间，第二开关耦接在输入端和第二输出端之间，第三开关耦接在第二输出端和地电位端之间，第四开关耦接在第一输出端和地电位端之间；
    同步信号发生电路，用于产生同步信号，其中在正弦交流电信号的前半周期，同步信号为第一状态，在正弦交流电信号的后半周期，同步信号为不同于第一状态的第二状态；
    开关驱动电路，用于根据同步信号的状态选择第一开关、第二开关、第三开关和第四开关中的至少一个开关以第二频率进行斩波，用于在第一输出端和第二输出端之间形成正弦包络斩波信号，其中正弦包络斩波信号的包络线与正弦交流电信号的波形同步，第二频率为正弦交流电信号的频率的10倍以上。
  2. 如权利要求1所述的无级调速电路，其中当同步信号为第一状态时，开关驱动电路导通第一开关，对第三开关进行斩波，同时关断第二开关和第四开关；当同步信号为第二状态时，开关驱动电路导通第二开关，对第四开关进行斩波，同时关断第一开关和第三开关。
  3. 如权利要求1所述的无级调速电路，其中当同步信号为第一状态时，开关驱动电路导通第一开关，关断第四开关，对第二开关和第三开关进行反相同步斩波；当同步信号为第二状态时，开关驱动电路导通第二开关，关断第三开关，对第一开关和第四开关进行反相同步斩波。
  4. 如权利要求1所述的无级调速电路，其中开关驱动电路进一步根据同步信号的状态，在同步信号的任一状态下选择第一开关、第二开关、第三开关和第四开关中的至少一个开关进行导通以及至少一个开关进行关断，用于在第一输出端和第二输出端之间形成正弦包络斩波信号。
  5. 如权利要求1所述的无级调速电路，其中开关驱动电路通过输出脉宽调制信号对开关进行斩波。
  6. 如权利要求1所述的无级调速电路，进一步包括整流电路，整流电路用于将市电正弦交流电信号转换成单向脉动馒头波信号。
  7. 如权利要求1所述的无级调速电路，其中同步信号基于正弦交流电信号产生，其中当正弦交流电信号大于零时，同步信号为第一状态；当正弦交流电信号小于零时，同步信号为不同于第一状态的第二状态。
  8. 如权利要求1所述的无级调速电路，进一步包括电容，耦接在输入端和地电位端之间。
  9. 如权利要求8所述的无级调速电路，其中当不考虑开关电路的容值时，输入端和地电位端之间的有效容值低于4.7微法。
  10. 如权利要求1所述的无级调速电路，其中第一开关、第二开关、第三开关和第四开关为高压功率开关管，第一开关和第二开关的漏极或集电极耦接输入端，第一开关的源极或发射极耦接第一输出端，第二开关的源极或发射极耦接第二输出端；第三开关和第四开关的源极或发射极耦接地电位端，第三开关的漏极或集电极耦接第二输出端，第四开关的漏极或集电极耦接第一输出端。
  11. 如权利要求1所述的无级调速电路，其中开关驱动电路包括：
    逻辑电路，具有输入端、第一输出端、第二输出端、第三输出端和第四输出端，其中逻辑电路的输入端耦接同步信号发生电路的输出端；
    第一半桥驱动电路，具有两个输入端和两个输出端，其中第一半桥驱动电路的两个输入端分别耦接逻辑电路的第一输出端和第二输出端，第一半桥驱动电路的两个输出端分别耦接第一开关的控制端和第四开关的控制端；以及
    第二半桥驱动电路，具有两个输入端和两个输出端，其中第二半桥驱动电路的两个输入端分别耦接逻辑电路的第三输出端和第四输出端，第二半桥驱动电路的两个输出端分别耦接第二开关的控制端和第三开关的控制端。
  12. 如权利要求1所述的无级调速电路，其中电机包括单相异步电机。
  13. 一种用于驱动电机的无级调速方法，包括：
    将正弦交流电信号全波整流成单向脉动馒头波信号；
    将单向脉动馒头波信号输入H桥开关电路的输入端；
    提供同步信号，其中在正弦交流电信号的前半周期，同步信号为第一状态，在正弦交流电信号的后半周期，同步信号为第二状态；
    根据同步信号的状态选择H桥开关电路中至少一个开关进行斩波，用于在H桥开关电路的输出端提供正弦包络斩波信号，其中正弦包络斩波信号的包络线与正弦交流电信号的波形同步；以及
    采用正弦包络斩波信号驱动电机，并通过调节对开关进行斩波的斩波信号的占空比调节电机转速。
  14. 如权利要求13所述的方法，其中根据同步信号的状态选择H桥开关电路中至少一个开关进行斩波的方法包括：
    提供与同步信号同步的第一驱动信号，用于驱动H桥开关电路中的第一开关；
    提供与同步信号反相的第二驱动信号，用于驱动H桥开关电路中的第二开关；
    将第一驱动信号与脉宽调制信号进行与运算形成第一斩波信号，用于驱动H桥开关电路中的第三开关；以及
    将第二驱动信号与脉宽调制信号进行与运算形成第二斩波信号，用于驱动H桥开关电路中的第四开关。
  15. 如权利要求13所述的方法，其中根据同步信号的状态选择H桥开关电路中至少一个开关进行斩波的方法包括：
    将同步信号与脉宽调制信号进行或运算形成第一驱动信号，用于驱动第一开关；
    将同步信号进行反相再与脉宽调制信号进行或运算形成第二驱动信号，用于驱动第二开关；
    将第二驱动信号进行反相，用于驱动第三开关；以及
    将第一驱动信号进行反相，用于驱动第四开关。
  16. 一种用于驱动电机的调速电路，包括：
    开关电路，具有输入端、地电位端、第一输出端和第二输出端，其中输入端用于接收正弦交流电信号经全波整流后的单向脉动馒头波信号，第一输出端和第二输出端之间用于耦接电机，开关电路包括第一开关、第二开关、第三开关和第四开关，其中第一开关耦接在输入端和第一输出端之间，第二开关耦接在输入端和第二输出端之间，第三开关耦接在第二输出端和地电位端之间，第四开关耦接在第一输出端和地电位端之间；
    同步信号发生电路，其输出端用于提供与正弦交流电信号关联的同步信号；以及
    开关驱动电路，用于根据同步信号在正弦交流电信号的前半周期，导通第一开关，对第三开关进行斩波，同时关断第二开关和第四开关；在正弦交流电信号的后半周期，导通第二开关，对第四开关进行斩波，同时关断第一开关和第三开关。
  17. 如权利要求16所述的调速电路，其中开关驱动电路包括：
    逻辑电路，具有输入端和至少两个输出端，其中逻辑电路的输入端耦接同步信号发生电路的输出端，逻辑电路的输出端提供至少两个逻辑信号；以及
    驱动级电路，具有至少两个输入端和至少两个输出端，其中驱动级电路的至少两个输入端用于接收逻辑电路的至少两个逻辑信号，驱动级电路的至少两个输出端用于控制第一开关、第二开关、第三开关和第四开关。
  18. 如权利要求17所述的调速电路，其中：
    同步信号在正弦交流电信号前半周期为第一状态，在正弦交流电信号后半周期为不同于第 一状态的第二状态；
    第一开关控制端的信号与同步信号波形同步；
    第二开关控制端的信号为同步信号的反相信号；
    第四开关控制端的信号为第二开关控制端的信号与脉宽调制信号的与信号；
    第三开关控制端信号为第一开关控制端信号与脉宽调制信号的与信号。
  19. 一种用于驱动电机的调速电路，包括：
    开关电路，具有输入端、地电位端、第一输出端和第二输出端，其中输入端用于接收正弦交流电信号经全波整流后的单向脉动馒头波信号，第一输出端和第二输出端之间用于耦接电机，开关电路包括第一开关、第二开关、第三开关和第四开关，其中第一开关耦接在输入端和第一输出端之间，第二开关耦接在输入端和第二输出端之间，第三开关耦接在第二输出端和地电位端之间，第四开关耦接在第一输出端和地电位端之间；
    同步信号发生电路，其输出端用于提供与正弦交流电信号关联的同步信号；以及
    开关驱动电路，用于根据同步信号在正弦交流电信号的前半周期，导通第一开关，关断第四开关，对第二开关和第三开关进行反相同步斩波；在正弦交流电信号的后半周期，导通第二开关，关断第三开关，对第一开关和第四开关进行反相同步斩波。
  20. 一种用于驱动电机的调速电路，包括：
    H桥开关电路，具有输入端、地电位端、第一输出端和第二输出端，其中输入端用于接收单向脉动馒头波信号，单向脉动馒头波信号为市电正弦交流电信号的全波整流信号，第一输出端和第二输出端之间用于耦接电机；以及
    开关驱动电路，在市电正弦交流电信号的前半周期，对H桥开关电路中的至少一个开关进行斩波，在市电正弦交流电信号的后半周期，对H桥开关电路中的另外至少一个开关进行斩波，用于在第一输出端和第二输出端之间产生正弦包络斩波信号，其中调速电路的半载功率因数大于0.9。
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