WO2020233097A1 - 功率因数校正电路、控制方法、存储介质、电器及家电 - Google Patents

功率因数校正电路、控制方法、存储介质、电器及家电 Download PDF

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Publication number
WO2020233097A1
WO2020233097A1 PCT/CN2019/123355 CN2019123355W WO2020233097A1 WO 2020233097 A1 WO2020233097 A1 WO 2020233097A1 CN 2019123355 W CN2019123355 W CN 2019123355W WO 2020233097 A1 WO2020233097 A1 WO 2020233097A1
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WIPO (PCT)
Prior art keywords
branch
current
interval
main line
sampleable
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PCT/CN2019/123355
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English (en)
French (fr)
Inventor
蔡骊
刘毅
姜凯
宾宏
Original Assignee
广东美的白色家电技术创新中心有限公司
美的集团股份有限公司
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Application filed by 广东美的白色家电技术创新中心有限公司, 美的集团股份有限公司 filed Critical 广东美的白色家电技术创新中心有限公司
Priority to JP2021568367A priority Critical patent/JP7275319B2/ja
Publication of WO2020233097A1 publication Critical patent/WO2020233097A1/zh
Priority to US17/529,168 priority patent/US20220077769A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4233—Arrangements for improving power factor of AC input using a bridge converter comprising active switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0083—Converters characterised by their input or output configuration
    • H02M1/0085—Partially controlled bridges
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/23—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only arranged for operation in parallel

Definitions

  • This application relates to the field of circuit technology, and in particular to a power factor correction circuit, a control method, a storage medium, electrical appliances and household appliances.
  • PFC power factor correction
  • the current power factor correction circuit needs to sample the current of each inductance branch in order to control the current of each parallel branch and realize current sharing.
  • the common Hall circuit collects the current of each inductance branch, which has a high cost.
  • This application mainly provides a power factor correction circuit, a control method, a storage medium, electrical appliances, and home appliances to solve the problem of high cost of sampling the inductor branch current by the power factor correction circuit.
  • the power factor correction circuit includes: at least two power adjustment branches connected in parallel with each other, the power adjustment branch includes a first switching unit, a second switching unit, and a branch sampling resistor connected in series; at least two inductive branches, inductive branches The first end of the circuit is connected to the first end of the AC power supply, and the second end of the inductance branch is connected between the first switch unit and the second switch unit of the corresponding power adjustment branch; the rectifier branch includes a power adjustment branch The first rectification unit and the second rectification unit are connected in parallel and connected in series, and further include a main line sampling resistor.
  • the first end of the main line sampling resistor is connected between the first rectification unit and the second rectification unit.
  • the capacitor branch is connected in parallel with the power adjustment branch and the load; the control circuit samples the branch current flowing through the sampling resistor of each branch and the main line current flowing through the main line sampling resistor respectively, and according to the sampling The obtained branch currents and main line currents perform switching control on each power regulation branch.
  • the control method includes: obtaining the branch current flowing through the branch sampling resistors of each power adjustment branch and the main line current flowing through the main line sampling resistors of each rectification branch; and adjusting each power branch according to the branch current and the main line current Perform switch control.
  • the storage medium stores program data, and when the program data is executed by the processor, the steps of the above method are realized.
  • the electrical appliance includes a connected processor and a memory, and the memory stores a computer program.
  • the processor executes the computer program, the steps of the above method are realized.
  • the home appliance includes the power factor correction circuit as described above.
  • the beneficial effect of the present application is that, different from the prior art, the present application discloses a power factor correction circuit, a control method, a storage medium, electrical appliances and household appliances.
  • the main line sampling resistor By connecting branch sampling resistors in series in each parallel power adjustment branch, and setting the main line sampling resistor, and connecting the first end of the main line sampling resistor between the first rectification unit and the second rectification unit, the main line sampling resistor is The second end is connected to the second end of the AC power supply, and the branch current flowing through the sampling resistors of each branch and the main line current flowing through the main line sampling resistors are sampled to indirectly obtain the current flowing through the inductor branch, which reduces the
  • the current sampling device requires that a relatively cost-effective current sampling solution can be used, so that the overall cost of the power factor correction circuit is effectively reduced.
  • FIG. 1 is a schematic structural diagram of an embodiment of a power factor correction circuit provided by the present application
  • Fig. 2 is a schematic structural diagram of another embodiment of a power factor correction circuit
  • FIG. 3 is a schematic diagram of the first state of the current flow path of the power factor correction circuit of FIG. 1;
  • FIG. 4 is a schematic diagram of a second state of the current flow path of the power factor correction circuit of FIG. 1;
  • FIG. 5 is a schematic diagram of a third state of the current flow path of the power factor correction circuit of FIG. 1;
  • FIG. 6 is a schematic diagram of a fourth state of the current flow path of the power factor correction circuit of FIG. 1;
  • FIG. 7 is a schematic diagram of the sampling interval of the branch current in the power factor correction circuit of FIG. 1;
  • FIG. 8 is a schematic diagram of waveforms of switch control signals, currents of each branch and equivalent branch current of each power adjustment branch in the power factor correction circuit of FIG. 1;
  • FIG. 9 is a schematic structural diagram of another embodiment of a power factor correction circuit provided by the present application.
  • FIG. 10 is a schematic flowchart of an embodiment of a control method of a power factor correction circuit provided by the present application.
  • FIG. 11 is a schematic flowchart of another embodiment of the control method of the power factor correction circuit provided by the present application.
  • FIG. 12 is a schematic structural diagram of an embodiment of a storage medium provided by the present application.
  • FIG. 13 is a schematic structural diagram of an embodiment of an electrical appliance provided by this application.
  • Fig. 14 is a schematic structural diagram of an embodiment of a household appliance provided by the present application.
  • first”, “second”, and “third” in the embodiments of this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first”, “second”, and “third” may explicitly or implicitly include at least one of the features.
  • “plurality” means at least two, such as two, three, etc., unless specifically defined otherwise.
  • the terms “including” and “having” and any variations thereof are intended to cover non-exclusive inclusion.
  • a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes unlisted steps or units, or optionally also includes Other steps or units inherent to these processes, methods, products or equipment.
  • FIG. 1 is a schematic structural diagram of an embodiment of a power factor correction circuit provided by the present application.
  • FIG. 1 only illustrates the connection relationship between one power adjustment branch 10 and the control circuit 50, and the connection relationship between the remaining power adjustment branches 10 and the control circuit 50 is all It is omitted, and the rest of the power adjustment branch 10 is not connected to the control circuit 50.
  • Figure 1 also shows three power adjustment branches 10.
  • the first switching unit level and the second switching unit of each power adjustment branch 10 have different signs, but in the following description, the first Take the power adjustment branch 10 as an example.
  • the power factor correction circuit 100 includes at least two parallel power adjustment branches 10, at least two inductance branches 20, a rectification branch 30, a capacitor branch 40, and a control circuit 50.
  • the power adjustment branch 10 is used for receiving and driving.
  • the signal regulates the branch current i L1 of the power adjustment branch 10, thereby realizing the control of the branch current i L1 and the output voltage V o of the power factor correction circuit 100, that is, the at least two parallel power adjustment branches 10 will be
  • the input current of the power factor correction circuit 100 is corrected to a sine wave with the same frequency and phase as the AC power supply, so that the output voltage Vo is stable.
  • each power adjustment branch 10 includes a first switch unit Q 1 , a second switch unit Q 2 and a branch sampling resistor R 1 connected in series in sequence.
  • the first switching unit Q 1 and the second switching unit Q 2 may be MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor), such as GaN MOSFET, super junction MOSFET or SiC- MOSFET.
  • MOSFETs Metal-Oxide-Semiconductor Field-Effect Transistor
  • the mode for controlling each power adjustment branch 10 is the same, and the switching control signals of the at least two parallel power adjustment branches 10 are sequentially shifted by a certain phase angle within one cycle, and the certain phase angle is The ratio of 360 degrees to the number of power adjustment branches 10, the switch control signal is a PWM (Pulse Width Modulation, pulse width modulation) drive signal.
  • the power factor correction circuit 100 includes two power adjustment branches 10, and the corresponding switch control signals are phase-shifted by 180 degrees in one cycle; as shown in FIGS. 1 and 8, the power factor correction circuit 100 includes three power Regulating branch 10, the corresponding switch control signal is sequentially shifted by 120 degrees in one cycle.
  • the number of at least two inductance branches 20 and the number of at least two power adjustment branches 10 are the same and correspond one-to-one. Specifically, a first end of the inductor branch of the AC power supply 20 connected to a first end 60, second end of the inductor 20 is connected to the corresponding branch of the first switching unit adjusting power branch 10 and Q 1 of the second switching unit Between Q 2 .
  • each inductance branch 20 is connected between the corresponding power adjustment branch 10 and the AC power source 60.
  • the power adjustment branch 10 can also be connected in parallel with 2, 4, 5, etc., and the inductive branch 20 correspondingly has 2, 4, 5, etc.
  • the branch 20 includes an inductor L 1, L of the first end of the AC power source terminal and the first inductor 60 1 is connected to the inductor, L 1 the second end of the inductor is connected to the corresponding branch of the power conditioner 10 Between a switch unit Q 1 and a second switch unit Q 2 .
  • Rectifier branch 30 comprises a power regulation for another branch 10 connected in parallel and in series a first rectifying unit Q 7 Q 8 and the second rectifier unit, i.e., a first rectifier unit connected in series with each other and the second rectifying unit Q 7 Q 8 as a whole It is connected in parallel with the power regulation branch 10.
  • the rectifying branch 30 further includes a main line sampling resistor R S , the first end of the main line sampling resistor R S is connected between the first rectifying unit Q 7 and the second rectifying unit Q 8 , and the second end of the main line sampling resistor R S is connected to AC The second end of the power supply 60.
  • the first rectification unit Q 7 and the second rectification unit Q 8 are both synchronous rectification switch tubes or diodes. As shown in Fig. 2, when the first rectifying unit Q 7 and the second rectifying unit Q 8 adopt diodes, there is no need to provide a driving circuit for controlling the first rectifying unit Q 7 and the second rectifying unit Q 8 , which further reduces the power factor correction. The cost of the circuit 100.
  • first rectification unit Q 7 and the second rectification unit Q 8 adopt synchronous rectification switching tubes, they are the same GaN MOSFET, super junction MOSFET or SiC-MOSFET as the first switching unit Q 1 , reducing The conduction loss of the rectifying branch 30 is reduced, and the efficiency of the power factor correction circuit 100 is further improved.
  • the inductor branch 40 includes an output capacitor C bus .
  • a first end of the first switching element Q 1, a first end of a first rectifying unit Q 7 are connected to the positive electrode of the output capacitor C bus, a second terminal of the second switching element Q 2, and Q 8 of the second rectifying unit Both ends are connected to the negative pole of the output capacitor C bus .
  • the control circuit 50 respectively samples the branch current i L1 flowing through the branch sampling resistor R 1 and the main line current I in flowing through the main line sampling resistor R S , and performs sampling according to the branch current i L1 and the main line current I in obtained by sampling.
  • Output switch control signal, the switch control signal is used to switch the corresponding power adjustment branch 10, that is, by adjusting the duty cycle of the respective switching control signals of the first switching unit Q 1 and the second switching unit Q 2 to control the flow power regulation branch 10 of the branch current i L1 and the capacitance branch output voltage V o 40 is regulated.
  • one of the power adjustment branches 10 is taken as an example to illustrate the flow path of the branch current in the power factor correction circuit 100.
  • the control circuit 50 When the input voltage V i of the AC power supply 60 is greater than 0, the second rectifying unit Q 8 of the rectifying branch 30 is turned on, and the control circuit 50 outputs a switching control signal to switch the first switching unit Q 1 and the second switching unit Q 2 control. 3, when the second switching element Q 2 is turned on, the first switching element Q 1 is turned off, the AC power source 60 to the energy storage inductor L 1, and further increase in the inductor current, the inductor current flows through a sampling branch Resistor R 1 and main line sampling resistor R S. 4, when the second switching element Q 2 is turned off, the first switching element Q 1 turns on, the inductor L 1 stored energy to charge the output capacitor C bus, when main inductor current flows through sampling resistor R S.
  • the switch 50 When the input voltage of the AC power supply 60 V i ⁇ 0, the branch of the first rectifier rectifying unit 30 is a long-pass Q 7, the switch 50 outputs a first control signal to the switching circuit. 1 Q unit and the second switching unit for switching Q control. As shown in FIG. 5, when the first switching unit Q 1 is turned on and the second switching unit Q 2 is turned off, the AC power supply 60 stores energy for the inductor L 1 , and the inductor current rises, and the inductor current flows through the main line sampling resistor R S. As shown in FIG.
  • Branch sampling resistor R is equal to the voltage drop on the second switching unit is turned on Q 2 is multiplied by the value a current sampling resistor R 1 of the branch, at the midpoint of the pulse timing acquisition branch switch control signal on a sampling resistor R That is, the conduction current of the second switching unit Q 2 can be obtained, and the conduction current is recorded as the branch current i L1 .
  • the switching control signal pulse middle time unit flowing through the second switch Q 2 is equal to the conduction current mid-current inductor L 1 riser 8, i.e. equal flow the average current through the inductor L 1, which is referred to as a branch current i L1;
  • input voltage V i ⁇ 0, the switching control signal pulse middle time unit flowing through the second switch Q 2 is turned on is equal to the inductor current the midpoint of the current drop segment L 1, i.e., equal to the average current flowing through the inductor L 1, which is referred to as a branch current i L1.
  • the operating frequency of the AC power supply 60 is much less than the power conditioner 10 on the first branch switching unit Q 1, a second switching unit switching frequency f sw 2 Q, for example, the operating frequency of the AC power supply 60 is 50H Z, the switching frequency f sw is 50kH Z, i.e., a sine wave in the period of the AC power supply 60 output voltage V i of the collected plurality of branch currents i L1, i.e., the collected branch current i L1 is the waveform of the AC power supply 60 with the same frequency sinusoidal phase wave.
  • the branch current i L1 cannot be directly collected in a partial interval within one sine wave cycle of the AC power supply 60, so the main line current I in needs to be collected to substitute the branch current i L1 in an equivalent manner.
  • the power factor correction circuit 100 samples the branch current i L1 flowing through each branch sampling resistor R 1 and the main line current I in flowing through the main line sampling resistor R S to indirectly obtain the branch current flowing through the inductor.
  • the current of the circuit 20 reduces the requirements on the current sampling device, and a relatively cost-effective current sampling solution can be used, so that the overall cost of the power factor correction circuit 100 can be effectively reduced.
  • the power factor correction circuit 100 provided in the present application is an interleaved parallel power factor correction circuit, which can increase output power and reduce input current harmonics.
  • each branch sampling period may be a sampling resistor R and the input voltage V i 1 in the phase change cycle of the input voltage V i of the AC power supply 60 provides a current phase angle [theta], and confirm the current
  • the phase angle ⁇ is within the sampleable interval, and then each switch control signal is output according to each branch current i L1 ; and the current phase angle ⁇ is confirmed to be outside the sampleable interval, and then the switching control signal is output according to the main line current I in .
  • the control circuit 50 outputs the comparison result of each branch current i L1 and the reference current I ref to each switch control signal; correspondingly confirms that the current phase angle ⁇ is outside the sampleable interval
  • the control circuit 50 divides the main line current I in by the number of power adjustment branches 10 and compares the result with the reference current I ref to output each switch control signal.
  • the current phase angle ⁇ of the AC power supply 60 current phase angle, the current control circuit 50 also collected magnitude of the input voltage V i of the AC power supply 60, and the PLL input current amplitude of the input voltage V i is the current phase to give Angle ⁇ .
  • the phase-locked loop PLL inputs the current phase angle ⁇ to the sampling current processing module.
  • the sampling current processing module confirms that the current phase angle ⁇ is within the sampleable interval, and outputs the branch current i L1 as the input signal I 1 and compares it with the reference current I ref . Compare; or, the sampling current processing module confirms that the current phase angle ⁇ is outside the sampleable interval, and outputs the input signal I 1 obtained after equivalent transformation of the main line current I in , and uses this input signal I 1 and the reference current I ref as Compare.
  • the switching subharmonics of the main line current I in are cancelled, and only the smaller higher harmonics flow through the main line sampling resistor R s , and the main line current
  • the value obtained by dividing I in by the number of power regulating branches 10 is very close to the average value of the inductor current of each power regulating branch 10, and can be used as a substitute branch for the non-sampling interval of the branch sampling resistor R 1 Current.
  • the control circuit 50 further obtains the reference output voltage V ref and the output voltage V o , and obtains the difference between the reference output voltage V ref and the output voltage V o through an adder, and the obtained difference is processed by the voltage loop controller Then the current peak value I p of the reference current I ref is obtained, and the current peak value I p and the current phase angle ⁇ are sinusoidally transformed and then input to the multiplier to obtain the current reference current I ref .
  • the sampling current processing module inputs the obtained branch current i L1 as the input signal I 1 to the corresponding adder, and obtains the branch current i L1 and the reference current I through the adder
  • the comparison result of ref is the error signal, and the switch control signal is output accordingly to control the corresponding power regulation branch 10 on and off.
  • the sampling current processing module divides the main line current I in by the number of power adjustment branches 10 to obtain the equivalent branch current as the input signal I 1 and inputs it to the corresponding adder, through The adder obtains the comparison result of the equivalent branch current and the reference current I ref , that is, the error signal, and outputs a switch control signal according to this, so as to perform switch control on the corresponding power adjustment branch 10.
  • the error signal of the branch current i L1 and the reference current I ref is adjusted by the current loop controller to obtain the modulated wave; the comparator is used to compare the obtained modulated wave with a given carrier, thereby generating the first a pulse width modulation signal; a first PWM modulator to obtain the first pulse width modulation signal, and outputs a switch control signal corresponding to the pulse width of the second switching element Q 2, to control the switching of the second switching element Q 2; a first After the pulse width modulation signal is inverted by the inverter, a second pulse width modulation signal complementary to the first pulse width modulation signal is generated. The second PWM modulator obtains the second pulse width modulation signal and outputs the corresponding pulse width Another switch control signal is sent to the first switch unit Q 1 to perform switch control on the first switch unit Q 1 .
  • the minimum sampling time T min is determined by factors such as the sampling chip of the control circuit 50, the sampling peripheral circuit, and the processing capability of the controller, and it is about 2-5 us.
  • the minimum sampling time control circuit 50 further samples the input voltage V i and capacitor branch output voltage V o 40 and the peak voltage V p, the output voltage V o obtained by sampling the input voltage V i, T min of the previously obtained Calculate the sampleable interval with the switching frequency f sw of the second switching unit.
  • the sampling interval may be a phase range corresponding to the input voltage V i in the 0 ° to ⁇ p and 180 ° - ⁇ p to 180 °.
  • the sampling interval may correspond to the input voltage V i of the phase interval of 180 ° + ⁇ n to 360 ° - ⁇ n.
  • the AC power supply 60 is a 220V / 50HZ
  • the minimum sampling time of the power factor correction circuit 100 is T min 3us
  • switching frequency f sw is 50kHz
  • the output voltage V o is 380V
  • ⁇ p 90 °
  • ⁇ n 10.5 °
  • the sampling interval may be in the input voltage V i is a phase variation period of 0 ° to 180 ° and 190.5 ° to 349.5 °
  • the remaining sections 180 ° to 190.5° and 349.5° to 360° are non-sampling intervals.
  • the non-sampling interval can be expanded by a percentage, for example, the non-sampling interval is expanded by 10%, 20%, etc. For example, if the non-sampling intervals 180° to 190.5° and 349.5° to 360° are expanded by 20%, the new non-sampling intervals are 178.95° to 191.55°, 348.45° to 1.05°, and the remaining intervals are sampleable intervals.
  • the power factor correction circuit samples the branch current i L1 flowing through the branch sampling resistor R 1 and the main line current I in flowing through the main line sampling resistor R S to indirectly obtain the branch current flowing through the inductor branch. 20, reducing the requirements for current sampling devices, and a relatively cost-effective current sampling scheme can be used, so that the overall cost of the power factor correction circuit 100 is effectively reduced; and the control circuit 50 obtains the branch current i L1 according to the sampling And the main line current I in to perform switching control on each power adjustment branch 10, that is, by adjusting the duty cycle of the respective switching control signals of the first switching unit Q 1 and the second switching unit Q 2 to control the power flow through the power adjustment branch 10 branch current i L1 and the capacitance branch to regulate the output voltage V o 40 of.
  • FIG. 10 is a schematic flowchart of an embodiment of a control method of a power factor correction circuit provided by the present application.
  • Step 11 Obtain the branch current flowing through the branch sampling resistor of each power adjustment branch and the main line current flowing through the main line sampling resistor of each rectifier branch.
  • the operating frequency of the AC power supply 60 in the power factor correction circuit 100 is much smaller than the switching frequency f sw of the first switching unit Q 1 and the second switching unit Q 2 on the power regulating branch 10.
  • the operating frequency of the AC power supply 60 is 50H Z
  • the switching frequency f sw is 50kH Z, i.e., a sine wave in the period of the AC power supply 60 output voltage V i of the collected plurality of branch currents i L1, i.e., collected branched
  • the waveform of the path current i L1 is a sine wave with the same frequency and phase as the AC power supply 60.
  • the branch current i L1 cannot be directly collected in a part of a period of a sine wave of the AC power supply 60, so the main line current I in needs to be collected to perform an equivalent transformation to replace the branch current i L1 .
  • Step 12 Output the switch control signal according to the branch current and the main line current.
  • the switch control signal is output according to the branch current i L1 and the main line current I in , and the switch control signal is used to switch the corresponding power adjustment branch 10.
  • FIG. 11 is a schematic flowchart of an embodiment of a control method of a power factor correction circuit provided by the present application.
  • Step 21 Obtain the branch current flowing through the branch sampling resistor of each power adjustment branch and the main line current flowing through the main line sampling resistor of each rectifier branch.
  • Step 22 Obtain the sampleable interval of the sampling resistor of each branch and the current phase angle of the input voltage.
  • the sampleable interval is the interval within the phase change period of the input voltage provided by the AC power source, and the sampleable interval is that the conduction time of the second switching unit Q 2 is greater than the minimum sampling required for sampling the branch current i L1
  • the interval of time T min is determined by factors such as the sampling chip of the control circuit 50, the sampling peripheral circuit, and the processing capability of the controller, and it is about 2-5 us.
  • the input voltage V i of the AC power supply 60 and the capacitor 40 of the branch output voltage V o is sampled, and the peak voltage obtained by sampling the input voltage V i V p, the output voltage V o, the previously obtained
  • the time T min and the switching frequency f sw of the second switching unit calculate the sampleable interval.
  • the sampling interval when the input voltage V i> 0, the sampling interval may be a phase range corresponding to the input voltage V i in the 0 ° to ⁇ p and 180 ° - ⁇ p to 180 °; when the input voltage V i ⁇ 0, the sampling interval may correspond to the input voltage V i of the phase interval of 180 ° + ⁇ n to 360 ° - ⁇ n.
  • the sampling interval may be in the input voltage V i is a phase variation period of 0 ° to 180 ° and 190.5 ° to 349.5 °, 180 ° interval remaining to 190.5 °, 349.5° to 360° is the non-sampling interval.
  • the non-sampling interval can be expanded by a percentage, for example, the non-sampling interval is expanded by 10%, 20%, etc. For example, if the non-sampling interval 180° to 190.5°, 349.5° to 360° is expanded by 20%, the new non-sampling interval is 178.95° to 191.55°, 348.45° to 1.05°.
  • the current phase angle [theta] to the current phase angle of the AC power supply 60 for example by collecting the input voltage V i is the current amplitude of the AC power supply 60 to extract the current phase angle ⁇ .
  • the input current amplitude of the input voltage V i of the PLL to obtain a current phase angle ⁇ .
  • Step 23 Confirm that the current phase angle is within the sampling interval, and output each switch control signal according to the current of each branch.
  • the control circuit 50 Confirming that the current phase angle ⁇ is within the sampleable interval, the control circuit 50 outputs each switch control signal according to the comparison result of each branch current i L1 and the reference current I ref to control the corresponding power adjustment branch 10 on and off.
  • the difference is obtained by the voltage
  • the loop controller processes the current peak value I p of the reference current I ref and then inputs the current peak value I p and the current phase angle ⁇ into the multiplier after sinusoidal transformation to obtain the current reference current I ref .
  • the error signal is processed to obtain a modulated wave.
  • the first PWM modulator obtains the first pulse width modulation signal, and outputs the corresponding pulse width switching control signal to the second switching unit Q 2, in order to control the switching of the second switching element Q 2;
  • a first pulse width modulation signal after further inverted by an inverter, to obtain a second pulse width modulation signal complementary to the first pulse width modulation signal, a second PWM modulation acquires the second pulse width modulation signal, and outputs a pulse width corresponding to the other switch control signals to the first switch unit Q 1, to control the switching of the first switching element Q 1.
  • Step 24 Confirm that the current phase angle is outside the sampleable interval, and output the switch control signal according to the main line current.
  • the control circuit 50 After confirming that the current phase angle ⁇ is outside the sampleable interval, the control circuit 50 outputs a switch control signal according to the comparison result of the main line current I in divided by the number of power adjustment branches 10 and the reference current I ref , and performs a control on each power adjustment branch 10 Switch control.
  • the main line current I in is divided by the number of power adjustment branches 10 to obtain the equivalent branch current, and the equivalent branch current is compared with the reference current I ref to obtain the error signal, and accordingly Each power adjustment branch 10 is switched on and off.
  • FIG. 11 a schematic structural diagram of an embodiment of a storage medium provided by the present application.
  • the computer-readable storage medium 70 stores program data 71, and when the program data 71 is executed by the processor, the control method of the power factor correction circuit as described in FIGS. 9 to 10 is realized.
  • the program data 71 is stored in a computer-readable storage medium 40, and includes several instructions for making a computer device (which can be a router, a personal computer, a server, or a network device, etc.) or a processor execute the methods described in the various embodiments of this application All or part of the steps.
  • the computer-readable storage medium 70 may be a U disk, a mobile hard disk, a read only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc., which can store program data.
  • FIG. 12 is a schematic structural diagram of an embodiment of an electrical appliance provided by the present application.
  • the electrical appliance 80 includes a connected processor 82 and a memory 81.
  • the memory 81 stores a computer program.
  • the processor 82 executes the computer program, the control method of the power factor correction circuit as described in FIGS. 9 to 10 is implemented.
  • the electrical appliance can be various electrical products such as air conditioners, refrigerators, televisions, wall breakers, dishwashers, etc., and it can also be mechanical equipment such as machine tools or electronic equipment such as mobile phones and computers. This application does not make specific categories of electrical appliances. limit.
  • FIG. 13 is a schematic structural diagram of an embodiment of a household appliance provided by the present application.
  • the home appliance includes the power factor correction circuit 100 as described above.
  • the home appliance can be various electrical products such as air conditioners, refrigerators, televisions, wall breakers, dishwashers, etc., and it can also be mechanical equipment such as machine tools, or electronic equipment such as mobile phones and computers. This application does not make specific categories of electrical appliances. limit.
  • this application discloses a power factor correction circuit, a control method, a storage medium, electrical appliances and household appliances.
  • the main line sampling resistor By connecting branch sampling resistors in series in each parallel power adjustment branch, and setting the main line sampling resistor, and connecting the first end of the main line sampling resistor between the first rectification unit and the second rectification unit, the main line sampling resistor is The second end is connected to the second end of the AC power supply.
  • the disclosed method and device may be implemented in other ways.
  • the device implementation described above is merely illustrative.
  • the division of the modules or units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components may be Combined or can be integrated into another system, or some features can be ignored or not implemented.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of this embodiment.
  • the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.

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Abstract

一种功率因数校正电路、控制方法、存储介质、电器及家电。该功率因数校正电路（100）包括：功率调节支路（10）包括依次串联的第一开关单元（Q1）、第二开关单元（Q2）及支路采样电阻（R 1）；电感支路（20）连接于交流电源（60）与功率调节支路（10）之间；整流支路（30）包括与功率调节支路（10）并联且彼此串联的第一整流单元（Q7）和第二整流单元（Q8），且包括主线采样电阻（R S），主线采样电阻（R S）第一端连接于第一整流单元（Q7）和第二整流单元（Q8）之间，主线采样电阻（R S）第二端连接交流电源（60）的第二端；电容支路（40）与功率调节支路（10）和负载（R L）并联；控制电路（50）分别对流经各支路采样电阻（R 1）的支路电流（I L1）和流经主线采样电阻（R S）的主线电流（I in）进行采样，并依此对各功率调节支路（10）进行开关控制。通过支路采样电阻（R 1）和主线采样电阻（R S），能够降低功率因数校正电路的整体成本。

Description

功率因数校正电路、控制方法、存储介质、电器及家电
本申请要求于2019年5月22日提交的申请号为2019104308211，发明名称为“功率因数校正电路、控制方法、存储介质、电器及家电”的中国专利申请的优先权，其通过引用方式全部并入本申请。
【技术领域】
本申请涉及电路技术领域，特别是涉及一种功率因数校正电路、控制方法、存储介质、电器及家电。
【背景技术】
为了消除电网谐波污染、提高功率因数,需要在电子设备的输入端增加功率因数校正(Power Factor Correction，PFC)变换器。工业上常用方案是带整流桥的boost型升压电路。无桥图腾柱PFC则是近两年由于WBG(Wide Bandgap Semiconductor，宽禁带)新器件的兴起而产生应用价值的高效率拓扑方案，由于去除了整流桥，电流导通路径中减少了一个二极管，减少了二极管的导通损耗，提升了系统。
现行的功率因数校正电路为了控制各并联支路的电流并实现均流需要对各电感支路电流采样，常用霍尔电路采集各电感支路的电流，成本较高。
【发明内容】
本申请主要提供一种功率因数校正电路、控制方法、存储介质、电器及家电，以解决功率因数校正电路对电感支路电流采样成本高的问题。
为解决上述技术问题，本申请采用的一个技术方案是：提供一种图功率因数校正电路、控制方法、存储介质、电器及家电。该功率因数校正电路包括：至少两路彼此并联的功率调节支路，功率调节支路包括依次串联的第一开关单元、第二开关单元及支路采样电阻；至少两路电感支路，电感支路的第一端与交流电源的第一端连接，电感支路的第二端连接于对应的功率调节支路的第一开关单元与第二开关单元之间；整流支路包括与功率调节支路并联且彼此串联 的第一整流单元和第二整流单元，并进一步包括主线采样电阻，主线采样电阻的第一端连接于第一整流单元和第二整流单元之间，主线采样电阻的第二端连接交流电源的第二端；电容支路与功率调节支路和负载并联；控制电路分别对流经各支路采样电阻的支路电流和流经主线采样电阻的主线电流进行采样，并根据采样获得的支路电流和主线电流对各功率调节支路进行开关控制。
为解决上述技术问题，本申请采用的另一个技术方案是：提供一种功率因数校正电路的控制方法。该控制方法包括：获取流经各功率调节支路的支路采样电阻的支路电流以及流经各整流支路的主线采样电阻的主线电流；根据支路电流和主线电流对各功率调节支路进行开关控制。
为解决上述技术问题，本申请采用的另一个技术方案是：提供一种存储介质。该存储介质存储有程序数据，程序数据被处理器执行时实现如上述方法的步骤。
为解决上述技术问题，本申请采用的另一个技术方案是：提供一种电器。该电器包括连接的处理器和存储器，存储器存储有计算机程序，处理器执行计算机程序时，实现如上述方法的步骤。
为解决上述技术问题，本申请采用的另一个技术方案是：提供一种家电。该家电包括如上述的功率因数校正电路。
本申请的有益效果是：区别于现有技术的情况，本申请公开了一种功率因数校正电路、控制方法、存储介质、电器及家电。通过在各彼此并联的功率调节支路中串联支路采样电阻，以及设置主线采样电阻，并将主线采样电阻的第一端连接于第一整流单元和第二整流单元之间，主线采样电阻的第二端连接交流电源的第二端，进而通过对流经各支路采样电阻的支路电流和流经主线采样电阻的主线电流进行采样，以间接获得流经电感支路的电流，降低了对电流采样器件的要求，可使用比较省成本的电流采样方案，使得功率因数校正电路的整体成本得到有效地降低了。
【附图说明】
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付 出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请提供的功率因数校正电路一实施例的结构示意图；
图2是功率因数校正电路另一实施例的结构示意图；
图3是图1功率因数校正电路电流流通路径的第一种状态示意图；
图4是图1功率因数校正电路电流流通路径的第二种状态示意图；
图5是图1功率因数校正电路电流流通路径的第三种状态示意图；
图6是图1功率因数校正电路电流流通路径的第四种状态示意图；
图7是图1功率因数校正电路中支路电流的可采样区间的示意图；
图8是图1功率因数校正电路中各功率调节支路的开关控制信号、各支路电流及等效支路电流的波形示意图；
图9是本申请提供的功率因数校正电路另一实施例的结构示意图；
图10是本申请提供的功率因数校正电路的控制方法一实施例的流程示意图；
图11是本申请提供的功率因数校正电路的控制方法另一实施例的流程示意图；
图12是本申请提供的存储介质一实施例的结构示意图；
图13是本申请提供的电器一实施例的结构示意图；
图14是本申请提供的家电一实施例的结构示意图。
【具体实施方式】
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例中的术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”、“第三”的特征可以明示或者隐含地包括至少一个该特征。本申请的描述中，“多个”的含义是至少两个，例如两个，三个等，除非 另有明确具体的限定。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
参阅图1，图1是本申请提供的功率因数校正电路一实施例的结构示意图。
控制电路50与各功率调节支路10的连接关系均相同，图1中仅示意了一路功率调节支路10与控制电路50的连接关系，其余功率调节支路10与控制电路50的连接关系全被省略，而非其余功率调节支路10不与控制电路50连接。图1还示出了三路功率调节支路10，为便于叙述，使各路功率调节支路10的第一开关单元级第二开关单元有不同的记号，但在后续叙述中主要以第一路功率调节支路10为例。
该功率因数校正电路100包括至少两路彼此并联的功率调节支路10、至少两路电感支路20、整流支路30、电容支路40和控制电路50，功率调节支路10用于接收驱动信号调控功率调节支路10的支路电流i L1，进而实现对功率因数校正电路100的支路电流i L1与输出电压V o的控制，即该至少两路彼此并联的功率调节支路10将功率因数校正电路100的输入电流校正为与交流电源同频同相的正弦波，以使得其输出电压V o的稳定。
该至少两路功率调节支路10彼此并联，且各功率调节支路10包括依次串联的第一开关单元Q 1、第二开关单元Q 2及支路采样电阻R 1。
可选地，第一开关单元Q 1和第二开关单元Q 2可以为MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor，金属氧化物半导体场效应晶体管)，例如GaN MOSFET、超结MOSFET或者SiC-MOSFET。
需要注意的是，控制每一功率调节支路10的模式均相同，该至少两路彼此并联的功率调节支路10的开关控制信号在一个周期内依次移相一定相位角，该一定相位角为360度与功率调节支路10的数量的比值，该开关控制信号为PWM (Pulse Width Modulation，脉冲宽度调制)驱动信号。例如，该功率因数校正电路100包括两路功率调节支路10，对应的开关控制信号在一个周期彼此移相180度；如图1、图8所示，该功率因数校正电路100包括三路功率调节支路10，对应的开关控制信号在一个周期依次移相120度。
对应地，至少两路电感支路20的数量与至少两路功率调节支路10的数量相同并一一对应。具体地，电感支路20的第一端与交流电源60的第一端连接，电感支路20的第二端连接于对应的功率调节支路10的第一开关单元Q 1与第二开关单元Q 2之间。
例如，3路彼此并联的功率调节支路10对应有3路电感支路20，每一电感支路20连接于对应的功率调节支路10与交流电源60之间。功率调节支路10还可以并联有2路、4路、5路等，电感支路20相应的有2路、4路、5路等。
具体地，电感支路20包括电感器L 1，电感器L 1的第一端与交流电源60的第一端连接，电感器L 1的第二端连接于对应的功率调节支路10的第一开关单元Q 1与第二开关单元Q 2之间。
整流支路30包括与功率调节支路10并联且彼此串联的第一整流单元Q 7和第二整流单元Q 8，即彼此串联的第一整流单元Q 7和第二整流单元Q 8作为一个整体与功率调节支路10并联。整流支路30进一步包括主线采样电阻R S，主线采样电阻R S的第一端连接于第一整流单元Q 7和第二整流单元Q 8之间，主线采样电阻R S的第二端连接交流电源60的第二端。
可选地，第一整流单元Q 7和第二整流单元Q 8均为同步整流开关管或二极管。如图2所示，第一整流单元Q 7和第二整流单元Q 8采用二极管时，可无需设置控制第一整流单元Q 7和第二整流单元Q 8的驱动电路，进一步降低了功率因数校正电路100的成本。如图1所示，第一整流单元Q 7和第二整流单元Q 8采用同步整流开关管时，即为与第一开关单元Q 1相同的GaN MOSFET、超结MOSFET或者SiC-MOSFET管，减少了整流支路30的导通损耗，进一步地提升了功率因数校正电路100的效率。
电容支路40与功率调节支路10、负载R L并联。即电容支路40的第一端与第一开关单元Q 1的第一端、第一整流单元Q 7的第一端、负载R L的第一端连接于第一公共节点，电容支路40的第二端与第二开关单元Q 2的第二端、第二整流单元Q 8的第二端、负载R L的第二端连接于第二公共节点，该第二公共节点还接参考地。
具体地，电感支路40包括输出电容C bus。第一开关单元Q 1的第一端、第一整流单元Q 7的第一端均与输出电容C bus的正极连接，第二开关单元Q 2的第二端、第二整流单元Q 8的第二端均与输出电容C bus的负极连接。
控制电路50分别对流经各支路采样电阻R 1的支路电流i L1和流经主线采样电阻R S的主线电流I in进行采样，并根据采样获得的支路电流i L1和主线电流I in输出开关控制信号，开关控制信号用于对相应的功率调节支路10进行开关控制，即通过调节第一开关单元Q 1、第二开关单元Q 2各自开关控制信号的占空比，以对流经功率调节支路10的支路电流i L1和电容支路40的输出电压V o进行调控。
现以其中一路功率调节支路10为例说明功率因数校正电路100中支路电流的流动路径。
当交流电源60的输入电压V i>0时，整流支路30的第二整流单元Q 8长通，控制电路50输出开关控制信号对第一开关单元Q 1与第二开关单元Q 2进行开关控制。如图3所示，当第二开关单元Q 2导通、第一开关单元Q 1关断时，交流电源60给电感器L 1储能，进而电感电流上升，电感电流依次流经支路采样电阻R 1和主线采样电阻R S。如图4所示，当第二开关单元Q 2关断、第一开关单元Q 1导通时，电感器L 1储存的能量给输出电容C bus充电，此时电感电流流经主线采样电阻R S。
当交流电源60的输入电压V i<0时，整流支路30的第一整流单元Q 7长通，控制电路50输出开关控制信号对第一开关单元Q 1与第二开关单元Q 2进行开关控制。如图5所示，当第一开关单元Q 1导通、第二开关单元Q 2关断时，交流电源60给电感器L 1储能，进而电感电流上升，电感电流流经主线采样电阻R S。如图6所示，当第一开关单元Q 1关断、第二开关单元Q 2导通时，电感器L 1储存的能量给输出电容C bus充电，此时电感电流依次流经支路采样电阻R 1和主线采样电阻R S。
支路采样电阻R 1上的压降等于第二开关单元Q 2的导通电流乘以支路采样电阻R 1的阻值，在开关控制信号的脉冲中点时刻采集支路采样电阻R 1上的压降，即可以获得第二开关单元Q 2的导通电流，将该导通电流记为支路电流i L1。
如图8所示，输入电压V i>0时，在开关控制信号的脉冲中点时刻流经第二开关单元Q 2的导通电流等于电感器L 1上升段的中点电流，即等于流经电感器L 1的平均电流，将其记为支路电流i L1；输入电压V i<0时，在开关控制信号的脉冲中点时刻流经第二开关单元Q 2的导通电流等于电感器L 1下降段的中点电流， 即等于流经电感器L 1的平均电流，将其记为支路电流i L1。
而且交流电源60的工作频率远小于功率调节支路10上第一开关单元Q 1、第二开关单元Q 2的开关频率f sw，例如交流电源60的工作频率为50H Z，开关频率f sw为50kH Z，即在交流电源60输出电压V i的一个正弦波周期内，将采集多个支路电流i L1，即采集到的支路电流i L1的波形为与交流电源60同频同相的正弦波。但在交流电源60的一个正弦波周期内的部分区间内无法直接采集到支路电流i L1，因而需要采集主线电流I in以进行等效替代支路电流i L1。
因而，本申请提供的功率因数校正电路100通过对流经各支路采样电阻R 1的支路电流i L1和流经主线采样电阻R S的主线电流I in进行采样，以间接获得流经电感支路20的电流，降低了对电流采样器件的要求，可使用比较省成本的电流采样方案，使得功率因数校正电路100的整体成本得到有效地降低。
而且，本申请提供的功率因数校正电路100为交错并联式功率因数校正电路，其可以增加输出功率，降低输入电流谐波。
参阅图9，控制电路50进一步获取各支路采样电阻R 1在交流电源60所提供的输入电压V i的相位变化周期内的可采样区间和输入电压V i的当前相位角θ，并确认当前相位角θ位于可采样区间内，进而根据各支路电流i L1输出各开关控制信号；以及确认当前相位角θ位于可采样区间外，进而根据主线电流I in输出开关控制信号。
具体地，对应确认当前相位角θ位于可采样区间内，控制电路50将各支路电流i L1与参考电流I ref的比较结果输出各开关控制信号；对应确认当前相位角θ位于可采样区间外，控制电路50将主线电流I in除以功率调节支路10的数量后与参考电流I ref的比较结果输出各开关控制信号。
当前相位角θ为交流电源60的当前相位角，控制电路50还采集交流电源60的输入电压V i的当前幅值，并将输入电压V i的当前幅值输入锁相环PLL以得到当前相位角θ。锁相环PLL将当前相位角θ输入到采样电流处理模块，采样电流处理模块确认当前相位角θ位于可采样区间内，将支路电流i L1作为输入信号I 1输出并与参考电流I ref作比较；或者，采样电流处理模块确认当前相位角θ位于可采样区间外，将主线电流I in作等效变换后得到的输入信号I 1输出，并将此输入信号I 1与参考电流I ref作比较。
具体地，至少两路彼此并联的功率调节支路10由于多路交错，主线电流I in的开关次谐波被抵消，只剩较小的高次谐波流经主线采样电阻R s，主线电流I in 除以功率调节支路10的数量后所得到的数值，与每个功率调节支路10的电感电流的平均值很接近，进而可作为支路采样电阻R 1不可采样区间的替代支路电流。
控制电路50进一步还获取参考输出电压V ref和输出电压V o，并将参考输出电压V ref和输出电压V o通过加法器得到两者的差值，所得到的差值经电压环控制器处理后得到参考电流I ref的电流峰值I p，将电流峰值I p和当前相位角θ经正弦变换后输入到乘法器，即可得到当前的参考电流I ref。
确认当前相位角θ位于可采样区间内，采样电流处理模块将所获取的各支路电流i L1作为输入信号I 1输入到相应的加法器，通过加法器得到支路电流i L1与参考电流I ref的比较结果，即误差信号，并据此输出开关控制信号，以对相应的功率调节支路10进行开关控制。
确认当前相位角θ位于可采样区间外，采样电流处理模块将主线电流I in除以功率调节支路10的数量所得到的等效支路电流作为输入信号I 1输入到相应的加法器，通过加法器得到等效支路电流与参考电流I ref的比较结果，即误差信号，并据此输出开关控制信号，以对相应的功率调节支路10进行开关控制。
例如，将该支路电流i L1与参考电流I ref的误差信号经电流环控制器进行调节处理，以得到调制波；利用比较器比较所得到的调制波和给定的载波，从而生成第一脉冲宽度调制信号；第一PWM调制器获取该第一脉冲宽度调制信号，并输出相应脉冲宽度的开关控制信号至第二开关单元Q 2，以对第二开关单元Q 2进行开关控制；第一脉冲宽度调制信号还经过反相器反相后，生成与第一脉冲宽度调制信号互补的第二脉冲宽度调制信号，第二PWM调制器获取该第二脉冲宽度调制信号，并输出相应脉冲宽度的另一开关控制信号至第一开关单元Q 1，以对第一开关单元Q 1进行开关控制。
具体地，当各功率调节支路10的第二开关单元Q 2导通时，存在流经各支路采样电阻R 1的支路电流i L1，其中可采样区间为第二开关单元Q 2的导通时间大于对支路电流i L1进行采样所需的最小采样时间T min的区间。
最小采样时间T min由控制电路50的采样芯片、采样外围电路、控制器处理能力等因素所决定，其约为2～5us。
控制电路50进一步对输入电压V i和电容支路40的输出电压V o进行采样，并根据采样获得的输入电压V i的峰值电压V p、输出电压V o、预先获得的最小采样时间T min和第二开关单元的开关频率f sw计算该可采样区间。
具体地，当输入电压V i＞0时，可采样区间对应于输入电压V i的相位区间中的0°至θ p以及180°-θ p内至180°。当输入电压V i＜0时，可采样区间对应于输入电压V i的相位区间中的180°+θ n至360°-θ n。
其中，
Figure PCTCN2019123355-appb-000001
例如，如图6所示，交流电源60为220V/50HZ，则其峰值电压V p为311V，该功率因数校正电路100的最小采样时间T min为3us、开关频率f sw为50kHz，输出电压V o为380V，则可得到θ p＝90°，θ n＝10.5°，在输入电压V i的一个相位变化周期内的可采样区间为0°至180°和190.5°至349.5°，其余区间180°至190.5°、349.5°至360°为非采样区间。
进一步地，为避免系统误差的影响，在可采样区间中保留适当的裕量，即可将非采样区间按百分比扩大，例如将非采样区间扩大10％、20％等。例如将非采样区间180°至190.5°、349.5°至360°均扩大20％，则新的非采样区间为178.95°至191.55°、348.45°至1.05°，其余区间为可采样区间。
进而，本申请提供的功率因数校正电路通过对流经各支路采样电阻R 1的支路电流i L1和流经主线采样电阻R S的主线电流I in进行采样，以间接获得流经电感支路20的电流，降低了对电流采样器件的要求，可使用比较省成本的电流采样方案，使得功率因数校正电路100的整体成本得到有效地降低；并且控制电路50根据采样获得的支路电流i L1和主线电流I in对各功率调节支路10进行开关控制，即通过调节第一开关单元Q 1、第二开关单元Q 2各自开关控制信号的占空比，以对流经功率调节支路10的支路电流i L1和电容支路40的输出电压V o进行调控。
参阅图10，图10是本申请提供的功率因数校正电路的控制方法一实施例的流程示意图。
步骤11：获取流经各功率调节支路的支路采样电阻的支路电流以及流经各整流支路的主线采样电阻的主线电流。
功率因数校正电路100中交流电源60的工作频率远小于功率调节支路10上第一开关单元Q 1、第二开关单元Q 2的开关频率f sw。例如交流电源60的工作频率为50H Z，开关频率f sw为50kH Z，即在交流电源60输出电压V i的一个正弦波周期内，将采集多个支路电流i L1，即采集到的支路电流i L1的波形为与交流电源60同频同相的正弦波。但交流电源60的一个正弦波周期内的部分区间内无 法直接采集到支路电流i L1，因而需要采集主线电流I in以进行等效变换，进而替代支路电流i L1。
步骤12：根据支路电流和主线电流输出开关控制信号。
根据支路电流i L1和主线电流I in输出开关控制信号，该开关控制信号用于对相应的功率调节支路10进行开关控制。可以理解的，在交流电源60的一个正弦波周期内，当能够获取到支路电流i L1时，采用支路电流i L1作为输入信号以输出开关控制信号，进而对相应的功率调节支路10进行开关控制；当无法获取到支路电流i L1时，获取主线电流I in以进行等效变换，进而替代支路电流i L1，从而采用主线电流I in作为输入信号以输出开关控制信号。
对各功率调节支路10进行开关控制，即通过调节第一开关单元Q 1、第二开关单元Q 2各自开关控制信号的占空比，以对流经功率调节支路10的电流和电容支路40的输出电压V o进行调控。
参阅图11，图11是本申请提供的功率因数校正电路的控制方法一实施例的流程示意图。
步骤21：获取流经各功率调节支路的支路采样电阻的支路电流以及流经各整流支路的主线采样电阻的主线电流。
步骤22：获取各支路采样电阻的可采样区间和输入电压的当前相位角。
该可采样区间为交流电源所提供的输入电压的相位变化周期内的区间，且该可采样区间为第二开关单元Q 2的导通时间大于对支路电流i L1进行采样所需的最小采样时间T min的区间。其中，最小采样时间T min由控制电路50的采样芯片、采样外围电路、控制器处理能力等因素所决定，其约为2～5us。
具体地，对交流电源60的输入电压V i和电容支路40的输出电压V o进行采样，并根据采样获得的输入电压V i的峰值电压V p、输出电压V o、预先获得的最小采样时间T min和第二开关单元的开关频率f sw计算可采样区间。
在本实施例中，当输入电压V i＞0时，可采样区间对应于输入电压V i的相位区间中的0°至θ p以及180°-θ p内至180°；当输入电压V i＜0时，可采样区间对应于输入电压V i的相位区间中的180°+θ n至360°-θ n。
其中，
Figure PCTCN2019123355-appb-000002
例如，交流电源60为220V/50H Z，则其峰值电压V p为311V，该功率因数校正电路100的最小采样时间T min为3us、开关频率f sw为50kHz，输出电压V o为 380V，则可得到θ p＝90°，θ n＝10.5°，在输入电压V i的一个相位变化周期内的可采样区间为0°至180°和190.5°至349.5°，其余区间180°至190.5°、349.5°至360°为非采样区间。
进一步地，为避免系统误差的影响，在可采样区间中保留适当的裕量，即可将非采样区间按百分比扩大，例如将非采样区间扩大10％、20％等。例如将非采样区间180°至190.5°、349.5°至360°均扩大20％，则新的非采样区间为178.95°至191.55°、348.45°至1.05°。
当前相位角θ为交流电源60的当前相位角，例如通过采集交流电源60的输入电压V i的当前幅值，以提取当前相位角θ。例如，将输入电压V i的当前幅值输入锁相环PLL，从而得到当前相位角θ。
步骤23：确认当前相位角位于可采样区间内，根据各支路电流输出各开关控制信号。
确认当前相位角θ位于可采样区间内，控制电路50根据各支路电流i L1与参考电流I ref的比较结果输出各开关控制信号，以对相应的功率调节支路10进行开关控制。
例如，通过获取功率因数校正电路100的参考输出电压V ref和输出电压V o，并将参考输出电压V ref和输出电压V o通过加法器得到两者的差值，所得到的差值经电压环控制器处理后得到参考电流I ref的电流峰值I p，之后将电流峰值I p和当前相位角θ经正弦变换后输入到乘法器，即可得到当前的参考电流I ref。
以及将支路电流i L1与参考电流I ref的作比较，以得到误差信号，并据此对各功率调节支路10进行开关控制。
具体地，将该误差信号经过处理后，以得到调制波。比较所得到的调制波和给定的载波，以得到第一脉冲宽度调制信号；第一PWM调制器获取该第一脉冲宽度调制信号，并输出相应脉冲宽度的开关控制信号至第二开关单元Q 2，以对第二开关单元Q 2进行开关控制；第一脉冲宽度调制信号还经过反相器反相后，得到与第一脉冲宽度调制信号互补的第二脉冲宽度调制信号，第二PWM调制器获取该第二脉冲宽度调制信号，并输出相应脉冲宽度的另一开关控制信号至第一开关单元Q 1，以对第一开关单元Q 1进行开关控制。
步骤24：确认当前相位角位于可采样区间外，根据主线电流输出所述开关控制信号。
确认当前相位角θ位于可采样区间外，控制电路50根据主线电流I in除以功率调节支路10的数量后与参考电流I ref的比较结果输出开关控制信号，对各功率调节支路10进行开关控制。
具体地，将主线电流I in除以功率调节支路10的数量以得到等效支路电流，并将该等效支路电流与参考电流I ref的作比较，以得到误差信号，并据此对各功率调节支路10进行开关控制。
利用该误差信号对功率调节支路10进行开关控制的过程，在步骤23中已详细描述，不再赘述。
参阅图11，本申请提供的存储介质一实施例的结构示意图。
该计算机可读存储介质70存储有程序数据71，程序数据71在被处理器执行时，实现如图9至图10所描述的功率因数校正电路的控制方法。
该程序数据71存储于一个计算机可读存储介质40中，包括若干指令用于使得一台计算机设备(可以路由器、个人计算机、服务器或者网络设备等)或处理器执行本申请各个实施例所述方法的全部或部分步骤。可选的，计算机可读存储介质70可以为U盘、移动硬盘、只读存储器(ROM)、随机存取存储器(RAM)、磁盘或者光盘等各种可以存储程序数据的介质。
参阅图12，本申请提供的电器一实施例的结构示意图。
该电器80包括连接的处理器82和存储器81，存储器81存储有计算机程序，处理器82执行该计算机程序时，实现如图9至图10所描述的功率因数校正电路的控制方法。
该电器可以是空调器、冰箱、电视机、破壁机、洗碗机等各种电器产品，其也可以是机床等机械设备或手机、计算机等电子设备，本申请对该电器的具体品类不作限制。
参阅图13，本申请提供的家电一实施例的结构示意图。
该家电包括如上述的功率因数校正电路100。该家电可以是空调器、冰箱、电视机、破壁机、洗碗机等各种电器产品，其也可以是机床等机械设备或手机、计算机等电子设备，本申请对该电器的具体品类不作限制。
区别于现有技术的情况，本申请公开了一种功率因数校正电路、控制方法、存储介质、电器及家电。通过在各彼此并联的功率调节支路中串联支路采样电阻，以及设置主线采样电阻，并将主线采样电阻的第一端连接于第一整流单元和第二整流单元之间，主线采样电阻的第二端连接交流电源的第二端，进而通 过对流经各支路采样电阻的支路电流和流经主线采样电阻的主线电流进行采样，以间接获得流经电感支路的电流，进而降低了对电流采样器件的要求，可使用比较省成本的电流采样方案，使得功率因数校正电路的整体成本得到有效地降低了。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于存储介质实施例及家电、电器实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
在本申请所提供的几个实施方式中，应该理解到，所揭露的方法以及设备，可以通过其它的方式实现。例如，以上所描述的设备实施方式仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施方式方案的目的。
另外，在本申请各个实施方式中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
以上所述仅为本申请的实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (15)

  1. 一种功率因数校正电路，其中，包括：
    至少两路彼此并联的功率调节支路，所述功率调节支路包括依次串联的第一开关单元、第二开关单元及支路采样电阻；
    至少两路电感支路，所述电感支路的第一端与交流电源的第一端连接，所述电感支路的第二端连接于对应的所述功率调节支路的所述第一开关单元与所述第二开关单元之间；
    整流支路，包括与所述功率调节支路并联且彼此串联的第一整流单元和第二整流单元，并进一步包括主线采样电阻，所述主线采样电阻的第一端连接于所述第一整流单元和第二整流单元之间，所述主线采样电阻的第二端连接所述交流电源的第二端；
    电容支路，与所述功率调节支路和负载并联；
    控制电路，分别对流经各所述支路采样电阻的支路电流和流经所述主线采样电阻的主线电流进行采样，并根据采样获得的所述支路电流和所述主线电流输出开关控制信号，所述开关控制信号用于对相应的所述功率调节支路进行开关控制。
  2. 根据权利要求1所述的功率因数校正电路，其中，所述控制电路进一步获取各所述支路采样电阻的可采样区间和输入电压的当前相位角，并确认所述当前相位角位于所述可采样区间内，根据各所述支路电流输出各所述开关控制信号，或确认所述当前相位角位于所述可采样区间外，根据所述主线电流输出所述开关控制信号；
    其中，所述可采样区间为交流电源所提供的所述输入电压的相位变化周期内的区间。
  3. 根据权利要求2所述的功率因数校正电路，其中，确认所述当前相位角位于所述可采样区间内，所述控制电路根据各所述支路电流与参考电流的比较 结果输出各所述开关控制信号；确认所述当前相位角位于所述可采样区间外，所述控制电路根据所述主线电流除以所述功率调节支路的数量后与参考电流的比较结果输出所述开关控制信号。
  4. 根据权利要求2所述的功率因数校正电路，其中，所述可采样区间为所述第二开关单元的导通时间大于对所述支路电流进行采样所需的最小采样时间的区间。
  5. 根据权利要求4所述的功率因数校正电路，其中，所述控制电路进一步对所述输入电压和所述电容支路的输出电压进行采样，并根据采样获得的所述输入电压的峰值电压、所述输出电压、预先获得的所述最小采样时间和所述第二开关单元的开关频率计算所述可采样区间。
  6. 根据权利要求1所述的功率因数校正电路，其中，所述第一整流单元和所述第二整流单元均为同步整流开关管或二极管。
  7. 一种功率因数校正电路的控制方法，其中，包括：
    获取流经各功率调节支路的支路采样电阻的支路电流以及流经各整流支路的主线采样电阻的主线电流；
    根据所述支路电流和所述主线电流输出开关控制信号，所述开关控制信号用于对相应的所述功率调节支路进行开关控制。
  8. 根据权利要求7所述的控制方法，其中，所述根据所述支路电流和所述主线电流输出开关控制信号的步骤包括：
    获取各所述支路采样电阻的可采样区间和输入电压的当前相位角；
    确认所述当前相位角位于所述可采样区间内，根据各所述支路电流输出各所述开关控制信号；或者
    确认所述当前相位角位于所述可采样区间外，根据所述主线电流输出所述开关控制信号；
    其中，所述可采样区间为交流电源所提供的所述输入电压的相位变化周期内的区间。
  9. 根据权利要求8所述的控制方法，其中，所述确认所述当前相位角位于所述可采样区间内，根据各所述支路电流输出各所述开关控制信号的步骤，具体包括：
    确认所述当前相位角位于所述可采样区间内，根据各所述支路电流与参考电流的比较结果输出各所述开关控制信号。
  10. 根据权利要求8所述的控制方法，其中，所述确认所述当前相位角位于所述可采样区间外，根据所述主线电流输出所述开关控制信号的步骤，具体包括：
    确认所述当前相位角位于所述可采样区间外，根据所述主线电流除以所述功率调节支路的数量后与参考电流的比较结果输出所述开关控制信号。
  11. 根据权利要求8所述的控制方法，其中，所述可采样区间为所述第二开关单元的导通时间大于对所述支路电流进行采样所需的最小采样时间的区间。
  12. 根据权利要求11所述的控制方法，其中，所述获取各所述支路采样电阻的可采样区间的步骤，具体包括：
    获取交流电源的输入电压和电容支路的输出电压；
    根据所述输入电压的峰值电压、所述输出电压、预先获得的所述最小采样时间和所述功率调节支路中第二开关单元的开关频率计算所述可采样区间。
  13. 一种存储介质，其上存储有程序数据，其中，所述程序数据被处理器执行时实现如权利要求7-12任一项所述方法的步骤。
  14. 一种电器，其中，包括连接的处理器和存储器，所述存储器存储有计算机程序，所述处理器执行所述计算机程序时，实现如权利要求7-12任一项所述方法的步骤。
  15. 一种家电，其中，包括如权利要求1至6任一项所述的功率因数校正电路。
PCT/CN2019/123355 2019-05-22 2019-12-05 功率因数校正电路、控制方法、存储介质、电器及家电 WO2020233097A1 (zh)

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