WO2020124869A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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Publication number
WO2020124869A1
WO2020124869A1 PCT/CN2019/081488 CN2019081488W WO2020124869A1 WO 2020124869 A1 WO2020124869 A1 WO 2020124869A1 CN 2019081488 W CN2019081488 W CN 2019081488W WO 2020124869 A1 WO2020124869 A1 WO 2020124869A1
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Prior art keywords
electrode
thin film
film transistor
pixel
driving circuit
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Ceased
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PCT/CN2019/081488
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English (en)
French (fr)
Inventor
蔡光育
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US16/603,787 priority Critical patent/US20210364867A1/en
Publication of WO2020124869A1 publication Critical patent/WO2020124869A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present application relates to the field of display, in particular to an array substrate and a display panel.
  • a liquid crystal display includes a display panel and a backlight module.
  • the display panel is composed of a color filter substrate, an array substrate, and a liquid crystal layer disposed between the color filter substrate and the array substrate. Its working principle is to control the rotation of the liquid crystal molecules of the liquid crystal layer by applying a driving voltage, and refract the light of the backlight module to generate a picture.
  • the array substrate uses a thin film transistor (Thin Film Transistor, TFT) or other semiconductor device as a switching element for whether the pixel unit receives image data.
  • TFT Thin Film Transistor
  • one pixel electrode is controlled by a pixel driving circuit. When a certain electrode line in the pixel electrode and the common electrode are short-circuited at a certain point, a dark spot will be generated in the entire pixel unit, resulting in poor product display.
  • the present application provides an array substrate and a display panel to solve the problem of poor display of the pixel unit after the pixel electrode and the common electrode in the pixel unit are short-circuited at a certain point.
  • an array substrate including a plurality of pixel units distributed in an array, the pixel unit including a first pixel driving circuit, a second pixel driving circuit, and a pixel driving circuit
  • a first transparent electrode, the first transparent electrode includes a first electrode trace and a second electrode trace insulated from each other;
  • the first pixel driving circuit is electrically connected to the first electrode wiring
  • the second pixel driving circuit is electrically connected to the second electrode wiring.
  • the first electrode trace includes a first main line and a first connection line at one end of the first main line
  • the second electrode trace includes a second main line and a second main line The second connection line at one end
  • the first main line is electrically connected to the first pixel driving circuit through the first connection line
  • the second main line is electrically connected to the second pixel driving circuit through the second connection line.
  • the first electrode traces and the second electrode traces are alternately arranged.
  • the first electrode trace is located on one side of the second electrode trace.
  • the first pixel driving circuit includes at least one first thin film transistor, and the second pixel circuit includes at least one second thin film transistor;
  • the first thin film transistor and the second thin film transistor are respectively located on both sides of the first transparent electrode.
  • the array substrate further includes a driving circuit for providing row-driven scanning signals
  • the first pixel driving circuit and the second pixel driving circuit are connected to the same-level row driving scanning signal line.
  • the array substrate includes:
  • a thin film transistor array disposed on the substrate, the thin film transistor array including a first thin film transistor and a second thin film transistor;
  • a planarization layer provided on the thin film transistor array
  • a second transparent electrode layer provided on the planarization layer
  • An interlayer dielectric layer provided on the second transparent electrode layer
  • a first transparent electrode layer provided on the interlayer dielectric layer, the first transparent electrode layer including the first transparent electrode;
  • the first electrode trace is electrically connected to the first drain of the first thin film transistor through the first via
  • the second electrode trace is connected to the first thin film transistor through the second via
  • the two drains are electrically connected.
  • both the first via and the second via penetrate through the interlayer dielectric layer and the planarization layer.
  • the number of the first electrode traces and the second electrode traces are the same.
  • the pixel unit is one of a red pixel unit, a green pixel unit and a blue pixel unit.
  • a display panel including a color filter substrate, an array substrate, and a liquid crystal layer between the color filter substrate and the array substrate;
  • the array substrate includes a plurality of pixel units distributed in an array.
  • the pixel unit includes a first pixel driving circuit, a second pixel driving circuit, and a first transparent electrode for driving the liquid crystal to turn over.
  • the first transparent electrode includes mutual insulation The first electrode trace and the second electrode trace;
  • the first pixel driving circuit is electrically connected to the first electrode wiring
  • the second pixel driving circuit is electrically connected to the second electrode wiring.
  • the first electrode trace includes a first main line and a first connection line at one end of the first main line
  • the second electrode trace includes a second main line and a second main line The second connection line at one end
  • the first main line is electrically connected to the first pixel driving circuit through the first connection line
  • the second main line is electrically connected to the second pixel driving circuit through the second connection line.
  • the first electrode traces and the second electrode traces are alternately arranged.
  • the first electrode trace is located on one side of the second electrode trace.
  • the first pixel driving circuit includes at least one first thin film transistor, and the second pixel circuit includes at least one second thin film transistor;
  • the first thin film transistor and the second thin film transistor are respectively located on both sides of the first transparent electrode.
  • the array substrate further includes a driving circuit for providing row-driven scanning signals
  • the first pixel driving circuit and the second pixel driving circuit are connected to the same-level row driving scanning signal line.
  • the array substrate includes:
  • a thin film transistor array disposed on the substrate, the thin film transistor array including a first thin film transistor and a second thin film transistor;
  • a planarization layer provided on the thin film transistor array
  • a second transparent electrode layer provided on the planarization layer
  • An interlayer dielectric layer provided on the second transparent electrode layer
  • a first transparent electrode layer provided on the interlayer dielectric layer, the first transparent electrode layer including the first transparent electrode;
  • the first electrode trace is electrically connected to the first drain of the first thin film transistor through the first via
  • the second electrode trace is connected to the first thin film transistor through the second via
  • the two drains are electrically connected.
  • both the first via and the second via penetrate through the interlayer dielectric layer and the planarization layer.
  • the number of the first electrode traces and the second electrode traces are the same.
  • the pixel unit is one of a red pixel unit, a green pixel unit and a blue pixel unit.
  • This application splits a pixel electrode into two sets of signal traces.
  • the two sets of signal traces are controlled by different pixel drive circuits. When one set of signal traces is short-circuited, the other set will still work normally, thereby improving The yield of the product.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by a first embodiment of this application;
  • FIG. 2 is a schematic structural diagram of a pixel unit provided by a second embodiment of this application.
  • FIG. 3 is a schematic structural diagram of an array substrate provided by a third embodiment of the present application.
  • the present application provides an array substrate and a display panel to solve the problem of poor display of the pixel unit after the pixel electrode and the common electrode in the pixel unit are short-circuited at a certain point.
  • FIG. 1 is a schematic structural diagram of an array substrate 100 according to a first embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a pixel unit 10 according to a second embodiment of the present application.
  • an array substrate 100 is provided, and the array substrate 100 includes a plurality of pixel units 10 distributed in an array.
  • the pixel unit 10 may be one of a red pixel unit, a green pixel unit, and a blue pixel unit.
  • the pixel unit 10 includes a first pixel driving circuit 111, a second pixel driving circuit 112, and a first transparent electrode 12 for driving the liquid crystal to turn over.
  • the first transparent electrode 12 includes a first electrode trace 121 insulated from each other Second electrode trace 122.
  • the array substrate 100 uses a semiconductor device such as a thin film transistor as a switching element for whether the pixel unit 10 receives image data.
  • a semiconductor device such as a thin film transistor as a switching element for whether the pixel unit 10 receives image data.
  • this application uses one pixel unit 10 to set two pixel drive circuits, and the original one pixel electrode (ie, the first transparent electrode in this application) 12) Divided into the first electrode trace 121 and the second electrode trace 122 for separate control, thereby preventing a short circuit of a certain electrode trace and causing a dark spot in the pixel unit 10.
  • the pixel driving circuit 111 is electrically connected to the first electrode trace 121, and the second pixel driving circuit 112 is electrically connected to the second electrode trace 122.
  • the first pixel driving circuit 111 includes at least one first thin film transistor 21, and the second pixel driving circuit 112 includes at least one second thin film transistor 22;
  • the first thin film transistor 21 and the second thin film transistor 22 are located on both sides of the first transparent electrode 12 respectively. In order to avoid the problem of mutual interference between the two.
  • the first pixel driving circuit 111 includes a first thin film transistor 21, and the second pixel driving circuit 112 includes a second thin film transistor 22.
  • the first transparent electrode 12 is not limited to being divided into the first electrode trace 121 and the second electrode trace 122, but can also be divided into n electrode traces (n is a positive integer not less than 2)
  • n is a positive integer not less than 2
  • Each type of electrode wiring is provided with a separate pixel driving circuit corresponding thereto, thereby preventing a short circuit of a certain electrode wiring from causing a dark spot in the pixel unit 10.
  • one first transparent electrode 12 is divided into two types of electrode traces, which facilitates the arrangement of the pixel driving circuit, and can avoid too many pixel driving circuits, which leads to complicated product wiring, the following mainly divides one pixel electrode into two types of electrode traces. Take the line as an example.
  • the first electrode traces 121 are electrically connected to each other, and the second electrode traces 122 are electrically connected to each other. That is, the first electrode trace 121 and the second electrode trace 122 belong to different signal circuits, so as to avoid the failure of one of them causing interference to the other.
  • the first electrode trace 121 includes a first main line 1212 and a first connection line 1211 at one end of the first main line 1212
  • the second electrode trace 122 includes a second main line 1222 and A second connection line 1221 at one end of the second main line 1222;
  • the first main line 1212 is electrically connected to the first pixel driving circuit 111 through the first connection line 1211, and the second main line 1222 is driven to the second pixel through the second connection line 1221.
  • the circuit 112 is electrically connected.
  • the first main lines 1212 and the second traces are arranged along a first direction, and the first direction is parallel to the trace direction of the scan lines in the array substrate 100.
  • the first electrode trace 121 and the second electrode trace 122 have the same shape.
  • the shapes of the first main line 1212 and the second main line 1222 include, but are not limited to, wavy, zigzag, and long.
  • the shapes of the first electrode trace 121 and the second electrode trace 122 can be flexibly set according to actual requirements.
  • the pitches of the main lines (including the first main line 1212 and the second main line 1222) in the first transparent electrode 12 are the same.
  • the distance between the main lines (including the first main line 1212 and the second main line 1222) in the first transparent electrode 12 is different.
  • the first electrode traces 121 and the second electrode traces 122 are alternately arranged.
  • the control effect of the first electrode trace 121 or the second electrode trace 122 on the liquid crystal deflection can be improved.
  • the first electrode trace 121 is located on one side of the second electrode trace 122. That is, the first electrode trace 121 and the second electrode trace 122 are respectively located in different areas in the pixel unit 10. Therefore, the problem that the arrangement of the electrode wiring in the array substrate 100 is complicated, resulting in a greatly increased difficulty in the related manufacturing process.
  • the array substrate 100 uses gate drive integration technology (Gate Driven on Array, GOA).
  • GOA Gate Driven on Array
  • the array substrate 100 further includes a driving circuit for providing row-driven scanning signals
  • the first pixel driving circuit 111 and the second pixel driving circuit 112 are connected to the same-level row driving scanning signal line.
  • FIG. 3 is a schematic structural diagram of an array substrate 100 according to a third embodiment of the present application.
  • the array substrate 100 includes a substrate 17, a thin film transistor array, a planarization layer 13, a second transparent electrode layer 14, an interlayer dielectric layer 15 and a first transparent electrode layer in this order.
  • the substrate 17 is one of a flexible substrate and a rigid liner.
  • the thin film transistor array provided on the substrate 17 includes a first thin film transistor 21 and a second thin film transistor 22.
  • the first thin film transistor 21 includes a first active layer 212, a first gate 211, a first source 213, and a first drain 214.
  • the second thin film transistor 22 includes a first active layer 222, a second gate 221, a first source 223, and a second drain 224.
  • the source 213 (214) of the first thin film transistor 21 is shared with the second thin film transistor 22, so that the data received by the first electrode trace 121 and the second electrode trace 122 The signal is the same.
  • the first transparent electrode layer includes a plurality of first transparent electrodes 12, and each of the first transparent electrodes 12 belongs to one pixel unit 10.
  • the first transparent electrode layer and the second transparent electrode layer 14 are insulated from each other by the interlayer dielectric layer 15.
  • the interlayer dielectric layer 15 is relatively thin, and a break point is likely to occur to cause a short circuit between the first transparent electrode layer and the second electrode layer, and this application can effectively solve this problem.
  • the first electrode trace 121 is electrically connected to the first drain 21 of the first thin film transistor 21 through the first via 161, and the second electrode trace 122 passes through the second The hole 162 is electrically connected to the second drain of the second thin film transistor 22;
  • the first source electrode 213 of the first thin film transistor 21 is shared with the second source electrode 223 of the second thin film transistor 22, so that the data received by the first electrode trace 121 and the second electrode trace 122 The signal is the same.
  • first via 161 and the second via 162 both penetrate the interlayer dielectric layer 15 and the planarization layer 13.
  • the number of the first electrode trace 121 and the second electrode trace 122 are the same.
  • the number of the first electrode trace 121 and the second electrode trace 122 are different.
  • a display panel including a color filter substrate, an array substrate 100, and a liquid crystal layer between the color filter substrate and the array substrate 100;
  • the array substrate 100 includes a plurality of pixel units 10 distributed in an array.
  • the pixel unit 10 includes a first pixel driving circuit 111, a second pixel driving circuit 112, and a first transparent electrode 12 for driving the liquid crystal to turn over.
  • a transparent electrode 12 includes a first electrode trace 121 and a second electrode trace 122 insulated from each other;
  • first pixel driving circuit 111 and the first electrode trace 121 are electrically connected, and the second pixel driving circuit 112 and the second electrode trace 122 are electrically connected.
  • This application splits a pixel electrode into two sets of signal traces.
  • the two sets of signal traces are controlled by different pixel drive circuits. When one set of signal traces is short-circuited, the other set will still work normally. , Which in turn improves the yield of the product.

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  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本申请提出了一种阵列基板及显示面板。所述阵列基板包括多个像素单元。像素单元包括第一像素驱动电路、第二像素驱动电路以及用以驱动液晶翻转的第一透明电极。第一透明电极包括第一电极走线和第二电极走线。其中，第一像素驱动电路与第一电极走线与电连接，第二像素驱动电路与第二电极走线电连接。

Description

阵列基板及显示面板 技术领域
本申请涉及显示领域，特别涉及一种阵列基板及显示面板。
 背景技术
已知，液晶显示器包括显示面板与背光模组。显示面板由一彩膜基板、一阵列基板以及一设置于所述彩膜基板和所述阵列基板之间的液晶层构成。其工作原理是通过施加驱动电压来控制液晶层的液晶分子旋转，将背光模组的光线折射出来产生画面。
阵列基板采用薄膜晶体管(Thin Film Transistor，TFT)等半导体器件作为像素单元是否接收图像数据的开关元件。现有的像素单元内，一个像素电极由一个像素驱动电路控制，当像素电极内的某一电极线与公共电极在某一点发生短路后会造成整个像素单元产生暗点，导致产品显示不良。
因此，目前亟需一种阵列基板及显示面板以解决上述问题。
 技术问题
本申请提供了一种阵列基板及显示面板，以解决像素单元内像素电极和公共电极在某一点发生短路后，像素单元显示不良的问题。
 技术解决方案
根据本申请的一个方面，提供了一种阵列基板，所述阵列基板包括多个阵列分布的像素单元，所述像素单元包括第一像素驱动电路、第二像素驱动电路以及用以驱动液晶翻转的第一透明电极，所述第一透明电极包括相互绝缘的第一电极走线和第二电极走线；
其中，所述第一像素驱动电路与所述第一电极走线与电连接，所述第二像素驱动电路与所述第二电极走线电连接。
根据本申请一实施例，所述第一电极走线包括第一主线以及位于所述第一主线一端的第一连接线，所述第二电极走线包括第二主线以及位于所述第二主线一端的第二连接线；
其中，所述第一主线通过所述第一连接线与所述第一像素驱动电路电连接，所述第二主线通过所述第二连接线与所述第二像素驱动电路电连接。
根据本申请一实施例，所述第一电极走线和所述第二电极走线交替排列。
根据本申请一实施例，所述第一电极走线位于所述第二电极走线的一侧。
根据本申请一实施例，所述第一像素驱动电路至少包括一个第一薄膜晶体管，所述第二像素电路至少包括一个第二薄膜晶体管；
其中，所述第一薄膜晶体管和所述第二薄膜晶体管分别位于所述第一透明电极的两侧。
根据本申请一实施例，所述阵列基板还包括用以提供行驱动扫描信号的驱动电路；
所述第一像素驱动电路和所述第二像素驱动电路连接同一级行驱动扫描信号线。
根据本申请一实施例，所述阵列基板包括：
衬底；
设置在所述衬底上的薄膜晶体管阵列，所述薄膜晶体管阵列包括第一薄膜晶体管和第二薄膜晶体管；
设置在所述薄膜晶体管阵列上的平坦化层；
设置在所述平坦化层上的第二透明电极层；
设置在所述第二透明电极层上的层间介质层；
设置在所述层间介质层上的第一透明电极层，所述第一透明电极层包括所述第一透明电极；
其中，所述第一电极走线通过第一过孔与所述第一薄膜晶体管的第一漏极电连接，所述第二电极走线通过第二过孔与所述第二薄膜晶体管的第二漏极电连接。
根据本申请一实施例，所述第一过孔和第二过孔均贯穿所述层间介质层和所述平坦化层。
根据本申请一实施例，所述第一电极走线和所述第二电极走线的数目相同。
根据本申请一实施例，所述像素单元为红色像素单元、绿色像素单元和蓝色像素单元中的其中一者。
根据本申请的另一个方面，还提供了一种显示面板，包括彩膜基板、阵列基板以及位于所述彩膜基板和所述阵列基板之间的液晶层；
所述阵列基板包括多个阵列分布的像素单元，所述像素单元包括第一像素驱动电路、第二像素驱动电路以及用以驱动液晶翻转的第一透明电极，所述第一透明电极包括相互绝缘的第一电极走线和第二电极走线；
其中，所述第一像素驱动电路与所述第一电极走线与电连接，所述第二像素驱动电路与所述第二电极走线电连接。
根据本申请一实施例，所述第一电极走线包括第一主线以及位于所述第一主线一端的第一连接线，所述第二电极走线包括第二主线以及位于所述第二主线一端的第二连接线；
其中，所述第一主线通过所述第一连接线与所述第一像素驱动电路电连接，所述第二主线通过所述第二连接线与所述第二像素驱动电路电连接。
根据本申请一实施例，所述第一电极走线和所述第二电极走线交替排列。
根据本申请一实施例，所述第一电极走线位于所述第二电极走线的一侧。
根据本申请一实施例，所述第一像素驱动电路至少包括一个第一薄膜晶体管，所述第二像素电路至少包括一个第二薄膜晶体管；
其中，所述第一薄膜晶体管和所述第二薄膜晶体管分别位于所述第一透明电极的两侧。
根据本申请一实施例，所述阵列基板还包括用以提供行驱动扫描信号的驱动电路；
所述第一像素驱动电路和所述第二像素驱动电路连接同一级行驱动扫描信号线。
根据本申请一实施例，所述阵列基板包括：
衬底；
设置在所述衬底上的薄膜晶体管阵列，所述薄膜晶体管阵列包括第一薄膜晶体管和第二薄膜晶体管；
设置在所述薄膜晶体管阵列上的平坦化层；
设置在所述平坦化层上的第二透明电极层；
设置在所述第二透明电极层上的层间介质层；
设置在所述层间介质层上的第一透明电极层，所述第一透明电极层包括所述第一透明电极；
其中，所述第一电极走线通过第一过孔与所述第一薄膜晶体管的第一漏极电连接，所述第二电极走线通过第二过孔与所述第二薄膜晶体管的第二漏极电连接。
根据本申请一实施例，所述第一过孔和第二过孔均贯穿所述层间介质层和所述平坦化层。
根据本申请一实施例，所述第一电极走线和所述第二电极走线的数目相同。
根据本申请一实施例，所述像素单元为红色像素单元、绿色像素单元和蓝色像素单元中的其中一者。
 有益效果
本申请通过将一个像素电极拆分为两组信号走线，两组信号走线分别采用不同的像素驱动电路控制，当一组信号走线发生短路时，另一组仍会正常工作，进而提升了产品的良率。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请第一实施例提供的阵列基板的结构示意图；
图2为本申请第二实施例提供的像素单元的结构示意图；
图3为本申请第三实施例提供的阵列基板的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请提供了一种阵列基板及显示面板，以解决像素单元内像素电极和公共电极在某一点发生短路后，像素单元显示不良的问题。
请参阅图1，图1为本申请第一实施例提供的阵列基板100的结构示意图。
请参阅图2，图2为本申请第二实施例提供的像素单元10的结构示意图。
根据本申请的一个方面，提供了一种阵列基板100，所述阵列基板100包括多个阵列分布的像素单元10。
在一种实施例中，所述像素单元10可以为红色像素单元、绿色像素单元和蓝色像素单元中的其中一者。
所述像素单元10包括第一像素驱动电路111、第二像素驱动电路112以及用以驱动液晶翻转的第一透明电极12，所述第一透明电极12包括相互绝缘的第一电极走线121和第二电极走线122。
阵列基板100采用薄膜晶体管等半导体器件作为像素单元10是否接收图像数据的开关元件。与现有结构中一个像素单元10设置一个像素驱动电路不同的是，本申请采用一个像素单元10设置两个像素驱动电路，并将原有的一个像素电极（即本申请中的第一透明电极12）划分为第一电极走线121和第二电极走线122以进行分别控制，进而防止某一电极走线发生短路导致像素单元10发生暗点的现象。
其中，所述像素驱动电路111与所述第一电极走线121与电连接，所述第二像素驱动电路112与所述第二电极走线122电连接。
在一种实施例中，所述第一像素驱动电路111至少包括一个第一薄膜晶体管21，所述第二像素驱动电路112至少包括一个第二薄膜晶体管22；
其中，所述第一薄膜晶体管21和所述第二薄膜晶体管22分别位于所述第一透明电极12的两侧。从而避免两者之间产生相互干扰的问题。
在一种实施例中，所述第一像素驱动电路111包括一个第一薄膜晶体管21，所述第二像素驱动电路112包括一个第二薄膜晶体管22。
在一种实施例中，第一透明电极12并不仅限于划分为第一电极走线121和第二电极走线122，也可以划分为n种电极走线（n为不小于2的正整数），其中每种电极走线设置单独的像素驱动电路与其对应，进而防止某一电极走线发生短路导致像素单元10发生暗点的现象。
由于一个第一透明电极12划分为两种电极走线利于像素驱动电路的排布，且能避免过多的像素驱动电路导致产品走线复杂，因此下面主要以一个像素电极划分为两种电极走线为例进行说明。
在一种实施例中，所述第一电极走线121之间相互电连接，所述第二电极走线122走线相互电连接。即所述第一电极走线121和所述第二电极走线122归属于不同的信号电路，从而避免其中一者的不良导致对另外一者的干扰。
在一种实施例中，所述第一电极走线121包括第一主线1212以及位于所述第一主线1212一端的第一连接线1211，所述第二电极走线122包括第二主线1222以及位于所述第二主线1222一端的第二连接线1221；
其中，所述第一主线1212通过所述第一连接线1211与所述第一像素驱动电路111管电连接，所述第二主线1222通过所述第二连接线1221与所述第二像素驱动电路112电连接。
在一种实施例中，所述第一主线1212和所述第二走线沿第一方向排布，所述第一方向平行于阵列基板100中扫面线的走线方向。
在一种实施例中，所述第一电极走线121和所述第二电极走线122的形状相同。
在一种实施例中，所述第一主线1212和所述第二主线1222的形状包括但不仅限于波浪状、折线状和长条状。所述第一电极走线121和所述第二电极走线122的形状可根据实际需求进行灵活设置。
在一种实施例中，所述第一透明电极12中主线（包括第一主线1212和第二主线1222）的间距相同。
在一种实施例中，所述第一透明电极12中主线（包括第一主线1212走线和第二主线1222）的间距不同。
在一种实施例中，所述第一电极走线121和所述第二电极走线122交替排列。通过设置所述第一电极走线121和所述第二电极走线122交替排列，能够提升第一电极走线121或第二电极走线122对液晶偏转的控制效果。
在一种实施例中，所述第一电极走线121位于所述第二电极走线122的一侧。即所述第一电极走线121和所述第二电极走线122分别位于像素单元10内的不同区域。从而避免在阵列基板100中由于电极走线排布复杂，导致相关制程难度大大增加的问题。
在一种实施例中，所述阵列基板100采用栅驱动集成技术（Gate Driven on Array，GOA）。
在一种实施例中，所述阵列基板100还包括用以提供行驱动扫描信号的驱动电路；
所述第一像素驱动电路111和所述第二像素驱动电路112连接同一级行驱动扫描信号线。
请参阅图3，图3为本申请第三实施例提供的阵列基板100的结构示意图。
在一种实施例中，所述阵列基板100包括依次衬底17、薄膜晶体管阵列、平坦化层13、第二透明电极层14、层间介质层15和第一透明电极层。
在一种实施例中，所述衬底17为柔性衬底和刚性衬中的其中一者。
设置在所述衬底17上的所述薄膜晶体管阵列包括第一薄膜晶体管21和第二薄膜晶体管22。
在一种实施例中，所述第一薄膜晶体管21包括第一有源层212，第一栅极211，第一源极213和第一漏极214。
在一种实施例中，所述第二薄膜晶体管22包括第一有源层222，第二栅极221，第一源极223和第二漏极224。
在一种实施例中，所述第一薄膜晶体管21的源极213（214）与所述第二薄膜晶体管22共用，使得所述第一电极走线121和第二电极走线122接收的数据信号相同。
所述第一透明电极层包括多个第一透明电极12，每个所述第一透明电极12归属于一个所述像素单元10。
在一种实施例中，所述第一透明电极层和所述第二透明电极层14通过所述层间介质层15相互绝缘。在现有结构中，层间介质层15相对较薄，容易发生断点造成第一透明电极层和第二电极层短路，本申请能够有效解决这一问题。
在一种实施例中，所述第一电极走线121通过第一过孔161与所述第一薄膜晶体管21的第一漏极21电连接，所述第二电极走线122通过第二过孔162与所述第二薄膜晶体管22的第二漏极电连接；
其中，所述第一薄膜晶体管21的第一源极213与所述第二薄膜晶体管22的第二源极223共用，使得所述第一电极走线121和第二电极走线122接收的数据信号相同。
在一种实施例中，所述第一过孔161和第二过孔162均贯穿所述层间介质层15和所述平坦化层13。
在一种实施例中，所述第一电极走线121和所述第二电极走线122的数目相同。
在一种实施例中，所述第一电极走线121和所述第二电极走线122的数目不同。
根据本发明的另一种方面，还提供了一种显示面板，包括彩膜基板、阵列基板100以及位于所述彩膜基板和所述阵列基板100之间的液晶层；
所述阵列基板100包括多个阵列分布的像素单元10，所述像素单元10包括第一像素驱动电路111、第二像素驱动电路112以及用以驱动液晶翻转的第一透明电极12，所述第一透明电极12包括相互绝缘的第一电极走线121和第二电极走线122；
其中，所述第一像素驱动电路111与所述第一电极走线121与电连接，所述第二像素驱动电路112与所述第二电极走线122电连接。
有益效果：本申请通过将一个像素电极拆分为两组信号走线，两组信号走线分别采用不同的像素驱动电路控制，当一组信号走线发生短路时，另一组仍会正常工作，进而提升了产品的良率。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板，其包括多个阵列分布的像素单元，所述像素单元包括第一像素驱动电路、第二像素驱动电路以及用以驱动液晶翻转的第一透明电极，所述第一透明电极包括相互绝缘的第一电极走线和第二电极走线；
    其中，所述第一像素驱动电路与所述第一电极走线与电连接，所述第二像素区域电路与所述第二电极走线电连接。
  2. 根据权利要求1所述的阵列基板，其中，所述第一电极走线包括第一主线以及位于所述第一主线一端的第一连接线，所述第二电极走线包括第二主线以及位于所述第二主线一端的第二连接线；
    其中，所述第一主线通过所述第一连接线与所述第一像素驱动电路电连接，所述第二主线通过所述第二连接线与所述第二像素驱动电路电连接。
  3. 根据权利要求1所述的阵列基板，其中，所述第一电极走线和所述第二电极走线交替排列。
  4. 根据权利要求1所述的阵列基板，其中，所述第一电极走线位于所述第二电极走线的一侧。
  5. 根据权利要求1所述的阵列基板，其中，所述第一像素驱动电路至少包括一个第一薄膜晶体管，所述第二像素电路至少包括一个第二薄膜晶体管；
    其中，所述第一薄膜晶体管和所述第二薄膜晶体管分别位于所述第一透明电极的两侧。
  6. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括用以提供行驱动扫描信号的驱动电路；
    所述第一像素驱动电路和所述第二像素驱动电路连接同一级行驱动扫描信号线。
  7. 根据权利要求5所述的阵列基板，其中，包括：
    衬底；
    设置在所述衬底上的薄膜晶体管阵列，所述薄膜晶体管阵列包括第一薄膜晶体管和第二薄膜晶体管；
    设置在所述薄膜晶体管阵列上的平坦化层；
    设置在所述平坦化层上的第二透明电极层；
    设置在所述第二透明电极层上的层间介质层；
    设置在所述层间介质层上的第一透明电极层，所述第一透明电极层包括所述第一透明电极；
    其中，所述第一电极走线通过第一过孔与所述第一薄膜晶体管的第一漏极电连接，所述第二电极走线通过第二过孔与所述第二薄膜晶体管的第二漏极电连接。
  8. 根据权利要求7所述的阵列基板，其中，所述第一过孔和第二过孔均贯穿所述层间介质层和所述平坦化层。
  9. 根据权利要求1所述的阵列基板，其中，所述第一电极走线和所述第二电极走线的数目相同。
  10. 根据权利要求1所述的阵列基板，其特征在于，所述像素单元为红色像素单元、绿色像素单元和蓝色像素单元中的其中一者。
  11. 一种显示面板，其包括彩膜基板、阵列基板以及位于所述彩膜基板和所述阵列基板之间的液晶层；
    所述阵列基板包括多个阵列分布的像素单元，所述像素单元包括第一像素驱动电路、第二像素驱动电路以及用以驱动液晶翻转的第一透明电极，所述第一透明电极包括相互绝缘的第一电极走线和第二电极走线；
    其中，所述第一像素驱动电路与所述第一电极走线与电连接，所述第二像素区域电路与所述第二电极走线电连接。
  12. 根据权利要求11所述的显示面板，其中，所述第一电极走线包括第一主线以及位于所述第一主线一端的第一连接线，所述第二电极走线包括第二主线以及位于所述第二主线一端的第二连接线；
    其中，所述第一主线通过所述第一连接线与所述第一像素驱动电路电连接，所述第二主线通过所述第二连接线与所述第二像素驱动电路电连接。
  13. 根据权利要求11所述的显示面板，其中，所述第一电极走线和所述第二电极走线交替排列。
  14. 根据权利要求11所述的显示面板，其中，所述第一电极走线位于所述第二电极走线的一侧。
  15. 根据权利要求11所述的显示面板，其中，所述第一像素驱动电路至少包括一个第一薄膜晶体管，所述第二像素电路至少包括一个第二薄膜晶体管；
    其中，所述第一薄膜晶体管和所述第二薄膜晶体管分别位于所述第一透明电极的两侧。
  16. 根据权利要求11所述的显示面板，其中，所述阵列基板还包括用以提供行驱动扫描信号的驱动电路；
    所述第一像素驱动电路和所述第二像素驱动电路连接同一级行驱动扫描信号线。
  17. 根据权利要求15所述的显示面板，其中，包括：
    衬底；
    设置在所述衬底上的薄膜晶体管阵列，所述薄膜晶体管阵列包括第一薄膜晶体管和第二薄膜晶体管；
    设置在所述薄膜晶体管阵列上的平坦化层；
    设置在所述平坦化层上的第二透明电极层；
    设置在所述第二透明电极层上的层间介质层；
    设置在所述层间介质层上的第一透明电极层，所述第一透明电极层包括所述第一透明电极；
    其中，所述第一电极走线通过第一过孔与所述第一薄膜晶体管的第一漏极电连接，所述第二电极走线通过第二过孔与所述第二薄膜晶体管的第二漏极电连接。
  18. 根据权利要求17所述的显示面板，其中，所述第一过孔和第二过孔均贯穿所述层间介质层和所述平坦化层。
  19. 根据权利要求11所述的显示面板，其中，所述第一电极走线和所述第二电极走线的数目相同。
  20. 根据权利要求11所述的显示面板，其中，所述像素单元为红色像素单元、绿色像素单元和蓝色像素单元中的其中一者。
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