WO2019071815A1 - 阵列基板及其应用的显示面板 - Google Patents

阵列基板及其应用的显示面板 Download PDF

Info

Publication number
WO2019071815A1
WO2019071815A1 PCT/CN2017/117080 CN2017117080W WO2019071815A1 WO 2019071815 A1 WO2019071815 A1 WO 2019071815A1 CN 2017117080 W CN2017117080 W CN 2017117080W WO 2019071815 A1 WO2019071815 A1 WO 2019071815A1
Authority
WO
WIPO (PCT)
Prior art keywords
line
jumper
pixel
groups
lines
Prior art date
Application number
PCT/CN2017/117080
Other languages
English (en)
French (fr)
Inventor
李泽尧
Original Assignee
惠科股份有限公司
重庆惠科金渝光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 惠科股份有限公司, 重庆惠科金渝光电科技有限公司 filed Critical 惠科股份有限公司
Priority to US15/745,548 priority Critical patent/US10593707B2/en
Publication of WO2019071815A1 publication Critical patent/WO2019071815A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the present application relates to the field of wiring technologies, and in particular, to an array substrate and a display panel thereof.
  • Liquid crystal display devices display images using the electrical and optical properties of liquid crystals.
  • the liquid crystal has anisotropy, for example, a difference in refractive index and dielectric constant between the major axis and the minor axis of the molecule.
  • the molecular arrangement and optical properties of the liquid crystal are easily adjustable.
  • the liquid crystal display device displays an image by changing the arrangement direction of the liquid crystal molecules according to the magnitude of the electric field to adjust the transmittance of light transmitted through the polarizing plate.
  • the liquid crystal display device includes a liquid crystal panel and a driving circuit, wherein a plurality of pixels are arranged in a matrix form, the driving circuit includes a gate driver for driving a gate line of the liquid crystal panel, and a data line for driving the liquid crystal panel Data drive.
  • the driving circuit includes a gate driver for driving a gate line of the liquid crystal panel, and a data line for driving the liquid crystal panel Data drive.
  • the left and right adjacent sub-pixels of the half source driving (HSD) pixel array share one data line. This halved the number of data lines relative to the number of data lines of a conventional liquid crystal driven pixel array, reducing production costs. However, since the time at which the gate signal is turned on is halved, the charging time of the data line to the pixel is only one-half of the normal structure, which tends to cause insufficient charging of the pixel.
  • the AC drive mode adopted by many products is a 2-point inversion.
  • Column 2 dot inversion is a combination of column inversion and dot inversion, which is represented by positive and negative polarity inversion in two sub-pixels (2 points) on each column, and adjacent two columns of sub-pixels in column units. Positive and negative polarity reversal.
  • the data drive IC reverses the drive signal voltage in units of two addressing times (2Hsync cycles).
  • the waveform frequency is between dot inversion and column inversion, so its power consumption is much lower. Inverted at the point.
  • an object of the present application is to provide an array substrate and a display panel thereof, and adjust the signal receiving sequence of the display area line by the cross-line design.
  • An array substrate includes: a substrate including a display area and a peripheral wiring area thereof, wherein a plurality of active switches, a plurality of pixel units, and a plurality of signal lines are disposed in the display area, The plurality of pixel units are respectively coupled to the plurality of active switches, and the plurality of active switches are electrically coupled to the plurality of signal lines respectively, wherein the plurality of signal lines comprise a plurality of gate lines and a plurality of sources
  • Each of the pixel units includes a first sub-pixel and a second sub-pixel, and the first sub-pixel and the second sub-pixel are electrically coupled to different gate lines through respective active switches, and The same source line is coupled to the same, the plurality of input interfaces of the plurality of gate lines are disposed in the wiring area; the gate driving module is disposed in the wiring area, and the gate driving module includes multiple outputs And a plurality of connection lines
  • each jumper set includes a jumper wire and a flat wire
  • the flat wire is a fold line, a straight line, a curve, or a diagonal line.
  • the plurality of jumper groups include at least one of a two line combination, a three line combination, and a four line combination.
  • the gate driving module outputs a control signal through the plurality of output interfaces in a first order, and the control signal receiving order of the plurality of input interfaces is input in a second order. And wherein the plurality of connection lines acquire the control signal from the plurality of output interfaces in the first order, and output the control signal to the plurality of input interfaces in the second sequence.
  • the first sequence is the same as the line arrangement order of the plurality of output interfaces.
  • the gate driving module includes a gate flip-chip film overlying an edge of the substrate, and the gate flip chip includes the plurality of output interfaces.
  • the plurality of connection lines are disposed in a fan-out area of the wiring area.
  • the plurality of pairs of wiring groups and the plurality of jumper groups are alternately arranged in an adjacent manner, or the plurality of pairs of wiring groups are continuous or partially continuous. The way to interact with the plurality of jumper groups.
  • the second object of the present application is an array substrate, comprising: a substrate, a wiring area including a display area and a periphery thereof, a plurality of active switches, a plurality of pixel units, and a plurality of signal lines disposed on the display area,
  • the plurality of pixel units are respectively coupled to the plurality of active switches, and the plurality of active switches are electrically coupled to the plurality of signal lines respectively, wherein the plurality of signal lines comprise a plurality of gate lines and a plurality of source lines a line, each of the pixel units includes a first sub-pixel and a second sub-pixel, wherein the first sub-pixel and the second sub-pixel are electrically coupled to different gate lines through respective active switches, and electrical Coupling the same source line, a plurality of input interfaces of the plurality of gate lines are disposed in the wiring area, the plurality of input interfaces include a first input interface and a second input interface; a gate driving module, setting In the routing area, the gate driving module includes
  • the second object of the present application is a display panel comprising: an opposite substrate; and an array substrate disposed opposite to the opposite substrate; wherein the array substrate comprises the technical features of any of the above embodiments Array substrate.
  • the application can not significantly change the premise of the existing production process, and can maintain the original process requirements and product costs.
  • the wiring design can change the control signal receiving sequence of the display area, and adjust the signal receiving order to adjust the pole of the pixel unit.
  • the purpose of sex is to slow down the problem of bright and dark lines on the display.
  • this is the control signal receiving sequence that can change the display area through the wiring design. Therefore, the signal output order of the driving components (such as the driving IC and the driving chip) is not particularly adjusted, and the component adjustment cost can be relatively reduced.
  • this is a control signal receiving sequence that can change the display area by wiring design, so it can be applied to many types of display panels, and the applicability is relatively high.
  • FIG. 1a is a schematic diagram of the architecture of an exemplary display device.
  • Figure 1b is a schematic diagram of the wiring of the fan-out area of an exemplary display device.
  • Figure 1c is a schematic illustration of the polarity of a pixel unit of an exemplary display device.
  • 2a is a schematic diagram showing the wiring of a display panel according to an embodiment of the method of the present application.
  • 2b is a schematic diagram showing the wiring of a display panel according to an embodiment of the method of the present application.
  • 2c is a schematic diagram showing the pixel polarity of a half-source driven display panel according to an embodiment of the present application.
  • 2d is a schematic diagram showing the wiring of a display panel according to an embodiment of the method of the present application.
  • the word “comprising” is to be understood to include the component, but does not exclude any other component.
  • “on” means located above or below the target component, and does not mean that it must be on the top based on the direction of gravity.
  • FIG. 1a is a schematic diagram of the architecture of an exemplary display device.
  • a liquid crystal display includes: a control board 100, the control board 100 includes a Timing Controller (TCON) 101, and a printed circuit board 103, and a flexible flat cable is passed between the control board ( The flexible flat cable (FFC) 102 is connected; the source flip chip 104 and the gate flip chip 105 are respectively connected to the data lines and the scanning lines in the display area 106.
  • TCON Timing Controller
  • FFC Flexible flat cable
  • the driving manner of the display device includes: the system motherboard provides color (eg, R/G/B) compression signals, control signals, and power transmission to the control board 100.
  • the sequence controller 101 on the control board 100 processes the signals, and together with the power source processed by the driving circuit, is transmitted to the source circuit of the printed circuit board 103 through a flexible flat cable (FFC) 102, for example.
  • the gate circuit transmits the necessary data and power to the display area 106 through the source flip chip 104 and the gate flip chip 105, thereby enabling the display to obtain power and signals for presenting the picture.
  • FIG. 1b is a schematic diagram of the wiring of the fan-out area of an exemplary display device.
  • the flip chip is provided with a corresponding integrated circuit (IC).
  • the channels of the integrated circuit are substantially connected to the conductive lines of the display region 106 according to their order.
  • the connected conductive lines are also different.
  • the gate integrated circuit is connected to a scan line (gate line), such as a source integrated circuit that is connected to a data line (source line).
  • the channel arrangement order of the gate integrated circuit 107 is g1 to gn, and the signal output order of the gate integrated circuit is also adjusted as in the channel signal output order.
  • FIG. 1c is a schematic diagram of pixel arrangement of a semi-source driven display panel, which is shown in conjunction with FIG. 1a and FIG. 1b for understanding.
  • the display area 106 includes a plurality of active switches and a plurality of pixel units.
  • the pixel unit is electrically coupled to the active switch, and the active switch is electrically coupled to the scan line and the data line.
  • Each pixel unit is composed of a first sub-pixel and a second sub-pixel of different colors, but the different scan lines are connected by an active switch, but the connections share the same data line.
  • the pixel unit on the scan line D1 the first sub-pixel and the second sub-pixel are respectively connected to the scan line G1 and the scan line G2 through an active switch, but share one data line D1.
  • the number of data lines is reduced by about half compared with the conventional display panel, but the time for turning on the gate signal of the scan lines is halved, so the charging time of the data lines to the pixels is only two points of the conventional structure. one.
  • the display panel is a column 2 dot inversion driving method.
  • Column 2 dot inversion is a combination of column inversion and dot inversion, which is represented by positive and negative polarity inversion in two sub-pixels (2 points) on each column, and adjacent two columns of sub-pixels in column units. Positive and negative polarity reversal.
  • FIG. 1c when the column 2-point inversion is applied to the half-source driving pixel array, since the time of turning on the gate signal is halved, the charging time of the data line to the pixel is only one-half of the conventional structure, which easily leads to the pixel. Insufficient charge.
  • the delay of the data signal reaching the adjacent pixels is greatly different.
  • the sub-pixels located in the subsequent charging may have insufficient charging, thus causing the phase.
  • There is a difference in the brightness of the adjacent pixels causing a problem of vertical bright lines on the display, which affects the display quality, especially at low gray levels.
  • the array substrate 200 includes a substrate 201, a display area 106 and a peripheral wiring area 108 thereof, a plurality of active switches, a plurality of pixel units, and a plurality of strips.
  • the signal lines are disposed on the display area 106, the plurality of pixel units are respectively coupled to the plurality of active switches, and the plurality of active switches are electrically coupled to the plurality of signal lines, respectively, the plurality of signals
  • the line includes a plurality of gate lines 210 and a plurality of source lines, each of the pixel units includes a first sub-pixel and a second sub-pixel, and the first sub-pixel and the second sub-pixel pass corresponding active switching
  • the plurality of input lines 211 of the plurality of gate lines 210 are disposed in the wiring area 108; the gate driving module 220 is electrically coupled to the same source line.
  • the gate driving module 220 includes a plurality of output interfaces 222.
  • the plurality of connection lines 230 are disposed between the plurality of input interfaces 211 and the plurality of output interfaces 222.
  • the plurality of input interfaces 211 and the plurality of output interfaces 222 sexually coupled; wherein the plurality of connection lines 230 include a plurality of pairs of wiring groups 231 and a plurality of jumper groups 232, the plurality of pairs of wiring groups 231 are alternately disposed with the plurality of jumper groups 232,
  • the signal output order of the plurality of jumper groups 232 is different from the signal output order of the plurality of pairs of wiring groups 231.
  • each of the plurality of jumper sets 232 includes a jumper wire and a flat wire, the flat wire being a fold line, a straight line, a curve, or a diagonal line.
  • the gate driving module 220 outputs control signals through the plurality of output interfaces 222 in a first order, and the control signal receiving order of the plurality of input interfaces 211 is input in a second order.
  • the plurality of connection lines 230 obtain the control signals from the plurality of output interfaces 222 in the first order, and output the control signals to the plurality of input interfaces 211 in the second order.
  • the first order is different, identical, or partially identical to the line arrangement order of the plurality of output interfaces 222.
  • the jumper set 232 includes a two-line combination.
  • the two line combination includes a first line 232a and a second line 232b.
  • the second line 232b is disposed in a fold line manner, and the first line 232a is disposed in a cross-line manner.
  • the first line 232a is connected between the output interface g1 and the input interface G2, and the second line 232b is connected between the output interface g2 and the input interface G1. It is assumed that the order of the control signals passing through the output interface is (g1->g2), and the order in which the control signals reach the input interface is (G2->G1).
  • FIG. 2b is a schematic diagram showing the wiring of the display panel according to an embodiment of the method according to the present application.
  • the pair of wiring groups 231 are two-line arrangement
  • the jumper group 232 is also a two-line combination, which are mutually arranged in a manner that the adjacent line groups are different.
  • the first sequence is the same as the line arrangement order of the plurality of output interfaces 222, that is, the order in which the gate driving module 220 outputs a control signal is (g1->g8), and the plurality of input interfaces 211 obtain control.
  • the order of the signals is (G1->G2->G4->G3->G5->G6->G8->G7).
  • the plurality of pairs of wiring sets 231 are interactively disposed with the plurality of jumper sets 232 in a continuous or partially continuous manner.
  • FIG. 2c is a schematic diagram showing the pixel polarity of a half-source driven display panel according to an embodiment of the present application.
  • Each pixel unit is composed of a first sub-pixel and a second sub-pixel of different colors, but the different scan lines are connected by corresponding active switches, but the connections share the same data line.
  • the pixel unit on the scan line D1 the first sub-pixel and the second sub-pixel are respectively connected to the scan line G1 and the scan line G2 through an active switch, but share one data line D1, and all pixel units are set in this manner. .
  • the control signals are obtained in reverse order, and the subsequent lines operate in the same manner.
  • the G2n+1 line and the G2n+2 line will obtain control signals in reverse order. That is, the charging order of the pixel unit connected to the G2n+1 line and the G2n+2 line is opposite to the charging order of the pixel unit connected to the G2n-1 line and the 2nth line. .
  • the column 2-point inversion is applied to the entire column of the half-source driving pixels, since the polarity of the two points of the adjacent pixels of the same row is the same, the problem that the delay of the data signal reaching the adjacent pixels greatly differs, but the problem still exists.
  • the pixel units with insufficient charging can be staggered and dispersed, and the vertical bright and dark lines are reduced to improve the display uniformity of the display panel.
  • the first sequence is different from the line arrangement order of the plurality of output interfaces 222.
  • the order in which the gate driving module 220 outputs the control signals is (g1->g2->g4-> G3->g6->g5->g7->g8).
  • the pair of wiring groups 231 and the jumper group 232 are disposed in two lines, and are selectively arranged alternately with each other.
  • a pair connection group 231 is disposed between the output interface (g3, g4) and the input interface (G3, G4), and the output interface (g5, g6) and the input interface (G5, G6)
  • the jumper group 232 is disposed between the two, so that the order in which the plurality of input interfaces 211 obtain the control signals can be maintained as (G1->G2->G4->G3->G5->G6->G8->G7) .
  • the jumper group 232 and the pair of wiring groups 231 are appropriately set to make the g2n+1
  • the charging sequence of the pixel unit connected to the strip line and the g2n+2 lines is opposite to the charging order of the pixel unit connected to the g2n-1 line and the 2nth line.
  • the jumper set 232 includes at least one of a two line combination, a three line combination, and a four line combination.
  • the gate driving module 220 includes a gate flip chip 105 overlying an edge of the substrate 201 , and the gate flip chip 105 includes the plurality of output interfaces 221 .
  • the plurality of connection lines 230 are disposed in a fan-out area of the wiring area 108.
  • an array substrate 200 of the present application includes: a substrate 201, a wiring area 108 including a display area 106 and its periphery, a plurality of active switches, a plurality of pixel units, and a plurality of signal line settings.
  • the plurality of pixel units are respectively coupled to the plurality of active switches, and the plurality of active switches are electrically coupled to the plurality of signal lines respectively, and the plurality of signal lines include multiple a gate line 210 and a plurality of source lines, each of the pixel units comprising a first sub-pixel and a second sub-pixel, wherein the first sub-pixel and the second sub-pixel are electrically coupled by a corresponding active switch
  • the different gate lines 210 are electrically coupled to the same source lines
  • the plurality of input interfaces 211 of the plurality of gate lines 210 are disposed in the wiring area 106, and the plurality of input interfaces 211 include inputs.
  • the interface G1 and the input interface G2 are disposed in the routing area 108.
  • the gate driving module 220 includes a plurality of output interfaces 222.
  • the gate driving module 220 is configured according to the plurality of output interfaces 222.
  • the lines are arranged in order to output a control signal,
  • the plurality of output interfaces 222 include an output interface g1 and an output interface g2.
  • the plurality of connection lines 230 are disposed between the plurality of input interfaces 211 and the plurality of output interfaces 222, so that the plurality of input interfaces 211 are respectively The plurality of output interfaces 222 are electrically coupled to each other; wherein the plurality of connection lines 230 include a plurality of pairs of wiring groups 231 and a plurality of jumper groups 232, and the pair of wiring groups 231 interact with the jumper group 232
  • the jumper group 232 includes a two-line combination, the two-line combination includes a first line 232a and a second line 232b, and the first line 232a is connected between the output interface g1 and the input interface G2.
  • the second line 232b is connected between the output interface g2 and the input interface G1, the second line 232b is disposed in a fold line, a straight line, a curve or a diagonal line, and the first line 232a is arranged in an interline manner, the second line
  • the signal input sequence of the line combination is opposite to the signal output order, and the order in which the plurality of output interfaces 222 output the control signals is different from the order in which the plurality of input interfaces 211 receive the control signals.
  • a display panel of the present application includes: an array substrate and an opposite substrate disposed opposite to each other; wherein the array substrate includes any one of the array substrates 200 of the foregoing embodiments.
  • the array substrate further comprises any of the previously described embodiments.
  • the display panel of the present application may be, for example, a liquid crystal display panel, but is not limited thereto, and may also be an OLED display panel, a W-OLED display panel, a QLED display panel, a plasma display panel, and a curved surface. Display panel or other type of display panel.
  • the application can not significantly change the premise of the existing production process, and can maintain the original process requirements and product costs.
  • the wiring design can change the control signal receiving sequence of the display area, and adjust the signal receiving order to adjust the pole of the pixel unit.
  • the purpose of sex is to slow down the problem of bright and dark lines on the display.
  • this is the control signal receiving sequence that can change the display area through the wiring design. Therefore, the signal output order of the driving components (such as the driving IC and the driving chip) is not particularly adjusted, and the component adjustment cost can be relatively reduced.
  • this is a control signal receiving sequence that can change the display area by wiring design, so it can be applied to many types of display panels, and the applicability is relatively high.

Landscapes

  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板及其应用的显示面板。阵列基板包括：具有显示区（106）和布线区（108）的基板（201），多条信号线、多个主动开关和像素单元设置于显示区（106），多条信号线包括多条栅极线（210）与多条源极线，每一像素单元的两子像素通过相应主动开关分别电性耦接相异的栅极线（210）与相同的源极线，多条栅极线（210）的多个输入接口（211）设置于布线区（108）；栅极驱动模块（220），设置于布线区（108），包括多个输出接口（222）；多个连接线路（230），设置于多个输入接口（211）与多个输出接口（222）之间，使多个输入接口（211）分别与多个输出接口（222）电性耦接；其中，多个连接线路（230）包括对接线组（231）与跨接线组（232），对接线组（231）与跨接线组（232）交互设置，跨接线组（232）的信号输出顺序与对接线组（231）的信号输出顺序为相异。

Description

阵列基板及其应用的显示面板 技术领域
本申请涉及一种布线技术领域，特别涉及一种阵列基板及其应用的显示面板。
背景技术
液晶显示设备利用液晶的电气性质及光学性质显示影像。液晶具有各向异性，例如，在分子的主轴与次轴之间折射率及介电常数存在差异。液晶的分子排列与光学性质是可轻易调节的。液晶显示设备藉由根据电场的量级改变液晶分子的排列方向以调节透过偏光板的光的透射比，来显示影像。
液晶显示设备包括液晶面板以及驱动电路，于该液晶面板中复数个像素排列成矩阵的形式，该驱动电路包含用来驱动该液晶面板的闸线的闸驱动器以及用来驱动该液晶面板的数据线的数据驱动器。为了降低液晶显示设备的成本，已经考虑到藉由在维持液晶面板分辨率的同时降低数据线的数量来减少数据驱动器的输出信道数量。
半源极驱动(Half Source Driving，HSD)像素阵列的左右相邻亚像素共享一条数据线。这就使得数据线的数目相对于传统液晶驱动像素阵列的数据线数目减半，减少了生产成本。然而，由于栅极信号开启的时间减半，数据线对像素充电时间仅有正常结构的二分之一，容易导致像素充电不足。
另外，为了降低显示器的功耗，许多产品采用的交流驱动方式为列2点反转。列2点反转是列反转和点反转的合成，表现为在每一列上以两个子像素(2点)为单位正负极性反转，相邻的两列子像素则以列为单位正负极性反转。从驱动波形来看，数据驱动IC以两个寻址时间(2Hsync周期)为单位，反转驱动信号电压，波形频率介于点反转和列反转之间，所以其功耗会远远低于点反转。
当列2点反转应用到半源极驱动像素整列上时，由于同一行相邻像素2点的极性相同，数据信号在到达相邻像素的延迟存在很大差异，这就导致相邻像素的亮度会存在差异，在显示上引起垂直亮暗线的问题，从而影响了显示品质，特别是在低灰阶下这种现象尤为明显。
发明内容
为了解决上述技术问题，本申请的目的在于，提供一种阵列基板及其应用的显示面板，通过跨线设计，调整显示区线路的信号接收顺序。
本申请的目的及解决其技术问题是采用以下技术方案来实现的。依据本申请提出的一种阵列基板，所述阵列基板包括：基板，包括显示区及其外围的布线区，多个主动开关、多个像素单元和多 条信号线设置于所述显示区，所述多个像素单元分别耦接于所述多个主动开关，所述多个主动开关分别电性耦接所述多条信号线，所述多条信号线包括多条栅极线与多条源极线，每一像素单元包括第一子像素及第二子像素组成，所述第一子像素与所述第二子像素通过相应的主动开关电性耦接相异的栅极线，及电性耦接相同的源极线，所述多条栅极线的多个输入接口设置于所述布线区；栅极驱动模块，设置于所述布线区，所述栅极驱动模块包括多个输出接口；多个连接线路，设置于所述多个输入接口与所述多个输出接口之间，使所述多个输入接口分别与所述多个输出接口电性耦接；其中，所述多个连接线路包括多个对接线组与多个跨接线组，所述多个对接线组与所述多个跨接线组交互设置，所述多个跨接线组的信号输出顺序与所述多个对接线组的信号输出顺序为相异。
本申请解决其技术问题还可采用以下技术措施进一步实现。
在本申请的一实施例中，每一跨接线组包括一跨接线与一平接线，所述平接线为折线、直线、曲线或斜线。
在本申请的一实施例中，所述多个跨接线组包括二线路组合、三线路组合与四线路组合中至少其一者。
在本申请的一实施例中，所述栅极驱动模块将控制信号通过所述多个输出接口以第一顺序输出，所述多个输入接口的所述控制信号接收顺序是以第二顺序输入，其中，所述多个连接线路自所述多个输出接口以所述第一顺序取得所述控制信号，以所述第二顺序输出所述控制信号至所述多个输入接口。
在本申请的一实施例中，所述第一顺序与所述多个输出接口的线路排列顺序相同。
在本申请的一实施例中，所述栅极驱动模块包括栅极覆晶薄膜，压覆在所述基板的边缘，所述栅极覆晶薄膜包括所述多个输出接口。
在本申请的一实施例中，所述多个连接线路设置于所述布线区的扇出区。
在本申请的一实施例中，所述多个对接线组与所述多个跨接线组以相邻线组为相异的方式交互设置，或者所述多个对接线组以连续或局部连续的方式与所述多个跨接线组交互设置。
本申请的次一目的为一种阵列基板，其包括：基板，包括显示区及其外围的布线区，多个主动开关、多个像素单元和多条信号线设置于所述显示区，所述多个像素单元分别耦接于所述多个主动开关，所述多个主动开关分别电性耦接所述多条信号线，所述多条信号线包括多条栅极线与多条源极线，每一像素单元包括第一子像素及第二子像素组成，所述第一子像素与所述第二子像素通过相应的主动开关电性耦接相异的栅极线，及电性耦接相同的源极线，所述多条栅极线的多个输入接口设置于所述布线区，所述多个输入接口包括第一输入接口与第二输入接口；栅极驱动模块，设置于所述布线区，所述栅极驱动模块包括多个输出接口，所述栅极驱动模块依据所述多个输出接口的线 路排列顺序以输出控制信号，所述多个输出接口包括第一输出接口与第二输出接口；多个连接线路，设置于所述多个输入接口与所述多个输出接口之间，使所述多个输入接口分别与所述多个输出接口电性耦接；其中，所述多个连接线路包括多个对接线组与多个跨接线组，所述对接线组与所述跨接线组交互设置，所述跨接线组包括二线路组合，所述二线路组合包括第一线路与第二线路，所述第一线路连接于第一输出接口与第二输入接口之间，所述第二线路连接于第二输出接口与第一输入接口之间，所述第二线路是为折线、直线、曲线或斜线方式设置，所述第一线路是以跨线方式设置，所述二线路组合的信号输入顺序与信号输出顺序为相反，所述多个输出接口输出所述控制信号的顺序与所述多个输入接口的接收所述控制信号的顺序为相异。
本申请的次一目的为一种显示面板，其包括：对向基板；以及，阵列基板，与所述对向基板相对设置；其中，所述阵列基板包括上述任何一种实施例的技术特征的阵列基板。
本申请可以不大幅改变现有生产流程的前提，较能维持原制程需求和产品成本，通过布线设计即能改变显示区的控制信号接收顺序，借由调整信号接收顺序而达到调整像素单元的极性的目的，以此减缓显示画面的亮暗线问题。其次，此是通过布线设计即能改变显示区的控制信号接收顺序，因此不用特别调整驱动组件(如驱动IC，驱动芯片)的信号输出顺序，相对较能降低组件调节成本。其三，此是通过布线设计即能改变显示区的控制信号接收顺序，故可以适用于许多类型的显示面板，适用性相对较高。
附图说明
图1a为范例性的显示装置的架构示意图。
图1b为范例性的显示装置的扇出区的布线示意图。
图1c为范例性的显示装置的像素单元的极性示意图。
图2a为显示依据本申请的方法，一实施例的显示面板的布线示意图。
图2b为显示依据本申请的方法，一实施例的显示面板的布线示意图。
图2c为显示依据本申请的方法，一实施例半源极驱动的显示面板的像素极性示意图。
图2d为显示依据本申请的方法，一实施例的显示面板的布线示意图。
具体实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
附图和说明被认为在本质上是示出性的，而不是限制性的。在图中，结构相似的单元是以相同标号表示。另外，为了理解和便于描述，附图中示出的每个组件的尺寸和厚度是任意示出的，但是 本发明不限于此。
在附图中，为了清晰起见，夸大了层、膜、面板、区域等的厚度，亦夸大电路的设置范围。在附图中，为了理解和便于描述，夸大了一些层和区域的厚度，亦夸大电路的设置范围。将理解的是，当例如层、膜、区域、电路或基底的组件被称作“在”另一组件“上”时，所述组件可以直接在所述另一组件上，或者也可以存在中间组件。
另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括所述组件，但是不排除任何其它组件。此外，在说明书中，“在......上”意指位于目标组件上方或者下方，而不意指必须位于基于重力方向的顶部上。
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本发明提出的一种阵列基板及其应用的显示面板，其具体实施方式、结构、特征及其功效，详细说明如后。
图1a为范例性的显示装置的架构示意图。请参照图1a，一种液晶显示器，包括：控制板100，所述控制板100包括顺序控制器(Timing Controller，TCON)101；印刷电路板103，与所述控制板之间通过柔性扁平电缆(Flexible Flat Cable，FFC)102相连接；源极覆晶薄膜104和栅极覆晶薄膜105，分别与显示区106内的数据线及扫描线连接。
在一些实施例中，显示装置的驱动方式包括：系统主板提供颜色(例如：R/G/B)压缩信号、控制信号及电源传输至控制板100。控制板100上的顺序控制器101处理此等信号后，连同被驱动电路处理的电源，通过如柔性扁平电缆(Flexible Flat Cable，FFC)102，一并传输至印刷电路板103的源极电路及栅极电路，通过源极覆晶薄膜104和栅极覆晶薄膜105将必要性的数据与电源传输于显示区106，从而使得显示器获得呈现画面需求的电源、信号。
图1b为范例性的显示装置的扇出区的布线示意图，请配合图1a以利于了解。如1b所绘示，覆晶薄膜上设置有对应的集成电路(IC)，在一些实施例中，集成电路的通道大体上是依据其顺序而分别与显示区106的导电线路相连接。依据集成电路的不同，所连接的导电线路亦不相同。如栅极集成电路即连接扫描线(栅极线)，如源极集成电路即连接数据线(源极线)。
如图1b所绘示，以栅极集成电路107为例，所述栅极集成电路107的通道排列顺序为g1至gn，栅极集成电路的信号输出顺序也是被调整如同据通道信号输出顺序。
图1c为范列性的半源极驱动的显示面板的像素设置示意图,请配合图1a及图1b以利于理解。请参照图1c，显示区106包括多个主动开关与多个像素单元，像素单元电性耦接主动开关，主动开关电性耦接扫描线与数据线。每一像素单元由不同颜色的第一子像素及第二子像素组成，但通过主动开关连接相异扫描线，但连接共享同一数据线。例如扫描线D1上的像素单元，其所述第一子 像素及所述第二子像素通过主动开关分别连接至扫描线G1及扫描线G2，但共享一条数据线D1。如此方式设置所有像素单元，与传统的显示面板相比，数据线数目会减少约一半，但扫描线的栅极信号开启的时间减半，所以数据线对像素充电时间仅有传统结构的二分之一。
在一些实施侧中，显示面板为列2点反转的驱动方式。列2点反转是列反转和点反转的合成，表现为在每一列上以两个子像素(2点)为单位正负极性反转，相邻的两列子像素则以列为单位正负极性反转。如图1c，当列2点反转应用到半源极驱动像素整列上时，由于栅极信号开启的时间减半，数据线对像素充电时间仅有传统结构的二分之一，容易导致像素充电不足。而且，由于同一行相邻像素2点的极性相同，数据信号在到达相邻像素的延迟存在很大差异，一般而言，位于后续充电的子像素会有充电不足的现像，如此导致相邻像素的亮度会存在差异，引起显示上垂直亮暗线的问题，从而影响了显示品质，特别是在低灰阶下这种现象尤为明显。
图2a为显示依据本申请的方法，一实施例的显示面板的布线示意图。现有的显示面板组件设置请配合图1a至图1c以利于理解。请参照图2a，在本申请一实施例中，所述一种阵列基板200，包括：基板201，包括显示区106及其外围的布线区108，多个主动开关、多个像素单元和多条信号线设置于所述显示区106，所述多个像素单元分别耦接于所述多个主动开关，所述多个主动开关分别电性耦接所述多条信号线，所述多条信号线包括多条栅极线210与多条源极线，每一像素单元包括第一子像素及第二子像素组成，所述第一子像素与所述第二子像素通过相应的主动开关电性耦接相异的栅极线210，及电性耦接相同的源极线，所述多条栅极线210的的多个输入接口211设置于所述布线区108；栅极驱动模块220，设置于所述布线区108，所述栅极驱动模块220包括多个输出接口222；多个连接线路230，设置于所述多个输入接口211与所述多个输出接口222之间，使所述多个输入接口211分别与所述多个输出接口222电性耦接；其中，所述多个连接线路230包括多个对接线组231与多个跨接线组232，所述多个对接线组231与所述多个跨接线组232交互设置，所述多个跨接线组232的信号输出顺序与所述多个对接线组231的信号输出顺序为相异。
在一些实施例中，每一多个跨接线组232包括一跨接线与一平接线，所述平接线为折线、直线、曲线或斜线。
在一些实施例中，所述栅极驱动模块220将控制信号通过所述多个输出接口222以第一顺序输出，所述多个输入接口211的所述控制信号接收顺序是以第二顺序输入，其中，所述多个连接线路230自所述多个输出接口222以所述第一顺序取得所述控制信号，以所述第二顺序输出所述控制信号至所述多个输入接口211。
在一些实施例中，所述第一顺序与所述多个输出接口222的线路排列顺序相异、相同或局部相同。
如图2a所绘示，在一些实施例中，所述跨接线组232包括二线路组合。所述二线路组合包括第一线路232a与第二线路232b。所述第二线路232b是以折线方式设置，所述第一线路232a是以跨线方式设置。所述第一线路232a连接于输出接口g1与输入接口G2之间，所述第二线路232b连接于输出接口g2与输入接口G1之间。假定控制信号的通过所述输出接口的顺序为(g1->g2)，所述控制信号到达所述输入接口的顺序则为(G2->G1)。
如图2b为显示依据本申请的方法，一实施例的显示面板的布线示意图。在一些实施例中，所述对接线组231为两线路设置，所述跨接线组232亦是二线路组合，彼此之间以相邻线组为相异的方式交互设置。所述第一顺序与所述多个输出接口222的线路排列顺序相同，即所述栅极驱动模块220输出控制信号的顺序为(g1->g8)，而所述多个输入接口211取得控制信号的顺序为(G1->G2->G4->G3->G5->G6->G8->G7)。
在一些实施例中，所述多个对接线组231以连续或局部连续的方式与所述多个跨接线组232交互设置。
如图2c为显示依据本申请的方法，一实施例半源极驱动的显示面板的像素极性示意图。每一像素单元由不同颜色的第一子像素及第二子像素组成，但通过相应的主动开关连接相异扫描线，但连接共享同一数据线。例如扫描线D1上的像素单元，其所述第一子像素及所述第二子像素通过主动开关分别连接至扫描线G1及扫描线G2，但共享一条数据线D1，如此方式设置所有像素单元。所述多条栅极线210中，第G3条线路及第G4条线路，还有第G7条线路及第G8条线路，会以相反顺序取得控制信号，后续线路运作方式以此类推。如此，第G2n+1条线路及第G2n+2条线路，会以相反顺序取得控制信号。即是指，第G2n+1条线路及第G2n+2条线路所连接的像素单元的充电顺序，与第G2n-1条线路及第2n条线路所连接的像素单元的充电顺序，会正好相反。虽然，列2点反转应用到半源极驱动像素整列上时，由于同一行相邻像素2点的极性相同，数据信号在到达相邻像素的延迟存在很大差异的问题仍存在，但通过调整相邻行的像素单元的充电顺序，较能将充电不足的像素单元交错分散，降低垂直亮暗线情形，以提高显示面板的显示均齐性。
图2d为显示依据本申请的方法，一实施例的显示面板的布线示意图。在一些实施例中，所述第一顺序与所述多个输出接口222的线路排列顺序并不相同，例如：栅极驱动模块220输出控制信号的顺序为(g1->g2->g4->g3->g6->g5->g7->g8)。所述对接线组231与所述跨接线组232以二线路设置，彼此之间选择性的交互设置。其中，在所述输出接口(g3，g4)与所述输入接口(G3，G4)之间设置对接线组231，在所述输出接口(g5，g6)与所述输入接口(G5，G6)之间设置跨接线组232，如此，能使所述多个输入接口211取得控制信号的顺序维持为(G1->G2->G4->G3->G5->G6->G8->G7)。如此，依据栅极驱动模块220输出控制信号的顺序，以及所述多条栅极线接收控制信号的顺序，适度 的设置所述跨接线组232与所述对接线组231，令第g2n+1条线路及第g2n+2条线路所连接的像素单元的充电顺序，与第g2n-1条线路及第2n条线路所连接的像素单元的充电顺序，正好相反。
在一些实施例中，所述跨接线组232包括二线路组合、三线路组合与四线路组合中至少其一者。
在一些实施例中，所述栅极驱动模块220包括栅极覆晶薄膜105，压覆在所述基板201的边缘，所述栅极覆晶薄膜105包括所述多个输出接口221。
在一些实施例中，所述多个连接线路230设置于所述布线区108的扇出区。
在本申请一实施例中，本申请的一种阵列基板200，其包括：基板201，包括显示区106及其外围的布线区108，多个主动开关、多个像素单元和多条信号线设置于所述显示区106，所述多个像素单元分别耦接于所述多个主动开关，所述多个主动开关分别电性耦接所述多条信号线，所述多条信号线包括多条栅极线210与多条源极线，每一像素单元包括第一子像素及第二子像素组成，所述第一子像素与所述第二子像素通过相应的主动开关电性耦接相异的栅极线210，及电性耦接相同的源极线，所述多条栅极线210的多个输入接口211设置于所述布线区106，所述多个输入接口211包括输入接口G1与输入接口G2；栅极驱动模块220，设置于所述布线区108，所述栅极驱动模块220包括多个输出接口222，所述栅极驱动模块220依据所述多个输出接口222的线路排列顺序以输出控制信号，所述多个输出接口222包括输出接口g1与输出接口g2；多个连接线路230，设置于所述多个输入接口211与所述多个输出接口222之间，使所述多个输入接口211分别与所述多个输出接口222电性耦接；其中，所述多个连接线路230包括多个对接线组231与多个跨接线组232，所述对接线组231与所述跨接线组232交互设置，所述跨接线组232包括二线路组合，所述二线路组合包括第一线路232a与第二线路232b，所述第一线路232a连接于输出接口g1与输入接口G2之间，所述第二线路232b连接于输出接口g2与输入接口G1之间，所述第二线路232b是为折线、直线、曲线或斜线方式设置，所述第一线路232a是以跨线方式设置，所述二线路组合的信号输入顺序与信号输出顺序为相反，所述多个输出接口222输出所述控制信号的顺序，与所述多个输入接口211的接收所述控制信号的顺序为相异。
在本申请一实施例中，本申请的一种显示面板，其包括：相对设置的阵列基板与对向基板；其中，所述阵列基板包括前述各实施例中的任一种阵列基板200。
在一些实施例中，所述阵列基板更包括先前所述任一种实施方式。
在某些实施例中，本申请所述显示面板可例如为液晶显示面板，然不限于此，其亦可为OLED显示面板，W-OLED显示面板，QLED显示面板，等离子体显示面板，曲面型显示面板或其他类型显示面板。
本申请可以不大幅改变现有生产流程的前提，较能维持原制程需求和产品成本，通过布线设计 即能改变显示区的控制信号接收顺序，借由调整信号接收顺序而达到调整像素单元的极性的目的，以此减缓显示画面的亮暗线问题。其次，此是通过布线设计即能改变显示区的控制信号接收顺序，因此不用特别调整驱动组件(如驱动IC，驱动芯片)的信号输出顺序，相对较能降低组件调节成本。其三，此是通过布线设计即能改变显示区的控制信号接收顺序，故可以适用于许多类型的显示面板，适用性相对较高。
“在一些实施例中”及“在各种实施例中”等用语被重复地使用。此用语通常不是指相同的实施例；但它也可以是指相同的实施例。“包含”、“具有”及“包括”等用词是同义词，除非其前后文意显示出其它意思。
以上所述，仅是本申请的具体实施例而已，并非对本申请作任何形式上的限制，虽然本申请已以具体实施例揭露如上，然而并非用以限定本申请，任何熟悉本专业的技术人员，在不脱离本申请技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本申请技术方案的范围内。

Claims (20)

  1. 一种阵列基板，包括：
    基板，包括显示区及其外围的布线区，多个主动开关、多个像素单元和多条信号线设置于所述显示区，所述多个像素单元分别耦接于所述多个主动开关，所述多个主动开关分别电性耦接所述多条信号线，所述多条信号线包括多条栅极线与多条源极线，每一像素单元包括第一子像素及第二子像素组成，所述第一子像素与所述第二子像素通过相应的主动开关电性耦接相异的栅极线，及电性耦接相同的源极线，所述多条栅极线的多个输入接口设置于所述布线区；
    栅极驱动模块，设置于所述布线区，所述栅极驱动模块包括多个输出接口；
    多个连接线路，设置于所述多个输入接口与所述多个输出接口之间，使所述多个输入接口分别与所述多个输出接口电性耦接；
    其中，所述多个连接线路包括多个对接线组与多个跨接线组，所述多个对接线组与所述多个跨接线组交互设置，所述多个跨接线组的信号输出顺序与所述多个对接线组的信号输出顺序为相异。
  2. 如权利要求1所述的阵列基板，其中，每一跨接线组包括一跨接线与一平接线，所述平接线为折线。
  3. 如权利要求1所述的阵列基板，其中，每一跨接线组包括一跨接线与一平接线，所述平接线为直线。
  4. 如权利要求1所述的阵列基板，其中，每一跨接线组包括一跨接线与一平接线，所述平接线为曲线。
  5. 如权利要求1所述的阵列基板，其中，每一跨接线组包括一跨接线与一平接线，所述平接线为斜线。
  6. 如权利要求1所述的阵列基板，其中，所述多个跨接线组包括二线路组合、三线路组合与四线路组合中至少其一者。
  7. 如权利要求1所述的阵列基板，其中，所述栅极驱动模块将控制信号通过所述多个输出接口以第一顺序输出，所述多个输入接口的所述控制信号接收顺序是以第二顺序输入，其中，所述多个连接线路自所述多个输出接口以所述第一顺序取得所述控制信号，以所述第二顺序输出所述控制信号至所述多个输入接口。
  8. 如权利要求7所述的阵列基板，其中，所述第一顺序与所述多个输出接口的线路排列顺序相异。
  9. 如权利要求7所述的阵列基板，其中，所述第一顺序与所述多个输出接口的线路排列顺序相同。
  10. 如权利要求7所述的阵列基板，其中，所述第一顺序与所述多个输出接口的线路排列顺序局部相同。
  11. 如权利要求1所述的阵列基板，所述栅极驱动模块包括栅极覆晶薄膜，压覆在所述基板的边缘。
  12. 如权利要求11所述的阵列基板，所述栅极覆晶薄膜包括所述多个输出接口。
  13. 如权利要求1所述的阵列基板，其中，所述多个连接线路设置于所述布线区的扇出区。
  14. 如权利要求1所述的阵列基板，其中，所述多个对接线组与所述多个跨接线组以相邻线组为相异的方式交互设置。
  15. 如权利要求1所述的阵列基板，其中，所述多个对接线组以连续的方式与所述多个跨接线组交互设置。
  16. 如权利要求1所述的阵列基板，其中，所述多个对接线组以局部连续的方式与所述多个跨接线组交互设置。
  17. 一种阵列基板，包括：
    基板，包括显示区及其外围的布线区，多个主动开关、多个像素单元和多条信号线设置于所述显示区，所述多个像素单元分别耦接于所述多个主动开关，所述多个主动开关分别电性耦接所述多条信号线，所述多条信号线包括多条栅极线与多条源极线，每一像素单元包括第一子像素及第二子像素组成，所述第一子像素与所述第二子像素通过相应的主动开关电性耦接相异的栅极线，及电性耦接相同的源极线，所述多条栅极线的多个输入接口设置于所述布线区，所述多个输入接口包括第一输入接口与第二输入接口；
    栅极驱动模块，设置于所述布线区，所述栅极驱动模块包括多个输出接口，所述栅极驱动模块依据所述多个输出接口的线路排列顺序以输出控制信号，所述多个输出接口包括第一输出接口与第二输出接口；
    多个连接线路，设置于所述多个输入接口与所述多个输出接口之间，使所述多个输入接口分别与所述多个输出接口电性耦接；
    其中，所述多个连接线路包括多个对接线组与多个跨接线组，所述对接线组与所述跨接线组交互设置，所述跨接线组包括二线路组合，所述二线路组合包括第一线路与第二线路，所述第一线路连接于第一输出接口与第二输入接口之间，所述第二线路连接于第二输出接口与第一输入接口之间，所述第二线路是为折线、直线、曲线或斜线方式设置，所述第一线路是以跨线方式设置，所述二线路组合的信号输入顺序与信号输出顺序为相反，所述多个输出接口输出所述控制信号的顺序与所述多个输入接口的接收所述控制信号的顺序为相异。
  18. 一种显示面板，包括：
    对向基板；以及
    阵列基板，与所述对向基板相对设置；
    其中所述阵列基板，包括：
    基板，包括显示区及其外围的布线区，多个主动开关、多个像素单元和多条信号线设置于所述显示区，所述多个像素单元分别耦接于所述多个主动开关，所述多个主动开关分别电性耦接所述多条信号线，所述多条信号线包括多条栅极线与多条源极线，每一像素单元包括第一子像素及第二子像素组成，所述第一子像素与所述第二子像素通过相应的主动开关电性耦接相异的栅极线，及电性耦接相同的源极线，所述多条栅极线的多个输入接口设置于所述布线区；
    栅极驱动模块，设置于所述布线区，所述栅极驱动模块包括多个输出接口；
    多个连接线路，设置于所述多个输入接口与所述多个输出接口之间，使所述多个输入接口分别与所述多个输出接口电性耦接；
    其中，所述多个连接线路包括多个对接线组与多个跨接线组，所述多个对接线组与所述多个跨接线组交互设置，所述多个跨接线组的信号输出顺序与所述多个对接线组的信号输出顺序为相异。
  19. 如权利要求18所述的显示面板，其中，每一跨接线组包括一跨接线与一平接线，所述平接线为折线。
  20. 如权利要求18所述的显示面板，其中，每一跨接线组包括一跨接线与一平接线，所述平接线为直线。
PCT/CN2017/117080 2017-10-12 2017-12-19 阵列基板及其应用的显示面板 WO2019071815A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/745,548 US10593707B2 (en) 2017-10-12 2017-12-19 Array substrate and display panel using the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710946995.4A CN107765482A (zh) 2017-10-12 2017-10-12 阵列基板及其应用的显示面板
CN201710946995.4 2017-10-12

Publications (1)

Publication Number Publication Date
WO2019071815A1 true WO2019071815A1 (zh) 2019-04-18

Family

ID=61267415

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/117080 WO2019071815A1 (zh) 2017-10-12 2017-12-19 阵列基板及其应用的显示面板

Country Status (2)

Country Link
CN (1) CN107765482A (zh)
WO (1) WO2019071815A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107632477B (zh) 2017-10-12 2024-06-28 惠科股份有限公司 阵列基板及其应用的显示面板
CN114093275B (zh) * 2021-07-28 2022-12-02 荣耀终端有限公司 显示面板及终端设备
CN114283759A (zh) * 2021-12-30 2022-04-05 滁州惠科光电科技有限公司 像素结构、像素结构的驱动方法和显示面板
CN115064135A (zh) * 2022-07-08 2022-09-16 京东方科技集团股份有限公司 一种显示面板的驱动电路、驱动方法及显示装置
CN117496853A (zh) * 2023-03-17 2024-02-02 Tcl华星光电技术有限公司 显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070064190A1 (en) * 2005-09-12 2007-03-22 Samsung Electronics Co., Ltd. Liquid crystal display and method of fabricating the same
US20100245333A1 (en) * 2009-03-24 2010-09-30 Chao-Ching Hsu Liquid crystal display device capable of reducing image flicker and method for driving the same
CN104267555A (zh) * 2014-10-23 2015-01-07 深圳市华星光电技术有限公司 Tft阵列基板
CN105206211A (zh) * 2014-06-27 2015-12-30 乐金显示有限公司 显示装置
CN105319786A (zh) * 2015-11-26 2016-02-10 深圳市华星光电技术有限公司 具有低切换频率的数据线驱动极性的阵列基板
CN105575322A (zh) * 2015-12-17 2016-05-11 深圳市华星光电技术有限公司 半源极驱动显示面板

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102254522A (zh) * 2010-05-20 2011-11-23 联咏科技股份有限公司 驱动方法与驱动模块
CN201845154U (zh) * 2010-08-19 2011-05-25 华映视讯（吴江）有限公司 薄膜晶体管阵列基板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070064190A1 (en) * 2005-09-12 2007-03-22 Samsung Electronics Co., Ltd. Liquid crystal display and method of fabricating the same
US20100245333A1 (en) * 2009-03-24 2010-09-30 Chao-Ching Hsu Liquid crystal display device capable of reducing image flicker and method for driving the same
CN105206211A (zh) * 2014-06-27 2015-12-30 乐金显示有限公司 显示装置
CN104267555A (zh) * 2014-10-23 2015-01-07 深圳市华星光电技术有限公司 Tft阵列基板
CN105319786A (zh) * 2015-11-26 2016-02-10 深圳市华星光电技术有限公司 具有低切换频率的数据线驱动极性的阵列基板
CN105575322A (zh) * 2015-12-17 2016-05-11 深圳市华星光电技术有限公司 半源极驱动显示面板

Also Published As

Publication number Publication date
CN107765482A (zh) 2018-03-06

Similar Documents

Publication Publication Date Title
US10247994B2 (en) Pixel unit and driving method thereof
WO2019071815A1 (zh) 阵列基板及其应用的显示面板
US9348188B2 (en) Liquid crystal display
TWI419126B (zh) 液晶顯示器
US8836903B2 (en) Liquid crystal display
US8866715B2 (en) Active matrix substrate, liquid crystal panel, liquid crystal display device, liquid crystal display unit, and television receiver
US9646553B2 (en) Display device
US10971091B2 (en) Array substrate, display panel and driving method thereof, and display device
WO2001048546A1 (fr) Afficheur a cristaux liquides
CN107464538B (zh) 显示装置及其驱动方法
US10120244B2 (en) Display device
US11250799B2 (en) Display panel and display device suitable for low color cast display
CN106154668B (zh) 像素驱动系统、液晶显示器及像素驱动方法
KR20110017296A (ko) 액정 표시 장치
WO2019041336A1 (zh) 显示面板的驱动电路及驱动方法
WO2019052278A1 (zh) 显示面板的驱动方法及显示装置
CN105511187A (zh) 一种显示面板及显示装置
US10593707B2 (en) Array substrate and display panel using the same
WO2020107505A1 (zh) 显示驱动方法及液晶显示装置
WO2019061880A1 (zh) 显示面板及其显示装置
US8941569B2 (en) Liquid crystal display device, television receiver and display method employed in liquid crystal display device
WO2019184458A1 (zh) 显示装置及背光控制方法
US20090251403A1 (en) Liquid crystal display panel
US10290274B2 (en) Array substrate
US20240169952A1 (en) Display panel and display device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17928406

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17928406

Country of ref document: EP

Kind code of ref document: A1