WO2020124797A1 - 薄膜晶体管和显示面板 - Google Patents

薄膜晶体管和显示面板 Download PDF

Info

Publication number
WO2020124797A1
WO2020124797A1 PCT/CN2019/077128 CN2019077128W WO2020124797A1 WO 2020124797 A1 WO2020124797 A1 WO 2020124797A1 CN 2019077128 W CN2019077128 W CN 2019077128W WO 2020124797 A1 WO2020124797 A1 WO 2020124797A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
hole
contact portion
metal
sublayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/077128
Other languages
English (en)
French (fr)
Inventor
杨薇薇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US16/349,624 priority Critical patent/US11189731B2/en
Publication of WO2020124797A1 publication Critical patent/WO2020124797A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6746—Amorphous silicon

Definitions

  • the invention relates to the field of display technology, in particular to a thin film transistor and a display panel.
  • OLED Organic Light-emitting Diode
  • OLED Organic Light-Emitting Diode
  • Thin-film transistor (Thin-film Transistor, TFT) is used to drive OLED.
  • TFT1 manufacturing process as shown in FIG. 1, a substrate 11, a buffer layer 12, an active layer 13, a first gate insulating layer 14, a first gate 15, and a second gate insulating layer 16 are formed in this order.
  • a through hole a, a through hole b, a through hole c, and a through hole d will be simultaneously formed, wherein the through hole a and the through hole c extend from the dielectric layer 18 to the active layer 13.
  • the via d extends from the dielectric layer 18 to the first gate layer 15, and the via b extends from the dielectric layer 18 to the second gate layer 17.
  • the above through holes a, b, c and d are filled with metal to form the source and drain 19.
  • hydrogen fluoride is used for cleaning to remove the oxidation of the surface of the active layer 13 Thing.
  • hydrogen fluoride is highly corrosive, the first gate 15 and the second gate 17 will be corroded, resulting in abnormal signal transmission, and the yield of the thin film transistor is reduced.
  • An object of the present invention is to provide a thin film transistor and a display panel, which improve the yield of the thin film transistor.
  • An embodiment of the present invention provides a thin film transistor, which includes:
  • An active layer provided on the substrate
  • An insulating layer is provided on the active layer, and the insulating layer is provided with a first through hole and a second through hole;
  • a metal layer disposed on the insulating layer includes a first contact portion and a second contact portion disposed at the same interval, the first contact portion passes through the first through hole and the active layer Connection, the second contact portion is connected to the active layer through the second through hole;
  • a dielectric layer is provided on the metal layer, and the dielectric layer is provided with a third through hole corresponding to the first contact portion and a fourth through hole corresponding to the second contact portion;
  • a source electrode and a drain electrode, the source electrode and the drain electrode are disposed on the dielectric layer in the same layer, the source electrode is connected to the first contact portion through the third through hole, and the drain electrode passes through the The fourth through hole is connected to the second contact portion.
  • the metal layer further includes a first metal sublayer, an insulator sublayer, and a second metal sublayer;
  • the first metal sub-layer is provided on the insulating layer
  • the insulator sublayer is provided on the first metal sublayer
  • the second metal sublayer is provided on the insulating sublayer.
  • the second metal sublayer includes the first contact and the second contact.
  • the first through hole penetrates the insulating sublayer and the insulating layer
  • the second through hole penetrates the insulating sublayer and the insulating layer.
  • the first metal sublayer includes the first contact and the second contact.
  • the third through hole penetrates the dielectric layer and the insulator sublayer
  • the fourth through hole penetrates the dielectric layer and the insulator sublayer
  • the metal layer is composed of a Mo film layer or a three-layer film layer of Ti/Al/Ti.
  • the metal layer is composed of three layers of Ti/Al/Ti films
  • the thickness of the Ti film layer connected to the source electrode in the first contact portion is oxidized in a range of 0-30 nm;
  • the thickness of the Ti film layer connected to the source electrode in the second contact portion is oxidized in a range of 0-30 nm.
  • the resistance range between the source electrode and the first contact is 0.01 ohm-5 ohm
  • the resistance range between the drain electrode and the second contact is 0.01 ohm-5 ohm
  • the first through hole and the third through hole are arranged oppositely, or the first through hole and the third through hole are arranged oppositely; the second through hole and the first The four through holes are arranged oppositely, and the second through holes and the fourth through holes are arranged oppositely.
  • An embodiment of the present invention also provides a display panel, which includes a thin film transistor, and the thin film transistor includes:
  • An active layer provided on the substrate
  • An insulating layer is provided on the active layer, and the insulating layer is provided with a first through hole and a second through hole;
  • a metal layer disposed on the insulating layer includes a first contact portion and a second contact portion disposed at the same interval, the first contact portion passes through the first through hole and the active layer Connection, the second contact portion is connected to the active layer through the second through hole;
  • a dielectric layer is provided on the metal layer, and the dielectric layer is provided with a third through hole corresponding to the first contact portion and a fourth through hole corresponding to the second contact portion;
  • a source electrode and a drain electrode, the source electrode and the drain electrode are disposed on the dielectric layer in the same layer, the source electrode is connected to the first contact portion through the third through hole, and the drain electrode passes through the The fourth through hole is connected to the second contact portion.
  • the metal layer further includes a first metal sublayer, an insulator sublayer, and a second metal sublayer;
  • the first metal sub-layer is provided on the insulating layer
  • the insulator sublayer is provided on the first metal sublayer
  • the second metal sublayer is provided on the insulating sublayer.
  • the second metal sublayer includes the first contact and the second contact.
  • the first through hole penetrates the insulating sublayer and the insulating layer
  • the second through hole penetrates the insulating sublayer and the insulating layer.
  • the first metal sublayer includes the first contact and the second contact.
  • the third through hole penetrates the dielectric layer and the insulator sublayer
  • the fourth through hole penetrates the dielectric layer and the insulator sublayer
  • the metal layer is composed of a Mo film layer or a three-layer film layer of Ti/Al/Ti.
  • the metal layer is composed of three layers of Ti/Al/Ti films
  • the thickness of the Ti film layer connected to the source electrode in the first contact portion is oxidized in a range of 0-30 nm;
  • the thickness of the Ti film layer connected to the source electrode in the second contact portion is oxidized in a range of 0-30 nm.
  • the resistance range between the source electrode and the first contact is 0.01 ohm-5 ohm
  • the resistance range between the drain electrode and the second contact is 0.01 ohm-5 ohm
  • the first through hole and the third through hole are arranged oppositely, or the first through hole and the third through hole are arranged oppositely; the second through hole and the first The four through holes are arranged oppositely, and the second through holes and the fourth through holes are arranged oppositely.
  • the first through hole and the second through hole are provided to connect the metal layer to the active layer
  • the third through hole and the fourth through hole are provided to connect the metal layer to the source and drain Electrode connection, so that the active layer is electrically connected to the source electrode and the drain electrode through the metal layer, and the yield of the thin film transistor is improved.
  • FIG. 1 is a schematic flow chart of a method for manufacturing an existing thin film transistor.
  • FIG. 2 is a schematic structural diagram of a thin film transistor provided by an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a positional relationship between a first through hole and a third through hole provided by an embodiment of the present invention.
  • FIG. 4 is another schematic structural diagram of a thin film transistor provided by an embodiment of the present invention.
  • FIG. 5 is another schematic structural diagram of a thin film transistor provided by an embodiment of the present invention.
  • Embodiments of the present invention provide a thin film transistor and a display panel, where the display panel includes the thin film transistor.
  • FIG. 2 is a schematic structural diagram of a thin film transistor provided by an embodiment of the present invention.
  • the thin film transistor 2 includes a substrate 21, an active layer 22, an insulating layer 23, a metal layer 24, a dielectric layer 25, a source electrode 26, a drain electrode 27, a first through hole 28, and a second through hole 29 ⁇ Third through hole 30 and fourth through hole 31.
  • the substrate 21 is used to carry the active layer 22, the insulating layer 23 and the like on it.
  • the substrate 21 may be a flexible substrate composed of a flexible material such as polyimide, or may be a rigid substrate such as a glass substrate.
  • the active layer 22 is provided on the substrate 21, and the active layer 22 is composed of amorphous silicon a-si or polysilicon P-si material. As shown in FIG. 2, a buffer layer 32 may also be provided between the substrate 21 and the active layer 22.
  • the buffer layer 32 may be composed of materials such as SiN x and SiO x .
  • the insulating layer 23 is provided on the active layer 22.
  • the insulating layer 23 may be dug to form the first through hole 28 and the second through hole 29, that is, the first through hole 28 and the second through hole 29 are provided on the insulating layer 23. It should be noted that after the first through holes 28 and the second through holes 29 are formed, the first through holes 28 and the second through holes 29 may be washed with hydrogen fluoride to remove the first through holes 28 and the second through holes 29 Of oxides.
  • the metal layer 24 is provided on the insulating layer 23.
  • the first through hole 28 and the second through hole 29 are filled with metal materials such as molybdenum (Mo) or titanium/aluminum/titanium (Ti/Al/Ti), that is, the metal layer 24 may be composed of a Mo film layer or Ti /Al/Ti three-layer film composition.
  • Mo molybdenum
  • Ti/Al/Ti titanium/aluminum/titanium
  • the metal layer 24 may include a first contact portion 242 and a second contact portion 243, which are arranged at the same layer interval.
  • the first contact portion 242 is connected to the active layer 22 through the first through hole 28, and the second contact portion 243 is connected to the active layer 22 through the second through hole 29.
  • the dielectric layer 25 is provided on the metal layer 24.
  • the dielectric layer 25 may be bored to form third through holes 30 and fourth through holes 31, that is, the third through holes 30 and the fourth through holes 31 are provided on the dielectric layer 25.
  • the first through holes 28 and the third through holes 30 are oppositely arranged, or the first through holes 28 and the third through holes 30 are partially oppositely arranged.
  • the second through-hole 29 and the fourth through-hole 31 may also be oppositely arranged, or the second through-hole 29 and the fourth through-hole 31 are partially opposed.
  • the diameter of the first through-hole 28 may be larger than the diameter of the third through-hole 30 or less than or equal to the diameter of the third through-hole 30, and the diameter of the second through-hole 29 may be larger than the diameter of the fourth through-hole 31, It may also be smaller than or equal to the diameter of the fourth through hole 31, which is not specifically limited herein.
  • the source electrode 26 and the drain electrode 27 are disposed on the dielectric layer 25 in the same layer.
  • the third through hole 30 and the fourth through hole 31 may be filled with Ti/Al/Ti, covering the dielectric layer 25, and then patterned to form the source electrode 26 and the drain electrode 27 as shown in FIG.
  • the source electrode 26 is connected to the first contact portion 242 through the third through hole 30, and the drain electrode 27 is connected to the second contact portion 243 through the fourth through hole 31.
  • the source electrode 26 and the drain electrode 27 may be connected to the active layer 22 by using the first contact portion and the second contact portion of the metal layer 24 as a bridge.
  • the formed third through holes 30 and the fourth through holes 31 do not require treatment using hydrogen fluoride, that is, the metal layer 24 is prevented from being corroded by hydrogen fluoride.
  • the metal layer 24 when the metal layer 24 is composed of a Ti/Al/Ti three-layer film layer, that is, when the first contact portion 242 and the second contact portion 243 are both composed of a Ti/Al/Ti three-layer film layer group, the metal layer 24 The Ti film layer will be oxidized to form TiOx, where the thickness of TiOx is generally in the range of 0-50 nm. It should be noted that the thickness of the Ti film layer connected to the source electrode 26 in the first contact portion 242 is oxidized, and the thickness of the Ti film layer connected to the drain electrode 27 in the second contact portion 243 is oxidized. The resistance between the source 26 and the drain 27 has a great influence.
  • the depths of the third through holes 30 and the fourth through holes 31 can be effectively controlled, that is, the TiOx at the connection between the first contact portion 242 and the source electrode 26 and the second contact portion 243 can be effectively removed TiOx at the junction with the drain 27.
  • the thickness of the oxidized thickness of the Ti film layer connected to the source electrode 26 in the first contact portion 242 is controlled to be between 0-30 nm, and the Ti film connected to the drain electrode 27 in the second contact portion 243 The thickness of the oxidized layer is controlled between 0-30 nm.
  • the resistance range between the source electrode 26 and the first contact portion 242 can be controlled to 0.01-5 ohm, and the resistance range between the drain layer 27 and the second contact portion 243 can be controlled to 0.01-5 ohm.
  • the metal layer 24 further includes a first metal sublayer 244, an insulator sublayer 245, and a second metal sublayer 246.
  • the first metal sublayer 244 is disposed on the insulating layer 23
  • the insulating sublayer 245 is disposed on the first metal sublayer 244
  • the second metal sublayer 246 is disposed on the insulating sublayer 245.
  • the second metal sublayer 246 includes the first contact portion 242 and the second contact portion 243.
  • the third through hole 30 and the fourth through hole 31 are still provided on the dielectric layer 25.
  • the first through hole 28 penetrates the insulator layer 245 and the insulating layer 23, and the second through hole 29 also penetrates the insulator layer 245 and the insulating layer 23.
  • the first metal sublayer 244 includes the first contact portion 242 and the second contact portion 243.
  • the first through hole 28 and the second through hole 29 are still provided on the insulating layer 23, while the third through hole 30 penetrates the dielectric layer 25 and the insulating sublayer 245, and the fourth through hole 31 penetrates the dielectric layer 25 and the insulating sublayer 245.
  • the metal layer 24 may further include a metal sub-layer 241.
  • the metal sub-layer 241, the first contact portion 242 and the second contact portion 243 may be disposed at the same layer interval.
  • the first contact portion 242 and the second contact portion 243 may be disposed on both sides of the metal sub-layer 241.
  • the insulating layer 23 and the insulating sub-layer 245 may be punched first to form the first through hole 28 and the second through hole 29. Then, the first through hole 28 and the second through hole 29 are sequentially filled with Ti, Al, and Ti, and covered on the insulator layer 245. Finally, patterning is performed to form the first contact portion 242, the second contact portion 243, and the metal sub-layer 241 as shown in FIG. At this time, the metal sublayer 241 and the first metal sublayer 244 opposite thereto form a capacitor.
  • the insulating layer 23 may be first drilled to form the first through hole 28 and the second through hole 29. Then, the first through hole 28 and the second through hole 29 are sequentially filled with Ti, Al, and Ti, and covered on the insulating layer 23. Finally, patterning is performed to form the first contact portion 242, the second contact portion 243, and the metal sub-layer 241 as shown in FIG. At this time, the metal sub-layer 241 and the second metal sub-layer 246 disposed opposite thereto form a capacitor.
  • first contact portion 242, the second contact portion 243 and the metal sub-layer 241 can be made by one process.
  • the thin film transistor 2 further includes a fifth through hole 33 and a sixth through hole 34.
  • the fifth through hole 33 is provided in the dielectric layer 25 to connect the source electrode 26 or the drain electrode 27 to the metal sub-layer 241.
  • the sixth via hole 34 is provided on the dielectric layer 25 and the insulating sublayer 245 to connect the source electrode 26 or the drain electrode 27 to the first metal sublayer 244.
  • the fifth through hole 33 is provided in the dielectric layer 25 to connect the source electrode 26 or the drain electrode 27 to the second metal sub-layer 246.
  • the sixth via hole 34 is provided on the dielectric layer 25 and the insulating sublayer 245 to connect the source electrode 26 or the drain electrode 27 to the metal sublayer 241.
  • the first through hole and the second through hole are provided to connect the metal layer to the active layer
  • the third through hole and the fourth through hole are provided to connect the metal layer to the source and drain Electrode connection, so that the active layer is electrically connected to the source electrode and the drain electrode through the metal layer, and the yield of the thin film transistor is improved.

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种薄膜晶体管和显示面板，其中薄膜晶体管包括基板（21）、有源层（22）、绝缘层（23）、金属层（24）、介质层（25）、源漏极（26、27）、第一通孔（28）、第二通孔（29）、第三通孔（30）以及第四通孔（31）；金属层（24）中的第一接触部（242）通过第一通孔（28）与有源层（22）连接，第二接触部（243）通过第二通孔（243）与有源层（22）连接；源极（26）通过第三通孔（30）与第一接触部（242）连接，漏极（27）通过第四通孔（31）与第二接触部（243）连接。

Description

薄膜晶体管和显示面板 技术领域
本发明涉及显示技术领域，特别是涉及一种薄膜晶体管和显示面板。
 背景技术
在显示技术领域中，由于OLED（Organic Light-emitting Diode,有机发光二极管）显示器具有重量轻、自发光、广视角以及响应速度快等特点，得到广泛应用。
薄膜晶体管（Thin-film Transistor，TFT）用于驱动OLED。现有的TFT1制程过程中，如图1所示，依次形成基板11、缓冲层12、有源层13、第一栅极绝缘层14、第一栅极15、第二栅极绝缘层16、第二栅极17，以及介电层18之后，将同时形成通孔a、通孔b、通孔c以及通孔d，其中通孔a和通孔c从介电层18延伸到有源层13，通孔d从介电层18延伸到第一栅极层15，通孔b从介电层18延伸到第二栅极层17。然后再往上述通孔a、b、c以及d中填充金属，形成源漏极19。在此过程中，为了改善源漏极19与有源层13之间的电阻，在形成上述通孔a、b、c以及d后，会使用氟化氢进行清洗，以去除有源层13表面的氧化物。然而，由于氟化氢具有强腐蚀性，会将第一栅极15、第二栅极17腐蚀，导致信号传输异常，薄膜晶体管的良品率降低。
 技术问题
本发明的目的在于提供一种薄膜晶体管和显示面板，提高了薄膜晶体管的良品率。
 技术解决方案
本发明实施例提供了一种薄膜晶体管，其包括：
基板；
有源层，设置在所述基板上；
绝缘层，设置在所述有源层上，所述绝缘层上设有第一通孔和第二通孔；
金属层，设置在所述绝缘层上，所述金属层包括同层间隔设置的第一接触部和第二接触部，所述第一接触部通过所述第一通孔与所述有源层连接，所述第二接触部通过所述第二通孔与所述有源层连接；
介质层，设置在所述金属层上，所述介质层上设有分别与所述第一接触部对应的第三通孔，和与第二接触部对应的第四通孔；
源极和漏极，所述源极和漏极同层设置在所述介质层上，所述源极通过所述第三通孔与所述第一接触部连接，所述漏极通过所述第四通孔与所述第二接触部连接。
在一些实施例中，所述述金属层还包括第一金属子层、绝缘子层，以及第二金属子层；
所述第一金属子层，设置在所述绝缘层上；
所述绝缘子层，设置在所述第一金属子层上；
所述第二金属子层，设置在所述绝缘子层上。
在一些实施例中，所述第二金属子层包括所述的第一接触部和所述第二接触部。
在一些实施例中，所述第一通孔贯穿所述绝缘子层和所述绝缘层，所述第二通孔贯穿所述绝缘子层和所述绝缘层。
在一些实施例中，所述第一金属子层包括所述的第一接触部和所述第二接触部。
在一些实施例中，所述第三通孔贯穿所述介质层和所述绝缘子层，所述第四通孔贯穿所述介质层和所述绝缘子层。
在一些实施例中，所述金属层由Mo膜层或Ti/Al/Ti三层膜层组成。
在一些实施例中，所述金属层由Ti/Al/Ti三层膜层组成；
所述第一接触部中与所述源极连接的Ti膜层被氧化的厚度范围为0-30纳米；
所述第二接触部中与所述源极连接的Ti膜层被氧化的厚度范围为0-30纳米。
在一些实施例中，所述源极和所述第一接触部之间的电阻范围为0.01欧姆-5欧姆，所述漏极和所述第二接触部之间的电阻范围为0.01欧姆-5欧姆。
在一些实施例中，所述第一通孔和所述第三通孔相对设置，或所述第一通孔和所述第三通孔部分相对设置；所述第二通孔和所述第四通孔相对设置，所述第二通孔和所述第四通孔部分相对设置。
本发明实施例还提供了一种显示面板，其包括薄膜晶体管，所述薄膜晶体管包括：
基板；
有源层，设置在所述基板上；
绝缘层，设置在所述有源层上，所述绝缘层上设有第一通孔和第二通孔；
金属层，设置在所述绝缘层上，所述金属层包括同层间隔设置的第一接触部和第二接触部，所述第一接触部通过所述第一通孔与所述有源层连接，所述第二接触部通过所述第二通孔与所述有源层连接；
介质层，设置在所述金属层上，所述介质层上设有分别与所述第一接触部对应的第三通孔，和与第二接触部对应的第四通孔；
源极和漏极，所述源极和漏极同层设置在所述介质层上，所述源极通过所述第三通孔与所述第一接触部连接，所述漏极通过所述第四通孔与所述第二接触部连接。
在一些实施例中，所述述金属层还包括第一金属子层、绝缘子层，以及第二金属子层；
所述第一金属子层，设置在所述绝缘层上；
所述绝缘子层，设置在所述第一金属子层上；
所述第二金属子层，设置在所述绝缘子层上。
在一些实施例中，所述第二金属子层包括所述的第一接触部和所述第二接触部。
在一些实施例中，所述第一通孔贯穿所述绝缘子层和所述绝缘层，所述第二通孔贯穿所述绝缘子层和所述绝缘层。
在一些实施例中，所述第一金属子层包括所述的第一接触部和所述第二接触部。
在一些实施例中，所述第三通孔贯穿所述介质层和所述绝缘子层，所述第四通孔贯穿所述介质层和所述绝缘子层。
在一些实施例中，所述金属层由Mo膜层或Ti/Al/Ti三层膜层组成。
在一些实施例中，所述金属层由Ti/Al/Ti三层膜层组成；
所述第一接触部中与所述源极连接的Ti膜层被氧化的厚度范围为0-30纳米；
所述第二接触部中与所述源极连接的Ti膜层被氧化的厚度范围为0-30纳米。
在一些实施例中，所述源极和所述第一接触部之间的电阻范围为0.01欧姆-5欧姆，所述漏极和所述第二接触部之间的电阻范围为0.01欧姆-5欧姆。
在一些实施例中，所述第一通孔和所述第三通孔相对设置，或所述第一通孔和所述第三通孔部分相对设置；所述第二通孔和所述第四通孔相对设置，所述第二通孔和所述第四通孔部分相对设置。
 有益效果
本发明实施例的薄膜晶体管和显示面板，通过设置第一通孔、第二通孔，使金属层与有源层连接，设置第三通孔、第四通孔使金属层与源极、漏极连接，从而使有源层与源极、漏极通过金属层电性连接，提高了薄膜晶体管的良品率。
 附图说明
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下：
图1为现有薄膜晶体管的制作方法的流程示意图。
图2为本发明实施例提供的薄膜晶体管的结构示意图。
图3为本发明实施例提供的第一通孔和第三通孔的位置关系示意图。
图4为本发明实施例提供的薄膜晶体管的另一结构示意图。
图5为本发明实施例提供的薄膜晶体管的又一结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本发明的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
本发明实施例提供了一种薄膜晶体管和显示面板，其中显示面板包括该薄膜晶体管。请参照图2，图2为本发明实施例提供的薄膜晶体管的结构示意图。如图2所示，该薄膜晶体管2包括基板21、有源层22、绝缘层23、金属层24、介质层25、源极26、漏极27、第一通孔28、第二通孔29、第三通孔30和第四通孔31。
基板21用于承载其上的有源层22、绝缘层23等结构。该基板21可以是由聚酰亚胺等柔性材料组成的柔性基板，也可以是玻璃基板等刚性基板。
有源层22设置在基板21上，该有源层22由非晶硅a-si或多晶硅P-si材料组成。其中，如图2所示，基板21和有源层22之间还可以设置缓冲层32，该缓冲层32可以由SiN x、SiO x等材料组成。
绝缘层23设置在有源层22上。可以对绝缘层23挖孔，形成第一通孔28和第二通孔29，即第一通孔28和第二通孔29设置在绝缘层23上。需要说明的，形成第一通孔28和第二通孔29后，可以采用氟化氢对第一通孔28和第二通孔29进行清洗，以去除第一通孔28和第二通孔29内的氧化物。
金属层24设置在绝缘层23上。具体的，首先往第一通孔28、第二通孔29内填充钼（Mo）或钛/铝/钛（Ti/Al/Ti）等金属材料，即金属层24可以由Mo膜层或Ti/Al/Ti三层膜层组成。然后使金属材料覆盖绝缘层23，再进行图案化，形成金属层24。
在一实施例中，如图2所示，该金属层24可以包括第一接触部242和第二接触部243，二者同层间隔设置。第一接触部242通过第一通孔28与有源层22连接，第二接触部243通过第二通孔29与有源层22连接。
介质层25设置在金属层24上。可以对介质层25挖孔，形成第三通孔30和第四通孔31，即第三通孔30和第四通孔31设置在介质层25上。
如图3所示，第一通孔28和第三通孔30相对设置，或第一通孔28和第三通孔30部分相对设置。同理的，第二通孔29和第四通孔31也可以相对设置，或第二通孔29和第四通孔31部分相对设置。需要说明的是，第一通孔28直径可以大于第三通孔30的直径，也可以小于或等于第三通孔30的直径，第二通孔29直径可以大于第四通孔31的直径，也可以小于或等于第四通孔31的直径，在此不做具体限定。
源极26和漏极27同层设置在介质层25上。具体的，可以往第三通孔30和第四通孔31内填充Ti/Al/Ti，并覆盖介质层25，再进行图案化，形成如图1所示的源极26和漏极27。
其中，源极26通过第三通孔30与第一接触部242连接，漏极27通过第四通孔31与第二接触部243连接。此时，源极26和漏极27可以以金属层24的第一接触部和第二接触部作为桥梁，与有源层22连接。需要说明的是，形成的第三通孔30和第四通孔31不需要使用氟化氢的处理，即避免了金属层24被氟化氢腐蚀。
进一步的，当金属层24由Ti/Al/Ti三层膜层组成时，即第一接触部242和第二接触部243均由Ti/Al/Ti三层膜层组时，金属层24中的Ti膜层会被氧化，形成TiOx，其中TiOx的厚度范围一般为0-50纳米。需要说明的是，第一接触部242中与源极26连接的Ti膜层被氧化的厚度，以及第二接触部243中与漏极27连接的Ti膜层被氧化的厚度，对金属层24与源极26、漏极27之间的电阻有较大影响。
在本发明实施例中，第三通孔30和第四通孔31的深度可以得到有效控制，即可以有效去除第一接触部242中与源极26连接处的TiOx，以及第二接触部243中与漏极27连接处的TiOx。优选的，将第一接触部242中与源极26连接的Ti膜层被氧化的厚度范围为控制在0-30纳米之间，以及将第二接触部243中与漏极27连接的Ti膜层被氧化的厚度范围控制在0-30纳米之间。
综上，可以将源极26与第一接触部242之间的电阻范围控制在0.01-5欧姆之间，并将漏极层27与第二接触部243之间的电阻范围控制在0.01-5欧姆。
在一些实施例中，如图4或5所示，金属层24还包括第一金属子层244、绝缘子层245，以及第二金属子层246。其中，第一金属子层244设置在绝缘层23上，绝缘子层245设置在第一金属子层244上，第二金属子层246设置在绝缘子层245上。
如图4所示，第二金属子层246包括所述的第一接触部242和所述第二接触部243。此时，第三通孔30和第四通孔31仍然设置在介质层25上。而第一通孔28贯穿绝缘子层245和绝缘层23，第二通孔29也贯穿绝缘子层245和绝缘层23。
如图5所示，第一金属子层244包括所述的第一接触部242和所述第二接触部243。此时，第一通孔28和第二通孔29仍设置在绝缘层23上，而第三通孔30贯穿在介质层25和绝缘子层245，第四通孔31贯穿介质层25和绝缘子层245。
进一步的，如图4或5所示，该金属层24还可以包括金属子层241。金属子层241、第一接触部242和第二接触部243可以同层间隔设置。在一实施例中，第一接触部242和第二接触部243可以设置在金属子层241的两侧。
在一实施例中，可以先在绝缘层23、绝缘子层245上打孔，形成第一通孔28和第二通孔29。然后依次往第一通孔28和第二通孔29内填充Ti、Al以及Ti，并覆盖在绝缘子层245上。最后进行图案化，形成如图4所示的第一接触部242、第二接触部243以及金属子层241。此时，金属子层241和与其相对设置的第一金属子层244，形成电容。
在一实施例中，还可以先在绝缘层23打孔，形成第一通孔28和第二通孔29。然后依次往第一通孔28和第二通孔29内填充Ti、Al以及Ti，并覆盖在绝缘层23上。最后进行图案化，形成如图5所示的第一接触部242、第二接触部243以及金属子层241。此时，金属子层241和与其相对设置的第二金属子层246，形成电容。
综上，第一接触部242、第二接触部243以及金属子层241可以采用一道工艺制成。
相应的，薄膜晶体管2还包括第五通孔33和第六通孔34。如图4所示，第五通孔33设置在介质层25，使源极26或漏极27与金属子层241连接。第六通孔34设置在介质层25和绝缘子层245上，使源极26或漏极27与第一金属子层244连接。如图5所示，第五通孔33设置在介质层25，使源极26或漏极27与第二金属子层246连接。第六通孔34设置在介质层25和绝缘子层245上，使源极26或漏极27与金属子层241连接。
本发明实施例的薄膜晶体管和显示面板，通过设置第一通孔、第二通孔，使金属层与有源层连接，设置第三通孔、第四通孔使金属层与源极、漏极连接，从而使有源层与源极、漏极通过金属层电性连接，提高了薄膜晶体管的良品率。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种薄膜晶体管，其包括：
    基板；
    有源层，设置在所述基板上；
    绝缘层，设置在所述有源层上，所述绝缘层上设有第一通孔和第二通孔；
    金属层，设置在所述绝缘层上，所述金属层包括同层间隔设置的第一接触部和第二接触部，所述第一接触部通过所述第一通孔与所述有源层连接，所述第二接触部通过所述第二通孔与所述有源层连接；
    介质层，设置在所述金属层上，所述介质层上设有分别与所述第一接触部对应的第三通孔，和与所述第二接触部对应的第四通孔；
    源极和漏极，所述源极和漏极同层设置在所述介质层上，所述源极通过所述第三通孔与所述第一接触部连接，所述漏极通过所述第四通孔与所述第二接触部连接。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述述金属层还包括第一金属子层、绝缘子层，以及第二金属子层；
    所述第一金属子层，设置在所述绝缘层上；
    所述绝缘子层，设置在所述第一金属子层上；
    所述第二金属子层，设置在所述绝缘子层上。
  3. 根据权利要求2所述的薄膜晶体管，其中，所述第二金属子层包括所述的第一接触部和所述第二接触部。
  4. 根据权利要求3所述的薄膜晶体管，其中，所述第一通孔贯穿所述绝缘子层和所述绝缘层，所述第二通孔贯穿所述绝缘子层和所述绝缘层。
  5. 根据权利要求2所述的薄膜晶体管，其中，所述第一金属子层包括所述的第一接触部和所述第二接触部。
  6. 根据权利要求5所述的薄膜晶体管，其中，所述第三通孔贯穿所述介质层和所述绝缘子层，所述第四通孔贯穿所述介质层和所述绝缘子层。
  7. 根据权利要求1所述的薄膜晶体管，其中，所述金属层由Mo膜层或Ti/Al/Ti三层膜层组成。
  8. 根据权利要求1所述的薄膜晶体管，其中，所述金属层由Ti/Al/Ti三层膜层组成；
    所述第一接触部中与所述源极连接的Ti膜层被氧化的厚度范围为0-30纳米；
    所述第二接触部中与所述源极连接的Ti膜层被氧化的厚度范围为0-30纳米。
  9. 根据权利要求8所述的薄膜晶体管，其中，所述源极和所述第一接触部之间的电阻范围为0.01欧姆-5欧姆，所述漏极和所述第二接触部之间的电阻范围为0.01欧姆-5欧姆。
  10. 根据权利要求1所述的薄膜晶体管，其中，所述第一通孔和所述第三通孔相对设置，或所述第一通孔和所述第三通孔部分相对设置；所述第二通孔和所述第四通孔相对设置，所述第二通孔和所述第四通孔部分相对设置。
  11. 一种显示面板，其包括薄膜晶体管，所述薄膜晶体管包括：
    基板；
    有源层，设置在所述基板上；
    绝缘层，设置在所述有源层上，所述绝缘层上设有第一通孔和第二通孔；
    金属层，设置在所述绝缘层上，所述金属层包括同层间隔设置的第一接触部和第二接触部，所述第一接触部通过所述第一通孔与所述有源层连接，所述第二接触部通过所述第二通孔与所述有源层连接；
    介质层，设置在所述金属层上，所述介质层上设有分别与所述第一接触部对应的第三通孔，和与所述第二接触部对应的第四通孔；
    源极和漏极，所述源极和漏极同层设置在所述介质层上，所述源极通过所述第三通孔与所述第一接触部连接，所述漏极通过所述第四通孔与所述第二接触部连接。
  12. 根据权利要求11所述的显示面板，其中，所述述金属层还包括第一金属子层、绝缘子层，以及第二金属子层；
    所述第一金属子层，设置在所述绝缘层上；
    所述绝缘子层，设置在所述第一金属子层上；
    所述第二金属子层，设置在所述绝缘子层上。
  13. 根据权利要求12所述的显示面板，其中，所述第二金属子层包括所述的第一接触部和所述第二接触部。
  14. 根据权利要求13所述的显示面板，其中，所述第一通孔贯穿所述绝缘子层和所述绝缘层，所述第二通孔贯穿所述绝缘子层和所述绝缘层。
  15. 根据权利要求12所述的显示面板，其中，所述第一金属子层包括所述的第一接触部和所述第二接触部。
  16. 根据权利要求15所述的显示面板，其中，所述第三通孔贯穿所述介质层和所述绝缘子层，所述第四通孔贯穿所述介质层和所述绝缘子层。
  17. 根据权利要求11所述的显示面板，其中，所述金属层由Mo膜层或Ti/Al/Ti三层膜层组成。
  18. 根据权利要求11所述的显示面板，其中，所述金属层由Ti/Al/Ti三层膜层组成；
    所述第一接触部中与所述源极连接的Ti膜层被氧化的厚度范围为0-30纳米；
    所述第二接触部中与所述源极连接的Ti膜层被氧化的厚度范围为0-30纳米。
  19. 根据权利要求18所述的显示面板，其中，所述源极和所述第一接触部之间的电阻范围为0.01欧姆-5欧姆，所述漏极和所述第二接触部之间的电阻范围为0.01欧姆-5欧姆。
  20. 根据权利要求11所述的显示面板，其中，所述第一通孔和所述第三通孔相对设置，或所述第一通孔和所述第三通孔部分相对设置；所述第二通孔和所述第四通孔相对设置，所述第二通孔和所述第四通孔部分相对设置。
PCT/CN2019/077128 2018-12-18 2019-03-06 薄膜晶体管和显示面板 Ceased WO2020124797A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/349,624 US11189731B2 (en) 2018-12-18 2019-03-06 Thin-film transistor and display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811547021.XA CN109659357B (zh) 2018-12-18 2018-12-18 薄膜晶体管和显示面板
CN201811547021.X 2018-12-18

Publications (1)

Publication Number Publication Date
WO2020124797A1 true WO2020124797A1 (zh) 2020-06-25

Family

ID=66114754

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/077128 Ceased WO2020124797A1 (zh) 2018-12-18 2019-03-06 薄膜晶体管和显示面板

Country Status (3)

Country Link
US (1) US11189731B2 (zh)
CN (1) CN109659357B (zh)
WO (1) WO2020124797A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102508385A (zh) * 2011-11-17 2012-06-20 华映视讯（吴江）有限公司 像素结构、阵列基板及其制作方法
CN102646684A (zh) * 2012-02-17 2012-08-22 京东方科技集团股份有限公司 一种阵列基板及其制造方法和显示设备
KR20150048361A (ko) * 2013-10-28 2015-05-07 삼성디스플레이 주식회사 박막 트랜지스터, 박막 트랜지스터의 제조 방법 및 이를 포함한 유기 발광 표시 장치
CN105304722A (zh) * 2015-09-24 2016-02-03 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、显示基板、显示装置
CN107910335A (zh) * 2017-11-08 2018-04-13 武汉华星光电半导体显示技术有限公司 柔性显示面板、柔性显示面板制作方法及显示装置
US10147614B1 (en) * 2018-01-08 2018-12-04 United Microelectronics Corp. Oxide semiconductor transistor and method of manufacturing the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2002095834A1 (ja) * 2001-05-18 2004-09-09 三洋電機株式会社 薄膜トランジスタ及びアクティブマトリクス型表示装置及びそれらの製造方法
JP2004349451A (ja) * 2003-05-22 2004-12-09 Seiko Epson Corp 半導体装置及びその製造方法、電気光学装置及びその製造方法並びに電子機器
US9455337B2 (en) * 2014-06-18 2016-09-27 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
CN105742296B (zh) * 2016-03-31 2019-05-07 上海天马有机发光显示技术有限公司 一种阵列基板及其制备方法、显示面板和显示装置
DE102016218187B4 (de) * 2016-03-31 2020-12-24 Shanghai Tianma AM-OLED Co., Ltd. Array-Substrat und Herstellungsverfahren, Anzeigepaneel und Anzeigeeinrichtung
CN106684154A (zh) * 2016-12-30 2017-05-17 信利（惠州）智能显示有限公司 薄膜晶体管及其制备方法、阵列基板
CN107275350B (zh) * 2017-07-19 2020-03-10 京东方科技集团股份有限公司 阵列基板及其制作方法和显示装置
CN110164868B (zh) * 2018-02-28 2022-02-11 京东方科技集团股份有限公司 阵列基板、显示面板、显示装置及制作方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102508385A (zh) * 2011-11-17 2012-06-20 华映视讯（吴江）有限公司 像素结构、阵列基板及其制作方法
CN102646684A (zh) * 2012-02-17 2012-08-22 京东方科技集团股份有限公司 一种阵列基板及其制造方法和显示设备
KR20150048361A (ko) * 2013-10-28 2015-05-07 삼성디스플레이 주식회사 박막 트랜지스터, 박막 트랜지스터의 제조 방법 및 이를 포함한 유기 발광 표시 장치
CN105304722A (zh) * 2015-09-24 2016-02-03 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、显示基板、显示装置
CN107910335A (zh) * 2017-11-08 2018-04-13 武汉华星光电半导体显示技术有限公司 柔性显示面板、柔性显示面板制作方法及显示装置
US10147614B1 (en) * 2018-01-08 2018-12-04 United Microelectronics Corp. Oxide semiconductor transistor and method of manufacturing the same

Also Published As

Publication number Publication date
US11189731B2 (en) 2021-11-30
CN109659357B (zh) 2020-11-24
US20210184047A1 (en) 2021-06-17
CN109659357A (zh) 2019-04-19

Similar Documents

Publication Publication Date Title
CN108962946B (zh) 显示面板及其制造方法
WO2018227750A1 (zh) 柔性tft基板的制作方法
WO2018196087A1 (zh) 一种阵列基板、显示装置及其制作方法
CN106910750A (zh) 一种阵列基板、显示面板以及阵列基板的制作方法
WO2017092173A1 (zh) Tft背板结构及其制作方法
WO2013013599A1 (zh) 阵列基板及其制作方法、液晶面板、显示装置
WO2020113794A1 (zh) 显示面板及其制造方法
US20160268440A1 (en) Thin film transistor and fabrication method thereof, array substrate and display device
CN102646684A (zh) 一种阵列基板及其制造方法和显示设备
CN103715228A (zh) 阵列基板及其制造方法、显示装置
WO2018188146A1 (zh) 一种阵列基板、显示装置及其制作方法
CN107507929A (zh) Oled显示面板的柔性基底及其制备方法
CN103794652B (zh) 金属氧化物半导体薄膜晶体管及其制备方法
WO2020077785A1 (zh) 柔性显示装置
CN103018990A (zh) 一种阵列基板和其制备方法、及液晶显示装置
US11144170B2 (en) Display panel and display module
CN106920753B (zh) 薄膜晶体管及其制作方法、阵列基板和显示器
WO2016173012A1 (zh) 薄膜晶体管阵列基板及其制作方法
WO2015165174A1 (zh) 一种薄膜晶体管及其制作方法、显示基板、显示装置
WO2021003767A1 (zh) 薄膜晶体管基板的制作方法及薄膜晶体管基板
WO2020172918A1 (zh) 一种显示面板及其制作方法
WO2016033836A1 (zh) 氧化物半导体tft基板的制作方法及结构
WO2019100488A1 (zh) 背沟道蚀刻型tft基板及其制作方法
CN107863356A (zh) Tft基板及其制作方法
WO2020113856A1 (zh) 阵列基板的制备方法、阵列基板、显示面板和显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19899293

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19899293

Country of ref document: EP

Kind code of ref document: A1