WO2020119531A1

WO2020119531A1 - Surge protection circuit and terminal and surge voltage bleeding method for power interface

Info

Publication number: WO2020119531A1
Application number: PCT/CN2019/122784
Authority: WO
Inventors: 王飞
Original assignee: 中兴通讯股份有限公司
Priority date: 2018-12-14
Filing date: 2019-12-03
Publication date: 2020-06-18
Also published as: CN111327030A

Abstract

A surge protection circuit for a power interface, comprising: a surge/ESD suppression circuit (10), a fast response switch circuit (20) and a fast response voltage bleeder circuit (30), wherein one end of the surge/ESD suppression circuit (10) is separately connected to an input terminal and a control terminal of the fast response switch circuit (20), an input terminal of a power interface path, and a control terminal of the fast response voltage bleeder circuit (30); the other end of the surge/ESD suppression circuit (10) is grounded, and an output terminal of the fast response switch circuit (20) is connected to one end of the fast response voltage bleeder circuit (30) and an output terminal of a power interface circuit; and the other end of the fast response voltage bleeder circuit (30) is grounded. In addition, a surge protection terminal and a surge voltage bleeding method for the power interface are further set forth.

Description

Surge protection circuit, terminal and surge voltage discharge method of power supply interface

This disclosure requires the priority of the Chinese patent application CN201811540253.2 entitled "Surge Protection Circuits, Terminals and Surge Voltage Discharge Methods for Power Supply Interfaces" filed on December 14, 2018, the entire contents of which are incorporated by reference In this article.

Technical field

The present disclosure relates to the technical field of electronic products, and in particular, to a surge protection circuit, a terminal of a power interface, and a surge voltage relief method.

Background technique

In order to prevent possible surges from damaging electronic equipment, a transient suppression diode (TVS) is usually connected to the charging interface, and the TVS tube's avalanche breakdown effect under transient high voltage is used to discharge the surge impact , Clamp the surge voltage to a lower level, thereby protecting the charging chip of the device from injury. However, only the TVS is used to protect the power interface. Due to the presence of the clamping voltage, there will still be residual surge voltage in the power supply path. Excessive residual surge voltage may still cause damage to the charging chip. Generally, the higher the reverse turn-off voltage of the TVS, the higher its corresponding clamping voltage. However, the selection of TVS in surge protection requires a higher reverse withstand voltage capability to ensure the basic DC Withstand voltage requires lower clamping voltage, which increases the difficulty and cost of TVS production. Limited by the current process, only the trade-off between reverse turn-off voltage (VRWM) and clamping voltage (VCL) can be made, and the final result is either that the residual voltage of the surge is too high and the chip still has the risk of damage. Either the reverse turn-off voltage of the surge tube is too low (in order to ensure a lower clamping voltage), which leads to its DC withstand voltage being too low, and the surge tube is damaged (short circuit) and cannot be charged normally.

At present, there is an improved technical solution, TVS plus an independent OVP chip is used in combination, the overvoltage shutdown function of the OVP chip is used to further reduce the residual voltage of the surge to the starting voltage level of OVP. This kind of scheme not only increases the cost, but also requires the response speed and DC withstand voltage of OVP. At the same time, it sets a limit on the starting voltage of OVP (the starting voltage cannot be too high). If the starting voltage of the OVP is set too high, there is still a risk of chip damage, but if it is set too low, there may be a risk of affecting the normal charging function.

Summary of the invention

The main purpose of the present disclosure is to provide a surge protection circuit, terminal and surge voltage relief method for a power interface, aiming to achieve a simple and effective discharge of the surge voltage of the power interface.

To achieve the above object, the present disclosure provides a surge protection circuit for a power interface. The surge protection circuit for the power interface includes: a surge/ESD suppression circuit, a fast response switching circuit, and a fast response pressure relief circuit. One end of the ESD suppression circuit is connected to the input terminal and control terminal of the fast response switching circuit, the input terminal of the power interface path, and the control terminal of the quick response pressure relief circuit; the other end of the surge/ESD suppression circuit is grounded to quickly respond to the switching circuit Is connected to one end of the quick response pressure relief circuit and the output end of the power interface circuit; the other end of the quick response pressure relief circuit is grounded.

In addition, to achieve the above purpose, the present disclosure also provides a surge protection terminal for a power interface, the surge protection terminal for the power interface includes: a power interface and a surge protection circuit for the power interface, and a surge for the power interface The protection circuit includes: surge/ESD suppression circuit, fast response switch circuit, fast response pressure relief circuit, one end of the surge/ESD suppression circuit and the input terminal and control terminal of the fast response switch circuit, the input terminal of the power interface path, The control terminal of the quick response pressure relief circuit is connected; the other end of the surge/ESD suppression circuit is grounded; the output terminal of the quick response switch circuit is connected to one end of the quick response pressure relief circuit and the output terminal of the power interface circuit; the quick response pressure relief The other end of the circuit is grounded.

In addition, in order to achieve the above object, the present disclosure also provides a surge voltage relief method for a power interface. The surge voltage relief method for the power interface includes: receiving a surge voltage from an external input; a surge/ESD suppression circuit Suppress the surge voltage and obtain the residual voltage of the surge; the quick response switch circuit will automatically shut down in an instant, disconnect the connection between the input terminal of the power interface and the output terminal of the power interface, and the quick response pressure circuit automatically turns on, Short-circuit the output end of the power interface to ground to discharge the residual surge voltage.

The detection circuit of the active device of the present disclosure includes: a surge/ESD suppression circuit, a fast response switch circuit and a fast response pressure relief circuit, one end of the surge/ESD suppression circuit is respectively connected with the input terminal and control terminal of the fast response switch circuit, and the power supply The input end of the interface channel is connected to the control end of the quick response pressure relief circuit; the other end of the surge/ESD suppression circuit is grounded, the output end of the quick response switch circuit is connected to one end of the quick response pressure relief circuit, and the output end of the power interface circuit Connection; the other end of the quick response pressure relief circuit is grounded.

BRIEF DESCRIPTION

1 is a schematic structural diagram of a first embodiment of a surge protection circuit of a power interface of the present disclosure;

2 is a schematic structural diagram of a second embodiment of a surge protection circuit of a power interface of the present disclosure;

FIG. 3 is a schematic flowchart of an embodiment of a surge voltage relief method of a power interface of the present disclosure.

The realization, functional characteristics and advantages of the purpose of the present disclosure will be further described in conjunction with the embodiments and with reference to the drawings.

detailed description

It should be understood that the embodiments described herein are only used to explain the present disclosure and are not intended to limit the present disclosure.

In the subsequent description, the use of suffixes such as "module", "part" or "unit" used to denote an element is only for the benefit of the disclosure, and has no specific meaning in itself. Therefore, "module", "component" or "unit" can be used in a mixed manner.

Please refer to FIG. 1, which is a schematic structural diagram of a first embodiment of a surge protection circuit for a power interface of the present disclosure. The surge protection circuit of the power interface includes: a surge/ESD suppression circuit 10, a fast response switch circuit 20, a fast response pressure relief circuit 30, one end of the surge/ESD suppression circuit 10 and the input end of the fast response switch circuit 20, respectively Connected to the control terminal, the input terminal VIN of the power interface path, and the control terminal of the fast response pressure relief circuit 30; the other end of the surge/ESD suppression circuit 10 is grounded, the output terminal of the fast response switch circuit 20 and the fast response pressure relief circuit 30 Is connected to the output terminal VOUT of the power interface circuit; the other end of the quick response pressure relief circuit 30 is grounded.

When a surge occurs, the surge/ESD suppression circuit 10 first discharges and suppresses the surge, clamping the surge voltage to a lower level; then, the quick response switch circuit 20 will automatically turn off and off instantly. Turn on the connection between the input terminal (Vin) of the power interface and the output terminal (Vout) of the power interface; at the same time, the quick response pressure relief circuit 30 is automatically turned on, and the output terminal (Vout) of the power interface is short-circuited to the ground, so that the surge Residual pressure relief. At the end of the surge, the fast-response switch circuit 20 automatically restores the on-state, and the quick-response pressure relief circuit 20 automatically restores the off-state to ensure that the charging function is normal. In this way, the present disclosure performs triple protection against surge, which can minimize the residual voltage of the surge and greatly improve the reliability of the protection circuit. Only a limited number of discrete devices need to be added, which is simple to implement, has obvious power efficiency and lower cost. The present disclosure can simultaneously effectively protect ESD and power supply overshoot without adding additional circuits.

The detection circuit of the active device of the present disclosure includes: a surge/ESD suppression circuit, a fast response switch circuit, a fast response pressure relief circuit, one end of the surge/ESD suppression circuit and the input terminal and control terminal of the fast response switch circuit, and the power supply, respectively The input end of the interface channel is connected to the control end of the quick response pressure relief circuit; the other end of the surge/ESD suppression circuit is grounded, the output end of the quick response switch circuit is connected to one end of the quick response pressure relief circuit, and the output end of the power interface circuit Connection; the other end of the quick response pressure relief circuit is grounded. In the above way, when a surge occurs, the surge/ESD suppression circuit will first suppress the surge and clamp the surge voltage to a lower level; then, the fast response switching circuit will automatically shut down in an instant , Disconnect the connection between the input end of the power interface and the output end of the power interface; at the same time, the quick response pressure relief circuit is automatically turned on, and the output end of the power interface is short-circuited to the ground, thereby discharging the residual surge voltage. The surge/ESD suppression circuit, fast response switch circuit, and quick response pressure relief circuit perform triple suppression protection on the surge to reduce the residual voltage of the surge, thereby effectively protecting the charging chip from damage. And compared with the way of connecting a transient suppression diode at the charging interface, the present disclosure achieves triple protection against surges under the condition that the added cost is not much, and achieves the goal of effectively protecting the charging chip.

In one embodiment, referring to FIG. 2, based on the above embodiment, the surge/ESD suppression circuit includes: a transient suppression diode 11, the cathode of the transient suppression diode 11 is respectively connected to the input terminal and control of the fast response switching circuit 20 Terminal, the input terminal VIN of the power interface path, and the control terminal of the quick response pressure relief circuit 30 are connected, and the anode of the transient suppression diode 11 is grounded.

The fast response switching circuit includes: a P-channel power MOS tube 21, a first capacitor 22 and a first resistor 23, the first capacitor 22 and the first resistor 23 are connected in series, and the end of the first capacitor 22 away from the first resistor 23 is connected to Between the P-channel power MOS tube 21 and the input terminal VIN of the power interface path, the end of the first resistor 23 away from the first capacitor 22 is grounded. The source of the P-channel power MOS tube 21 is connected to the input terminal VIN, The negative electrode of the surge/ESD suppression circuit 11 is connected to one end of the first capacitor 22, the other end of the first capacitor 22 is connected to one end of the first resistor 23, the drain is connected to the output terminal VOUT of the power supply interface, and the gates are respectively The other end of the first capacitor 22 and one end of the first resistor 23 are connected, and the other end of the first resistor 23 is grounded.

The fast response pressure relief circuit 30 includes: an N-channel MOS transistor 31, a second capacitor 32 and a second resistor 33, the second capacitor 32 and the second resistor 33 are connected in series, and the end of the second resistor 33 away from the second capacitor 32 is grounded , The drain of the N-channel MOS tube 31 is connected to the output terminal VIN of the power supply interface, the drain of the P-channel power MOS tube 21, the source of the N-channel MOS tube 31 is grounded, the The gate is connected between the second capacitor 32 and the second resistor 33. The end of the second capacitor 32 away from the second resistor 33 is respectively connected to the input terminal VIN of the power supply interface, the negative electrode of the transient suppression diode 11, and the P-channel power MOS tube The source of 21 is connected to one end of the first capacitor 22.

In this embodiment, a transient suppression diode (TVS) 11 is included. By utilizing the TVS avalanche breakdown effect under transient high voltage, the transient suppression diode (TVS) 11 will discharge the surge impact and realize the surge The first protection. The implementation may also include a voltage-dividing resistor connected in series with the TVS.

The negative electrode of the transient suppression diode (TVS) 11 is connected to the input terminal (Vin, that is, the charging interface terminal, such as a USB interface) of the power supply interface, and the positive electrode of the transient suppression diode (TVS) 11 is grounded. When a surge occurs, the transient suppression diode (TVS) 11 will quickly discharge the surge, reducing the surge voltage to the clamping voltage level of the transient suppression diode (TVS) 11, such as clamping to 20V; in addition , TVS 11 also provides effective protection against ESD.

Fast response switch circuit 20: including a P-channel power MOS tube (Q1) 21, first capacitor (C1) 22 and first resistor (R1) 23, Q1 will be turned off instantaneously when a surge occurs The second protection of the surge. Among them, Q1 acts as a switch and is connected in series between the input terminal of the power interface (Vin, that is, the charging interface terminal, such as the USB interface) and the output terminal of the power interface (Vout, that is, the charging chip pin terminal); C1 and R1 form Q1 Control circuit. C1 has the characteristics of "direct-through", when the surge occurs, due to the effect of C1, the voltage of the gate (G) of Q1 is the same as the voltage of the source (S), so that Q1 enters the off state; R1 is the discharge The resistor pulls the gate (G) of Q1 low at the end of the surge, thereby allowing Q1 to return to its on state. The source (S) of Q1 is connected to the input (Vin) of the power interface, the negative electrode (C) of D1 and one end of C1, and the drain (D) of Q1 is connected to the output (Vout) of the power interface, that is, the charging chip tube The foot end) is connected, and the gate (G) of Q1 is connected to the other end of C1 and one end of R1. One end of C1 is connected to the input terminal (Vin) of the power interface, the negative electrode (C) of D1, and the source electrode (S) of Q1, and the other end of C1 is connected to one end of the gate (G) and R1 of Q1. One end of R1 is connected to the gate (G) of Q1 and the other end of C1, and the other end of R1 is grounded. The response speed of Q1 is in the order of nanoseconds, while the surge is in the order of microseconds, so Q1 can quickly respond to the surge. At the moment of the surge, the capacitor C1 has the characteristic of preventing the voltage at both ends from abruptly changing. Therefore, the voltage of the gate (G) of Q1 and the source (S) of Q1 are equivalent, so that Q1 is in the off state, thereby connecting the power supply. The output (Vout) is disconnected from the input (Vin). At the end of the surge, due to the bleed function of R1, the gate (G) of Q1 will be pulled down, so that Q1 will automatically return to the conductive state.

Quick response pressure relief circuit: including an N-channel MOS tube (Q2) 31, second capacitor (C2) 32 and second resistor (R2) 33, Q2 will be turned on instantaneously when the surge occurs, to achieve the surge Third protection.

Among them, Q2 acts as a switch and is connected in parallel to the output terminal (Vout) of the power supply interface; C2 and R2 form the control circuit of Q2. C2 has the characteristics of "direct-through", when the surge occurs, due to the effect of C2, the gate of Q2 is high, so that Q2 enters the conductive state; R2 is the bleeder resistance, Q2 will be at the end of the surge The gate of is pulled low, allowing Q2 to return to the off state. The drain (D) of Q2 is connected to the output (Vout) of the power supply interface, the drain (D) of Q1, the source (S) of Q2 is grounded, and the gate (G) of Q2 is connected to one end of C2 and R2 connection. One end of C2 is connected to the gate (G) of Q2 and one end of R2, the other end of C2 is connected to the input terminal (Vin) of the power supply interface, the negative electrode (C) of D1, the source (S) of Q1, and one end of C1 Connected. One end of R2 is connected to the gate (G) of Q2 and one end of C2, and the other end of R2 is grounded. The response speed of Q2 is in the order of nanoseconds, while the surge is in the order of microseconds, so Q2 can quickly respond to the surge. When a surge occurs, due to the action of the second capacitor C2, the gate of Q2 will be pulled high, causing Q2 to instantaneously turn on, thereby connecting the output terminal (Vout) of the power supply interface to ground to discharge the residual voltage of the surge Put, lower to 0V. At the end of the surge, the second resistor R2 will discharge the gate voltage of Q2, causing Q1 to turn off automatically.

In one embodiment, based on the above embodiment, the fast response switching circuit 20 may include: a PNP-type power transistor (not shown), a first capacitor 22 and a first resistor 23, the first capacitor 22 and the first The resistor 23 is connected in series, the end of the first capacitor 22 far away from the first resistor 23 is connected between the PNP power transistor 24 and the input terminal VIN of the power interface path, the end of the first resistance far away from the first capacitor is grounded,

The emitter of the PNP power transistor is connected to the input terminal of the power interface, the negative electrode of the surge/ESD suppression circuit, and the first capacitor one end, the other end of the first capacitor is connected to the first resistor one end, the PNP power transistor The collector of is connected to the output end of the power interface, the base of the PNP power transistor is connected to the other end of the first capacitor and the first end of the first resistor, respectively, and the other end of the first resistor is grounded.

The difference between this embodiment and the above embodiment is that the P-channel power MOS transistor in the fast response switching circuit is replaced with a PNP-type power transistor.

In an embodiment, based on the embodiment described above, the quick response pressure relief circuit may include:

An NPN transistor (not shown), a second capacitor 32 and a second resistor 33, the second capacitor 32 and the second resistor 33 are connected in series, the end of the second resistor 33 away from the second capacitor 32 is grounded, and the collector of the NPN transistor It is connected to the output of the power interface and the collector of the PNP power transistor, the emitter of the NPN transistor is grounded, the base of the NPN transistor is connected between the second capacitor and the second resistor, and the second capacitor is away from the second resistor One end of is connected to the input end of the power supply interface, the negative electrode of the transient suppression diode, the emitter of the PNP power transistor, and one end of the first capacitor.

The difference between this embodiment and the above embodiment is that the N-channel power MOS transistor in the fast response switching circuit is replaced with an NPN transistor.

In addition, an embodiment of the present disclosure also provides a surge protection terminal for a power interface. The surge protection terminal for the power interface includes: a power interface and a surge protection circuit for the power interface, and the surge protection circuit for the power interface includes ：Surge/ESD suppression circuit, fast response switching circuit, fast response pressure relief circuit, one end of the surge/ESD suppression circuit and the input terminal and control terminal of the fast response switch circuit, the input terminal of the power supply interface path, fast response relief The control terminal of the pressure circuit is connected; the other end of the surge/ESD suppression circuit is grounded, and the output terminal of the quick response switch circuit is connected to one end of the quick response pressure relief circuit and the output terminal of the power supply interface circuit; One end is grounded.

In one embodiment, the surge/ESD suppression circuit includes: a transient suppression diode, the negative electrode of the transient suppression diode and the input terminal and control terminal of the fast response switching circuit, the input terminal of the power interface path, fast In response to the control terminal connection of the pressure relief circuit, the positive pole is grounded.

In one embodiment, the fast response switching circuit includes: a P-channel power MOS transistor, a first capacitor and a first resistor, the first capacitor and the first resistor are connected in series, and the end of the first capacitor away from the first resistor is connected to P Between the channel power MOS tube and the input end of the power supply interface path, the end of the first resistor away from the first capacitor is grounded, and the source of the P-channel power MOS tube is connected to the input end of the power supply interface and the surge/ESD suppression circuit, respectively. The negative electrode is connected to one end of the first capacitor, the other end of the first capacitor is connected to one end of the first resistor, the drain is connected to the output terminal of the power supply interface, and the gate is connected to the other end of the first capacitor and the first resistor One end is connected, and the other end of the first resistor is grounded.

In one embodiment, the fast response switching circuit includes: a PNP-type power transistor, a first capacitor and a first resistor, the first capacitor and the first resistor are connected in series, and the end of the first capacitor away from the first resistor is connected to the PNP-type power Between the triode and the input end of the power supply interface path, the end of the first resistor away from the first capacitor is grounded. The emitter of the PNP power transistor is connected to the input end of the power supply interface, the negative electrode of the surge/ESD suppression circuit, and the first capacitor. One end is connected, the other end of the first capacitor is connected to one end of the first resistor, the collector of the PNP power triode is connected to the output end of the power interface, the base of the PNP power triode is connected to the other end of the first capacitor, One end of the first resistor is connected, and the other end of the first resistor is grounded.

In one embodiment, the fast response pressure relief circuit includes: an N-channel MOS transistor, a second capacitor and a second resistor, the second capacitor and the second resistor are connected in series, the end of the second resistor away from the second capacitor is grounded, NPN The collector of the transistor is connected to the output of the power interface and the collector of the PNP power transistor. The emitter of the NPN transistor is grounded. The base of the NPN transistor is connected between the second capacitor and the second resistor. The ends of the two capacitors far away from the second resistor are respectively connected to the input end of the power supply interface, the negative electrode of the transient suppression diode, the emitter of the PNP power transistor, and one end of the first capacitor.

In one embodiment, the fast response pressure relief circuit includes: an NPN transistor, a second capacitor, and a second resistor, the second capacitor and the second resistor are connected in series, the end of the second resistor away from the second capacitor is grounded, and the NPN transistor The emitter is connected to the output of the power interface and the drain of the P-channel power MOS tube, the collector of the NPN transistor is grounded, and the base of the NPN transistor is connected between the second capacitor and the second resistor. The ends of the two capacitors away from the second resistor are respectively connected to the input end of the power supply interface, the negative electrode of the transient suppression diode, the source of the P-channel power MOS tube, and one end of the first capacitor.

The surge protection circuit of the power supply interface in the surge protection terminal of the power supply interface in this embodiment is the same as that in the foregoing implementation, and is not repeated here.

In addition, an embodiment of the present disclosure also proposes a surge voltage relief method for a power interface.

Referring to FIG. 3, the surge voltage discharge method of the power interface includes: step S10, receiving an externally input surge voltage; step S20, the surge/ESD suppression circuit discharges the surge voltage to obtain a residual surge Step S30, the quick response switch circuit will be automatically turned off in an instant, disconnecting the connection between the input terminal of the power interface and the output terminal of the power interface, the quick response pressure relief circuit is automatically turned on, and the output terminal of the power interface is shorted to ground. In order to release the residual pressure of the surge.

This embodiment is based on the circuit in any of the above embodiments. During the implementation process, when a surge occurs, the surge/ESD suppression circuit first discharges the surge and clamps the surge voltage to a low Level, that is, the residual voltage of the surge is obtained; then, the quick response switch circuit will be automatically turned off in an instant, disconnecting the connection between the input terminal (Vin) and the output terminal (Vout) of the power interface; The circuit is automatically turned on, and the output terminal (Vout) of the power interface is short-circuited to the ground, so as to discharge the residual voltage of the surge. At the end of the surge, the fast-response switching circuit automatically restores the on-state, and the fast-response pressure relief circuit automatically restores the off-state to ensure that the charging function is normal. In this way, the present disclosure performs triple protection against surge, which can minimize the residual voltage of the surge and greatly improve the reliability of the protection circuit. Only a limited number of discrete devices need to be added, which is simple to implement, has obvious power efficiency and lower cost. The present disclosure can simultaneously effectively protect ESD and power supply overshoot without adding additional circuits.

The present disclosure can simply and effectively discharge the surge voltage of the power interface. In the above way, when a surge occurs, the surge/ESD suppression circuit will first suppress the surge and clamp the surge voltage to a lower level; then, the fast response switching circuit will automatically shut down in an instant , Disconnect the connection between the input end of the power interface and the output end of the power interface; at the same time, the quick response pressure relief circuit is automatically turned on, and the output end of the power interface is short-circuited to the ground, thereby discharging the residual surge voltage. The surge/ESD suppression circuit, fast response switch circuit, and quick response pressure relief circuit perform triple suppression protection on the surge to reduce the residual voltage of the surge, thereby effectively protecting the charging chip from damage. And compared with the way of connecting a transient suppression diode at the charging interface, the present disclosure achieves triple protection against surges with little added cost, and achieves the goal of effectively protecting the charging chip.

It should be noted that in this article, the terms "include", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system that includes a series of elements includes not only those elements, It also includes other elements that are not explicitly listed, or include elements inherent to this process, method, article, or system. Without more restrictions, the element defined by the sentence "include one..." does not exclude that there are other identical elements in the process, method, article or system that includes the element.

The sequence numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

The above are only the preferred embodiments of the present disclosure and do not limit the patent scope of the present disclosure. Any equivalent structure or equivalent process transformation made by using the contents of the specification and drawings of the present disclosure, or directly or indirectly used in other related technical fields , The same reason is included in the scope of patent protection of this disclosure.

Claims

A surge protection circuit for a power interface, wherein the surge protection circuit for the power interface includes: a surge/ESD suppression circuit, a fast response switching circuit, and a fast response pressure relief circuit,

One end of the surge/ESD suppression circuit is connected to the input end and control end of the fast response switching circuit, the input end of the power supply interface path, and the control end of the quick response pressure relief circuit;

The other end of the surge/ESD suppression circuit is grounded, and the output of the fast response switching circuit is connected to one end of the fast response pressure relief circuit and the output of the power interface circuit;

The other end of the quick response pressure relief circuit is grounded.
The surge protection circuit of the power interface according to claim 1, wherein the surge/ESD suppression circuit comprises:

Transient suppression diode, the cathode of the transient suppression diode is connected to the input terminal and control terminal of the fast response switching circuit, the input terminal of the power supply interface path, and the control terminal of the fast response pressure relief circuit, respectively. The positive electrode is grounded.
The surge protection circuit of the power interface according to claim 2, wherein the fast response switching circuit comprises:

P-channel power MOS tube, first capacitor and first resistor,

The first capacitor and the first resistor are connected in series. The end of the first capacitor away from the first resistor is connected between the P-channel power MOS tube and the input end of the power supply interface path. The end of the first resistor away from the first capacitor is grounded.

The source of the P-channel power MOS tube is connected to the input terminal of the power supply interface, the negative electrode of the surge/ESD suppression circuit, and one end of the first capacitor, the other end of the first capacitor is connected to the end of the first resistor, and the drain It is connected to the output end of the power supply interface, the gate is connected to the other end of the first capacitor and the one end of the first resistor, respectively, and the other end of the first resistor is grounded.
The surge protection circuit of the power interface according to claim 3, wherein the quick response pressure relief circuit comprises:

N-channel MOS tube, second capacitor and second resistor,

The second capacitor and the second resistor are connected in series, and the end of the second resistor away from the second capacitor is grounded.

The drain of the N-channel MOS tube is respectively connected to the output terminal of the power supply interface and the drain of the P-channel power MOS tube, the source of the N-channel MOS tube is grounded, and the gate of the N-channel MOS tube is connected to the second Between the capacitor and the second resistor, the end of the second capacitor away from the second resistor is connected to the input terminal of the power supply interface, the negative electrode of the transient suppression diode, the source of the P-channel power MOS tube, and the end of the first capacitor.
The surge protection circuit of the power interface according to claim 2, wherein the fast response switching circuit comprises:

PNP power transistor, first capacitor and first resistor,

The first capacitor and the first resistor are connected in series. The end of the first capacitor away from the first resistor is connected between the PNP power transistor and the input end of the power supply interface path. The end of the first resistor away from the first capacitor is grounded.

The emitter of the PNP power transistor is connected to the input terminal of the power interface, the negative electrode of the surge/ESD suppression circuit, and the first capacitor one end, the other end of the first capacitor is connected to the first resistor one end, the PNP power transistor The collector of is connected to the output end of the power interface, the base of the PNP power transistor is connected to the other end of the first capacitor and the first end of the first resistor, respectively, and the other end of the first resistor is grounded.
The surge protection circuit of the power supply interface according to claim 5, wherein the quick response pressure relief circuit comprises:

NPN transistor, second capacitor and second resistor,

The second capacitor and the second resistor are connected in series, and the end of the second resistor away from the second capacitor is grounded.

The collector of the NPN transistor is connected to the output of the power interface and the collector of the PNP power transistor, the emitter of the NPN transistor is grounded, and the base of the NPN transistor is connected between the second capacitor and the second resistor. The ends of the second capacitor away from the second resistor are respectively connected to the input end of the power supply interface, the negative electrode of the transient suppression diode, the emitter of the PNP power triode, and one end of the first capacitor.
A surge protection terminal of a power interface, wherein the surge protection terminal of the power interface includes: a power interface and a surge protection circuit of the power interface, and the surge protection circuit of the power interface includes: surge/ESD suppression Circuit, fast response switch circuit, fast response pressure relief circuit,

One end of the surge/ESD suppression circuit is connected to the input end and control end of the fast response switching circuit, the input end of the power supply interface path, and the control end of the quick response pressure relief circuit;

The other end of the surge/ESD suppression circuit is grounded, and the output of the fast response switching circuit is connected to one end of the fast response pressure relief circuit and the output of the power interface circuit;

The other end of the quick response pressure relief circuit is grounded.
The surge protection terminal of the power interface according to claim 7, wherein the surge/ESD suppression circuit comprises:

A transient suppression diode. The negative electrode of the transient suppression diode is connected to the input terminal and control terminal of the fast response switch circuit, the input terminal of the power supply interface path, and the control terminal of the fast response pressure relief circuit, respectively. The positive electrode is grounded.
The surge protection terminal of the power interface according to claim 8, wherein the fast response switching circuit comprises:

P-channel power MOS tube, first capacitor and first resistor,

The first capacitor and the first resistor are connected in series. The end of the first capacitor away from the first resistor is connected between the P-channel power MOS tube and the input end of the power supply interface path. The end of the first resistor away from the first capacitor is grounded.

The source of the P-channel power MOS tube is connected to the input terminal of the power supply interface, the negative electrode of the surge/ESD suppression circuit, and one end of the first capacitor, the other end of the first capacitor is connected to the end of the first resistor, and the drain It is connected to the output end of the power supply interface, the gate is connected to the other end of the first capacitor and the one end of the first resistor, respectively, and the other end of the first resistor is grounded.
A surge voltage relief method for a power interface, wherein the surge voltage relief method for the power interface includes:

Receive surge voltage from external input;

The surge/ESD suppression circuit discharges and suppresses the surge voltage to obtain the residual voltage of the surge;

The quick-response switch circuit will automatically shut off in an instant, disconnecting the connection between the input port of the power interface and the output port of the power interface. The residual pressure is released.