CN215733481U - Optimized reverse connection prevention protection and impact current suppression circuit - Google Patents
Optimized reverse connection prevention protection and impact current suppression circuit Download PDFInfo
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Abstract
The utility model discloses an optimized reverse connection prevention protection and impact current suppression circuit, wherein an air switch S1 is respectively connected with a first end of a power supply input end and a first end of a power supply output end, and a capacitor C2 is respectively connected with the first end and a second end of the power supply output end; the grid and the source of the MOS transistor Q1 and the grid and the source of the MOS transistor Q2 are connected with a driving circuit, and the input end of the driving circuit is connected with the first end of the power output end; the drain of the Q2 is connected with the second end of the power supply input end, the drain of the Q1 is connected with the second end of the power supply output end, the common source of the Q1 and the Q2, and the source and the drain of the Q1 are connected with a resistor R2 in parallel. Can effectively restrain the start-up in the twinkling of an eye generating line impulse current for MOS pipe closes to zero voltage and switches on through adjusting RC charging time constant, reduces the electric stress when MOS pipe switches on, makes MOS pipe lectotype not receive safe work area's restriction, possesses the protection function of preventing reverse connection simultaneously.
Description
Technical Field
The utility model relates to the technical field of electronic equipment, in particular to an optimized reverse connection prevention protection and impact current suppression circuit.
Background
In the electronic equipment, due to the existence of a large number of capacitive devices, at the moment of starting up the power supply, a capacitor is equivalent to a short circuit, and when the capacitor is charged, a large impact current can be generated on a power supply bus of the capacitor, and the impact current can damage a front-stage circuit device or trigger overcurrent protection of the front-stage power supply, so that the rear-stage equipment cannot work normally, and therefore the impact current needs to be restrained. The impact current is specifically required in the GJB181B-2012 aircraft supply characteristic 5.4.9: and cannot exceed 5 times of rated current. The current surge current suppression circuit which is widely used is a series resistor or a thermistor using negative temperature characteristics. However, the series resistor can work for a long time, and the overall efficiency of the power supply is reduced; the thermistor with negative temperature characteristic has the defects that the temperature rises and the resistance value drops after long-time work, and the thermistor fails when being started in a hot state. The method for restraining the impulse current by using the characteristic of the varistor region of the MOS tube has higher requirement on the safe working region of the MOS tube, and the MOS tube is easily damaged when the type is not selected properly. Meanwhile, many standards require reverse polarity on the input end of the electric equipment, for example, in the GJB181B-2012 airplane power supply characteristic 5.4.6, the direct-current electric equipment is required not to be damaged due to reverse connection of the positive line and the negative line. The MIL-STD-704 aircraft power supply characteristics HDC602 and LDC602 provide that dc consumers are not damaged when the power supply input exhibits reverse polarity. The anti-reverse-connection protection circuit widely applied at present is to serially connect a power diode in a power loop for anti-reverse-connection protection. The diode has large conduction voltage drop and is not suitable for being applied to large-current electric equipment.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide an optimized reverse connection prevention protection and impact current suppression circuit, which is used for solving the problem that a reverse connection prevention protection circuit in the prior art is used for performing reverse connection prevention protection by connecting a power diode in series in a power loop. The conduction voltage drop of the diode is large, and the diode is not suitable for being applied to large-current electric equipment.
The utility model solves the problems through the following technical scheme:
an optimized reverse connection prevention protection and impact current suppression circuit comprises an air switch S1, a MOS tube Q1, a MOS tube Q2, a capacitor C2 and a driving circuit for driving the MOS tube Q1 and the MOS tube Q2, wherein the air switch S1 is respectively connected with a first end of a power supply input end and a first end of a power supply output end, and the capacitor C2 is respectively connected with the first end and a second end of the power supply output end; the grid and the source of the MOS transistor Q1 and the grid and the source of the MOS transistor Q2 are connected with the driving circuit, and the input end of the driving circuit is connected with the first end of the power output end; the drain electrode of MOS pipe Q2 is connected with the second end of power input end, the drain electrode of MOS pipe Q1 is connected with the second end of power output end, MOS pipe Q1 and the common source of MOS pipe Q2, and parallel resistance R2 is connected between the source electrode and the drain electrode of MOS pipe Q1.
The driving circuit comprises a resistor R1 with a first end connected with the first end of the power output end, a second end of the resistor R1 is respectively connected with the first end of a resistor R3, the first end of a voltage stabilizing diode D1, the first end of a capacitor C1, the grid of a MOS transistor Q2 and the grid of a MOS transistor Q1, and the source of the MOS transistor Q2 and the source of the MOS transistor Q1 are connected with the second end of a resistor R3, the second end of the voltage stabilizing diode D1 and the second end of a capacitor C1.
The whole circuit has two working states of transient state and steady state, wherein the power-on process of the input end belongs to the transient working state, and then belongs to the steady state working state.
In a steady state operation, the resistor R1 and the resistor R3 form a voltage divider circuit, and the zener diode D1 is used to clamp the voltage across the resistor R3, thereby protecting the MOS transistor from being damaged by an excessively high voltage across the G-S. The voltage at the two ends of the resistor R3 is used for driving the MOS transistor Q1 and the MOS transistor Q2 to be conducted and operated in a steady state, at the moment, the MOS transistor Q1 and the MOS transistor Q2 are completely conducted, and the rear-end equipment works normally;
in a transient working state, when the air switch S1 is suddenly closed, the resistor R1 and the capacitor C1 form an RC charging circuit to charge the capacitor C1 connected in parallel to the two ends of the MOS transistor Q1G-S, the voltage across the capacitor C1 is a MOS transistor driving voltage, and since the RC charging circuit has a voltage delay effect, the MOS transistor driving voltage will rise slowly, the MOS transistor will be turned on in a delayed manner, and the delay time is determined by the time constants of the resistor R1 and the capacitor C1. In the process before the MOS tube is conducted, the power supply charges a rear-end capacitor C2 through a resistor R2 and a body diode of the MOS tube Q2, and further the starting surge current is restrained.
A resistor R4 is connected between the first end of the voltage stabilizing diode D1 and the first end of the capacitor C1.
In a steady-state operation state, the resistor R1 and the resistor R3 form a voltage divider circuit, and the zener diode D1 is used to clamp the voltage across the resistor R3, so as to protect the MOS transistor from being damaged by an excessively high voltage across the G-S of the Q2. The voltage across the resistor R3 is used for driving the MOS transistor Q2 to conduct in a steady state, and at the moment, the MOS transistor Q2 is completely conducted. The resistor R4 is connected in series between the gates of the MOS transistors Q2 and Q1, and although there is a voltage drop, the voltage across the capacitor C1 can be higher than the turn-on threshold voltage of the MOS transistor Q2 in the full input voltage range by selecting the resistance value of the resistor R4, and at this time, the MOS transistor Q2 is also completely turned on.
In a transient operating state, when the air switch S1 is suddenly closed, the resistor R1 and the resistor R3 form a voltage divider circuit, so that the voltage at the two ends of the resistor R3 is higher than the start threshold voltage of the MOS transistor Q1, the MOS transistor Q2 is instantly and completely turned on, and the zener diode D1 clamps the voltage at the two ends of the resistor R3 to protect the MOS transistor. And the resistor R1, the resistor R4 and the capacitor C1 form an RC charging circuit to charge the capacitor C1 connected in parallel to the two ends of the grid of the MOS transistor Q1, so that the driving voltage of the MOS transistor Q1 rises slowly and is delayed to be conducted, and the delay time is determined by the time constants of the resistor R1, the resistor R4 and the capacitor C1. Before the MOS tube is conducted, the power supply charges a rear-end capacitor C2 through a resistor R2 and the MOS tube Q1, and further starting impact current is restrained.
When the positive line and the negative line of the input end are reversely connected, the body diode of the MOS tube Q2 is reversely cut off, so that the rear-stage circuit is protected, and the reverse connection prevention protection effect is achieved.
The driving circuit comprises a second driving circuit for driving a MOS tube Q2 and a first driving circuit for driving a MOS tube Q1, wherein the second driving circuit comprises a resistor R1 'of which the first end is connected with the first end of the power output end, and the second end of the resistor R1' is respectively connected with the first end of a resistor R3 ', the first end of a voltage stabilizing diode D1' and the grid electrode of a MOS tube Q2; a second end of the resistor R3 'and a second end of the voltage stabilizing diode D1' are connected with a source electrode of the MOS transistor Q2; the first driving circuit comprises a resistor R4 ' with a first end connected with the first end of the power output end, and a second end of a resistor R4 ' is respectively connected with the first end of a resistor R5, the first end of a voltage stabilizing diode D2, the first end of a capacitor C1 ' and the grid electrode of a MOS transistor Q1; the second end of the resistor R5, the second end of the capacitor C1' and the second end of the zener diode D2 are connected to the source of the MOS transistor Q1.
The driving circuits of the MOS transistor Q1 and the MOS transistor Q2 are respectively and independently arranged, when the circuit works in a steady state, the resistor R1 and the resistor R3 form a voltage division circuit, and the voltage stabilizing diode D1 is used for clamping the voltage at two ends of the resistor R3 and protecting the MOS transistor so as to prevent the voltage at two ends of G-S of the MOS transistor Q2 from being damaged due to overhigh voltage. The voltage across the resistor R3 is used for driving the MOS transistor Q2 to conduct in a steady state, and at the moment, the MOS transistor Q2 is completely conducted. The resistor R4 and the resistor R5 form a voltage divider circuit, and the zener diode D2 is used to clamp the voltage across the resistor R5, and protect the MOS transistor from being damaged by the excessive voltage across the G-S of the Q1. The voltage across the resistor R5 is used for driving the MOS transistor Q1 to conduct in a steady state, and at the moment, the MOS transistor Q1 is completely conducted.
In a transient operating state, when the air switch S1 is suddenly closed, the resistor R1 and the resistor R3 form a voltage divider circuit, so that the voltage at the two ends of the resistor R3 is higher than the start threshold voltage of the MOS transistor Q1, the MOS transistor Q2 is instantly and completely turned on, and the zener diode D1 clamps the voltage at the two ends of the resistor R3 to protect the MOS transistor. And the resistor R4 and the capacitor C1 form an RC charging circuit to charge the capacitor C1 connected in parallel with the two ends of the grid of the MOS transistor Q1, so that the driving voltage of the MOS transistor Q1 slowly rises and the conduction is delayed, and the delay time is determined by the time constant of the resistor R4 and the capacitor C1. Before the MOS transistor Q1 is conducted, the power supply charges a rear-end capacitor C2 through a resistor R2 and the MOS transistor Q2, and further starting impact current is restrained.
When the positive line and the negative line of the input end are reversely connected, the body diode of the MOS tube Q2 is reversely cut off, so that the rear-stage circuit is protected, and the reverse connection prevention protection effect is achieved.
The first end of power input end is anodal input, and power input end's second end is negative input end, and power output end's first end is anodal output, and power output end's second end is negative output end, MOS pipe Q1 and MOS pipe Q2 are N channel MOSFET.
The first end of power input end is negative pole input, and power input end's second end is anodal input, and power output end's first end is negative pole output, and power output end's second end is anodal output, MOS pipe Q1 and MOS pipe Q2 are P channel MOSFET.
Compared with the prior art, the utility model has the following advantages and beneficial effects:
(1) the utility model can effectively inhibit the bus impact current at the moment of starting up, and the MOS tube is close to zero voltage conduction by adjusting the RC charging time constant of the MOS tube, thereby reducing the current stress when the MOS tube is conducted, avoiding the limitation of a safe working area when the MOS tube is selected, and ensuring that the MOS tube is completely conducted before the rear-stage power module is started. Meanwhile, the anti-reverse connection protection function is achieved.
(2) The utility model can lead the MOS tube to be conducted at a proper time point by adjusting the time constant of capacitor charging between the grid and the source of the MOS tube, can inhibit the instant impact current of starting, can lead the MOS tube to be conducted when the charging of a rear-stage capacitor is close to the input voltage, can reduce the current stress of the MOS tube, can lead the MOS tube not to be limited by a safe working area when the MOS tube is selected, and can ensure that the MOS tube is completely conducted before a rear-stage power module is started. Because the selection of the MOS tube with the impact current suppression and the reverse connection prevention protection is not limited by the safe working area, the MOS tube with the minimum conduction resistance can be selected, the conduction loss is reduced, and the efficiency and the reliability are improved.
(3) The utility model can select the impact current suppression and reverse connection prevention protection circuit suitable for the power supply positive line or the power supply negative line according to the application occasions.
Drawings
FIG. 1 is a schematic circuit diagram of a first embodiment of the present invention;
FIG. 2 is a diagram of an equivalent circuit of the MOS of FIG. 1 before charging;
FIG. 3 is a circuit schematic of a second embodiment of the present invention;
FIG. 4 is a circuit schematic of a third embodiment of the present invention;
FIG. 5 is a circuit schematic of a fourth embodiment of the present invention;
FIG. 6 is a schematic circuit diagram of a fifth embodiment of the present invention;
fig. 7 is a schematic circuit diagram of a sixth embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to examples, but the embodiments of the present invention are not limited thereto.
Example (b):
referring to fig. 1, an optimized reverse connection prevention protection and impact current suppression circuit includes an air switch S1, a MOS transistor Q1, a MOS transistor Q2, a capacitor C2, and a driving circuit for driving the MOS transistor Q1 and the MOS transistor Q2, where the air switch S1 is connected to a first end of a power input end and a first end of a power output end, and the capacitor C2 is connected to the first end and a second end of the power output end, respectively; the grid and the source of the MOS transistor Q1 and the grid and the source of the MOS transistor Q2 are connected with the driving circuit, and the input end of the driving circuit is connected with the first end of the power output end; the drain electrode of MOS pipe Q2 is connected with the second end of power input end, the drain electrode of MOS pipe Q1 is connected with the second end of power output end, MOS pipe Q1 and the common source of MOS pipe Q2, and parallel resistance R2 is connected between the source electrode and the drain electrode of MOS pipe Q1.
The driving circuit comprises a resistor R1 with a first end connected with a first end of a power output end, a second end of the resistor R1 is respectively connected with a first end of a resistor R3, a first end of a voltage stabilizing diode D1, a first end of a capacitor C1, a grid of a MOS transistor Q2 and a grid of a MOS transistor Q1, and a source of the MOS transistor Q2 and a source of the MOS transistor Q1 are connected with a second end of a resistor R3, a second end of the voltage stabilizing diode D1 and a second end of a capacitor C1;
the first end of power input end is anodal input, and power input end's second end is negative input end, and power output end's first end is anodal output, and power output end's second end is negative output end, MOS pipe Q1 and MOS pipe Q2 are N channel MOSFET.
The whole circuit has two working states of transient state and steady state, wherein the power-on process of the input end belongs to the transient working state, and then belongs to the steady state working state.
In a steady state operation, the resistor R1 and the resistor R3 form a voltage divider circuit, and the zener diode D1 is used to clamp the voltage across the resistor R3, thereby protecting the MOS transistor from being damaged by an excessively high voltage across the G-S. The voltage at the two ends of the resistor R3 is used for driving the MOS transistor Q1 and the MOS transistor Q2 to be conducted and operated in a steady state, at the moment, the MOS transistor Q1 and the MOS transistor Q2 are completely conducted, and the rear-end equipment works normally;
in a transient working state, when the air switch S1 is suddenly closed, the resistor R1 and the capacitor C1 form an RC charging circuit to charge the capacitor C1 connected in parallel to the two ends of the MOS transistor Q1G-S, the voltage across the capacitor C1 is a MOS transistor driving voltage, and since the RC charging circuit has a voltage delay effect, the MOS transistor driving voltage will rise slowly, the MOS transistor will be turned on in a delayed manner, and the delay time is determined by the time constants of the resistor R1 and the capacitor C1. In the process before the MOS tube is conducted, the power supply charges a rear-end capacitor C2 through a resistor R2 and a body diode of the MOS tube Q2, and further the starting surge current is restrained.
Before the MOS transistor Q1 is turned on, the power source charges the rear capacitor C2 through the R2 and the body diode D of the MOS transistor Q2, and the resistor R2 and the capacitor C2 form an RC charging loop, which is shown in fig. 2 as an equivalent schematic diagram. According to the charge formula of the capacitor:
uC＝US*[1-Exp(-t/τ2)] (1)
in the formula uCIs the voltage across the capacitor C2, Us is the input DC voltage, τ1Is a charging time constant, τ1R2 × C2, R2 is the charging resistor, and C2 is the post capacitor.
According to equation (1) and fig. 2, it can be calculated that the capacitor voltage will be charged to 95% of the input voltage after 3 time constants; after 5 time constants, the capacitor voltage will be charged to 99% of the input voltage.
From the above analysis, it can be seen that: the smaller the charging resistor R2, the faster the charging speed of the post-stage capacitor C2, and on the premise that the MOS transistor on-time is determined (i.e., the MOS gate voltage charging time constant is determined), the higher the voltage across C2 when the MOS is turned on, and the lower the voltage across the MOS drain-source, the smaller the current at the moment of turning on.
Before the MOS tube is conducted, the peak value of the charging current is determined by R2. The maximum surge current at the rated input voltage can be determined according to the rated input current, and then the value of R3 can be calculated.
R2＝US/Ilmt (2)
In the formula IlmtThe required limit current value is 5 times of the rated working current.
The capacitor C2 includes the line-to-line capacitance in the filter and the input filter capacitance in the subsequent system device or power module.
From the above analysis, the charging time constant τ of the capacitor C2 is shown1R2 × C2, the time required for the capacitor voltage to be charged close to the input voltage is 5 τ1＝5R2*C2。
In order to suppress the startup surge current, the MOS transistor should be completely turned on after the filter capacitor is fully charged and before the power module is started by adjusting the charging time constant of the gate capacitor of the MOS transistor, according to the charging formula of the capacitor:
Ug＝US*[1-Exp(-t/τ1)] (3)
in the formula of USIs an input voltage ugIs the voltage, tau, across the MOS transistor G-S capacitor C12Charging time constant, tau, for the gate capacitance of a MOS transistor2R1 × C1, R1 is the charging resistor, and C1 is the GS capacitor. This can be derived from equation (3): charging the GS capacitor of the MOS tube to the time constant multiple required by the MOS tube when the threshold voltage of the MOS tube is opened to 3.5V, and marking as N tau2. Therefore, the method comprises the following steps:
5τ1<N*τ2 (4)
the charging time constant of the gate capacitor of the MOS transistor can be calculated. After the allowance is reserved, the type of the MOS transistor grid capacitor C1 and the type of the charging resistor R1 can be selected.
When the positive line and the negative line of the input end are reversely connected, the body diode of the MOS tube Q2 is reversely cut off, so that the rear-stage circuit is protected, and the reverse connection prevention protection effect is achieved. The MOS transistor Q2 can be free from the limit value of a safe working area during model selection, and the MOS transistor with the minimum on-resistance can be selected to reduce the power loss during normal work under the condition of meeting the requirement of reverse connection voltage.
Example 2:
on the basis of embodiment 1, as shown in fig. 3, a resistor R4 is connected between the first end of the zener diode D1 and the first end of the capacitor C1.
In a steady-state operation state, the resistor R1 and the resistor R3 form a voltage divider circuit, and the zener diode D1 is used to clamp the voltage across the resistor R3, so as to protect the MOS transistor from being damaged by an excessively high voltage across the G-S of the Q2. The voltage across the resistor R3 is used for driving the MOS transistor Q2 to conduct in a steady state, and at the moment, the MOS transistor Q2 is completely conducted. The resistor R4 is connected in series between the gates of the MOS transistors Q2 and Q1, and although there is a voltage drop, the voltage across the capacitor C1 can be higher than the turn-on threshold voltage of the MOS transistor Q2 in the full input voltage range by selecting the resistance value of the resistor R4, and at this time, the MOS transistor Q2 is also completely turned on.
In a transient operating state, when the air switch S1 is suddenly closed, the resistor R1 and the resistor R3 form a voltage divider circuit, so that the voltage at the two ends of the resistor R3 is higher than the start threshold voltage of the MOS transistor Q1, the MOS transistor Q2 is instantly and completely turned on, and the zener diode D1 clamps the voltage at the two ends of the resistor R3 to protect the MOS transistor. And the resistor R1, the resistor R4 and the capacitor C1 form an RC charging circuit to charge the capacitor C1 connected in parallel to the two ends of the grid of the MOS transistor Q1, so that the driving voltage of the MOS transistor Q1 rises slowly and is delayed to be conducted, and the delay time is determined by the time constants of the resistor R1, the resistor R4 and the capacitor C1. Before the MOS tube is conducted, the power supply charges a rear-end capacitor C2 through a resistor R2 and the MOS tube Q1, and further starting impact current is restrained.
When the positive line and the negative line of the input end are reversely connected, the body diode of the MOS tube Q2 is reversely cut off, so that the rear-stage circuit is protected, and the reverse connection prevention protection effect is achieved.
Example 3:
as shown in fig. 4, an optimized anti-reverse connection protection and surge current suppression circuit includes an air switch S1, a MOS transistor Q1, a MOS transistor Q2, a capacitor C2, and a driving circuit for driving the MOS transistor Q1 and the MOS transistor Q2, where the air switch S1 is connected to a first end of a power input end and a first end of a power output end respectively, and the capacitor C2 is connected to the first end and a second end of the power output end respectively; the grid and the source of the MOS transistor Q1 and the grid and the source of the MOS transistor Q2 are connected with the driving circuit, and the input end of the driving circuit is connected with the first end of the power output end; the drain electrode of the MOS transistor Q2 is connected with the second end of the power supply input end, the drain electrode of the MOS transistor Q1 is connected with the second end of the power supply output end, the MOS transistor Q1 and the MOS transistor Q2 share a common source, and a resistor R2 is connected between the source electrode and the drain electrode of the MOS transistor Q1 in parallel; the driving circuit comprises a second driving circuit for driving a MOS tube Q2 and a first driving circuit for driving a MOS tube Q1, wherein the second driving circuit comprises a resistor R1 'of which the first end is connected with the first end of the power output end, and the second end of the resistor R1' is respectively connected with the first end of a resistor R3 ', the first end of a voltage stabilizing diode D1' and the grid electrode of a MOS tube Q2; a second end of the resistor R3 'and a second end of the voltage stabilizing diode D1' are connected with a source electrode of the MOS transistor Q2; the first driving circuit comprises a resistor R4 ' with a first end connected with the first end of the power output end, and a second end of a resistor R4 ' is respectively connected with the first end of a resistor R5, the first end of a voltage stabilizing diode D2, the first end of a capacitor C1 ' and the grid electrode of a MOS transistor Q1; the second end of the resistor R5, the second end of the capacitor C1' and the second end of the zener diode D2 are connected with the source electrode of the MOS transistor Q1; the first end of power input end is anodal input, and power input end's second end is negative input end, and power output end's first end is anodal output, and power output end's second end is negative output end, MOS pipe Q1 and MOS pipe Q2 are N channel MOSFET.
The driving circuits of the MOS transistor Q1 and the MOS transistor Q2 are respectively and independently arranged, when the circuit works in a steady state, the resistor R1 'and the resistor R3' form a voltage division circuit, and the voltage stabilizing diode D1 'is used for clamping the voltage at two ends of the resistor R3', so that the MOS transistor is protected to avoid the damage caused by overhigh voltage at two ends of G-S of the MOS transistor Q2. The voltage across the resistor R3' is used for driving the MOS transistor Q2 to conduct in a steady state, and at the moment, the MOS transistor Q2 is completely conducted. The resistor R4' and the resistor R5 form a voltage divider circuit, and the zener diode D2 is used to clamp the voltage across the resistor R5, protecting the MOS transistor from being damaged by the excessive voltage across the G-S of the Q1. The voltage across the resistor R5 is used for driving the MOS transistor Q1 to conduct in a steady state, and at the moment, the MOS transistor Q1 is completely conducted.
In a transient operating state, when the air switch S1 is suddenly closed, the resistor R1 ' and the resistor R3 ' form a voltage dividing circuit, so that the voltage at the two ends of the resistor R3 ' is higher than the start threshold voltage of the MOS transistor Q1, the MOS transistor Q2 is instantly and completely turned on, and the zener diode D1 ' clamps the voltage at the two ends of the resistor R3 ' to protect the MOS transistor. And the resistor R4 and the capacitor C1 ' form an RC charging circuit to charge the capacitor C1 ' connected in parallel with the two ends of the grid of the MOS transistor Q1, so that the driving voltage of the MOS transistor Q1 slowly rises and is delayed to be conducted, and the delay time is determined by the time constant of the resistor R4 and the capacitor C1 '. Before the MOS transistor Q1 is conducted, the power supply charges a rear-end capacitor C2 through a resistor R2 and the MOS transistor Q2, and further starting impact current is restrained.
When the positive line and the negative line of the input end are reversely connected, the body diode of the MOS tube Q2 is reversely cut off, so that the rear-stage circuit is protected, and the reverse connection prevention protection effect is achieved.
The first end of power input end is anodal input, and power input end's second end is negative input end, and power output end's first end is anodal output, and power output end's second end is negative output end, MOS pipe Q1 and MOS pipe Q2 are N channel MOSFET.
Example 4:
the inrush current suppression and reverse-connection prevention protection circuit in embodiment 1 can also be widely applied to a power supply positive line, as shown in fig. 5.
The inrush current suppression and reverse-connection prevention protection circuit in embodiment 2 can also be widely applied to the power supply positive line, as shown in fig. 6.
The inrush current suppression and reverse-connection prevention protection circuit in embodiment 3 can also be widely applied to the power supply positive line, as shown in fig. 7.
Namely, the first end of the power input end is a negative input end, the second end of the power input end is a positive input end, the first end of the power output end is a negative output end, the second end of the power output end is a positive output end, and the MOS transistor Q1 and the MOS transistor Q2 are P-channel MOSFETs.
Although the present invention has been described herein with reference to the illustrated embodiments thereof, which are intended to be preferred embodiments of the present invention, it is to be understood that the utility model is not limited thereto, and that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure.
Claims (6)
1. An optimized anti-reverse connection protection and impact current suppression circuit is characterized by comprising an air switch S1, a MOS tube Q1, a MOS tube Q2, a capacitor C2 and a driving circuit for driving the MOS tube Q1 and the MOS tube Q2, wherein the air switch S1 is respectively connected with a first end of a power supply input end and a first end of a power supply output end, and the capacitor C2 is respectively connected with the first end and a second end of the power supply output end; the grid and the source of the MOS transistor Q1 and the grid and the source of the MOS transistor Q2 are connected with the driving circuit, and the input end of the driving circuit is connected with the first end of the power output end; the drain electrode of MOS pipe Q2 is connected with the second end of power input end, the drain electrode of MOS pipe Q1 is connected with the second end of power output end, MOS pipe Q1 and the common source of MOS pipe Q2, and parallel resistance R2 is connected between the source electrode and the drain electrode of MOS pipe Q1.
2. The optimized reverse-connection-prevention protection and surge current suppression circuit as claimed in claim 1, wherein the driving circuit comprises a resistor R1 having a first end connected with the first end of the power output end, a second end of the resistor R1 is respectively connected with the first end of the resistor R3, the first end of the zener diode D1, the first end of the capacitor C1, the gate of the MOS transistor Q2 and the gate of the MOS transistor Q1, and the source of the MOS transistor Q2 and the source of the MOS transistor Q1 are connected with the second end of the resistor R3, the second end of the zener diode D1 and the second end of the capacitor C1.
3. The optimized reverse-connection prevention protection and surge current suppression circuit as claimed in claim 2, wherein a resistor R4 is connected between the first end of the zener diode D1 and the first end of the capacitor C1.
4. The optimized reverse-connection prevention protection and surge current suppression circuit as claimed in claim 1, wherein the driving circuit comprises a second driving circuit for driving a MOS transistor Q2 and a first driving circuit for driving a MOS transistor Q1, the second driving circuit comprises a resistor R1 'having a first end connected to the first end of the power output terminal, and a second end of the resistor R1' is respectively connected to the first end of a resistor R3 ', the first end of a zener diode D1' and the gate of a MOS transistor Q2; a second end of the resistor R3 'and a second end of the voltage stabilizing diode D1' are connected with a source electrode of the MOS transistor Q2; the first driving circuit comprises a resistor R4 ' with a first end connected with the first end of the power output end, and a second end of a resistor R4 ' is respectively connected with the first end of a resistor R5, the first end of a voltage stabilizing diode D2, the first end of a capacitor C1 ' and the grid electrode of a MOS transistor Q1; the second end of the resistor R5, the second end of the capacitor C1' and the second end of the zener diode D2 are connected to the source of the MOS transistor Q1.
5. The optimized reverse-connection prevention protection and surge current suppression circuit according to any one of claims 1-4, wherein the first terminal of the power input terminal is a positive input terminal, the second terminal of the power input terminal is a negative input terminal, the first terminal of the power output terminal is a positive output terminal, the second terminal of the power output terminal is a negative output terminal, and the MOS transistor Q1 and the MOS transistor Q2 are N-channel MOSFETs.
6. The optimized reverse-connection prevention protection and surge current suppression circuit according to any one of claims 1-4, wherein the first terminal of the power input terminal is a negative input terminal, the second terminal of the power input terminal is a positive input terminal, the first terminal of the power output terminal is a negative output terminal, the second terminal of the power output terminal is a positive output terminal, and the MOS transistor Q1 and the MOS transistor Q2 are P-channel MOSFETs.
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| CN202122208559.1U CN215733481U (en) | 2021-09-13 | 2021-09-13 | Optimized reverse connection prevention protection and impact current suppression circuit |
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| CN202122208559.1U CN215733481U (en) | 2021-09-13 | 2021-09-13 | Optimized reverse connection prevention protection and impact current suppression circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115313345A (en) * | 2022-10-12 | 2022-11-08 | 成都新欣神风电子科技有限公司 | Reverse connection prevention protection circuit for direct-current power supply |
| CN115513930A (en) * | 2022-10-27 | 2022-12-23 | 北京瀚海科技有限公司 | Power-on protection circuit for fan |
-
2021
- 2021-09-13 CN CN202122208559.1U patent/CN215733481U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115313345A (en) * | 2022-10-12 | 2022-11-08 | 成都新欣神风电子科技有限公司 | Reverse connection prevention protection circuit for direct-current power supply |
| CN115513930A (en) * | 2022-10-27 | 2022-12-23 | 北京瀚海科技有限公司 | Power-on protection circuit for fan |
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