CN213879275U

CN213879275U - Circuit for limiting impact current

Info

Publication number: CN213879275U
Application number: CN202022989052.XU
Authority: CN
Inventors: 张培艳
Original assignee: CIG Shanghai Co Ltd
Current assignee: CIG Shanghai Co Ltd
Priority date: 2020-12-11
Filing date: 2020-12-11
Publication date: 2021-08-03
Anticipated expiration: 2030-12-11

Abstract

The utility model discloses a limit impulse current's circuit, including resistance R1, R2, R3, R4, electric capacity C1, C2, C3, diode D1, D2 and MOS pipe Q1, resistance R1, parallelly connected between power input positive and negative ends behind the R2 series connection, resistance R3, one end is connected with power input positive terminal behind the R4 series connection, the other end is connected with MOS pipe Q1's grid, MOS pipe Q1's source and drain-source are connected with power input negative terminal, electric capacity C2, C3 connect in parallel respectively between power output positive and negative terminals, diode D1's positive pole is connected with resistance R3, the negative pole is connected with resistance R1, electric capacity C1's one end is connected with diode D1's negative pole, the other end is connected with power input negative terminal, diode D2's positive pole is connected with power input negative terminal, the negative pole is connected with resistance R3. The utility model discloses utilize MOS pipeline nature to open the district, a small amount of components and parts of cooperation can restrict impulse current, and the circuit is simple, and is with low costs, and shared area is little, is applicable to present complicated circuit board and arranges day by day.

Description

Circuit for limiting impact current

Technical Field

The utility model relates to an electric power tech field especially relates to a restriction impulse current's circuit.

Background

When the switching power supply is turned on, a surge current is inevitably generated because the capacitor is charged. The excessive rush current causes a series of problems, such as fuse blowing, instantaneous drop of input voltage waveform, and even instantaneous overload of power supply equipment. To avoid these problems, effective surge current limiting measures must be taken.

The commonly used method for inhibiting the impact current is to connect a negative temperature coefficient thermal current limiting resistor (NTC) in series, and the characteristics that the resistance is large in a cold state, so that the overlarge current can be limited, and after the circuit is started, the NTC is heated by the current, the temperature of the body rises, and the impedance is reduced are utilized. Although the method is simple, the method has the problems that the resistance value is not low enough in a hot state, the loss is large, and the method cannot be applied to a large-power scene, and in the process of repeatedly switching on and switching off, the NTC temperature is high, so that the current limiting effect cannot be achieved. Therefore, it is necessary to provide a further solution to the above problems.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a restriction impulse current's circuit to overcome the not enough that exists among the prior art.

In order to solve the technical problem, the technical scheme of the utility model is that:

a circuit for limiting impact current comprises resistors R1, R2, R3 and R4, capacitors C1, C2 and C3, diodes D1 and D2 and an MOS tube Q1, wherein the resistors R1 and R2 are connected in series and then connected in parallel between positive and negative ends of a power input, one end of each resistor R3 and R4 is connected in series and then connected with the positive end of the power input, the other end of each resistor R1 is connected with the grid of the MOS tube Q1, the source and the drain of the MOS tube Q1 are connected with the negative end of the power input, the capacitors C2 and C3 are connected in parallel between the positive and negative ends of the power output, the anode of the diode D1 is connected with the resistor R3, the cathode of the diode R1, one end of the capacitor C1 is connected with the cathode of the diode D1, the other end of the capacitor C1 is connected with the negative end of the power input, the anode of the diode D2 is connected with the negative end of the power input, and the cathode of the resistor R3 are connected with the resistor R3.

In a preferred embodiment of the present invention, the diode D2 is a 12V voltage regulator.

In a preferred embodiment of the present invention, the MOS transistor Q1 is an N-MOS transistor.

In a preferred embodiment of the present invention, the diode D1 is a schottky diode.

Compared with the prior art, the beneficial effects of the utility model are that:

the utility model discloses utilize MOS pipeline nature to open the district, a small amount of components and parts of cooperation can restrict impulse current, the circuit is simple, low cost, the shared area is little, be applicable to present complicated circuit board and arrange day by day, simultaneously, negative temperature coefficient temperature sensing current limiting resistor (NTC) has effectively been solved and has been influenced great problem by temperature factor, MOS intraductal resistance RDS (on) is little moreover, resistance is little when drain electrode and source electrode switch on promptly, thereby it is too big to have solved the loss that NTC leads to, use the limited problem of scene.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a circuit diagram of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention more clearly understood, the present invention will be described in further detail with reference to the accompanying drawings and detailed description. It should be noted that the embodiments and features of the embodiments of the present application may be combined with each other without conflict.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and therefore the scope of the present invention is not limited by the specific embodiments disclosed below.

As shown in fig. 1, a circuit for limiting a surge current includes resistors R1, R2, R3, R4, capacitors C1, C2, C3, diodes D1, D2, and a MOS transistor Q1, wherein the resistors R1, R2 are connected in series and then connected in parallel between positive and negative power input terminals, the resistors R3, R4 are connected in series and then have one end connected to the positive power input terminal and the other end connected to the gate of the MOS transistor Q1, the source and drain of the MOS transistor Q1 are connected to the negative power input terminal, the capacitors C2, C3 are connected in parallel between the positive and negative power output terminals, the anode of the diode D1 is connected to the resistor R3, the cathode is connected to the resistor R1, one end of the capacitor C1 is connected to the cathode of the diode D1, the other end is connected to the negative power input terminal, the anode of the diode D2 is connected to the negative power input terminal, and the cathode is connected to the resistor R3. Wherein, the diode D2 is a 12V voltage regulator tube. The MOS transistor Q1 is an N-MOS transistor. Diode D1 is a schottky diode.

After power-on, the current flowing through the resistors R1 and R3 charges the capacitor C1 first, and the voltage of the capacitor C1 rises slowly until the voltage rises to a divided voltage value determined by the resistances of R1 | R3 and R2. The gate voltage of the MOS transistor Q1 also gradually rises along with the divided voltage value, the time constant of the gate voltage can be estimated by R1 | R3 × C1, when the voltage is greater than the minimum threshold voltage of the MOS transistor Q1, the MOS transistor Q1 is linearly turned on along with the driving voltage until the driving voltage rises to the saturation turn-on voltage, and the MOS transistor Q1 is completely turned on. The drain and the source of the MOS transistor Q1 are gradually conducted, and a larger conducting impedance is started, so that the impact current generated by charging the capacitors C2 and C3 at the moment of starting up is effectively limited. When the circuit enters a stable working state, the drain and source electrodes of the MOS transistor Q1 are always in a saturated conduction state, and the loss is very low. The diode D2 is used to protect the gate of the MOS transistor Q1 from overvoltage breakdown, and a 12V regulator is generally selected. The diode D1, the resistors R1, R2 and R3 and the capacitor C1 slow down the turn-on speed of the MOS transistor Q1, meanwhile, the MOS transistor Q1 can be kept in a turn-off state when being powered on, and the rising speeds of different MOS transistor grid voltages are obtained by adjusting parameters of the resistors or the capacitors, so that different time constants are obtained, and the longer the time is, the better the impact current suppression effect is. The MOS transistor Q1 needs to select a material with Vds value greater than the highest input transient voltage.

To sum up, the utility model discloses utilize MOS pipeline nature to open the district, a small amount of components and parts of cooperation can restrict impulse current, the circuit is simple, and is with low costs, and the area occupied is little, is applicable to present complicated circuit board and arranges day by day, simultaneously, has effectively solved negative temperature coefficient temperature-sensitive current-limiting resistor (NTC) and has influenced great problem by temperature factor, and MOS intraductal resistance RDS (on) is little moreover, and resistance is little when drain electrode and source electrode switch on promptly to it is too big to have solved the loss that NTC leads to, uses the limited problem of scene.

The above description is only for the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present invention, and all should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A circuit for limiting impact current is characterized by comprising resistors R1, R2, R3 and R4, capacitors C1, C2 and C3, diodes D1 and D2 and a MOS tube Q1, wherein the resistors R1 and R2 are connected in series and then connected in parallel between positive and negative ends of a power input, the resistors R3 and R4 are connected in series and then connected with one end to the positive end of the power input and the other end to the gate of the MOS tube Q1, the source and the drain of the MOS tube Q1 are connected with the negative end of the power input, the capacitors C2 and C3 are respectively connected in parallel between the positive and negative ends of the power output, the anode of the diode D1 is connected with the resistor R3, the cathode of the resistor R1 is connected, one end of the capacitor C1 is connected with the cathode of the diode D1, the other end of the capacitor D2 is connected with the negative end of the power input, and the cathode of the resistor R3 is connected with the anode of the diode D2.

2. The circuit for limiting inrush current of claim 1, wherein the diode D2 is a 12V regulator.

3. The circuit for limiting inrush current of claim 1, wherein the MOS transistor Q1 is an N-MOS transistor.

4. The inrush current limiting circuit of claim 1, wherein the diode D1 is a schottky diode.