CN217545586U - Startup surge suppression protection circuit - Google Patents
Startup surge suppression protection circuit Download PDFInfo
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- CN217545586U CN217545586U CN202221114013.8U CN202221114013U CN217545586U CN 217545586 U CN217545586 U CN 217545586U CN 202221114013 U CN202221114013 U CN 202221114013U CN 217545586 U CN217545586 U CN 217545586U
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Abstract
The utility model relates to a start surge suppression protection circuit. Belonging to the technical field of startup protection circuits. The start-up surge suppression protection circuit comprises an input capacitor, wherein two ends of the input capacitor are connected with a positive power supply electrode and a negative power supply electrode, the start-up surge suppression protection circuit further comprises a first field effect tube, a second field effect tube, a current-limiting resistor and a delay capacitor, a source electrode and a drain electrode of the first field effect tube are connected between the positive power supply electrode and the input capacitor after being connected with the current-limiting resistor in parallel, a grid electrode of the first field effect tube is connected with a drain electrode of the second field effect tube, a grid electrode of the second field effect tube is connected with the negative power supply electrode after being connected with the delay capacitor in series, and a source electrode of the second field effect tube is connected with the input capacitor. The utility model provides a circuit can the active absorption fall surge voltage in the twinkling of an eye at the electronic product start, can be according to the in-service use demand of oneself simultaneously, reasonable design starting current and activation time.
Description
Technical Field
The utility model relates to a start surge suppression protection circuit. Belonging to the technical field of startup protection circuits.
Background
In order to ensure that the power supply can work safely and reliably under severe environment and sudden failure, various protection circuits must be designed, such as protection circuits for preventing soft start of surge, overvoltage, undervoltage, overheating, overcurrent, short circuit, phase failure and the like.
The conventional surge and current limiting circuits are usually separated, that is, an input terminal of a power management unit is provided with an independent surge voltage suppression circuit and an independent surge current suppression circuit respectively.
The surge voltage suppression circuit clamps the surge voltage input to the power management unit to be within a specified voltage range; the inrush current suppression circuit will limit the current to some specified range at startup.
Most of the traditional surge voltage suppression circuits are composed of combined circuits of TVS, gas discharge tubes, piezoresistors and other passive components, and if high-precision voltage clamping is to be realized, some power supply monitoring chips are required to be matched for realization.
The conventional surge current suppression circuit is mainly realized by using a supply resistor or a thermistor for current limiting, and the working principle is as shown in fig. 1: the circuit utilizes a negative temperature coefficient thermistor to limit current. The circuit is simple, easy to realize and low in cost. However, the circuit is greatly influenced by the ambient temperature, and meanwhile, the thermistor always has a voltage drop, so that the power supply efficiency is influenced.
The surge voltage and surge current suppression circuit realized by simple passive components has limited effect, can not effectively protect the circuit, and the current limiting circuit can also increase larger extra power consumption.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model is to provide a start surge suppression protection circuit effectively keeps apart surge voltage, restriction surge current to make the product stable excessive, normal work at last electricity or hot plug in-process.
The utility model relates to a start surge suppression protection circuit, including input capacitance, positive and power negative are connected at input capacitance's both ends, start surge suppression protection circuit still includes first field effect transistor, second field effect transistor, current-limiting resistor, time delay electric capacity, inserts between positive and the input capacitance after the source electrode and the drain electrode of first field effect transistor are parallelly connected with current-limiting resistor, and the grid of first field effect transistor is connected with the drain electrode of second field effect transistor, connects the power negative pole after the grid of second field effect transistor establishes ties with time delay electric capacity, and input capacitance is connected to the source electrode of second field effect transistor.
Further preferably, the first field effect transistor is a P-channel field effect transistor.
Further preferably, the second field effect transistor is an N-channel field effect transistor.
Further preferably, the start-up surge suppression protection circuit further includes a first voltage limiting resistor and a second voltage limiting resistor, the first voltage limiting resistor is connected between the positive electrode of the power supply and the gate of the first field-effect transistor, and the second voltage limiting resistor is connected between the gate of the first field-effect transistor and the drain of the second field-effect transistor.
Further preferably, the start-up surge suppression protection circuit further includes a third voltage limiting resistor and a fourth voltage limiting resistor, the third voltage limiting resistor is connected between the positive electrode of the power supply and the gate of the second field effect transistor, and the fourth voltage limiting resistor is connected in parallel with the delay capacitor.
The utility model relates to a start surge suppression protection circuit compares in prior art's scheme, has following advantage:
the utility model provides a surge voltage and surge current suppression circuit that is realized by miniwatt N channel field effect transistor and high-power P channel field effect transistor combination. The circuit can effectively absorb the surge voltage at the moment of starting the electronic product, and can reasonably design the starting current and the starting time according to the actual use requirement of the circuit.
Drawings
Fig. 1 is a schematic diagram of a conventional surge protection suppression circuit.
Fig. 2 is the utility model discloses start surge suppression protection circuit's schematic diagram.
Detailed Description
For a better understanding of the present invention, reference will now be made in detail to the present invention, examples of which are illustrated in the accompanying drawings.
Fig. 2 is a schematic diagram of the start-up surge suppression protection circuit of the present invention. The utility model provides a surge voltage and surge current suppression circuit that combination was realized by miniwatt N channel field effect transistor and high-power P channel field effect transistor, C is input capacitance.
In fig. 2, R1 is a power resistor, when Q1 is not turned on, the on-current is limited by R1, and R1 is bypassed after Q1 is turned on. Q1 is the switch tube, when Q1 switches on, the bypass drops R1, for the power supply of back stage circuit. Q2 is a control tube and is used for controlling the conduction of Q1, and when Q2 is conducted, Q1 is conducted. R2 and R3 are used to control the turn-on voltage of Q1. R4 and R5 are used to control the turn-on voltage of Q2. C1 is used for delaying time and is combined with R4 to adjust the conduction time of Q1. The working principle of the circuit is as follows:
a) At the moment of power-on
Since it is not time to charge C1, Q2 is off, so Q1 is off, and the front-end power supply powers the subsequent circuit through R1, and the maximum charging current is the ratio of the input voltages U and R1, independent of other components in the circuit. Therefore, the circuit can adjust the current limiting value by adjusting the resistance value of the R1.
If a surge voltage is generated at the time of power-on, the surge voltage is completely absorbed by R1, and the surge voltage does not have any influence on the subsequent power management unit.
b) In the starting process
During start-up, the input power will charge C1 through R4. When the voltage on C1 reaches a certain value (Q2 threshold), Q2 will turn on slowly, and at this time, the impedance to ground of R3 decreases, so that the G voltage of Q1 gradually decreases, and Q1 turns on slowly. At this time, the on-resistance of Q1 is gradually reduced to be connected in parallel with R1, and power is supplied to the subsequent circuit.
c) After the start is finished
After the start-up is completed, Q1 is fully turned on, and the on-resistance is about m Ω in magnitude according to the selection of the tube, and after the on-resistance is connected with R1 in parallel, R1 is basically bypassed, so that the front-end power supply supplies power to the rear-stage circuit through Q1.
The above-mentioned embodiments are only for describing the preferred embodiments of the present invention, and are not intended to limit the scope of the present invention, and various modifications and improvements made by those skilled in the art without departing from the design spirit of the present invention should fall into the protection scope defined by the claims of the present invention.
Claims (5)
1. The utility model provides a start surge suppression protection circuit, includes input capacitance, and the positive pole of power and power negative pole are connected at input capacitance's both ends, its characterized in that: the start-up surge suppression protection circuit further comprises a first field effect transistor, a second field effect transistor, a current-limiting resistor and a delay capacitor, wherein a source electrode and a drain electrode of the first field effect transistor are connected in parallel with the current-limiting resistor and then are connected between a positive electrode of a power supply and the input capacitor, a grid electrode of the first field effect transistor is connected with a drain electrode of the second field effect transistor, a grid electrode of the second field effect transistor is connected with a negative electrode of the power supply after being connected in series with the delay capacitor, and a source electrode of the second field effect transistor is connected with the input capacitor.
2. The power-on surge suppression protection circuit according to claim 1, wherein: the first field effect transistor is a P-channel field effect transistor.
3. The power-on surge suppression protection circuit according to claim 1, wherein: the second field effect transistor is an N-channel field effect transistor.
4. The power-on surge suppression protection circuit according to claim 1, wherein: the start-up surge suppression protection circuit further comprises a first voltage limiting resistor and a second voltage limiting resistor, the first voltage limiting resistor is connected between the positive electrode of the power supply and the grid electrode of the first field effect transistor, and the second voltage limiting resistor is connected between the grid electrode of the first field effect transistor and the drain electrode of the second field effect transistor.
5. The power-on surge suppression protection circuit according to claim 1, wherein: the start-up surge suppression protection circuit further comprises a third voltage limiting resistor and a fourth voltage limiting resistor, the third voltage limiting resistor is connected between the positive electrode of the power supply and the grid electrode of the second field effect transistor, and the fourth voltage limiting resistor is connected with the delay capacitor in parallel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221114013.8U CN217545586U (en) | 2022-05-07 | 2022-05-07 | Startup surge suppression protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221114013.8U CN217545586U (en) | 2022-05-07 | 2022-05-07 | Startup surge suppression protection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217545586U true CN217545586U (en) | 2022-10-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221114013.8U Active CN217545586U (en) | 2022-05-07 | 2022-05-07 | Startup surge suppression protection circuit |
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| CN (1) | CN217545586U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116032105A (en) * | 2023-03-24 | 2023-04-28 | 深圳市南方硅谷半导体股份有限公司 | Power supply overvoltage protection IC |
-
2022
- 2022-05-07 CN CN202221114013.8U patent/CN217545586U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116032105A (en) * | 2023-03-24 | 2023-04-28 | 深圳市南方硅谷半导体股份有限公司 | Power supply overvoltage protection IC |
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