CN212163158U - Impulse current peak value and rising slope suppression circuit - Google Patents
Impulse current peak value and rising slope suppression circuit Download PDFInfo
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- CN212163158U CN212163158U CN202021226286.2U CN202021226286U CN212163158U CN 212163158 U CN212163158 U CN 212163158U CN 202021226286 U CN202021226286 U CN 202021226286U CN 212163158 U CN212163158 U CN 212163158U
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Abstract
The utility model discloses an impulse current peak value and rising slope suppression circuit, including simulation direct current voltage source and switch SS1, still include MOS pipe Q1, filter capacitance C2 and drive circuit, drive circuit includes resistance R2, stabilivolt D2, electric capacity C1 and resistance R1, resistance R1 series resistance R2, stabilivolt D2 and electric capacity C1 and resistance R2 are parallelly connected; the gate of the MOS transistor Q1 is connected with the node between the resistor R1 and the resistor R2, and the source and the drain of the MOS transistor Q1 are connected in series between the negative input end and the negative output end of the analog direct-current voltage source; the filter capacitor C2 is arranged between the positive output end and the negative output end of the analog direct-current voltage source; the power inductor L1 and the power resistor R3 are connected in series and then connected in parallel between the source and the drain of the MOS transistor Q1. The peak value and the rising slope of the bus impact current at the moment of starting are restrained, and the resistor R3 and the inductor L1 are bypassed during normal operation, so that power is not consumed.
Description
Technical Field
The utility model relates to a power technical field, specific theory is an impulse current peak value and rising slope suppression circuit.
Background
In the power supply system of the electronic equipment, because a large number of capacitive devices exist, at the moment of starting up a power supply, a capacitor is equivalent to a short circuit, a large impact current can be generated on a power supply bus when the capacitor is charged, and the impact current has a high rising slope because the power-on time is short. When the peak value is too large, the previous stage circuit device can be damaged or the overcurrent protection of the previous stage power supply system can be triggered, and when the rising slope is too large, the bus voltage can be pulled down, so that the normal operation of other equipment of the same power supply system can be influenced, and the peak value and the rising slope of the impact current need to be restrained.
The peak value of the inrush current is specifically required in the GJB181B-2012 aircraft supply characteristic 5.4.9: and cannot exceed 5 times of rated current. The peak value of the surge current in the MIL-STD-704 aircraft power supply characteristic LDC101 is specified to be not more than 6 times of the rated current, and the rising slope of the surge current is specified to be not more than 10A/us in some aircraft characteristic test requirements.
The current surge current suppression circuit which is widely used is a series resistor or a thermistor using negative temperature characteristics. However, the series resistor can work for a long time, and the overall efficiency of the power supply is reduced; the thermistor with negative temperature characteristic has the defects that the temperature rises and the resistance value drops after long-time work, and the thermistor fails when being started in a hot state. The method for restraining the impulse current by using the characteristic of the varistor region of the MOS tube has higher requirement on the safe working region of the MOS tube, and the MOS tube is easily damaged when the type is not selected properly.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide an impulse current and slope suppression circuit that rises for power supply start is too big and the too high problem of slope that rises in the twinkling of an eye among the solution prior art.
The utility model discloses a following technical scheme solves above-mentioned problem:
a surge current peak value and rising slope suppression circuit comprises a simulation direct current voltage source and a switch SS1, wherein two ends of the switch SS1 are connected with a positive electrode input end and a positive electrode output end of the simulation direct current voltage source, the surge current peak value and rising slope suppression circuit further comprises an MOS tube Q1, a filter capacitor C2 and a driving circuit, the driving circuit comprises a resistor R2, a voltage-regulator tube D2, a capacitor C1 and a resistor R1, one end of the resistor R1 is connected with the positive electrode output end of the simulation direct current voltage source, the other end of the resistor R2 is connected with a negative electrode input end of the simulation direct current voltage source, and the voltage-regulator tube D2, the capacitor C1 and the resistor R2; the gate of the MOS transistor Q1 is connected with a node between the resistor R1 and the resistor R2, and the source and the drain of the MOS transistor Q1 are connected in series between the negative input end and the negative output end of the analog direct-current voltage source; the filter capacitor C2 is arranged between the positive output end and the negative output end of the analog direct-current voltage source; the power inductor L1 and the power resistor R3 are connected in series and then connected in parallel between the source and the drain of the MOS transistor Q1.
The whole circuit has two working states of transient state and steady state, wherein the power-on process of the input end belongs to the transient working state, and then belongs to the steady state working state.
In a steady-state working state, the resistor R1 and the resistor R2 form a voltage division circuit, voltage at two ends of the resistor R2 is used for driving the MOS tube to conduct stably to work, and the voltage regulator tube D2 is used for clamping voltage at two ends of the resistor R2, so that the MOS tube Q1 is prevented from being damaged due to overhigh voltage, and the effect of protecting the MOS tube Q1 is achieved. In a steady-state working state, the MOS transistor Q1 is completely conducted, the power resistor R3 and the power inductor L1 are bypassed, energy is not consumed completely, and the rear-end equipment works normally;
in a transient working state, when the switch SS1 is suddenly closed, the resistor R1 and the capacitor C1 form an RC charging circuit to charge the capacitor C1 connected in parallel to the end of the MOS transistor Q1G-S, the voltage across the capacitor C1 is the driving voltage of the MOS transistor Q1, and since the RC charging circuit has a voltage delay effect, the driving voltage of the MOS transistor Q1 will slowly rise, the MOS transistor Q1 will be turned on in a delayed manner, and the delay time is determined by the time constants of the resistor R1 and the capacitor C1. In the process, the analog direct-current voltage source charges a rear-end filter capacitor C2 through a power resistor R3 and a power inductor L1, the power resistor R3 inhibits the peak value of starting impact current in the charging process, and the power inductor L1 inhibits the rising slope of the power inductor. The peak value and the rising slope of bus impact current at the moment of starting can be effectively inhibited, the RC charging time constant of the MOS tube Q1 can be adjusted, the MOS tube Q1 is close to zero voltage and conducted, the current stress when the MOS tube Q1 is conducted is reduced, the MOS tube is not limited by a safe working area during model selection, and the MOS tube can be completely conducted before the starting of a rear-stage power module.
The switch SS1 is an air switch.
The MOS transistor Q1 is an N communication MOSFET, the source electrode of the MOS transistor Q1 is connected with the negative electrode input end of the analog direct current voltage source, and the drain electrode of the MOS transistor Q1 is connected with the negative electrode output end of the analog direct current voltage source.
Compared with the prior art, the utility model, following advantage and beneficial effect have:
(1) the utility model discloses effectively restrain the start in the twinkling of an eye generating line impulse current's peak value and slope that rises, and the resistance of restriction impulse current peak value and the inductance of restriction impulse current slope that rises are by the bypass at normal during operation, can not the consumed power.
(2) The utility model discloses an electric capacity charge time constant between adjustment MOS pipe GS (bars-source electrode) for it switches on at suitable time point, both can restrain the start impulse current in the twinkling of an eye, can switch on the MOS pipe again when rear capacitor charges and is close input voltage, with the current stress that reduces the MOS pipe, no longer receive the limit value of safe workspace when making the MOS pipe lectotype, can guarantee again to switch on the MOS pipe completely before rear power module starts.
Drawings
Fig. 1 is a schematic circuit diagram of the present invention;
fig. 2 is a charging equivalent circuit before the MOS transistor is turned on.
Detailed Description
The present invention will be described in further detail with reference to examples, but the present invention is not limited thereto.
Example (b):
with reference to fig. 1, a circuit for suppressing a peak value and a rising slope of an impact current includes an analog dc voltage source and an air switch SS1, both ends of the air switch SS1 are connected to an anode input terminal Vin + and an anode output terminal Vout + of the analog dc voltage source, and further includes a MOS transistor Q1, a filter capacitor C2, and a driving circuit, where the driving circuit includes a resistor R2, a regulator D2, a capacitor C1, and a resistor R1, one end of the resistor R1 is connected to the anode output terminal Vout + of the analog dc voltage source, and the other end is connected to a cathode input terminal Vin of the analog dc voltage source through the resistor R2, and the regulator D2 and the capacitor C1 are connected in parallel to the resistor R2; the gate of the MOS transistor Q1 is connected with a node between the resistor R1 and the resistor R2, and the source and the drain of the MOS transistor Q1 are connected in series between the negative input end Vin-and the negative output end Vout-of the analog direct-current voltage source; the filter capacitor C2 is arranged between the positive output end and the negative output end of the analog direct-current voltage source; the power inductor L1 and the power resistor R3 are connected in series and then connected in parallel between the source and the drain of the MOS transistor Q1.
The whole circuit has two working states of transient state and steady state, wherein the power-on process of the input end belongs to the transient working state, and then belongs to the steady state working state.
In a steady-state working state, the resistor R1 and the resistor R2 form a voltage division circuit, voltage at two ends of the resistor R2 is used for driving the MOS tube to conduct stably to work, and the voltage regulator tube D2 is used for clamping voltage at two ends of the resistor R2, so that the MOS tube Q1 is prevented from being damaged due to overhigh voltage, and the effect of protecting the MOS tube Q1 is achieved. In a steady-state working state, the MOS transistor Q1 is completely conducted, the power resistor R3 and the power inductor L1 are bypassed, energy is not consumed completely, and the rear-end equipment works normally;
in a transient working state, when the air switch SS1 is suddenly closed, the resistor R1 and the capacitor C1 form an RC charging circuit to charge the capacitor C1 connected in parallel to the end of the MOS transistor Q1G-S, the voltage across the capacitor C1 is the driving voltage of the MOS transistor Q1, and because the RC charging circuit has a voltage delay effect, the driving voltage of the MOS transistor Q1 will slowly rise, the MOS transistor Q1 will be turned on in a delayed manner, and the delay time is determined by the time constants of the resistor R1 and the capacitor C1. In the process, the analog direct-current voltage source charges the rear-end filter capacitor C2 through the power resistor R3 and the power inductor L1, the power resistor R3 inhibits a starting impact current peak value in the charging process, and the power inductor L1 inhibits a rising slope of the power inductor, and the specific principle analysis is as follows:
before the MOS transistor Q1 is turned on, the analog dc voltage source charges the rear filter capacitor C2 through the power resistor R3 and the power inductor L1, and the power resistor R3, the power inductor L1 and the filter capacitor C2 form an RLC charging loop, which is shown in fig. 2 as an equivalent schematic diagram.
When air switch SS1 is closed, the circuit shown in FIG. 2 is a typical zero state response of a second order circuit with a capacitor voltage uCIs an independent variable column equation, which has:
uC+uR+uL＝US (1)
in the formula uCIs the voltage across the filter capacitor C2, uRIs the voltage across the power resistor R3, uLIs the voltage across the power inductor L1, Us is the input DC voltage, iLIs the charging current of the capacitor C2.
The method can be obtained by the formula (1):
substituting formula (2) for formula (3) includes:
equation (4) is written in standard form as follows:
wherein, α = R/2L,
then there is
The inductor current, i.e. the capacitor charging current, can be expressed as:
when t is β, i.e. t is β/ω, the current iLA peak is reached.
The peak current divided by the time approximates the rising slope of the inrush current.
By adopting the scheme of the invention, the MOS tube GS is conducted at a proper time point by adjusting the time constant of capacitor charging between the MOS tubes GS, so that the instant impact current of starting can be inhibited, the MOS tube GS can be conducted when the charging of the rear-stage capacitor is close to the input voltage, the current stress of the MOS tube is reduced, the MOS tube GS is not limited by the limit value of a safe working area when the type selection is carried out, and the MOS tube GS can be completely conducted before the starting of the rear-stage power module. Meanwhile, the rising slope of the impact current can be limited through the inductance. And the resistor for limiting the peak value of the impact current and the inductor for limiting the rising slope of the impact current are bypassed during normal operation, so that power is not consumed.
Although the present invention has been described herein with reference to the illustrated embodiments thereof, which are merely preferred embodiments of the present invention, it is to be understood that the present invention is not limited thereto, and that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure.
Claims (3)
1. A surge current peak value and rising slope suppression circuit comprises an analog direct current voltage source and a switch SS1, wherein two ends of the switch SS1 are connected with a positive electrode input end and a positive electrode output end of the analog direct current voltage source, the surge current peak value and rising slope suppression circuit is characterized by further comprising an MOS tube Q1, a filter capacitor C2 and a driving circuit, the driving circuit comprises a resistor R2, a voltage stabilizing tube D2, a capacitor C1 and a resistor R1, one end of the resistor R1 is connected with the positive electrode output end of the analog direct current voltage source, the other end of the resistor R2 is connected with a negative electrode input end of the analog direct current voltage source, and the voltage stabilizing tube D2 and the capacitor C1 are connected with the resistor R2 in; the gate of the MOS transistor Q1 is connected with a node between the resistor R1 and the resistor R2, and the source and the drain of the MOS transistor Q1 are connected in series between the negative input end and the negative output end of the analog direct-current voltage source; the filter capacitor C2 is arranged between the positive output end and the negative output end of the analog direct-current voltage source; the power inductor L1 and the power resistor R3 are connected in series and then connected in parallel between the source and the drain of the MOS transistor Q1.
2. The inrush current peak and rising slope suppression circuit of claim 1, wherein the switch SS1 is an air switch.
3. The circuit as claimed in claim 1, wherein the MOS transistor Q1 is an N-channel MOSFET, the source of the MOS transistor Q1 is connected to the negative input terminal of the analog DC voltage source, and the drain of the MOS transistor Q1 is connected to the negative output terminal of the analog DC voltage source.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021226286.2U CN212163158U (en) | 2020-06-29 | 2020-06-29 | Impulse current peak value and rising slope suppression circuit |
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| CN202021226286.2U CN212163158U (en) | 2020-06-29 | 2020-06-29 | Impulse current peak value and rising slope suppression circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117691847A (en) * | 2024-02-01 | 2024-03-12 | 成都新欣神风电子科技有限公司 | Positive line impact current suppression circuit based on N-channel MOS tube |
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2020
- 2020-06-29 CN CN202021226286.2U patent/CN212163158U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117691847A (en) * | 2024-02-01 | 2024-03-12 | 成都新欣神风电子科技有限公司 | Positive line impact current suppression circuit based on N-channel MOS tube |
| CN117691847B (en) * | 2024-02-01 | 2024-05-03 | 成都新欣神风电子科技有限公司 | Positive line impact current suppression circuit based on N-channel MOS tube |
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