CN117691847A - Positive line impact current suppression circuit based on N-channel MOS tube - Google Patents

Positive line impact current suppression circuit based on N-channel MOS tube Download PDF

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Publication number
CN117691847A
CN117691847A CN202410138099.5A CN202410138099A CN117691847A CN 117691847 A CN117691847 A CN 117691847A CN 202410138099 A CN202410138099 A CN 202410138099A CN 117691847 A CN117691847 A CN 117691847A
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resistor
filter capacitor
line
tube
boost
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CN117691847B (en
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王威
彭亭
刘强
熊亚丽
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CHENGDU XINXIN SHENFENG ELECTRONIC TECHNOLOGY CO LTD
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CHENGDU XINXIN SHENFENG ELECTRONIC TECHNOLOGY CO LTD
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0038—Circuits or arrangements for suppressing, e.g. by masking incorrect turn-on or turn-off signals, e.g. due to current spikes in current mode control
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention discloses a positive line impulse current suppression circuit based on an N-channel MOS tube, which relates to the technical field of power supply and comprises a power resistor, an NMOS tube, an input filter capacitor, a reference voltage stabilizing source, a delay charging circuit, a booster circuit, a voltage division feedback circuit, a boost output filter capacitor, a floating resistor and an output filter capacitor; the reference voltage stabilizing source adopts a voltage stabilizing tube; the delay charging circuit comprises a resistor and a capacitor; the boost circuit comprises an inductor, a diode and a boost control chip; the voltage division feedback circuit includes two resistors. The invention can accurately restrain the peak value of the startup surge current, and the power resistor charges the line-to-line capacitor after startup, thereby effectively restraining the bus surge current at the startup moment; the NMOS tube arranged on the positive line is conducted through delay charging driving, and the charging power resistor is bypassed after the NMOS tube is conducted, so that the power loss during normal operation can be effectively reduced, and the device is particularly suitable for a large-current scene. The invention can be extended to have anti-reverse connection protection.

Description

Positive line impact current suppression circuit based on N-channel MOS tube
Technical Field
The invention relates to the technical field of power supply, in particular to a positive line impact current suppression circuit based on an N-channel MOS tube.
Background
At the moment of starting up the direct current power supply, the capacitor between the rear stages is equivalent to a short circuit, and larger impact current can be generated on a power supply bus when the capacitor is charged, and the impact current is too large to damage a front-stage circuit device or trigger the overcurrent protection of the front-stage power supply, so that other homologous electronic equipment cannot work normally, and the impact current needs to be restrained.
At present, the impact current is limited by a mode of connecting MOS tubes in parallel with a power resistor, and the impact current suppression method is simple in circuit and wide in application range, but has certain limitation in certain application occasions. For example, in an on-board electronic device, a negative line of a power supply is often connected with a ground line (device casing), under such an application scenario, current directly passes through the ground line to form a loop, and an impact current suppression circuit in the negative line loop cannot effectively suppress impact current at a starting moment, and needs to be placed on a positive line. The conventional impact current suppression method placed on the positive line adopts a P-channel MOS tube, and the mode is simple to drive. But the on-resistance of the P-channel MOS tube is larger, so that the bus power loss is larger in normal operation, and the P-channel MOS tube is not suitable for a large-current scene.
Disclosure of Invention
Aiming at the problems in the background art, the invention provides a positive line impact current suppression circuit based on an N-channel MOS tube, which can effectively and accurately suppress the instant impact current of starting up, simultaneously reduce the bus power loss in normal operation, and is particularly suitable for a heavy current scene.
In order to achieve the above object, the present invention provides the following solutions:
in one aspect, the invention provides a positive line impact current suppression circuit based on an N-channel MOS transistor, comprising: the power resistor R1, the NMOS tube Q1, the input filter capacitor C1, the reference voltage stabilizing source, the delay charging circuit, the booster circuit, the voltage division feedback circuit, the boost output filter capacitor C4, the floating resistor R5 and the output filter capacitor C5; the reference voltage stabilizing source adopts a voltage stabilizing tube D2; the delay charging circuit comprises a resistor R3 and a capacitor C3; the boost circuit comprises an inductor L1, a diode D3 and a boost control chip U1; the voltage division feedback circuit comprises a resistor R7 and a resistor R6;
the drain electrode of the NMOS tube Q1 and one end of the power resistor R1 are connected with a direct current input power supply positive line VIN+; the source electrode of the NMOS tube Q1 is respectively connected with the other end of the power resistor R1, one end of the input filter capacitor C1, the negative electrode of the voltage stabilizing tube D2, one end of the resistor R3, one end of the inductor L1 and one end of the output filter capacitor C5; the enabling end EN of the boost control chip U1 is respectively connected with the other end of the resistor R3 and one end of the capacitor C3; the SW terminal of the boost control chip U1 is respectively connected with the other end of the inductor L1 and the anode of the diode D3; the cathode of the diode D3 is respectively connected with one end of the resistor R7, one end of the boost output filter capacitor C4 and the grid electrode of the NMOS tube Q1; the FB terminal of the boost control chip U1 is respectively connected with the other end of the resistor R7 and one end of the resistor R6; the positive electrode of the voltage stabilizing tube D2, the other end of the capacitor C3, the GND terminal of the boost control chip U1, the other end of the resistor R6 and the other end of the boost output filter capacitor C4 are all connected with one end of the floating resistor R5; the other end of the floating resistor R5 is respectively connected with the other end of the input filter capacitor C1 and the other end of the output filter capacitor C5.
Optionally, the other end of the input filter capacitor C1 is also connected with a direct current input power supply negative line VIN-; the direct current input power supply positive line VIN+ and the direct current input power supply negative line VIN-are respectively connected with two ends of the direct current input power supply.
Optionally, the charging time constant of the direct current input power supply for charging the line-to-line capacitance through the power resistor R1 isThe method comprises the steps of carrying out a first treatment on the surface of the Wherein->Is the resistance value of the power resistor R1, +.>Between lines of wiresThe capacitance of the capacitor.
Optionally, the peak value of the impact current at the starting moment of the direct current input power supply isThe method comprises the steps of carrying out a first treatment on the surface of the Wherein->The power supply voltage is input for direct current.
Optionally, two ends of the output filter capacitor C5 are respectively connected with an output positive line VOUT+ and an output negative line VOUT-.
On the other hand, the invention also provides a positive line impact current suppression circuit with a reverse connection prevention protection function and based on the N-channel MOS tube, which comprises the following components: the power resistor R1, the NMOS tube Q2, the input filter capacitor C1, a reference voltage stabilizing source, a delay charging circuit, a boost circuit, a voltage division feedback circuit, a boost output filter capacitor C4, a floating resistor R5 and an output filter capacitor C5; the reference voltage stabilizing source adopts a voltage stabilizing tube D2; the delay charging circuit comprises a resistor R3 and a capacitor C3; the boost circuit comprises an inductor L1, a diode D3 and a boost control chip U1; the voltage division feedback circuit comprises a resistor R7 and a resistor R6;
the drain electrode of the NMOS tube Q1 and one end of the power resistor R1 are connected with a direct current input power supply positive line VIN+; the source electrode of the NMOS tube Q1 is respectively connected with the other end of the power resistor R1 and the source electrode of the NMOS tube Q2; the drain electrode of the NMOS tube Q2 is respectively connected with one end of the input filter capacitor C1, the negative electrode of the voltage stabilizing tube D2, one end of the resistor R3, one end of the inductor L1 and one end of the output filter capacitor C5; the enabling end EN of the boost control chip U1 is respectively connected with the other end of the resistor R3 and one end of the capacitor C3; the SW terminal of the boost control chip U1 is respectively connected with the other end of the inductor L1 and the anode of the diode D3; the cathode of the diode D3 is respectively connected with one end of the resistor R7, one end of the boost output filter capacitor C4, the grid electrode of the NMOS tube Q1 and the grid electrode of the NMOS tube Q2; the FB terminal of the boost control chip U1 is respectively connected with the other end of the resistor R7 and one end of the resistor R6; the positive electrode of the voltage stabilizing tube D2, the other end of the capacitor C3, the GND terminal of the boost control chip U1, the other end of the resistor R6 and the other end of the boost output filter capacitor C4 are all connected with one end of the floating resistor R5; the other end of the floating resistor R5 is respectively connected with the other end of the input filter capacitor C1 and the other end of the output filter capacitor C5.
Optionally, the other end of the input filter capacitor C1 is also connected with a direct current input power supply negative line VIN-; the direct current input power supply positive line VIN+ and the direct current input power supply negative line VIN-are respectively connected with two ends of the direct current input power supply.
Optionally, the charging time constant of the direct current input power supply for charging the line-to-line capacitance through the power resistor R1 isThe method comprises the steps of carrying out a first treatment on the surface of the Wherein->Is the resistance value of the power resistor R1, +.>Is the capacitance of the line-to-line capacitance.
Optionally, the peak value of the impact current at the starting moment of the direct current input power supply isThe method comprises the steps of carrying out a first treatment on the surface of the Wherein->The power supply voltage is input for direct current.
Optionally, two ends of the output filter capacitor C5 are respectively connected with an output positive line VOUT+ and an output negative line VOUT-.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the positive line impulse current suppression circuit based on the N-channel MOS tube comprises a power resistor, an NMOS tube, an input filter capacitor, a reference voltage stabilizing source, a delay charging circuit, a booster circuit, a voltage division feedback circuit, a booster output filter capacitor, a floating resistor and an output filter capacitor; the reference voltage stabilizing source adopts a voltage stabilizing tube; the delay charging circuit comprises a resistor and a capacitor; the boost circuit comprises an inductor, a diode and a boost control chip; the voltage division feedback circuit comprises two resistors. The invention can accurately restrain the peak value of the startup surge current, and the power resistor charges the line-to-line capacitor after startup, thereby effectively restraining the bus surge current at the startup moment; the NMOS tube is connected through the delay charging drive and is arranged on the positive line, and the charging power resistor is bypassed after the NMOS tube is connected. Furthermore, the invention can be further expanded to have the reverse connection preventing protection function, and the power loss caused by reverse connection preventing of the positive line can be reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of a positive line impact current suppression circuit based on an N-channel MOS tube;
fig. 2 is a schematic diagram of specific circuit connection of a positive line impact current suppression circuit based on an N-channel MOS transistor according to an embodiment of the present invention;
fig. 3 is a schematic diagram of specific circuit connection of a positive line impact current suppression circuit with anti-reverse connection protection function based on an N-channel MOS transistor according to a second embodiment of the present invention;
FIG. 4 is a waveform diagram of a startup instant no-load startup when the output filter capacitance is 56 uF;
fig. 5 is a waveform diagram of the start-up instant no-load start-up when the output filter capacitance is 100 uF.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention aims to provide a positive line impact current suppression circuit based on an N-channel MOS tube, which can effectively and accurately suppress the impact current at the moment of starting up, simultaneously reduce the bus power loss during normal operation, and is particularly suitable for a large-current scene.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Fig. 1 is a block diagram of a positive line impact current suppression circuit based on an N-channel MOS transistor. Referring to fig. 1, the positive line impact current suppression circuit based on an N-channel MOS transistor of the present invention includes: the power circuit comprises a power resistor, an NMOS tube, an input filter capacitor, a reference voltage stabilizing source, a delay charging circuit, a boost circuit, a voltage division feedback circuit, a boost output filter capacitor, a floating resistor and an output filter capacitor. The invention has the innovation points that the NMOS tube arranged on the positive line of the direct current input power supply can be delayed to be driven and conducted, the power loss of the bus in normal operation is reduced while the instant surge current of the starting is effectively and accurately restrained, and the reliability of the surge current restraining circuit is improved. In the first embodiment of the invention, the adopted NMOS tube, namely the N-channel MOS tube, only comprises an NMOS tube Q1; in the second embodiment of the present invention, the N-channel MOS transistor includes an NMOS transistor Q1 and an NMOS transistor Q2; the details are described below.
Example 1
Referring to fig. 2, a positive line impact current suppression circuit based on an N-channel MOS transistor according to an embodiment of the present invention includes: the power resistor R1, the NMOS tube Q1, the input filter capacitor C1, the reference voltage stabilizing source, the delay charging circuit, the booster circuit, the voltage division feedback circuit, the boost output filter capacitor C4, the floating resistor R5 and the output filter capacitor C5; the reference voltage stabilizing source adopts a voltage stabilizing tube D2; the delay charging circuit comprises a resistor R3 and a capacitor C3; the boost circuit comprises an inductor L1, a diode D3 and a boost control chip U1; the voltage division feedback circuit comprises a resistor R7 and a resistor R6.
Referring to fig. 2, the drain of the NMOS transistor Q1 and one end of the power resistor R1 are both connected to the positive line vin+ of the dc input power supply. The source electrode of the NMOS tube Q1 is respectively connected with the other end of the power resistor R1, one end of the input filter capacitor C1, the negative electrode of the voltage stabilizing tube D2, one end of the resistor R3, one end of the inductor L1 and one end of the output filter capacitor C5; the connection point between the other end of the power resistor R1 and the source electrode of the NMOS transistor Q1 is denoted as VS. The enable end EN of the boost control chip U1 is connected to the other end of the resistor R3 and one end of the capacitor C3, respectively. The SW terminal of the boost control chip U1 is connected to the other end of the inductor L1 and the anode of the diode D3, respectively. The cathode of the diode D3 is respectively connected with one end of the resistor R7, one end of the boost output filter capacitor C4 and the grid electrode of the NMOS tube Q1; the connection point between one end of the boost output filter capacitor C4 and the gate of the NMOS transistor Q1 is denoted as VG. The FB terminal of the boost control chip U1 is connected to the other end of the resistor R7 and one end of the resistor R6, respectively. The positive electrode of the voltage stabilizing tube D2, the other end of the capacitor C3, the GND terminal of the boost control chip U1, the other end of the resistor R6 and the other end of the boost output filter capacitor C4 are all connected with one end of the floating resistor R5. The other end of the floating resistor R5 is respectively connected with the other end of the input filter capacitor C1 and the other end of the output filter capacitor C5.
The other end of the input filter capacitor C1 is also connected with a direct current input power supply negative line VIN-; the positive line VIN+ and the negative line VIN-of the direct current input power supply are respectively connected with two ends of the direct current input power supply, and the voltage of the direct current input power supply is recorded as。
Two ends of the output filter capacitor C5 are respectively connected with an output positive line VOUT+ and an output negative line VOUT-, VOUThe voltage between T+ and VOUT is recorded as。
The working principle of the positive line impact current suppression circuit based on the N-channel MOS tube is as follows.
The N-channel MOS tube Q1 is connected in parallel with the power resistor R1 and is arranged on the positive line of a direct current input power supply, and the input filter capacitor C1 and the output filter capacitor C5 are respectively used for input filtering and output filtering. The voltage stabilizing tube D2 generates a reference voltage stabilizing source for supplying power to the boost control chip U1, and a delay charging circuit formed by a resistor R3 and a capacitor C3 is connected with an enable end EN of the boost control chip U1 to control delay operation of the boost control chip U1. The inductor L1, the diode D3 and the boost control chip U1 form a boost circuit, so that the stable voltage of the voltage stabilizing tube D2 is increased. The resistor R7 and the resistor R6 form a voltage division feedback circuit for setting the output voltage of the booster circuit. The boost output filter capacitor C4 is an output filter capacitor of the boost circuit, and is used for smoothing filtering and attenuating output voltage ripple of the boost circuit. The floating resistor R5 is connected in series with the whole booster circuit and is used for generating a floating network, so that the voltage generated by the booster circuit is higher than the input voltage and is used for driving and conducting an N-channel MOS tube arranged on a positive line.
During normal startup, the voltage at the two ends of the gate and the source of the NMOS tube Q1 is low, which is insufficient to drive the NMOS tube to be conducted, and the input voltage charges the capacitor between the rear-stage wires through the power resistor R1, so that the peak value of the instantaneous surge current during startup is accurately restrained. When the input voltage reaches the breakdown voltage of the voltage stabilizing tube D2, the voltages at two ends of the voltage stabilizing tube D2 are clamped to the voltage VD2, the voltage VD2 charges the capacitor C3 at the enabling end of the boost control chip U1 through the resistor R3, and the voltages at two ends of the capacitor C3 slowly rise. When the voltage at two ends of the capacitor C3 exceeds the starting threshold of the boost control chip U1, the boost control chip U1 starts to work, and boosts the input voltage, that is, the voltage VD2 at two ends of the regulator tube D2, to the set value VC4. Because VC4 is greater than VD2, the VG point potential is higher than the VS point potential, i.e. the gate-source voltage V of NMOS transistor Q1 GS Is high. When V is GS When the turn-on threshold voltage of the NMOS transistor Q1 is higher, the NMOS transistor Q1 turns on, and the power resistor R1 is bypassed. The DC input power source takes extremely low power loss asThe latter stage provides energy.
Before the NMOS transistor Q1 is turned on, the dc input power charges the line-to-line capacitance, which includes C1, C5 and other line-to-line equivalent capacitances, through the power resistor R1. The charging time constant of the line-to-line capacitance isWherein->Is the resistance value of the power resistor R1, +.>Is the capacitance of the line-to-line capacitance. The peak value of the impulse current is precisely inhibited, and the peak value of the impulse current is +.>。
Aiming at the limitations of the common negative line impact current suppression circuit, the invention provides a positive line impact current suppression circuit based on an N-channel MOS tube, wherein an NMOS tube Q1 is turned on in a delayed manner after the power is turned on, and an inter-line capacitor is charged through a power resistor R1, so that bus impact current at the moment of the power on can be effectively suppressed; the boost control chip U1 is enabled to start working in a delayed mode through charging the capacitor C3 at the enabling end of the boost control chip U1, and then the NMOS tube Q1 is driven to be conducted in a delayed mode, and therefore the positive line impact current suppression method based on the NMOS tube is achieved; after the NMOS tube Q1 is conducted, the charging power resistor R1 is bypassed, so that the power loss in normal operation is reduced, and the N-channel MOS tube is particularly suitable for a high-current scene because the on-resistance of the N-channel MOS tube is smaller than that of the P-channel MOS tube.
Example two
The invention can be further expanded into a positive line impact current suppression circuit with a reverse connection prevention protection function and based on a positive line N-channel MOS tube, as shown in figure 3. The N-channel MOS tube Q2 is connected in series behind the N-channel MOS tube Q1, and the two tubes are back to back and share one driving signal, so that the reverse connection prevention protection effect can be achieved.
Referring to fig. 3, the N-channel MOS transistor-based positive line impact current suppression circuit with anti-reverse connection protection function includes: the power resistor R1, the NMOS tube Q2, the input filter capacitor C1, a reference voltage stabilizing source, a delay charging circuit, a boost circuit, a voltage division feedback circuit, a boost output filter capacitor C4, a floating resistor R5 and an output filter capacitor C5; the reference voltage stabilizing source adopts a voltage stabilizing tube D2; the delay charging circuit comprises a resistor R3 and a capacitor C3; the boost circuit comprises an inductor L1, a diode D3 and a boost control chip U1; the voltage division feedback circuit comprises a resistor R7 and a resistor R6.
Referring to fig. 3, the drain of the NMOS transistor Q1 and one end of the power resistor R1 are both connected to the positive line vin+ of the dc input power supply. The source electrode of the NMOS tube Q1 is respectively connected with the other end of the power resistor R1 and the source electrode of the NMOS tube Q2. The drain electrode of the NMOS tube Q2 is respectively connected with one end of the input filter capacitor C1, the negative electrode of the voltage stabilizing tube D2, one end of the resistor R3, one end of the inductor L1 and one end of the output filter capacitor C5, and the connection point is denoted as VS. The enable end EN of the boost control chip U1 is connected to the other end of the resistor R3 and one end of the capacitor C3, respectively. The SW terminal of the boost control chip U1 is connected to the other end of the inductor L1 and the anode of the diode D3, respectively. The negative electrode of the diode D3 is connected to one end of the resistor R7, one end of the boost output filter capacitor C4, the gate of the NMOS transistor Q1, and the gate of the NMOS transistor Q2, respectively, and the connection point is denoted as VG. The FB terminal of the boost control chip U1 is connected to the other end of the resistor R7 and one end of the resistor R6, respectively. The positive electrode of the voltage stabilizing tube D2, the other end of the capacitor C3, the GND terminal of the boost control chip U1, the other end of the resistor R6 and the other end of the boost output filter capacitor C4 are all connected with one end of the floating resistor R5. The other end of the floating resistor R5 is respectively connected with the other end of the input filter capacitor C1 and the other end of the output filter capacitor C5.
The other end of the input filter capacitor C1 is also connected with a direct current input power supply negative line VIN-; the positive line VIN+ and the negative line VIN-of the direct current input power supply are respectively connected with two ends of the direct current input power supply, and the voltage of the direct current input power supply is recorded as. The two ends of the output filter capacitor C5 are respectively connected with an output positive line VOUT+ and an output negative line VOUT-, and the voltages between VOUT+ and VOUT-are recorded as +.>。
The second embodiment is similar to the first embodiment in the working principle of the positive line impact current suppression circuit, and is mainly different in that the reverse connection prevention protection function is further realized by using the N-channel MOS transistor Q2, which is not described herein.
The test is performed on the positive line impact current suppression circuit based on the N-channel MOS transistor provided by the first embodiment of the present invention, and the obtained starting-up instant no-load starting waveform diagrams are shown in fig. 4 and 5, in which five curves from top to bottom are respectively: 1) Input voltage, i.e. DC input supply voltageThe method comprises the steps of carrying out a first treatment on the surface of the 2) Input current, i.e. loop current of the whole circuit; 3) The gate-source voltage, i.e. the voltage V across the gate of NMOS transistor Q1 relative to its source (i.e. output positive line) GS The method comprises the steps of carrying out a first treatment on the surface of the 4) Output voltage, i.e. VOUT+ and VOUT-voltage +.>The method comprises the steps of carrying out a first treatment on the surface of the 5) The gate voltage, i.e., the voltage of the gate of NMOS transistor Q1 relative to the negative line of the circuit.
At t F1 At the moment, the direct current input power supply is suddenly electrified, at the moment, the input voltage is rapidly increased from 0 to rated input voltage, the input current is limited to a specified value (12.7A) by a power resistor R1 connected in parallel with an NMOS tube Q1, and the output voltage is still 0 at the moment because the voltage at two ends of a capacitor cannot be suddenly changed; at t F1 To t F2 In the time, the capacitor is charged through the current limiting resistor, the output voltage slowly rises to the input voltage value, the boosting circuit is not started at the moment, the output voltage is used as the gate voltage of the NMOS tube Q1 after passing through the inductor L1 and the diode D3, and therefore the gate voltage of the NMOS tube Q1 is equal to the output voltage minus the diode voltage drop, and the gate-source voltage is the diode voltage drop; at t F2 To t F3 In the course of time, the time period,the back-end capacitor is full, the voltage of the enabling end of the boost control chip U1 does not reach the starting threshold, and the boost control chip U1 does not work until t F3 At moment, the voltage of the enabling end of the boost control chip U1 is charged to the starting threshold value, the boost control chip U1 starts to work, the grid voltage is slowly increased to 40V, the grid source voltage is increased to 12V, the NMOS tube Q1 is opened, and the circuit enters a normal working state.
As can be seen from fig. 4 and fig. 5, the invention can effectively raise the gate voltage to drive the N-channel NMOS Q1 on the positive line, and can adapt to the working conditions of different output filter capacitors by adjusting the working time of the booster circuit.
The positive line impact current suppression circuit based on the N-channel MOS tube uses common components such as a resistor, a capacitor, a voltage stabilizing tube, a diode, the N-channel MOS tube, a boost control chip and the like, and the boost control chip is enabled to work in a delayed mode by adjusting the resistance-capacitance parameter of the enabling end of the boost control chip, so that the reference voltage stabilizing source is boosted in a delayed mode to generate a driving signal higher than input voltage, and the driving signal is used for driving the N-channel MOS tube connected on a bus in series in a delayed mode. The charging time constant of the time delay work of the boost control chip isWherein->Is the resistance value of the resistor R3 +.>Is the capacitance of the capacitor C3. Before the N channel MOS tube is conducted, the power resistor connected in parallel with the N channel MOS tube charges the line-to-line capacitor, and startup surge current is accurately restrained. After the N-channel MOS tube is conducted, the power resistor is bypassed, and the direct current input power supply supplies energy for the later stage with extremely low power loss.
The positive line impact current suppression circuit based on the N-channel MOS tube has the following characteristics: (1) The peak value of the startup surge current can be accurately restrained, the line-to-line capacitor is charged through the power resistor after startup, and the bus surge current at the startup moment can be effectively restrained; (2) The N-channel MOS tube arranged on the positive line is driven to be conducted through delayed charging, and after the N-channel MOS tube is conducted, a charging power resistor is bypassed, so that power loss in normal operation is reduced; (3) The positive line impact current suppression circuit is based on the N-channel MOS tube and is arranged on the input positive line, so that the problem that the impact current suppression circuit is invalid due to the grounding of the negative line is avoided while the power loss during normal operation is reduced, and the applicability is stronger; (4) The power loss caused by reverse connection prevention of the positive line can be reduced by expanding the power supply device with reverse connection prevention protection function based on the positive line NMOS tube.
The terms "R1", "R3", and the like in the description and in the claims are used for distinguishing between similar objects and not necessarily for limiting the number of objects. Furthermore, in the description herein, reference to the terms "one embodiment," "some embodiments," "an exemplary embodiment," "an example," "a particular example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present invention and the core ideas thereof; also, it is within the scope of the present invention to be modified by those of ordinary skill in the art in light of the present teachings. In view of the foregoing, this description should not be construed as limiting the invention.

Claims (10)

1. The positive line impact current suppression circuit based on the N-channel MOS tube is characterized by comprising: the power resistor R1, the NMOS tube Q1, the input filter capacitor C1, the reference voltage stabilizing source, the delay charging circuit, the booster circuit, the voltage division feedback circuit, the boost output filter capacitor C4, the floating resistor R5 and the output filter capacitor C5; the reference voltage stabilizing source adopts a voltage stabilizing tube D2; the delay charging circuit comprises a resistor R3 and a capacitor C3; the boost circuit comprises an inductor L1, a diode D3 and a boost control chip U1; the voltage division feedback circuit comprises a resistor R7 and a resistor R6;
the drain electrode of the NMOS tube Q1 and one end of the power resistor R1 are connected with a direct current input power supply positive line VIN+; the source electrode of the NMOS tube Q1 is respectively connected with the other end of the power resistor R1, one end of the input filter capacitor C1, the negative electrode of the voltage stabilizing tube D2, one end of the resistor R3, one end of the inductor L1 and one end of the output filter capacitor C5; the enabling end EN of the boost control chip U1 is respectively connected with the other end of the resistor R3 and one end of the capacitor C3; the SW terminal of the boost control chip U1 is respectively connected with the other end of the inductor L1 and the anode of the diode D3; the cathode of the diode D3 is respectively connected with one end of the resistor R7, one end of the boost output filter capacitor C4 and the grid electrode of the NMOS tube Q1; the FB terminal of the boost control chip U1 is respectively connected with the other end of the resistor R7 and one end of the resistor R6; the positive electrode of the voltage stabilizing tube D2, the other end of the capacitor C3, the GND terminal of the boost control chip U1, the other end of the resistor R6 and the other end of the boost output filter capacitor C4 are all connected with one end of the floating resistor R5; the other end of the floating resistor R5 is respectively connected with the other end of the input filter capacitor C1 and the other end of the output filter capacitor C5.
2. The positive line impact current suppression circuit based on the N-channel MOS tube according to claim 1, wherein the other end of the input filter capacitor C1 is also connected with a direct current input power negative line VIN-; the direct current input power supply positive line VIN+ and the direct current input power supply negative line VIN-are respectively connected with two ends of the direct current input power supply.
3. The positive line surge current suppression circuit based on the N-channel MOS transistor according to claim 2, wherein the direct current input power supply charges line-to-line capacitance through a power resistor R1Is (1) a charging time constant ofThe method comprises the steps of carrying out a first treatment on the surface of the Wherein->Is the resistance value of the power resistor R1, +.>Is the capacitance of the line-to-line capacitance.
4. The positive line rush current suppression circuit based on an N-channel MOS tube of claim 3, wherein the rush current peak value at the starting instant of the DC input power supply isThe method comprises the steps of carrying out a first treatment on the surface of the Wherein->The power supply voltage is input for direct current.
5. The positive line impact current suppression circuit based on the N-channel MOS transistor according to claim 1, wherein two ends of the output filter capacitor C5 are respectively connected with an output positive line VOUT+ and an output negative line VOUT-.
6. The utility model provides a positive line impulse current suppression circuit based on N channel MOS pipe of protection function is prevented reverse connection in area which characterized in that includes: the power resistor R1, the NMOS tube Q2, the input filter capacitor C1, a reference voltage stabilizing source, a delay charging circuit, a boost circuit, a voltage division feedback circuit, a boost output filter capacitor C4, a floating resistor R5 and an output filter capacitor C5; the reference voltage stabilizing source adopts a voltage stabilizing tube D2; the delay charging circuit comprises a resistor R3 and a capacitor C3; the boost circuit comprises an inductor L1, a diode D3 and a boost control chip U1; the voltage division feedback circuit comprises a resistor R7 and a resistor R6;
the drain electrode of the NMOS tube Q1 and one end of the power resistor R1 are connected with a direct current input power supply positive line VIN+; the source electrode of the NMOS tube Q1 is respectively connected with the other end of the power resistor R1 and the source electrode of the NMOS tube Q2; the drain electrode of the NMOS tube Q2 is respectively connected with one end of the input filter capacitor C1, the negative electrode of the voltage stabilizing tube D2, one end of the resistor R3, one end of the inductor L1 and one end of the output filter capacitor C5; the enabling end EN of the boost control chip U1 is respectively connected with the other end of the resistor R3 and one end of the capacitor C3; the SW terminal of the boost control chip U1 is respectively connected with the other end of the inductor L1 and the anode of the diode D3; the cathode of the diode D3 is respectively connected with one end of the resistor R7, one end of the boost output filter capacitor C4, the grid electrode of the NMOS tube Q1 and the grid electrode of the NMOS tube Q2; the FB terminal of the boost control chip U1 is respectively connected with the other end of the resistor R7 and one end of the resistor R6; the positive electrode of the voltage stabilizing tube D2, the other end of the capacitor C3, the GND terminal of the boost control chip U1, the other end of the resistor R6 and the other end of the boost output filter capacitor C4 are all connected with one end of the floating resistor R5; the other end of the floating resistor R5 is respectively connected with the other end of the input filter capacitor C1 and the other end of the output filter capacitor C5.
7. The positive line impact current suppression circuit with the reverse connection prevention protection function and based on the N-channel MOS tube as claimed in claim 6, wherein the other end of the input filter capacitor C1 is also connected with a direct current input power negative line VIN-; the direct current input power supply positive line VIN+ and the direct current input power supply negative line VIN-are respectively connected with two ends of the direct current input power supply.
8. The positive line surge current suppression circuit with reverse connection prevention protection function based on an N-channel MOS tube as claimed in claim 7, wherein the charging time constant of the direct current input power supply for charging the line-to-line capacitor through the power resistor R1 isThe method comprises the steps of carrying out a first treatment on the surface of the Wherein->Is the resistance value of the power resistor R1, +.>Is the capacitance of the line-to-line capacitance.
9. The positive line surge current suppression circuit with reverse connection prevention protection function based on the N-channel MOS tube as claimed in claim 8, wherein the surge current peak value at the starting moment of the direct current input power supply isThe method comprises the steps of carrying out a first treatment on the surface of the Wherein->The power supply voltage is input for direct current.
10. The positive line impact current suppression circuit with the reverse connection prevention protection function and based on the N-channel MOS tube as claimed in claim 6, wherein two ends of the output filter capacitor C5 are respectively connected with an output positive line VOUT+ and an output negative line VOUT-.
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