CN217642711U - Input surge voltage and starting current suppression circuit based on MOSFET - Google Patents
Input surge voltage and starting current suppression circuit based on MOSFET Download PDFInfo
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- CN217642711U CN217642711U CN202221524474.2U CN202221524474U CN217642711U CN 217642711 U CN217642711 U CN 217642711U CN 202221524474 U CN202221524474 U CN 202221524474U CN 217642711 U CN217642711 U CN 217642711U
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Abstract
The utility model discloses an input surge voltage and starting current suppression circuit based on MOSFET, including MOS pipe Q2, the electric capacity C3 of control MOS pipe miller voltage time, the stabilivolt ZD2 of control clamp voltage amplitude and the charge pump drive circuit who uses U2 as the core, the utility model discloses a C3 electric capacity is adjusted MOS pipe and is opened the time length of stage miller voltage, and the constant current characteristic that utilizes miller voltage stage generating line current Id carries out the constant current to electric capacity and charges and restrain starting current, and through the linear voltage stabilizing circuit that ZD2 and Q2 constitute, when surge voltage arrives, the linear region that utilizes MOS pipe clamps surge voltage, the utility model discloses the characteristic of the self of make full use of MOS pipe uses a MOS pipe, has solved the transient surge voltage problem promptly and has solved the starting impulse current problem again, and MOS loss is low during normal work, and is efficient, and a whole set of circuit parameter is adjustable, and is extensive in application.
Description
Technical Field
The utility model relates to a starting circuit technical field specifically is an input surge voltage and starting current suppression circuit based on MOSFET.
Background
Transient surge voltage generated by on-off inductive load or on-off high-power load, circuit fault and the like in the system can damage the power supply if the voltage is not inhibited at the front stage of the power supply and exceeds the bearable limit voltage value of the input end of the power supply.
The conventional method is to use a voltage dependent resistor and a TVS for suppression at the front stage of a power supply, and although the passive clamping is simple, the problems of easy aging and damage of components, low clamping voltage precision and the like exist, so that the problems can be effectively solved due to the occurrence of an active surge voltage suppression circuit.
At the moment of starting the power supply, because the power supply input circuit part is designed with a large-capacity electrolytic capacitor, microsecond-level impact current can be generated, and if the impact current is too large, misoperation of other electric components in the system can be caused, so that an impact current suppression circuit needs to be added at the front end of the power supply to reduce the adverse effect of the power supply starting moment on the system.
The common method is to directly connect the negative temperature coefficient thermistor in series or connect the high-power resistor and the relay in series to solve the problem, although the scheme of connecting the negative temperature coefficient thermistor in series is simple, the loss is large, the efficiency is low, the components are easy to age, the scheme of connecting the high-power resistor in series and the relay in series is large in size, an auxiliary power supply and a delay circuit are required to be added for controlling the relay, and the circuit is complex, so the prior art needs to be improved and improved.
Originally need design one set of circuit when dealing with the interior surge voltage problem of system, need design another set of circuit when dealing with impulse current problem when the power starts in addition, need two sets of circuits altogether to solve above problem respectively.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide an input surge voltage and starting current suppression circuit based on MOSFET uses one set of circuit can solve input transient state surge voltage's problem and starting impulse current's problem simultaneously.
In order to achieve the above purpose, the utility model provides a following technical scheme: an input surge voltage and starting current suppression circuit based on MOSFET comprises an input end anode VIN +, an input end cathode VIN-, an output end anode Vout + and an output end cathode Vout-, the input end anode VIN + is respectively connected with a pin 2 of an MOS tube Q2 and a pin 1 of a resistor R1, a pin 2 of the resistor R1 is connected with a pin 1 of a resistor R2, a pin 2 of the resistor R2 is connected with a pin 1 of a resistor R3, a pin 2 of the resistor R3 is connected with a pin 2 of a voltage stabilizing tube ZD1, a pin 2 of the resistor R3 is connected with a pin 1 of a capacitor C2, a pin 2 of the resistor R3 is connected with a pin 8 of an integrated circuit U2, a pin 1 of the voltage stabilizing tube ZD1 is connected with an output end cathode Vout-, a pin 2 of the capacitor C2 is connected with a pin 2 of an output end cathode Vout-, a pin 8 of the integrated circuit U2 is connected with a pin 4 of the integrated circuit U2, a pin 8 of the integrated circuit U2 is connected with a pin 2 of a pin of a resistor R24, a pin 1 of the resistor R24 is connected with a pin 2 of a pin of a resistor R23, a pin 1 of a resistor R24 is connected with a pin 7 of an integrated circuit U2, a pin 1 of a resistor R23 is connected with a pin 1 of a capacitor C6, a pin 1 of a resistor R23 is connected with a pin 2 of the integrated circuit U2, a pin 2 of the integrated circuit U2 is connected with a pin 6 of the integrated circuit U2, a pin 2 of the capacitor C6 is connected with a pin 1 of the integrated circuit U2, a pin 2 of the capacitor C6 is connected with a negative pole Vout-of an output end, a pin 5 of the integrated circuit U2 is connected with a pin 1 of a capacitor C8, a pin 2 of the capacitor C8 is connected with a negative pole Vout-of the output end, a pin 3 of the integrated circuit U2 is connected with a pin 2 of a resistor R22, a pin 1 of an MOS tube Q2 is connected with a pin 2 of a resistor R16, a pin 1 of the MOS tube Q2 is connected with a pin 2 of a voltage regulator tube ZD4, a pin 3 of the MOS tube Q2 is connected with a pin 1 of the voltage regulator tube ZD4, a pin 3 of the MOS tube Q2 is connected with a positive pole Vout + of the output end, a pin 1 of the resistor R16 is connected with a pin 1 of the capacitor C3, and a pin 2 of the resistor ZD2 is connected with a voltage regulator tube ZD4, a pin 1 of a resistor R16 is connected with a pin 1 of a resistor R17, a pin 2 of a capacitor C3 is connected with a negative electrode Vout-of an output end, a pin 1 of a voltage-regulator tube ZD3 is connected with the negative electrode Vout-of the output end, a pin 2 of the voltage-regulator tube ZD3 is connected with a pin 2 of the resistor R17, a pin 2 of the resistor R17 is connected with a pin 1 of a resistor R19, a pin 1 of the voltage-regulator tube ZD3 is connected with a positive electrode Vout + of the output end, a pin 2 of the resistor R19 is connected with a pin 2 of a diode D3, a pin 1 of the diode D3 is connected with a pin 1 of a capacitor C4, a pin 1 of the diode D3 is connected with a pin 2 of a diode D2, a pin 1 of the diode D2 is connected with a positive electrode Vout + of the output end, and a pin 2 of the capacitor C4 is connected with a pin 1 of a resistor R22.
Further, the MOS transistor Q2 is an N-channel MOS transistor.
Further, the capacitor C3 is a chip multilayer ceramic capacitor.
Further, the voltage regulator tube ZD2 is a voltage regulator diode.
Further, the charge pump driving circuit of the integrated circuit U2 is an MOS transistor driving circuit formed by using a 555 integrated circuit chip as a core, and includes an integrated circuit chip U2, a resistor R1, a resistor R2, a resistor R3, a resistor R16, a resistor R17, a resistor R19, a resistor R22, a resistor R23, a resistor R24, a capacitor C2, a capacitor C4, a capacitor C6, a capacitor C8, a diode D2, a diode D3, a zener diode ZD1, a zener diode ZD3, and a zener diode ZD4.
Compared with the prior art, the beneficial effects of the utility model are as follows:
the utility model discloses an input surge voltage and starting current suppression circuit based on MOSFET uses one set of circuit can solve the surge voltage problem simultaneously and starts the impulse current problem, through the time length of C3 capacitance control MOS pipe opening stage miller voltage, utilizes the constant current characteristic of miller voltage stage busbar current Id to carry out the constant current to electric capacity and charge and restrain the starting current, through ZD2 and the linear voltage stabilizing circuit that Q2 constitutes, when surge voltage arrives, utilizes the linear region of MOS pipe to clamp surge voltage, the utility model discloses the characteristics of itself of make full use of MOS pipe use a MOS pipe, have both solved transient state surge voltage problem and have solved the starting impulse current problem again, and MOS loss is low during normal work, and is efficient, and a whole set of circuit parameter is adjustable, uses extensively.
Drawings
Fig. 1 is a circuit diagram of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 1, an input surge voltage and start current suppression circuit based on a MOSFET according to an embodiment of the present invention includes an input end positive electrode VIN +, an input end negative electrode VIN-, an output end positive electrode Vout +, and an output end negative electrode Vout-, the input end positive electrode VIN + is respectively connected to pin 2 of a MOS transistor Q2 and pin 1 of a resistor R1, pin 2 of the resistor R1 is connected to pin 1 of a resistor R2, pin 2 of the resistor R2 is connected to pin 1 of a resistor R3, pin 2 of the resistor R3 is connected to pin 2 of a regulator ZD1, pin 2 of the resistor R3 is connected to pin 1 of a capacitor C2, pin 2 of the resistor R3 is connected to pin 8 of an integrated circuit U2, pin 1 of the regulator ZD1 is connected to an output end negative electrode Vout-, pin 2 of the capacitor C2 is connected to output end negative electrode Vout-, pin 8 of the integrated circuit U2 is connected to pin 4 of the integrated circuit U2, pin 8 of the integrated circuit U2 is connected to pin 2 of a resistor R24, a pin 1 of a resistor R24 is connected with a pin 2 of a resistor R23, a pin 1 of the resistor R24 is connected with a pin 7 of an integrated circuit U2, a pin 1 of the resistor R23 is connected with a pin 1 of a capacitor C6, a pin 1 of the resistor R23 is connected with a pin 2 of the integrated circuit U2, a pin 2 of the integrated circuit U2 is connected with a pin 6 of the integrated circuit U2, a pin 2 of the capacitor C6 is connected with a pin 1 of the integrated circuit U2, a pin 2 of the capacitor C6 is connected with a pin 2 of an output end cathode Vout-, a pin 5 of the integrated circuit U2 is connected with a pin 1 of a capacitor C8, a pin 2 of the capacitor C8 is connected with a pin 2 of the output end cathode Vout-, a pin 3 of the integrated circuit U2 is connected with a pin 2 of a resistor R22, a pin 1 of an MOS tube Q2 is connected with a pin 2 of a resistor R16, a pin 1 of the MOS tube Q2 is connected with a pin 2 of a pin ZD4, a pin 3 of the MOS tube Q2 is connected with a pin 1 of a stabilivolt ZD4, a pin 3 of the MOS tube Q2 is connected with a pin Vout + of the output end, and a pin 3 of the capacitor C16 is connected with a pin 1 of the stabilivolt C3, a pin 1 of a resistor R16 is connected with a pin 2 of a voltage regulator tube ZD2, a pin 1 of the resistor R16 is connected with a pin 1 of a resistor R17, a pin 2 of a capacitor C3 is connected with a negative electrode Vout-of an output end, a pin 1 of the voltage regulator tube ZD3 is connected with a negative electrode Vout-of the output end, a pin 2 of the voltage regulator tube ZD3 is connected with a pin 2 of the resistor R17, a pin 2 of the resistor R17 is connected with a pin 1 of a resistor R19, a pin 1 of the voltage regulator tube ZD3 is connected with an anode Vout + of the output end, a pin 2 of the resistor R19 is connected with a pin 2 of a diode D3, a pin 1 of the diode D3 is connected with a pin 1 of a capacitor C4, a pin 1 of the diode D3 is connected with a pin 2 of a diode D2, a pin 1 of the diode D2 is connected with an anode Vout + of the output end, and a pin 2 of the capacitor C4 is connected with a pin 1 of a resistor R22.
In the above embodiment, the MOS transistor Q2 is an N-channel MOS transistor; the capacitor C3 is a sheet-shaped multilayer ceramic capacitor; the voltage stabilizing tube ZD2 is a voltage stabilizing diode; the charge pump driving circuit of the integrated circuit U2 is an MOS tube driving circuit which takes a 555 integrated circuit chip as a core, and comprises the integrated circuit chip U2, a resistor R1, a resistor R2, a resistor R3, a resistor R16, a resistor R17, a resistor R19, a resistor R22, a resistor R23, a resistor R24, a capacitor C2, a capacitor C4, a capacitor C6, a capacitor C8, a diode D2, a diode D3, a zener diode ZD1, a zener diode ZD3 and a zener diode ZD4.
The working principle is as follows: when the MOS tube works normally, an input voltage of 110V forms a stabilized voltage supply through resistors R1, R2 and R3 and a stabilized voltage diode ZD1, ZD1 is a 12V stabilized voltage tube, the stabilized voltage supply can output 12V, a capacitor C2 is used for filtering for a power supply, the 12V voltage is connected to an 8 pin of a U2 integrated circuit chip 555 to be used as a power supply voltage, a circuit formed by the U2, the resistors R24, R23 and the capacitor C6 generates a high-frequency square wave with the frequency of 110K, peak detection and level displacement are carried out by the resistors R22, C4, D2 and D3, the voltage at a node connected with the resistors C4 and D3 is changed into a square wave with the low level of 110V and the high level of about 120V, the square wave charges the capacitor C3 through the resistors D3, R17 and R19, the voltage filtered by the C3 is stabilized through the resistors R16 and R4 to supply power to a grid electrode of the MOS tube Q2, the grid source voltage is controlled to be more than 10V, the MOS tube works in a saturation region, the MOS tube Q2 is conducted, the MOS tube has milliohm loss, the output voltage drop and the output voltage and the fundamental input voltage is very low voltage.
When surge voltage of an input end surges, for example, the surge voltage of 385V and 10mS is inrush, ZD2 is a 170V voltage stabilizing diode, after the inrush surge voltage exceeds the voltage stabilizing value of ZD2, ZD2 starts to act, the voltage of a grid electrode of Q2 cannot rise along with the inrush surge high voltage, the grid electrode voltage of Q2 is reduced along with the clamping action of ZD2, the MOS tube enters a linear region, the output voltage is stabilized near 170V at the moment, surge voltage Uds generated between drain electrodes at two ends of the MOS tube in the inrush moment absorbs energy, the voltage difference Uds is the difference between the input voltage and the output voltage, the output voltage is stabilized near the voltage stabilizing value of ZD2, and the high-voltage and low-energy peaks are absorbed by the MOS tube Q2 at the moment when the surge voltage suppression process is finished.
The same circuit can also inhibit starting impact current at the moment of power supply starting, can change the switching characteristic curve of the MOS tube Q2 by adjusting the capacitance value of the C3 capacitor, and prolong the time of working at Miller voltage in the starting process of the MOS tube, so as to prolong the time of working in a constant current state when the MOS tube is started, and achieve the effect of charging a rear-end capacitor in an approximately constant current state, thereby playing the role of inhibiting surge current at the moment of power-on, wherein the smaller the capacitance value of C3 is, the shorter the constant-current charging time is, the weaker the ability of inhibiting starting impact current is, the larger the capacitance value of C3 is, the longer the constant-current charging time is, the stronger the ability of inhibiting starting impact current is, but the capacitance value of C3 cannot be too large, the MOS tube is burnt due to too long constant-current charging time, and the capacitance value of C3 is selected according to the size of a filter capacitor at the actual input end and the impact resistance of the MOS tube when the circuit is actually used.
In conclusion: the utility model provides an input surge voltage and starting current suppression circuit based on MOSFET, two kinds of problems are solved to one set of circuit, and the peripheral device that the circuit used is few, and control circuit is simple reliable, can effectively reduce the starting impulse current and reduce the adverse effect to the system, and the back power of clamper surge voltage protection improves the stability of system, and the components and parts normal during operation low power dissipation that the circuit used, efficient uses components and parts few, and the operational reliability is high.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (5)
1. The utility model provides an input surge voltage and starting current suppression circuit based on MOSFET, includes positive input VIN +, input negative pole VIN-, positive output Vout + and the negative output Vout-, its characterized in that: the positive electrode VIN + of the input end is respectively connected with a pin 2 of an MOS transistor Q2 and a pin 1 of a resistor R1, a pin 2 of the resistor R1 is connected with a pin 1 of the resistor R2, a pin 2 of the resistor R2 is connected with a pin 1 of a resistor R3, a pin 2 of the resistor R3 is connected with a pin 2 of a voltage stabilizing tube ZD1, a pin 2 of the resistor R3 is connected with a pin 1 of a capacitor C2, a pin 2 of the resistor R3 is connected with a pin 8 of an integrated circuit U2, a pin 1 of the voltage stabilizing tube ZD1 is connected with a negative electrode Vout-of the output end, and a pin 2 of the capacitor C2 is connected with a negative electrode Vout-of the output end;
the pin 8 of the integrated circuit U2 is connected with the pin 4 of the integrated circuit U2, the pin 8 of the integrated circuit U2 is connected with the pin 2 of the resistor R24, the pin 1 of the resistor R24 is connected with the pin 2 of the resistor R23, the pin 1 of the resistor R24 is connected with the pin 7 of the integrated circuit U2, the pin 1 of the resistor R23 is connected with the pin 1 of the capacitor C6, the pin 1 of the resistor R23 is connected with the pin 2 of the integrated circuit U2, the pin 2 of the integrated circuit U2 is connected with the pin 6 of the integrated circuit U2, the pin 2 of the capacitor C6 is connected with the pin 1 of the integrated circuit U2, the pin 2 of the capacitor C6 is connected with the negative pole Vout < - >, the pin 5 of the integrated circuit U2 is connected with the pin 1 of the capacitor C8, and the pin 2 of the capacitor C8 is connected with the negative pole Vout < - >;
a pin 3 of an integrated circuit U2 is connected with a pin 2 of a resistor R22, a pin 1 of an MOS tube Q2 is connected with a pin 2 of a resistor R16, a pin 1 of the MOS tube Q2 is connected with a pin 2 of a voltage regulator tube ZD4, a pin 3 of the MOS tube Q2 is connected with a pin 1 of the voltage regulator tube ZD4, a pin 3 of the MOS tube Q2 is connected with an anode Vout + of an output end, a pin 1 of the resistor R16 is connected with a pin 1 of a capacitor C3, a pin 1 of the resistor R16 is connected with a pin 2 of the voltage regulator tube ZD2, a pin 1 of the resistor R16 is connected with a pin 1 of the resistor R17, a pin 2 of the capacitor C3 is connected with a cathode Vout-of the output end, a pin 1 of the voltage regulator tube ZD3 is connected with a cathode Vout-of the output end, a pin 2 of the voltage regulator tube ZD3 is connected with a pin 2 of the resistor R17, a pin 2 of the resistor R17 is connected with a pin 1 of the resistor R19, a pin 1 of the voltage regulator tube ZD3 is connected with an anode Vout + Vout of the output end, a pin 2 of the diode ZD3 is connected with a pin 2 of the diode D3, a pin 1 of the diode D4, and a diode D2 of the diode D4 is connected with a diode D2 of the diode D4, and a diode D4 of the diode D2 of the diode D4.
2. A MOSFET-based input surge voltage and start-up current suppression circuit according to claim 1, wherein: and the MOS tube Q2 is an N-channel MOS tube.
3. A MOSFET-based input surge voltage and start-up current suppression circuit according to claim 1, wherein: the capacitor C3 is a sheet-shaped multilayer ceramic capacitor.
4. A MOSFET-based input surge voltage and start-up current suppression circuit according to claim 1, wherein: and the voltage stabilizing tube ZD2 is a voltage stabilizing diode.
5. A MOSFET based input surge voltage and start-up current suppression circuit according to claim 1, wherein: the charge pump driving circuit of the integrated circuit U2 is an MOS tube driving circuit which is formed by taking a 555 integrated circuit chip as a core, and comprises an integrated circuit chip U2, a resistor R1, a resistor R2, a resistor R3, a resistor R16, a resistor R17, a resistor R19, a resistor R22, a resistor R23, a resistor R24, a capacitor C2, a capacitor C4, a capacitor C6, a capacitor C8, a diode D2, a diode D3, a voltage stabilizing diode ZD1, a voltage stabilizing diode ZD3 and a voltage stabilizing diode ZD4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221524474.2U CN217642711U (en) | 2022-06-17 | 2022-06-17 | Input surge voltage and starting current suppression circuit based on MOSFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221524474.2U CN217642711U (en) | 2022-06-17 | 2022-06-17 | Input surge voltage and starting current suppression circuit based on MOSFET |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217642711U true CN217642711U (en) | 2022-10-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221524474.2U Active CN217642711U (en) | 2022-06-17 | 2022-06-17 | Input surge voltage and starting current suppression circuit based on MOSFET |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217642711U (en) |
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2022
- 2022-06-17 CN CN202221524474.2U patent/CN217642711U/en active Active
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