CN220021114U - Silicon gate MOS integrated circuit with ESD protection circuit structure - Google Patents

Abstract

The utility model discloses a silicon gate MOS integrated circuit with an ESD protection circuit structure, which comprises: an internal integration module and an electrostatic protection module; the electrostatic protection module is arranged between the internal integration module and the external equipment; the electrostatic protection module is used for conducting a communication loop between the external equipment and the grounding end of the silicon gate MOS integrated circuit when detecting that the voltage value of the electric signal transmitted by the external equipment is larger than or equal to the voltage value of the protection trigger voltage. According to the utility model, when the electrostatic protection module detects that the electric signal transmitted by the external equipment is an electrostatic large-voltage signal, namely, the voltage value of the electric signal is larger than or equal to the voltage value of the protection trigger voltage, the electric signal input by the external equipment is quickly released through a communication loop between the external equipment and the grounding end of the silicon gate MOS integrated circuit before being input into the internal integrated module, so that the accidental occurrence of burning the internal integrated module of the silicon gate MOS integrated circuit is avoided.

Description

Silicon gate MOS integrated circuit with ESD protection circuit structure

Technical Field

The utility model relates to the technical field of ESD protection circuits, in particular to a silicon gate MOS integrated circuit with an ESD protection circuit structure.

Background

The silicon gate MOS integrated circuit is an integrated circuit which is formed by taking a Metal Oxide Semiconductor (MOS) field effect transistor as a main element, and the electrostatic capacity of a core circuit of the traditional silicon gate integrated circuit is greatly reduced along with the gradual increase of the density of the MOS integrated circuit and the gradual decrease of the size of components; on the other hand, the silicon gate integrated circuit generally contains more materials such as plastics, rubber and the like which are easy to generate and accumulate static electricity, so that the probability of the integrated circuit being damaged by the static electricity is greatly increased. Therefore, the silicon gate MOS integrated circuit is extremely vulnerable to electrostatic shock signals. In order to solve the above-mentioned problems, there is a need for a silicon gate MOS integrated circuit having an ESD (Electro-Static discharge) protection circuit structure.

The foregoing is provided merely for the purpose of facilitating understanding of the technical solutions of the present utility model and is not intended to represent an admission that the foregoing is prior art.

Disclosure of Invention

The utility model mainly aims to provide a silicon gate MOS integrated circuit with an ESD protection circuit structure, which aims to solve the technical problem that the existing silicon gate MOS integrated circuit is damaged due to electrostatic impact.

In order to achieve the above object, the present utility model provides a silicon gate MOS integrated circuit having an ESD protection circuit structure, the silicon gate MOS integrated circuit having an ESD protection circuit structure comprising:

an internal integration module and an electrostatic protection module;

the static protection module is arranged between the internal integration module and external equipment;

and the electrostatic protection module is used for conducting a communication loop between the external equipment and the grounding end of the silicon gate MOS integrated circuit when detecting that the voltage value of the electric signal transmitted by the external equipment is greater than or equal to the voltage value of the protection trigger voltage.

Optionally, the electrostatic protection module includes: the circuit control submodule and the electrostatic discharge submodule, the protection trigger voltage comprises: a first protection trigger voltage;

the path control sub-module is respectively connected with the electrostatic discharge sub-module, the internal integration module and the external equipment, and the electrostatic discharge sub-module is respectively connected with the internal integration module and the external equipment;

the passage control sub-module is used for transmitting a first passage signal to the electrostatic discharge sub-module when detecting that the voltage value of the electric signal transmitted by the external equipment is larger than or equal to the voltage value of the switching voltage;

and the electrostatic discharge sub-module is used for conducting a communication loop between the external equipment and the grounding end of the silicon gate MOS integrated circuit when the first channel signal is received and the voltage value of the electric signal transmitted by the external equipment is detected to be larger than or equal to the voltage value of the first protection trigger voltage.

Optionally, the protection trigger voltage further includes: a second protection trigger voltage;

the path control sub-module is further configured to send a second path signal to the electrostatic discharge sub-module when detecting that the voltage value of the electrical signal sent by the external device is smaller than the voltage value of the switching voltage;

and the electrostatic discharge sub-module is used for conducting a communication loop between the external equipment and the grounding end of the silicon gate MOS integrated circuit when the second path signal is received and the voltage value of the electric signal transmitted by the external equipment is detected to be larger than or equal to the voltage value of the second protection trigger voltage.

Optionally, the electrostatic discharge submodule includes: a voltage control unit and an electrostatic protection unit;

the voltage control unit is respectively connected with the access control sub-module and the static protection unit, and the static protection unit is connected with the external equipment;

the voltage control unit is used for conducting the electrostatic protection unit and the first grid grounding loop of the grounding end when receiving the first channel signal;

the electrostatic protection unit is used for conducting a communication loop between the external equipment and the grounding end of the silicon gate MOS integrated circuit when the first gate grounding loop is conducted and the voltage value of the electric signal transmitted by the external equipment is detected to be larger than or equal to the voltage value of the first protection trigger voltage;

the voltage control unit is used for conducting the second grid grounding loop of the grounding end and the electrostatic protection unit when the second path signal is received;

and the electrostatic protection unit is used for conducting a communication loop between the external equipment and the grounding end of the silicon gate MOS integrated circuit when the second grid grounding loop is conducted and the voltage value of the electric signal transmitted by the external equipment is detected to be larger than or equal to the voltage value of the first protection trigger voltage.

Optionally, the internal integration module includes: an internal integrated unit and a first resistor;

the first end of the first resistor is connected with the external equipment, the path control submodule and the electrostatic discharge submodule respectively;

the second end of the first resistor is connected with the internal integrated unit.

Optionally, the path control submodule includes: the second resistor, the capacitor and the voltage stabilizing tube;

the first end of the second resistor is respectively connected with the external equipment, the first end of the first resistor and the electrostatic protection unit, and the second end of the second resistor is respectively connected with the first end of the capacitor, the cathode of the voltage stabilizing tube and the voltage control unit;

and the second end of the capacitor and the anode of the voltage stabilizing tube are grounded.

Optionally, the voltage control unit includes: a first NMOS tube;

the grid electrode of the first NMOS tube is respectively connected with the second end of the second resistor, the first end of the capacitor and the cathode of the voltage stabilizing tube, the drain electrode of the first NMOS tube is respectively connected with the electrostatic protection unit, and the source electrode of the first NMOS tube is grounded.

Optionally, the electrostatic protection unit includes: the second NMOS tube and the third resistor;

the first end of the third resistor is connected with the drain electrode of the first NMOS tube and the grid electrode of the second NMOS tube respectively, and the drain electrode of the second NMOS tube is connected with the first end of the first resistor, the first end of the second resistor and the external equipment respectively;

and the source electrode of the second NMOS tube and the second end of the third resistor are grounded.

Optionally, the electrostatic protection unit further includes: a PMOS tube and a fourth resistor;

the source electrode of the PMOS tube is connected with the source electrode of the second NMOS tube, the drain electrode and the grid electrode of the PMOS tube are connected with the substrate of the second NMOS tube and the first end of the fourth resistor, and the second end of the fourth resistor is grounded.

The utility model discloses a silicon gate MOS integrated circuit with an ESD protection circuit structure, which comprises an internal integrated module and an electrostatic protection module; the electrostatic protection module is arranged between the internal integration module and the external equipment; and the electrostatic protection module is used for conducting a communication loop between the external equipment and the grounding end of the silicon gate MOS integrated circuit when detecting that the voltage value of the electric signal transmitted by the external equipment is greater than or equal to the voltage value of the protection trigger voltage. The electrostatic protection module includes: the circuit control submodule and the static electricity release submodule are used for protecting trigger voltage, and the trigger voltage comprises: a first protection trigger voltage; the passage control submodule is respectively connected with the static electricity discharge submodule, the internal integration module and the external equipment, and the static electricity discharge submodule is respectively connected with the internal integration module and the external equipment; the access control sub-module is used for transmitting a first access signal to the electrostatic discharge sub-module when detecting that the voltage value of the electric signal transmitted by the external equipment is greater than or equal to the voltage value of the switching voltage; and the electrostatic discharge sub-module is used for conducting a communication loop between the external equipment and the grounding end of the silicon gate MOS integrated circuit when the first channel signal is received and the voltage value of the electric signal transmitted by the external equipment is detected to be larger than or equal to the voltage value of the first protection trigger voltage. The protection trigger voltage further includes: a second protection trigger voltage; the access control sub-module is also used for transmitting a second access signal to the electrostatic discharge sub-module when detecting that the voltage value of the electric signal transmitted by the external equipment is smaller than the voltage value of the switching voltage; and the electrostatic discharge sub-module is used for conducting a communication loop between the external equipment and the grounding end of the silicon gate MOS integrated circuit when the second path signal is received and the voltage value of the electric signal transmitted by the external equipment is detected to be larger than or equal to the voltage value of the second protection trigger voltage. According to the utility model, different access signals can be transmitted to the electrostatic discharge submodule through the access control submodule according to the electric signals transmitted by external equipment, so that the electrostatic discharge submodule selects an electrostatic protection unit grid grounding loop corresponding to the received access signals, the electrostatic protection unit is provided with a corresponding protection trigger voltage, and the electrostatic protection structure of the silicon gate MOS integrated circuit can be closed in a normal working state, and the electric signals of the external equipment are not influenced to be normally input into the internal integrated unit; when external electrostatic signals are poured into the silicon gate MOS integrated circuit to generate quick power-on large-voltage signals (namely, when the voltage value of an electric signal transmitted by external equipment is larger than or equal to the voltage value of the second protection trigger voltage) or other types of large-voltage signals (namely, when the voltage value of an electric signal transmitted by external equipment is larger than or equal to the voltage value of the first protection trigger voltage), the electrostatic protection structure can correspondingly conduct and rapidly discharge electrostatic current. Therefore, the utility model not only can enable the electric signal input by the external equipment to be released rapidly through the communication loop between the external equipment and the grounding end of the silicon gate MOS integrated circuit before being input into the internal integrated module, thereby avoiding the accidental occurrence of burning the internal integrated module of the silicon gate MOS integrated circuit, but also can effectively protect the silicon gate integrated circuit from being damaged by static electricity and simultaneously not affect the normal operation of the silicon gate MOS integrated circuit, and has high reliability; and when a large electrostatic voltage signal is input, the third resistor arranged between the grid electrode of the second NMOS tube and the ground can reduce the voltage value of the first protection trigger voltage of the electrostatic protection structure, namely, the large electrostatic impact signal can be quickly discharged, so that the response speed of the electrostatic protection circuit can be improved, and the reliability of electrostatic protection of the silicon gate MOS integrated circuit is further improved.

Drawings

In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a first functional block diagram of a first embodiment of a silicon gate MOS integrated circuit with an ESD protection circuit structure according to an embodiment of the present utility model;

fig. 2 is a second functional block diagram of a first embodiment of a silicon gate MOS integrated circuit with an ESD protection circuit structure according to an embodiment of the present utility model;

fig. 3 is a third functional block diagram of a first embodiment of a silicon gate MOS integrated circuit with an ESD protection circuit structure according to an embodiment of the present utility model;

fig. 4 is a schematic circuit diagram of a path control sub-module in a first embodiment of a silicon gate MOS integrated circuit having an ESD protection circuit structure according to an embodiment of the present utility model;

fig. 5 is a schematic circuit diagram of an electrostatic protection unit in a first embodiment of a silicon gate MOS integrated circuit having an ESD protection circuit structure according to an embodiment of the present utility model;

fig. 6 is a schematic circuit diagram of a first embodiment of a silicon gate MOS integrated circuit with an ESD protection circuit structure according to an embodiment of the present utility model;

fig. 7 is a schematic circuit diagram of an electrostatic protection unit in a second embodiment of a silicon gate MOS integrated circuit with an ESD protection circuit structure according to an embodiment of the present utility model;

fig. 8 is a schematic circuit diagram of a second embodiment of a silicon gate MOS integrated circuit with an ESD protection circuit structure according to an embodiment of the present utility model.

Reference numerals illustrate:

reference numerals	Name of the name	Reference numerals	Name of the name
				C	Capacitance device	R1～R4	First to fourth resistors
Q1～Q2	First to second NMOS transistors	Q3	PMOS tube
				D	Drain electrode	G	Grid electrode
S	Source electrode	ZD	Voltage stabilizing tube

The achievement of the objects, functional features and advantages of the present utility model will be further described with reference to the accompanying drawings, in conjunction with the embodiments.

Detailed Description

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.

The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

It should be noted that the description of "first", "second", etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implying an indication of the number of technical features being indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the technical solutions should be considered that the combination does not exist and is not within the scope of protection claimed by the present utility model.

Referring to fig. 1, fig. 1 is a functional block diagram of a first embodiment of a silicon gate MOS integrated circuit with an ESD protection circuit structure according to an embodiment of the present utility model, and based on fig. 1, a first embodiment of a silicon gate MOS integrated circuit with an ESD protection circuit structure according to the present utility model is proposed.

In this embodiment, the silicon gate MOS integrated circuit with the ESD protection circuit structure includes: an internal integration module and an electrostatic protection module 20;

the electrostatic protection module 20 is disposed between the internal integration module and the external device 1;

the electrostatic protection module 20 is configured to, when detecting that the voltage value of the electrical signal transmitted by the external device 1 is greater than or equal to the voltage value of the protection trigger voltage, turn on a communication loop between the external device 1 and the ground terminal of the silicon gate MOS integrated circuit.

It should be noted that, the external device 1 may transmit an electrical signal through the input/output port of the silicon gate MOS integrated module, where the electrical signal should be transmitted to the electrostatic protection module 20 first and then to the internal integrated module, and the internal integrated module is an internal core module for implementing the main function of the silicon gate MOS integrated circuit. It can be understood that the electrostatic protection module 20 is disposed between the internal integrated module and the external device 1, so that electrostatic impact transmitted by the external device 1 can be released as soon as possible, and accidents caused by delayed release and burning of devices of the internal integrated module can be avoided.

It should be understood that, in order to ensure that the static electricity impact flows to the static electricity protection module 20 after being input into the silicon gate MOS integrated circuit through the input/output port, the internal integrated module in this embodiment may include: the device comprises an internal integrated unit and a first resistor R1, wherein a first end of the first resistor R1 is respectively connected with an external device 1, a path control sub-module 201 and an electrostatic discharge sub-module 202; the second end of the first resistor R1 is connected with the internal integrated unit. The first resistor R1 may have a buffer resistor added between the internal integrated unit (i.e. the core functional unit of the silicon gate MOS integrated circuit) and the input/output port connected to the external device, and due to the current limiting and voltage limiting effects of the first resistor R1, more current flowing into the input/output port of the silicon gate MOS integrated circuit from the external device 1 may flow to the electrostatic protection module 20 first, so that a certain delay function may be provided when the electrostatic impact arrives, so that the electrostatic protection module 20 performs a larger protection function, and the ESD resistance of the silicon gate MOS integrated circuit is improved.

It is easy to understand that the ESD protection module 20 only starts ESD protection when the silicon gate MOS integrated circuit is subjected to the input of electrostatic shock by the external device 1, and in the normal operating state of the silicon gate integrated circuit, the electrostatic protection device in the electrostatic protection module 20 is required to be in a closed state, so as to avoid affecting the normal operation of the silicon gate MOS integrated circuit.

Therefore, further, as shown in fig. 2, fig. 2 is a second functional block diagram of a first embodiment of a silicon gate MOS integrated circuit with an ESD protection circuit structure according to an embodiment of the present utility model, where the electrostatic protection module 20 includes: the path control sub-module 201 and the electrostatic discharge sub-module 202, the protection trigger voltage includes: a first protection trigger voltage;

the path control sub-module 201 is respectively connected with the electrostatic discharge sub-module 202, the internal integration module and the external device 1, and the electrostatic discharge sub-module 202 is respectively connected with the internal integration module and the external device 1;

the path control sub-module 201 is configured to send a first path signal to the electrostatic discharge sub-module 202 when detecting that the voltage value of the electrical signal sent by the external device 1 is greater than or equal to the voltage value of the switching voltage;

the electrostatic discharge sub-module 202 is configured to, when the first channel signal is received and the voltage value of the electrical signal transmitted by the external device 1 is detected to be greater than or equal to the voltage value of the first protection trigger voltage, turn on a communication loop between the external device 1 and the ground terminal of the silicon gate MOS integrated circuit.

The protection trigger voltage further includes: a second protection trigger voltage;

the path control sub-module 201 is further configured to send a second path signal to the electrostatic discharge sub-module 202 when detecting that the voltage value of the electrical signal sent by the external device 1 is smaller than the voltage value of the switching voltage;

the electrostatic discharge sub-module 202 is configured to, when the second path signal is received and the voltage value of the electrical signal transmitted by the external device 1 is detected to be greater than or equal to the voltage value of the second protection trigger voltage, turn on a communication loop between the external device 1 and the ground terminal of the silicon gate MOS integrated circuit.

It should be noted that, the above-mentioned path control sub-module 201 may be configured to transmit different path signals (the first path signal and the second path signal) to the electrostatic discharge sub-module 202 according to the voltage value of the electrical signal input by the external device, and the corresponding protection trigger voltages after the electrostatic discharge sub-module 202 receives the different path signals are different. Specifically, after the first path signal is input to the electrostatic discharge sub-module 202, the protection trigger voltage of the electrostatic discharge sub-module 202 corresponds to the first protection trigger voltage; after the first path signal is input to the electrostatic discharge sub-module 202, the protection trigger voltage of the electrostatic discharge sub-module 202 is correspondingly the second protection trigger voltage.

It should be understood that the voltage values of the first protection trigger voltage and the second protection trigger voltage are not the same, but as long as the voltage value of the electrical signal transmitted by the external device 1 received by the electrostatic discharge sub-module 202 is greater than or equal to the voltage value of the first protection trigger voltage or the second protection trigger voltage, the electrostatic discharge sub-module 202 will conduct the communication loop between the external device 1 and the ground terminal of the silicon gate MOS integrated circuit.

Further, as shown in fig. 3, fig. 3 is a third functional block diagram of a first embodiment of a silicon gate MOS integrated circuit with an ESD protection circuit structure according to an embodiment of the present utility model, where the electrostatic discharge sub-module 202 includes: a voltage control unit 2021 and an electrostatic protection unit 2022;

the voltage control unit 2021 is connected to the path control sub-module 201 and the electrostatic protection unit 2022, and the electrostatic protection unit 2022 is connected to the external device 1;

the voltage control unit 2021 is configured to send an on signal to the electrostatic protection unit 2022 when receiving the driving signal; the electrostatic protection unit 2022 is configured to, when receiving the start signal, turn on a communication loop between the external device 1 and the ground.

The voltage control unit 2021 is further configured to send a shutdown signal to the electrostatic protection unit 2022 when receiving the stop signal; the electrostatic protection unit 2022 is further configured to shut off a communication loop between the external device 1 and the ground terminal when the shutdown signal is received.

It should be noted that, the voltage control unit 2021 may be configured to control the actual trigger voltage of the electrostatic protection structure of the silicon gate MOS integrated circuit to be the first protection trigger voltage or the second protection trigger voltage; the electrostatic protection unit 2022 is configured to conduct a communication loop drain between the external device 1 and the ground terminal of the silicon gate MOS integrated circuit when detecting that the electrical signal transmitted by the external device 1 is greater than the actual trigger voltage (the first protection trigger voltage or the second protection trigger voltage).

Specifically, as shown in fig. 4, fig. 4 is a schematic circuit diagram of a path control sub-module 201 in a first embodiment of a silicon gate MOS integrated circuit with ESD protection circuit structure according to an embodiment of the present utility model, where the path control sub-module 201 includes: the second resistor R2, the capacitor C and the voltage stabilizing tube ZD;

the first end of the second resistor R2 is respectively connected with the external device 1, the first end of the first resistor R1 and the electrostatic protection unit 2022, and the second end of the second resistor R2 is respectively connected with the first end of the capacitor C, the cathode of the voltage stabilizing tube ZD and the voltage control unit 2021;

the second end of the capacitor C and the anode of the voltage stabilizing tube ZD are grounded.

Specifically, the voltage control unit 2021 includes: a first NMOS tube Q1;

the gate G of the first NMOS transistor Q1 is connected to the second end of the second resistor R2, the first end of the capacitor C, and the cathode of the regulator ZD, the drain D of the first NMOS transistor Q1 is connected to the electrostatic protection unit 2022, and the source S of the first NMOS transistor Q1 is grounded.

Specifically, as shown in fig. 5, fig. 5 is a schematic circuit diagram of an electrostatic protection unit 2022 in a first embodiment of a silicon gate MOS integrated circuit with an ESD protection circuit structure according to an embodiment of the present utility model, where the electrostatic protection unit 2022 includes: a second NMOS tube Q2 and a third resistor R33;

the first end of the third resistor R3 is connected with the drain electrode D of the first NMOS transistor Q1 and the gate electrode G of the second NMOS transistor Q2, and the drain electrode D of the second NMOS transistor Q2 is connected with the first end of the first resistor R1, the first end of the second resistor R2 and the external device 1;

the source S of the second NMOS transistor Q2 and the second end of the third resistor R3 are grounded.

It should be noted that, as shown in fig. 4, the electrical signal transmitted by the external device 1 in the embodiment will first flow through the second resistor R2 and the capacitor C, and then flow to the voltage stabilizing tube ZD. The voltage at the cathode of the regulator tube ZD rises slowly due to the charge-discharge characteristic of the capacitor C. Since the voltage value of the electrostatic signal is too large compared with the voltage value of the normal power-on signal, the electrostatic signal appears as a fast power-on signal in practical application, so when the electrostatic impact signal is input, the voltage increase speed at the cathode of the voltage regulator ZD will be far later than the voltage increase speed input by the electrostatic protection unit 2022, and the embodiment can determine whether the electrical signal input by the external device 1 is the electrostatic signal based on the voltage increase speed.

It should be understood that the second NMOS transistor Q2 in the electrostatic protection unit 2022 does not have an ability to withstand electrostatic current, and actually the structure for implementing the ESD protection function is a parasitic bipolar transistor in the second NMOS transistor Q2. In practical application, after a large voltage is input to the drain electrode D of the second NMOS transistor Q2 with the grounded gate electrode G, the reverse PN junction between the drain electrode D and the substrate is broken down, so that the substrate current of the second NMOS transistor Q2 is gradually increased, the gradually increased substrate current can forward bias the PN junction between the substrate and the source electrode S, and further the parasitic NPN formed by the drain electrode D, the source electrode S and the substrate of the second NMOS transistor Q2 is turned on, so that the electrostatic large current can be released based on the turned-on parasitic NPN, thereby achieving clamping of the voltage of the input/output port, and clamping the voltage at the first end of the first resistor R1 under normal voltage to realize electrostatic protection; when the negative ESD stress is faced, the forward biased diode formed by the P-well region and the drain D in the second NMOS transistor Q2 can also realize electrostatic protection.

It should be understood that if the resistor R is added between the gate G and the ground of the second NMOS transistor Q2 with the grounded gate G, the parasitic NPN in the second NMOS transistor Q2 can be released to enable the electrostatic current to flow more, so as to protect the thin gate oxide layer of each MOS device in the internal integrated module, and enable the ESD protection structure of the silicon gate MOS integrated circuit to exert a larger protection effect; the voltage divider is also equivalent to a voltage divider between the gate electrode G and the source electrode S of the second NMOS transistor Q2, so as to reduce the voltage between the gate and the source of the second NMOS transistor Q2, further reduce the trigger voltage of the ESD protection circuit, and improve the reliability of the ESD protection circuit.

It can be understood that the larger the resistance of the connection resistor between the gate G and the ground of the second NMOS transistor Q2, the more the voltage division is, the smaller the voltage between the gate G and the source S is, and the smaller the trigger voltage of the ESD protection circuit is. Therefore, as shown in fig. 4, if the gate G of the second NMOS transistor Q2 is grounded through the third resistor R3 in the present embodiment, the corresponding ESD protection trigger voltage is low (because the resistance of the third resistor R3 is generally large, the voltage division effect is strong); in the embodiment, if the gate G of the second NMOS transistor Q2 passes through the voltage control unit 2021, i.e. the first NMOS transistor Q1 is grounded, the corresponding ESD protection trigger voltage is higher (because the resistance of the first NMOS transistor Q1 is usually smaller, the voltage division effect is smaller). Therefore, if the first NMOS transistor Q1 is turned on, the corresponding ESD trigger voltage is the first protection trigger voltage; when the first NMOS transistor Q1 is turned off, the corresponding ESD trigger voltage is the second protection trigger voltage, so the first NMOS transistor Q1 indirectly controls the ESD trigger voltage.

It is to be understood that, in conjunction with the above analysis, the voltage regulator ZD in the present embodiment can be used to control the ground loop conduction of different gates G of the dead point protection unit. Specifically, the switching voltage may be a reverse breakdown voltage of the voltage regulator ZD, when the channel control module detects that the voltage value of the electrical signal transmitted by the external device 1 is greater than or equal to the voltage value of the switching voltage, the voltage regulator ZD breaks down reversely, so as to clamp the gate voltage G of the first NMOS transistor Q1, which is equivalent to transmitting the first channel signal to the electrostatic discharge sub-module 202 to turn on the first NMOS transistor Q1, so that the gate electrode G of the second NMOS transistor Q2 is grounded through the first NMOS transistor Q1, that is, the gate electrode G of the second NMOS transistor Q2 is grounded with low resistance, at this time, the ESD protection trigger voltage corresponding to the electrostatic protection unit 2022 is the first protection trigger voltage, and the voltage value of the first protection trigger voltage is greater; when the path control module detects that the voltage value of the electrical signal transmitted by the external device 1 is smaller than the voltage value of the switching voltage, the voltage stabilizing tube ZD is not conducted, which is equivalent to transmitting the second path signal to the electrostatic discharge sub-module 202 to cut off the first NMOS tube Q1, so that the gate G of the second NMOS tube Q2 is grounded through the third resistor R3, that is, the gate G of the second NMOS tube Q2 is grounded with high resistance, at this time, the ESD protection trigger voltage corresponding to the electrostatic protection unit 2022 is the second protection trigger voltage, and the voltage value of the second protection trigger voltage is smaller.

In practical application, for ease of understanding, taking fig. 6 as an example for illustration, fig. 6 is a schematic circuit diagram of a silicon gate MOS integrated circuit with an ESD protection circuit structure in a first embodiment of the silicon gate MOS integrated circuit according to the embodiment of the present utility model, as shown in fig. 6, when a port is normally powered on, a difference between a voltage at a drain D of the second NMOS transistor Q2 and a voltage at a cathode of the voltage regulator tube ZD is not large, when the voltage at the drain D of the second NMOS transistor Q2 is raised, the voltage at the cathode of the voltage regulator tube ZD is also raised synchronously, when the voltage at the cathode of the voltage regulator tube ZD is raised to a switching voltage, the voltage regulator tube ZD breaks down reversely, so that a voltage of a gate G of the first NMOS transistor Q1 is raised to a conducting voltage and clamped, which is equivalent to transmitting a first channel signal to the first NMOS transistor Q1 to conduct the first NMOS transistor Q1, and further, the gate G of the second NMOS transistor Q2 is grounded through the first NMOS transistor Q1, that is connected to a low resistance, and at this time, the gate G of the second NMOS transistor Q2 and the third NMOS transistor Q3 have a trigger voltage value larger than the trigger voltage. The voltage value of the normal power-on voltage received at the drain D of the second NMOS transistor Q2 is usually not greater than the voltage value of the first protection trigger voltage, so that the second NMOS transistor Q2 is usually not turned on, i.e. the electrical signal transmitted by the external device 1 can normally flow into the internal integrated module. It is easy to understand that, if the voltage value delivered by the external device 1 is greater than the voltage value of the first protection trigger voltage, the second NMOS Q2 is still turned on and is turned on as a leakage path to protect the devices of the internal integrated module of the silicon gate MOS integrated circuit.

When the external device 1 inputs a rapidly-rising electrostatic large voltage signal to the silicon gate MOS integrated circuit, the voltage rising speed difference between the cathode of the voltage stabilizing tube ZD and the drain D of the second NMOS tube Q2 is larger. When the voltage at the drain D of the second NMOS transistor Q2 rises rapidly, the second resistor R2 and the first capacitor C control the cathode of the regulator tube ZD to fail to rise rapidly, the regulator tube ZD will not breakdown reversely, the voltage of the gate G of the first NMOS transistor Q1 cannot rise to the on voltage (i.e. the above-mentioned switching voltage), and the first NMOS transistor Q1 is turned off. At this time, the gate G of the second NMOS Q2 may be grounded through the third resistor R3, and since the voltage value of the second protection trigger voltage corresponding to the ESD protection structure formed by the second NMOS Q2 and the third resistor R3 is low, the input voltage received at the drain D of the second NMOS Q2 will be rapidly greater than the second protection trigger voltage, so that the second NMOS Q2 is rapidly opened as a leakage path.

As can be seen from the above analysis, the electrostatic protection unit 2022 provided in the present embodiment is provided with two paths of the ground paths of the gate G, so that the ESD protection structure of the electrostatic protection unit 2022 can be quickly turned on only when the drain D is subjected to the electrostatic large voltage signal, and the normal power-on operation of the silicon gate MOS integrated circuit is not affected. In the normal working state of the silicon gate MOS integrated circuit, the electrostatic discharge protection device (namely the second NMOS tube Q2) is in a closed state, and the electric signal input of the input/output port is not influenced; when external electrostatic signals are injected into the silicon gate MOS integrated circuit to generate quick power-on high-voltage signals or other types of large-voltage signals are suffered by the input/output port, the electrostatic discharge protection device (namely the second NMOS tube Q2) is correspondingly conducted to quickly discharge electrostatic current or other types of large current.

The present embodiment proposes a silicon gate MOS integrated circuit having an ESD protection circuit structure, the silicon gate MOS integrated circuit having the ESD protection circuit structure including: an internal integration module and an electrostatic protection module; the electrostatic protection module is arranged between the internal integration module and the external equipment; and the electrostatic protection module is used for conducting a communication loop between the external equipment and the grounding end of the silicon gate MOS integrated circuit when detecting that the voltage value of the electric signal transmitted by the external equipment is greater than or equal to the voltage value of the protection trigger voltage. An electrostatic protection module, comprising: the circuit control submodule and the static electricity release submodule are used for protecting trigger voltage, and the trigger voltage comprises: a first protection trigger voltage; the passage control submodule is respectively connected with the static electricity discharge submodule, the internal integration module and the external equipment, and the static electricity discharge submodule is respectively connected with the internal integration module and the external equipment; the access control sub-module is used for transmitting a first access signal to the electrostatic discharge sub-module when detecting that the voltage value of the electric signal transmitted by the external equipment is greater than or equal to the voltage value of the switching voltage; and the electrostatic discharge sub-module is used for conducting a communication loop between the external equipment and the grounding end of the silicon gate MOS integrated circuit when the first channel signal is received and the voltage value of the electric signal transmitted by the external equipment is detected to be larger than or equal to the voltage value of the first protection trigger voltage. The protection trigger voltage further includes: a second protection trigger voltage; the access control sub-module is also used for transmitting a second access signal to the electrostatic discharge sub-module when detecting that the voltage value of the electric signal transmitted by the external equipment is smaller than the voltage value of the switching voltage; and the electrostatic discharge sub-module is used for conducting a communication loop between the external equipment and the grounding end of the silicon gate MOS integrated circuit when the second path signal is received and the voltage value of the electric signal transmitted by the external equipment is detected to be larger than or equal to the voltage value of the second protection trigger voltage. According to the embodiment, different access signals can be transmitted to the electrostatic discharge submodule through the access control submodule according to the electric signals transmitted by external equipment, so that the electrostatic discharge submodule selects an electrostatic protection unit grid grounding loop corresponding to the received access signals, the electrostatic protection unit sets corresponding protection trigger voltage, and the electrostatic protection structure of the silicon gate MOS integrated circuit can be closed in a normal working state, and the electric signals of the external equipment are not influenced to be normally input into the internal integrated unit; when external electrostatic signals are poured into the silicon gate MOS integrated circuit to generate quick power-on large-voltage signals (namely, when the voltage value of an electric signal transmitted by external equipment is larger than or equal to the voltage value of the second protection trigger voltage) or other types of large-voltage signals (namely, when the voltage value of an electric signal transmitted by external equipment is larger than or equal to the voltage value of the first protection trigger voltage), the electrostatic protection structure can correspondingly conduct and rapidly discharge electrostatic current. Therefore, the embodiment not only can enable the electric signal input by the external equipment to be released rapidly through the communication loop between the external equipment and the grounding end of the silicon gate MOS integrated circuit before being input into the internal integrated module, thereby avoiding the accidental occurrence of burning the internal integrated module of the silicon gate MOS integrated circuit, but also can effectively protect the silicon gate integrated circuit from being damaged by static electricity and simultaneously not affect the normal operation of the silicon gate MOS integrated circuit, and has high reliability; and when the electrostatic large voltage signal is input, the third resistor arranged between the grid electrode of the second NMOS tube and the ground can reduce the voltage value of the first protection trigger voltage of the electrostatic protection structure, namely, the electrostatic large impact signal can be quickly discharged when the electrostatic large impact signal is input, so that the response speed of the electrostatic protection circuit can be improved, and the electrostatic protection reliability of the silicon gate MOS integrated circuit is further improved.

Referring to fig. 7, fig. 7 is a functional block diagram of a second embodiment of a silicon gate MOS integrated circuit with ESD protection circuit structure according to an embodiment of the present utility model.

It can be understood that, after the parasitic transistor in the second NMOS transistor Q2 in the electrostatic protection unit 2022 is turned on due to the reverse avalanche breakdown of the drain-liner PN junction, the parasitic transistor needs to be prevented from being damaged due to the thermal breakdown of the electrostatic voltage, so the electrostatic protection triggering voltage in this embodiment may further include: a PMOS tube Q3 and a fourth resistor R4;

the source electrode S of the PMOS tube Q3 is connected with the source electrode S of the second NMOS tube Q2, the drain electrode D and the grid electrode G of the PMOS tube Q3 are connected with the substrate of the second NMOS tube Q2 and the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is grounded.

It should be noted that thermal breakdown refers to the fact that silicon in a MOS device is burned out by melting due to heat accumulation, and thus thermal breakdown is an irreversible damage. In order to avoid this, the above PMOS transistor Q3 and the fourth resistor R4 may be used to control the release current generated when the second NMOS transistor Q2 is turned on not to be too high, and at the same time, the maintenance voltage of the electrostatic protection unit 2022 may be increased, so as to improve the robustness of ESD protection.

It can be understood that, in order to ensure the reliability of the electrostatic discharge path, the resistance of the fourth resistor R4 in the present embodiment should be smaller than that of the first resistor R1 to ensure that the electrostatic signal flows to the electrostatic protection module 20 more.

In practical application, for ease of understanding, fig. 8 is taken as an example for illustration, and fig. 8 is a functional block diagram of a second embodiment of a silicon gate MOS integrated circuit with ESD protection circuit structure according to an embodiment of the present utility model. After the electrostatic current flows into the drain D of the second NMOS transistor Q2, the parasitic PNP of the PMOS transistor Q3 can be accelerated to turn on due to the amplifying action of the parasitic NPN of the second NMOS transistor Q2, so that the turn-on speed of the electrostatic protection structure after the PMOS transistor Q3 is increased is not greatly reduced. Meanwhile, the positive feedback network formed by the parasitic NPN of the second NMOS tube Q2 and the parasitic PNP formed between the second NMOS tube Q2 and the PMOS tube Q3 and the positive feedback network formed by the parasitic NPN of the second NMOS tube Q2 and the parasitic PNP of the PMOS tube Q3 have the effect of weakening each other, so that the latch-up effect can be avoided, and the thermal breakdown phenomenon of the second NMOS tube Q2 and the PMOS tube Q3 can be avoided. The fourth resistor R4 can further reduce the discharge current, thereby improving the sustain voltage and the robustness of ESD protection.

The embodiment discloses that the electrostatic protection unit further includes: a PMOS tube and a fourth resistor; the source electrode of the PMOS tube is connected with the source electrode of the second NMOS tube, the drain electrode and the grid electrode of the PMOS tube are connected with the substrate of the second NMOS tube and the first end of the fourth resistor, and the second end of the fourth resistor is grounded. The embodiment can avoid latch-up effect and thermal breakdown through the PMOS tube; the electrostatic discharge current can be reduced through the PMOS tube and the fourth resistor, so that the maintenance voltage is improved, and the robustness of the ESD protection is improved, namely the electrostatic protection reliability and the robustness of the silicon gate MOS integrated circuit can be further improved through the PMOS tube and the fourth resistor.

The foregoing description is only of the preferred embodiments of the present utility model, and is not intended to limit the scope of the utility model, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.

Claims (9)

1. A silicon gate MOS integrated circuit having an ESD protection circuit structure, the silicon gate MOS integrated circuit comprising: an internal integration module and an electrostatic protection module;

the static protection module is arranged between the internal integration module and external equipment;

and the electrostatic protection module is used for conducting a communication loop between the external equipment and the grounding end of the silicon gate MOS integrated circuit when detecting that the voltage value of the electric signal transmitted by the external equipment is greater than or equal to the voltage value of the protection trigger voltage.

2. A silicon gate MOS integrated circuit having an ESD protection circuit structure as recited in claim 1, wherein said electrostatic protection module comprises: the circuit control submodule and the electrostatic discharge submodule, the protection trigger voltage comprises: a first protection trigger voltage;

the path control sub-module is respectively connected with the electrostatic discharge sub-module, the internal integration module and the external equipment, and the electrostatic discharge sub-module is respectively connected with the internal integration module and the external equipment;

the passage control sub-module is used for transmitting a first passage signal to the electrostatic discharge sub-module when detecting that the voltage value of the electric signal transmitted by the external equipment is larger than or equal to the voltage value of the switching voltage;

and the electrostatic discharge sub-module is used for conducting a communication loop between the external equipment and the grounding end of the silicon gate MOS integrated circuit when the first channel signal is received and the voltage value of the electric signal transmitted by the external equipment is detected to be larger than or equal to the voltage value of the first protection trigger voltage.

3. The silicon gate MOS integrated circuit having an ESD protection circuit structure of claim 2, wherein the protection trigger voltage further comprises: a second protection trigger voltage;

the path control sub-module is further configured to send a second path signal to the electrostatic discharge sub-module when detecting that the voltage value of the electrical signal sent by the external device is smaller than the voltage value of the switching voltage;

and the electrostatic discharge sub-module is used for conducting a communication loop between the external equipment and the grounding end of the silicon gate MOS integrated circuit when the second path signal is received and the voltage value of the electric signal transmitted by the external equipment is detected to be larger than or equal to the voltage value of the second protection trigger voltage.

4. A silicon gate MOS integrated circuit having an ESD protection circuit structure as recited in claim 3, wherein said electrostatic discharge submodule comprises: a voltage control unit and an electrostatic protection unit;

the voltage control unit is respectively connected with the access control sub-module and the static protection unit, and the static protection unit is connected with the external equipment;

the voltage control unit is used for conducting the electrostatic protection unit and the first grid grounding loop of the grounding end when receiving the first channel signal;

the electrostatic protection unit is used for conducting a communication loop between the external equipment and the grounding end of the silicon gate MOS integrated circuit when the first gate grounding loop is conducted and the voltage value of the electric signal transmitted by the external equipment is detected to be larger than or equal to the voltage value of the first protection trigger voltage;

the voltage control unit is used for conducting the second grid grounding loop of the grounding end and the electrostatic protection unit when the second path signal is received;

and the electrostatic protection unit is used for conducting a communication loop between the external equipment and the grounding end of the silicon gate MOS integrated circuit when the second grid grounding loop is conducted and the voltage value of the electric signal transmitted by the external equipment is detected to be larger than or equal to the voltage value of the first protection trigger voltage.

5. A silicon gate MOS integrated circuit having an ESD protection circuit structure as in claim 4, wherein said internal integration module comprises: an internal integrated unit and a first resistor;

the first end of the first resistor is connected with the external equipment, the path control submodule and the electrostatic discharge submodule respectively;

the second end of the first resistor is connected with the internal integrated unit.

6. A silicon gate MOS integrated circuit having an ESD protection circuit structure as defined in claim 5, wherein said path control submodule comprises: the second resistor, the capacitor and the voltage stabilizing tube;

the first end of the second resistor is respectively connected with the external equipment, the first end of the first resistor and the electrostatic protection unit, and the second end of the second resistor is respectively connected with the first end of the capacitor, the cathode of the voltage stabilizing tube and the voltage control unit;

and the second end of the capacitor and the anode of the voltage stabilizing tube are grounded.

7. A silicon gate MOS integrated circuit having an ESD protection circuit structure as recited in claim 6, wherein said voltage control unit comprises: a first NMOS tube;

the grid electrode of the first NMOS tube is respectively connected with the second end of the second resistor, the first end of the capacitor and the cathode of the voltage stabilizing tube, the drain electrode of the first NMOS tube is respectively connected with the electrostatic protection unit, and the source electrode of the first NMOS tube is grounded.

8. A silicon gate MOS integrated circuit having an ESD protection circuit structure as recited in claim 7, wherein said electrostatic protection unit comprises: the second NMOS tube and the third resistor;

the first end of the third resistor is connected with the drain electrode of the first NMOS tube and the grid electrode of the second NMOS tube respectively, and the drain electrode of the second NMOS tube is connected with the first end of the first resistor, the first end of the second resistor and the external equipment respectively;

and the source electrode of the second NMOS tube and the second end of the third resistor are grounded.

9. The silicon gate MOS integrated circuit having an ESD protection circuit structure of claim 8 wherein the electrostatic protection unit further comprises: a PMOS tube and a fourth resistor;

the source electrode of the PMOS tube is connected with the source electrode of the second NMOS tube, the drain electrode and the grid electrode of the PMOS tube are connected with the substrate of the second NMOS tube and the first end of the fourth resistor, and the second end of the fourth resistor is grounded.