JP2011083043A - Power supply voltage control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power supply voltage control circuit capable of gradually starting a power supply voltage of a load circuit side even if a power supply having a low internal voltage is connected. <P>SOLUTION: A power supply input terminal and a bypass capacitor are connected to each other via a current limit resistor and an MOS switch which are inserted in parallel. A resistor for connecting a power supply input terminal to a gate and a second MOS switch inserted between the gate and a ground are connected to the gate of the MOS switch. A line for supplying a voltage of the bypass capacitor to the gate of the second MOS switch is provided. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a power supply voltage control circuit for controlling a rising characteristic of a power supply voltage in an electronic device, particularly a portable / power-saving electronic device.

  Many small electronic devices in recent years use a lithium ion battery having a large current capacity as a power source. Lithium ion batteries have low internal resistance and are particularly suitable for applications that consume large currents such as digital cameras.

JP 2003-187803 A

  On the other hand, in the case of a power-saving electronic device, since only a small capacitor of about 1 μF, for example, is provided as a bypass capacitor provided in the power input circuit, when a lithium ion battery having a low internal resistance is used as a power source, The bypass capacitor is charged at once, and the power supply starts up sharply. Some semiconductor circuits such as microcomputers built into power-saving devices require that the power supply voltage be raised over a certain period of time. If the power supply suddenly starts up, the circuit will be damaged. There was a risk of it.

  An object of the present invention is to provide a power supply voltage control circuit that gently raises the power supply voltage on the load circuit side even when a power supply having a small internal resistance is connected.

  According to the first aspect of the present invention, there are provided an input terminal connected to a power source, a bypass capacitor connected in parallel to a load circuit, and currents inserted in parallel between the input terminal and the hot terminal of the bypass capacitor. A limiting resistor and a MOS switch; and a switching circuit that turns off the MOS switch when a power source is connected to the input terminal and turns on when the voltage across the bypass capacitor exceeds a predetermined value. It is characterized by that.

  The invention according to claim 2 is characterized in that the switching circuit includes a resistor connecting the input terminal and the gate of the MOS switch, a second MOS switch inserted between the gate of the MOS switch and the ground, And a line for supplying the voltage of the hot terminal of the bypass capacitor to the gate of the second MOS switch.

  According to a third aspect of the present invention, a line for supplying the voltage of the hot terminal of the bypass capacitor to the gate of the second MOS switch includes a plurality of voltage dividing resistors for dividing the voltage of the hot terminal of the bypass capacitor, and a voltage dividing resistor. And a line connecting the pressure point and the gate of the second MOS switch.

  According to a fourth aspect of the present invention, there is provided a third MOS switch that is turned on when the power source is disconnected from the input terminal in parallel with the bypass capacitor.

  According to the present invention, since the power supply voltage is supplied to the bypass capacitor via the current limiting resistor when the power supply is turned on, the voltage (load voltage) on the bypass capacitor side gradually increases, and the load circuit is damaged. There is no. In addition, since the MOS switch is turned on and the current limiting resistor is short-circuited when the load voltage rises to a predetermined value or more, load regulation during operation is not deteriorated.

Circuit diagram of a power supply voltage control circuit according to an embodiment of the present invention Diagram showing changes in voltage and current when the power supply voltage control circuit is turned on Circuit diagram of a power supply voltage control circuit according to another embodiment of the present invention The figure which shows the change of the voltage and electric current at the time of power-off in other embodiment

A power supply voltage control circuit according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit diagram of a power supply voltage control circuit. A power source (for example, a lithium ion battery) BAT is connected to the input (INPUT) side via a power switch SW. A load circuit L is connected to the output (OUTPUT) side. The load circuit L is a power saving semiconductor circuit such as a microcomputer. A bypass capacitor C1 is provided in parallel with the load circuit L. The bypass capacitor C1 is a capacitor for absorbing voltage fluctuation due to power supply voltage ripple or load current fluctuation. In the case of a small power saving device, as the bypass capacitor C1, for example, a small one of about 1 μF is used.

  In this embodiment, the power source BAT is connected via the switch SW. However, a connector (plug, jack, etc.) is provided instead of the switch, and the power source BAT is connected to this connector. May be.

  Resistors R1 and R2 for current limitation are inserted in series in a path from the power supply BAT to the load circuit L. A PMOS transistor PMOS1 is connected in parallel with the resistor R2.

  The resistor R1 is a small resistor for preventing an overcurrent with respect to the PMOS transistor PMOS1. The resistance value of the resistor R1 is, for example, about 1Ω. The resistor R2 is a resistor that limits the rise when the power is turned on and restricts the voltage supplied to the load circuit L (hereinafter referred to as the load voltage) to rise gently. The resistance value of the resistor R2 is a relatively large value of about 4.7 kΩ, for example.

  The PMOS transistor PMOS1 has a source connected to the input (INPUT) side and a drain connected to the resistor R1 side. The voltage of INPUT is applied to the gate of the PMOS transistor PMOS1 through the resistor R4. As a result, when the power switch SW is turned on, the gate of the PMOS transistor PMOS1 is pulled up to the voltage of the power supply BAT (power supply voltage), and the gate-source voltage becomes a negative voltage, so the PMOS transistor PMOS1 is turned off. The resistance value of the resistor R4 is about 100 kΩ.

  Since the PMOS transistor PMOS1 is turned off when the power is turned on, the power supply voltage is supplied to the bypass capacitor C1 and the load circuit L via the resistors R1 and R2 when the power switch SW is turned on. Since the resistor R2 is sufficiently large as a resistor inserted in the power supply path, the load voltage, that is, the voltage across the bypass capacitor C1 rises slowly. Thereby, it is possible to prevent the voltage of the load circuit L from rising sharply.

  The drain of the NMOS transistor NMOS is connected to the gate of the PMOS transistor PMOS1 connected in parallel to the resistor R2. The source of the NMOS transistor NMOS is connected to the ground. Therefore, the NMOS transistor NMOS is off when the gate voltage is below the threshold value.

  A voltage Va obtained by dividing the load voltage, that is, the voltage across the bypass capacitor C1 by resistors R5 and R6, is applied to the gate of the NMOS transistor NMOS. When this Va becomes higher than the threshold voltage of the NMOS transistor NMOS, the transistor NMOS is turned on, and the gate of the PMOS transistor PMOS1 is grounded. When the gate of the PMOS transistor PMOS1 is grounded, the voltage between the gate and the source becomes positive and turns on, thereby short-circuiting the resistor R2. As a result, the resistor R2 is removed from the path from the power supply BAT to the load circuit L, and the resistance value in the power supply path is only the resistor R1, so that a large current can be supplied without voltage fluctuation. If the PMOS transistor PMOS1 can pass a large current, the resistor R1 is unnecessary.

  A discharging resistor R3 is connected between the input terminal INPUT and the ground. The resistance value of the resistor R3 is about 100 kΩ. When the power switch SW is turned off, the PMOS transistor PMOS1 is turned off because the drain voltage decreases. Therefore, the electric charge charged in the capacitor C1 is discharged through the resistors R5, R6 and the resistors R1, R2, R3.

  In this embodiment, the voltage divided by the resistors R5 and R6 is applied to the gate of the NMOS transistor NMOS. If the threshold voltage of the NMOS transistor is sufficiently high, the hot side of the bypass capacitor C1 and the gate of the NMOS transistor are applied. May be directly connected.

  FIG. 2 is a diagram showing changes in the voltage value of INPUT, the voltage value of the bypass capacitor C1 (load voltage value), and the current value of the bypass capacitor C1 when the power is turned on. The upper part of the figure shows the voltage value of the bypass capacitor C1, the middle part of the figure shows the current value of the bypass capacitor C1, and the lower part of the figure shows the change of the voltage value of the INPUT.

  When the power switch SW is turned on, the voltage of INPUT rises steeply to the power supply voltage. On the other hand, since a current gradually flows to the capacitor C1 via the resistors R1 and R2, the voltage between the terminals of the capacitor C1 gradually rises. Since the PMOS transistor PMOS1 is turned on when the inter-terminal voltage exceeds a certain value, the current flows all at once, the capacitor C1 is charged, and the inter-terminal voltage becomes the same as the power supply voltage.

  FIG. 3 is a diagram showing a modification of the power supply voltage control circuit. In this embodiment, another PMOS transistor PMOS2 is provided. The source of the PMOS transistor PMOS2 is connected between the resistors R1 and R2, and the drain of the PMOS transistor PMOS2 is grounded. The voltage of the input terminal INPUT is supplied to the source of the PMOS transistor PMOS2. Since the power supply voltage is applied to the gate while the power switch SW is on, the PMOS transistor PMOS2 is off, but when the power switch SW is off, the gate voltage drops to the drain voltage (0V). Therefore, the PMOS transistor PMOS2 is turned on. As a result, the electric charge stored in the bypass capacitor C1 is discharged via the resistors R1 and PMOS2 in addition to the paths of the resistors R5 and R6 and the resistors R1, R2 and R3, and quickly discharged as shown in FIG. Is done. FIG. 4 is a diagram illustrating changes in the power supply voltage and the voltage value (load voltage value) of the bypass capacitor C1 when the power is off.

  The resistors R2 and R3 can be replaced with a bidirectional constant current circuit.

Claims (4)

An input terminal connected to the power source;
A bypass capacitor connected in parallel to the load circuit;
A current limiting resistor and a MOS switch inserted in parallel with each other between the input terminal and the hot terminal of the bypass capacitor;
An open / close circuit that turns off the MOS switch when a power supply is connected to the input terminal, and turns on when the voltage across the bypass capacitor reaches a predetermined value;
Power supply voltage control circuit with   The open / close circuit includes a resistor connecting the input terminal and the gate of the MOS switch, a second MOS switch inserted between the gate of the MOS switch and the ground, and the hot terminal of the bypass capacitor. The power supply voltage control circuit according to claim 1, further comprising: a line that supplies a voltage to a gate of the second MOS switch.   A line for supplying the voltage of the hot terminal of the bypass capacitor to the gate of the second MOS switch includes a plurality of voltage dividing resistors that divide the voltage of the hot terminal of the bypass capacitor, a voltage dividing point, and the second point. The power supply voltage control circuit according to claim 2, further comprising a line connecting the gate of the MOS switch.   4. The power supply voltage control circuit according to claim 1, further comprising a third MOS switch that is turned on in parallel with the bypass capacitor when the power is cut off from the input terminal.

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