CN117767244A - Interface protection circuit and interface device - Google Patents
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- CN117767244A CN117767244A CN202410186509.3A CN202410186509A CN117767244A CN 117767244 A CN117767244 A CN 117767244A CN 202410186509 A CN202410186509 A CN 202410186509A CN 117767244 A CN117767244 A CN 117767244A
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Abstract
The invention provides an interface protection circuit and an interface device, which relate to the technical field of interface protection, wherein the interface protection circuit comprises: an input port, an output port, and a protection circuit disposed at the input port and the output port; the protection circuit includes: a switching circuit including a switch and a switch control circuit; the switch control circuit is used for responding to the overvoltage signal and controlling the switch to be in an off state based on the overvoltage signal; the overvoltage protection circuit is used for responding to the overvoltage event generated by the input port and sending an overvoltage signal to the switch control circuit; and the surge residual voltage discharging circuit is used for responding to the overvoltage signal and carrying out surge residual voltage discharging treatment on the output port based on the overvoltage signal. The interface protection circuit and the interface device provided by the invention can enable the surge residual voltage of the output port to be rapidly discharged, and protect the chip connected with the output port, thereby ensuring the service life of the chip and the service efficiency of the whole interface device.
Description
Technical Field
The present invention relates to the field of interface protection technologies, and in particular, to an interface protection circuit and an interface device.
Background
With the continuous development of interface technology, the application of interface technology capable of transmitting current, data, audio, video and other high-speed signals and meeting the charging of hundreds of watts or even higher wattage on mobile devices such as notebook computers, mobile phones, tablets and the like is becoming more common.
Such as USB (Universal Serial Bus, USB, universal serial bus) interfaces, but some interfaces, such as Type-C interfaces in USB interfaces, have very small size of Type-C connectors and sockets, and the distance between signal contacts is very narrow, so that the Type-C interfaces can easily cause short circuit between pins caused by mechanical twisting during plugging, and further damage chips behind the interfaces.
In addition, when an incompatible charging cable or an incompatible charger connection interface is used, the occurrence of damage to the chip is possibly aggravated, and the service life of the chip and the service efficiency of the interface device are seriously affected.
Disclosure of Invention
Accordingly, an objective of the present invention is to provide an interface protection circuit and an interface device for alleviating the above-mentioned problems.
In a first aspect, an embodiment of the present invention provides an interface protection circuit, including: an input port, an output port, and a protection circuit disposed at the input port and the output port; the input port is connected to an interface to be protected, and the output port is connected to a chip corresponding to the interface to be protected; the protection circuit includes: a switching circuit including a switch and a switch control circuit; the switch is connected in series on a connecting path of the input port and the output port; the control end of the switch is connected with the switch control circuit; the switch control circuit is used for responding to an overvoltage signal and controlling the switch to be in an off state based on the overvoltage signal; the input end of the overvoltage protection circuit is connected to the input port, and the output end of the overvoltage protection circuit is connected to the switch control circuit; the overvoltage protection circuit is used for responding to the input port to generate an overvoltage event and sending the overvoltage signal to the switch control circuit; the input end of the surge residual voltage bleeder circuit is connected to the output end of the overvoltage protection circuit, and the output end of the surge residual voltage bleeder circuit is connected to the output port; and the surge residual voltage discharging circuit is used for responding to the overvoltage signal and carrying out surge residual voltage discharging treatment on the output port based on the overvoltage signal.
With reference to the first aspect, the embodiment of the present invention provides a first possible implementation manner of the first aspect, where the surge residual voltage bleeder circuit includes a pulse circuit and a bleeder path, and the bleeder path is configured with a bleeder device with a preset impedance; the input end of the pulse circuit is connected with the output end of the overvoltage protection circuit, and the output end of the pulse circuit is connected with the discharge passage; the pulse circuit is used for responding to the overvoltage signal to generate a pulse signal and sending the pulse signal to the relief passage; the discharging passage is used for responding to the pulse signal and communicating with the discharging passage so that the discharging device can discharge the surge residual voltage of the output port.
With reference to the first possible implementation manner of the first aspect, the embodiment of the present invention provides a second possible implementation manner of the first aspect, where the pulse circuit is a single pulse circuit, and the pulse signal is a single pulse signal.
With reference to the second possible implementation manner of the first aspect, an embodiment of the present invention provides a third possible implementation manner of the first aspect, where the switch control circuit is further connected to the bleed-off path; the switch control circuit is further configured to send a bleed signal to the bleed path based on the over-voltage signal; the relief passage is also used for responding to the relief signal so that the relief device can carry out relief treatment on the surge residual voltage of the output port.
With reference to the first possible implementation manner of the first aspect, an embodiment of the present invention provides a fourth possible implementation manner of the first aspect, where the switch is formed by a power tube, and the switch control circuit is a turn-off circuit matched with the power tube.
With reference to the first aspect, an embodiment of the present invention provides a fifth possible implementation manner of the first aspect, where the interface protection circuit further includes a system protection circuit connected to the input port; the system protection circuit is used for responding to the overvoltage event generated by the input port and protecting the connection path of the input port and the output port.
With reference to the fifth possible implementation manner of the first aspect, the embodiment of the present invention provides a sixth possible implementation manner of the first aspect, wherein the system protection circuit includes an ESD protection circuit and/or a surge protection circuit.
With reference to the first aspect, an embodiment of the present invention provides a seventh possible implementation manner of the first aspect, where the interface protection circuit further includes an output clamping circuit connected to the output port; the output clamping circuit is used for clamping the output port voltage signal so as to carry out clamping protection on the output port.
In a second aspect, an embodiment of the present invention further provides an interface device, where the interface device is configured with the interface protection circuit in the first aspect.
With reference to the second aspect, an embodiment of the present invention provides a first possible implementation manner of the second aspect, where the interface device includes a plurality of interfaces to be protected, and each of the interfaces to be protected is configured with the interface protection circuit.
The embodiment of the invention has the following beneficial effects:
the interface protection circuit and the interface device provided by the embodiment of the invention are characterized in that a protection circuit is arranged between an input port and an output port of the interface protection circuit; the switch of the protection circuit is connected in series on the connecting path of the input port and the output port; the overvoltage protection circuit in the protection circuit can respond to the input port to generate an overvoltage event, and sends an overvoltage signal to the switch control circuit, so that the switch control circuit can respond to the overvoltage signal and control the switch to be in an off state, meanwhile, the surge residual voltage bleeder circuit can respond to the overvoltage signal and perform surge residual voltage bleeder treatment on the output port based on the overvoltage signal, the overvoltage protection circuit is matched with the surge residual voltage bleeder circuit to rapidly respond to the overvoltage event generated by the input port, further, the surge residual voltage of the output port is rapidly released, the protection effect is achieved on a chip connected with the output port, and further the service life of the chip and the service efficiency of the whole interface equipment are guaranteed.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In order to make the above objects, features and advantages of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are some embodiments of the invention and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a block diagram of an interface protection circuit according to an embodiment of the present invention;
FIG. 2 is a block diagram of another interface protection circuit according to an embodiment of the present invention;
FIG. 3 is a block diagram illustrating another interface protection circuit according to an embodiment of the present invention;
fig. 4 is an application schematic diagram of an interface protection circuit according to an embodiment of the present invention;
fig. 5 is a waveform diagram according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In general, the plugging of some interfaces is easy to occur the phenomenon of interface short circuit, such as Type-C interface, the size of the connector and the socket is very small, the distance between the signal contact points is also very narrow, and the Type-C interface is easy to cause the phenomenon of pin short circuit caused by mechanical twisting during plugging, thereby damaging the chip behind the interface.
For example, when charging a 100W USB interface, V BUS The highest voltage of the pin can reach 20V, and when the Type-C interface is inserted, V is easy to be caused due to mechanical distortion BUS Adjacent pins to pins and V BUS The pins are shorted and a momentary high voltage occurs in the interface, particularly the CC (configuration channel) pin or the SBU (sideband use) pin. The CC pins and SBU pins of the chips connected to the rear are generally only about 6V in withstand voltage, so that the short circuit between the pins is very easy to damage the rear chips, such as a USB-to-Type-C chip or a USB PD (power release) controller chip.
In addition, besides the problem that the mechanical twisting during the insertion of the Type-C interface may cause a short circuit, the use of an incompatible charging cable (cable), an incompatible charger (adapter), etc. may aggravate the occurrence of such damage. In extreme cases, due to the cable inductance and relatively high V BUS The existence of voltage, if short circuit occurs, the CC pin or SBU pin of the following chip can easily reach 30V, even higher surge voltage.
Based on the above, the interface protection circuit and the interface device provided by the embodiment of the invention can effectively alleviate the technical problems.
For the sake of understanding the present embodiment, first, an interface protection circuit disclosed in the present embodiment will be described in detail.
In one possible implementation manner, the embodiment of the invention provides an interface protection circuit, which includes: an input port, an output port, and a protection circuit disposed between the input port and the output port; the input port is connected to the interface to be protected, and the output port is connected to the chip corresponding to the protection interface.
The chip connected to the output port is usually an interface chip or a main control chip, such as a Type-C interface main control chip, or may be other chips or devices, etc., specifically, the embodiment of the present invention is not limited to this specific actual use situation.
Further, the interface to be protected refers to an input port where events such as short circuit, overvoltage, or ESD, surge, etc. of the system may occur.
Specifically, a block diagram of an interface protection circuit as shown in fig. 1 shows an input port 10, a protection circuit 20, and an output port 30.
Wherein the protection circuit 20 further includes:
a switching circuit including a switch 201 and a switch control circuit 202; the switch 201 is connected in series with the connection path of the input port and the output port; the control end of the switch is connected with the switch control circuit; a switch control circuit 202 for controlling the switch to be in an off state based on the overvoltage signal in response to the overvoltage signal;
an overvoltage protection circuit 203, an input terminal of the overvoltage protection circuit 203 is connected to the input port 10, and an output terminal of the overvoltage protection circuit is connected to the switch control circuit 202; the overvoltage protection circuit 203 is configured to send an overvoltage signal to the switch control circuit 202 in response to the input port 10 generating an overvoltage event, so that the switch control circuit 202 controls the switch 201 to be turned off;
a surge residual voltage bleeder circuit 204, wherein an input end of the surge residual voltage bleeder circuit 204 is connected to an output end of the overvoltage protection circuit 203, and an output end of the surge residual voltage bleeder circuit 204 is connected to the output port 30; the surge residual voltage discharging circuit is used for responding to the overvoltage signal and carrying out surge residual voltage discharging treatment on the output port based on the overvoltage signal.
In practical use, the overvoltage protection circuit used in the embodiment of the invention can adopt a fast response overvoltage protection circuit, is responsible for detecting the voltage of an input port, can fast respond and turn off a switch when overvoltage events such as surge voltage occur, and takes a Type-C interface as an example, the input port and the output port in the embodiment of the invention can be used for a CC or SBU channel of a main control chip of the Type-C interface, and the switch is in a closed state when signals are transmitted during normal operation, and when the channel of a CC pin or SBU pin has surge, for example, surge voltage exceeding 40V occurs, the overvoltage protection circuit 203 can respond to the overvoltage event and further disconnect the switch, and meanwhile, the surge residual voltage relief circuit 204 can perform surge residual voltage relief treatment on the output port so as to realize overvoltage protection of the main control chip of the Type-C interface.
Therefore, the interface protection circuit provided by the embodiment of the invention is provided with the protection circuit between the input port and the output port of the interface protection circuit; the switch of the protection circuit is connected in series on the connecting path of the input port and the output port; the overvoltage protection circuit in the protection circuit can respond to the input port to generate an overvoltage event, and sends an overvoltage signal to the switch control circuit, so that the switch control circuit can respond to the overvoltage signal and control the switch to be in an off state, meanwhile, the surge residual voltage bleeder circuit can respond to the overvoltage signal and perform surge residual voltage bleeder treatment on the output port based on the overvoltage signal, the overvoltage protection circuit is matched with the surge residual voltage bleeder circuit to rapidly respond to the overvoltage event generated by the input port, further, the surge residual voltage of the output port is rapidly released, the protection effect is achieved on a chip connected with the output port, and further the service life of the chip and the service efficiency of the whole interface equipment are guaranteed.
In practical use, the surge residual voltage bleeder circuit in the embodiment of the invention comprises a pulse circuit and a bleeder circuit, wherein the bleeder circuit is usually a rapid bleeder circuit and is generally configured with a bleeder device with preset impedance, wherein the bleeder device can be a device preset on an interface chip or a circuit with a bleeder function, such as a resistor, a diode or a MOS (metal oxide semiconductor) tube, and the like, and can be arranged in the bleeder circuit as the bleeder device.
For ease of understanding, fig. 2 shows a block diagram of another interface protection circuit based on fig. 1, where IN fig. 2, the input port is denoted as IN and the output port is denoted as OUT. The switch is denoted SW. Also, a pulse circuit 205 and a bleed path 206 of the surge residual voltage bleed circuit are further shown in fig. 2.
The input end of the pulse circuit 205 is connected with the output end of the overvoltage protection circuit 203, and the output end of the pulse circuit 205 is connected with the discharge passage 206; the pulse circuit 205 is configured to respond to the overvoltage signal, generate a pulse signal, and send the pulse signal to the bleed-off path 206; the bleed passage 206 is configured to communicate with the bleed passage 206 in response to the pulse signal, so that the bleed device bleeds the surge residual voltage of the output port.
In actual use, the pulse circuit is a single pulse circuit, and the corresponding pulse signal is a single pulse signal. After detecting that the voltage of the input port exceeds a set threshold, the overvoltage protection circuit can generate a low-to-high overvoltage signal to the single pulse circuit, and the single pulse circuit can generate a single pulse signal, for example, a pulse width signal of about a few microseconds is sent to the discharging passage to control the discharging passage to rapidly discharge the surge residual voltage of the input port, and in the discharging passage, proper discharging impedance can be configured to rapidly reduce the surge residual voltage of the output port, so that a chip behind the output port is safer.
Further, on the basis of fig. 2, fig. 3 also shows a block diagram of another interface protection circuit, wherein in fig. 3, the switch control circuit 202 is also connected to the bleed-off path 206; the switch control circuit 202 is further configured to send a bleed signal to the bleed path 206 based on the over-voltage signal; the bleed passage 206 is also configured to respond to a bleed signal to cause the bleed device to bleed the surge residual voltage at the output port.
In practical use, after the monopulse signal generated by the monopulse circuit shown in fig. 2 is sent to the bleeder circuit, the bleeder circuit is stopped once, that is, based on the monopulse signal, the bleeder circuit is triggered only once, and when the voltage of the input interface is always too high, the switch control circuit 202 always controls the switch to be in an off state, that is, the overvoltage protection circuit 203 always provides an overvoltage signal for the switch control circuit 202, so in fig. 3, the switch control circuit 202 is connected with the bleeder circuit 206, the switch control circuit 202 can send the bleeder signal to the bleeder circuit 206, so that the bleeder circuit 206 can further perform bleeder based on the bleeder signal sent by the switch control circuit 202 after bleeding based on the monopulse signal, that is, the monopulse circuit and the switch control circuit can jointly control the residual voltage to quickly bleed under normal operation.
IN addition, the above-mentioned switch control circuit 202 is connected to the bleed-off path 206, and when the system IN which the interface protection circuit operates is not powered, or when the single-pulse circuit cannot operate, the power is directly taken from the IN input terminal, that is, a signal capable of controlling the bleed-off path is generated by the switch control circuit of the switch SW, so that the residual voltage can be quickly bled off.
Further, in the embodiment of the present invention, the switch is configured by a power tube, and the switch control circuit is a power tube matched turn-off circuit, for example, a power tube pull-down turn-off circuit, where a gate of the power tube is a control end and is connected to the switch control circuit, and a source and a drain of the power tube are respectively connected to an input port and an output port, so that the switch control circuit controls the turn-on or turn-off of the power tube to realize turn-off of the switch. In specific implementation, an MOS tube may be used, and a specific model of the MOS tube may be set according to an actual use condition, which is not limited in the embodiment of the present invention.
Further, the interface protection circuit provided in the embodiment of the invention further comprises a system protection circuit connected with the input port; the system protection circuit is used for responding to an overvoltage event generated by the input port and protecting the connection path of the input port and the output port. Specifically, the system protection circuit includes ESD (electronstatic discharge) protection circuits and/or surge protection circuits, wherein the system protection circuit 40 is shown in fig. 2 and 3, respectively.
IN practical use, the system protection circuit is also called a system ESD/charge protection circuit, taking a Type-C interface as an example, it is assumed that the input port IN can withstand high voltage, such as 30V, while the withstand voltage of an interface chip connected with the output port OUT or a main control chip of the Type-C interface is generally only 6V, and typically the Type-C interface can generate 40V Surge or 8KV system ESD at the input port IN due to short circuit, so the system ESD/charge protection circuit is required to clamp, discharge Surge or system ESD energy.
Further, in fig. 2 and 3, the interface protection circuit according to the embodiment of the present invention further includes an output clamp circuit 50 connected to the output port OUT; the output clamp circuit 50 is used for clamping the output port voltage signal to clamp and protect the output port.
In particular, the Output Clamp circuit is also referred to as an Output Clamp circuit. In actual use, the output clamp circuit may be pre-configured with a clamp voltage threshold so that after the voltage at the output port exceeds the clamp voltage threshold, a clamp process may be performed.
For easy understanding, the following takes a Type-C interface as an example, and further describes an interface protection circuit provided in the embodiment of the present invention with reference to fig. 2 and fig. 3.
Assuming that the pulse circuit 205 shown IN fig. 2 and 3 is a single pulse circuit, as shown IN fig. 2, if a Surge of 40V or more occurs IN the input port IN, the system protection circuit 40 (system ESD/charge protection circuit) will respond quickly, so that the voltage of the input port will be clamped at about 30V; meanwhile, the overvoltage protection circuit rapidly responds to the condition that the input port exceeds a set threshold (such as 5V), then an overvoltage signal from low to high, namely a OVP (Overvoltage Protection) signal, is output, based on the overvoltage signal, the switch control circuit can control the switch to be in an off state, meanwhile, based on the overvoltage signal, the single pulse circuit can generate a single pulse signal, such as pulse width of about a few microseconds, to control the operation of the relief passage, at the moment, the relief passage can rapidly relieve the Surge residual voltage of the output port, so that a chip behind the output port is safer, and then the output clamping circuit is responsible for clamping the Surge of the output port or the residual voltage of the system ESD/merge protection circuit.
Further, based on fig. 3, when the monopulse circuit cannot work normally, or after the monopulse signal response sent by the monopulse circuit is finished, the monopulse circuit can be connected with the bleeder path 206 through the switch control circuit 202, and the bleeder path is further controlled to work based on the bleeder signal sent by the switch control circuit 202, so that the bleeder path maintains the bleeder function when the voltage of the input port is high enough. When a Surge of 40V or more occurs, the System ESD/charge module discharges the charge energy while the Surge clamp is at about 30V. Meanwhile, when IN is IN surge, the input end has enough voltage and current to generate a proper control signal, so that the residual voltage release passage is controlled, and the quick release of the output end OUT is completed. When the system works normally, the two parts can be combined to control the residual pressure to be released quickly.
Further, based on the above interface protection circuit, the embodiment of the invention also provides an interface device, which is configured with the above interface protection circuit.
Further, for the interface device, a plurality of interfaces to be protected are generally included, where each interface to be protected is configured with the above-mentioned interface protection circuit, for example, also taking a Type-C interface as an example, there are generally two CC pins and two SBU pins, so for an interface device with a Type-C interface, there are generally at least four interfaces to be protected, where each interface to be protected may be configured with the above-mentioned interface protection circuit.
For easy understanding, fig. 4 shows an application schematic of an interface protection circuit, where IN fig. 4, a Type-C interface is taken as an example, and an example is described IN which four interfaces to be protected are configured with the interface protection circuit at the same time, that is, IN fig. 4, four input ports including IN1, IN2, IN3, and IN4, and four output ports corresponding to OUT1, OUT2, OUT3, and OUT4, and switches on each corresponding path are denoted as SW1, SW2, SW3, and SW4.
The application diagram shown in fig. 4 can be generally applied to a Type-C interface, two CC pins and two SBU pins.
When the interface device works IN normal operation and when a Surge of 40V or more occurs IN a channel corresponding to any IN input port, the system protection circuit 40 (system ESD/charge protection circuit) clamps the Surge of the input port to about 30V, then the overvoltage protection circuit 203 rapidly responds to an output overvoltage signal, and the output overvoltage protection circuit is matched with a single pulse signal generated by a single pulse circuit to control the Surge residual voltage relief circuit 204 to rapidly relieve the pressure, and meanwhile, the output clamping circuit 50 is responsible for clamping the Surge of the output port or the residual voltage of the system ESD/charge protection circuit which is too high.
Further, when the interface device is not powered, or the single pulse circuit response is completed, or the single pulse circuit is not working, since the switch control circuit 202 is further connected to the bleed-off path 206, the switch control circuit 202 may also generate a control signal, that is, the bleed-off signal in the embodiment of the present invention, to control the bleed-off path to directly and rapidly bleed off the residual voltage until the surge of the input port disappears.
In addition, the pulse circuit or the single pulse circuit can be connected with the input port, when the whole system of the interface equipment is not powered, the pulse circuit or the single pulse circuit can also take electricity from the input port by utilizing a surge to generate a pulse signal, meanwhile, an upper edge is generated by utilizing a surge event of the input port, the pulse circuit or the single pulse circuit is stable, and the generated upper edge can generate a short pulse to control a release passage to release rapidly. That is, the rising edge generation circuit 401 shown in fig. 4 may generate a rising edge with a surge event of the input port and, at the same time, the pulse circuit 205 may also be directly connected to the input port, that is, directly connected to the input port through the selector 400 in fig. 4, to take power from the input port.
In fig. 4, the four interface protection circuits are shown to share the same pulse circuit 205, that is, in fig. 4, the overvoltage signals OVP1, OVP2, OVP3 or OVP4 of each path may be directly input to the pulse circuit 205, corresponding to fig. 4, the pulse signal PWM generated by the pulse circuit 205 may be sent to each bleed-off path 206, in other embodiments, each interface protection circuit may be configured with one pulse circuit, or one pulse circuit is used for each two interface protection circuits, and so on, specifically, a certain number of interface protection circuits may be set to share one pulse circuit according to the actual use situation, specifically, the embodiment of the present invention is not limited to this.
Further, for ease of understanding, fig. 5 also shows a waveform diagram, in which time is represented by an abscissa and voltage is represented by an ordinate as a routine description, and as shown in fig. 5, the above-described pulse circuit is described as an example of a single pulse circuit, and thus fig. 5 is actually a surge residual voltage relief waveform diagram based on control of the single pulse circuit.
When the input port IN is IN surge IN the normal working mode, the input port IN is clamped at about 30V, as shown by a horizontal line a1 IN fig. 5; if the input port IN exceeds about 5V, the overvoltage protection circuit sends an overvoltage signal to the switch control circuit to control the switch control circuit to turn off the switch SW, as IN fig. 5, if the time T1 of the dotted line exceeds 5V, the overvoltage protection circuit starts to work, and meanwhile, the clamping circuit clamps the voltage of the output port, such as about 6.5V; if there is no surge residual voltage relief circuit, the waveform diagram of the output port OUT is shown by a dashed line a2 in fig. 5, that is, after the time T1, the output port OUT has a small surge residual, that is, the dashed line has a rising trend to T2; if the single pulse circuit is used and the surge residual voltage bleeder circuit is matched, the surge residual voltage of the output port OUT can be rapidly discharged, namely, at the position T2 corresponding to the dotted line a3 in FIG. 5, the surge residual voltage of the output port OUT can be rapidly discharged, so that a chip behind the output port OUT can be safer.
Therefore, the interface protection circuit and the interface device provided by the embodiment of the invention can utilize the overvoltage protection circuit to quickly respond to the surge voltage of the input port and control the surge residual voltage discharging circuit in a matched manner, so that the residual voltage of the output port after the switch is turned off can be quickly discharged, the safety of a chip connected with the output port is further ensured, the service life of the chip is ensured, and the service efficiency of the whole interface device is also improved.
The interface device provided by the embodiment of the invention has the same technical characteristics as the interface protection circuit provided by the embodiment, so that the same technical problems can be solved, and the same technical effects can be achieved.
The embodiment of the invention provides an interface protection circuit and a computer program product of an interface device, which comprises a computer readable storage medium storing program codes, wherein the program codes comprise instructions for executing the method described in the previous method embodiment, and specific implementation can be referred to the method embodiment and will not be described herein.
In addition, in the description of embodiments of the present invention, unless explicitly stated and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood by those skilled in the art in specific cases.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Finally, it should be noted that: the above examples are only specific embodiments of the present invention for illustrating the technical solution of the present invention, but not for limiting the scope of the present invention, and although the present invention has been described in detail with reference to the foregoing examples, it will be understood by those skilled in the art that the present invention is not limited thereto: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or perform equivalent substitution of some of the technical features, while remaining within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (10)
1. An interface protection circuit, the interface protection circuit comprising: an input port, an output port, and a protection circuit disposed at the input port and the output port;
the input port is connected to the interface to be protected, and the output port is connected to the chip corresponding to the interface to be protected;
the protection circuit includes:
a switching circuit including a switch and a switch control circuit; the switch is connected in series on a connecting path of the input port and the output port; the control end of the switch is connected with the switch control circuit; the switch control circuit is used for responding to an overvoltage signal and controlling the switch to be in an off state based on the overvoltage signal;
the input end of the overvoltage protection circuit is connected to the input port, and the output end of the overvoltage protection circuit is connected to the switch control circuit; the overvoltage protection circuit is used for responding to the input port to generate an overvoltage event and sending the overvoltage signal to the switch control circuit;
the input end of the surge residual voltage bleeder circuit is connected to the output end of the overvoltage protection circuit, and the output end of the surge residual voltage bleeder circuit is connected to the output port; and the surge residual voltage discharging circuit is used for responding to the overvoltage signal and carrying out surge residual voltage discharging treatment on the output port based on the overvoltage signal.
2. The interface protection circuit of claim 1, wherein the surge residual voltage bleed circuit comprises a pulse circuit and a bleed path configured with a bleed device of a preset impedance;
the input end of the pulse circuit is connected with the output end of the overvoltage protection circuit, and the output end of the pulse circuit is connected with the discharge passage; the pulse circuit is used for responding to the overvoltage signal to generate a pulse signal and sending the pulse signal to the relief passage;
the discharging passage is used for responding to the pulse signal and communicating with the discharging passage so that the discharging device can discharge the surge residual voltage of the output port.
3. The interface protection circuit of claim 2, wherein the pulse circuit is a single pulse circuit and the pulse signal is a single pulse signal.
4. The interface protection circuit of claim 3, wherein the switch control circuit is further coupled to the bleed path;
the switch control circuit is further configured to send a bleed signal to the bleed path based on the over-voltage signal;
the relief passage is also used for responding to the relief signal so that the relief device can carry out relief treatment on the surge residual voltage of the output port.
5. The interface protection circuit of claim 2, wherein the switch is a power tube, and the switch control circuit is a shut-off circuit matched to the power tube.
6. The interface protection circuit of claim 1, further comprising a system protection circuit coupled to the input port;
the system protection circuit is used for responding to the overvoltage event generated by the input port and protecting the connection path of the input port and the output port.
7. The interface protection circuit of claim 6, wherein the system protection circuit comprises an ESD protection circuit and/or a surge protection circuit.
8. The interface protection circuit of claim 1, further comprising an output clamp circuit coupled to the output port;
the output clamping circuit is used for clamping the output port voltage signal so as to carry out clamping protection on the output port.
9. An interface device, characterized in that the interface device is provided with an interface protection circuit according to any one of claims 1-8.
10. The interface device of claim 9, wherein the interface device comprises a plurality of interfaces to be protected, each interface to be protected configured with the interface protection circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410186509.3A CN117767244B (en) | 2024-02-20 | 2024-02-20 | Interface protection circuit and interface device |
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| CN202410186509.3A CN117767244B (en) | 2024-02-20 | 2024-02-20 | Interface protection circuit and interface device |
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| CN117767244B CN117767244B (en) | 2024-05-14 |
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| Publication number | Publication date |
|---|---|
| CN117767244B (en) | 2024-05-14 |
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