WO2020113747A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2020113747A1
WO2020113747A1 PCT/CN2019/070021 CN2019070021W WO2020113747A1 WO 2020113747 A1 WO2020113747 A1 WO 2020113747A1 CN 2019070021 W CN2019070021 W CN 2019070021W WO 2020113747 A1 WO2020113747 A1 WO 2020113747A1
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Prior art keywords
layer
temperature polysilicon
low
array substrate
polysilicon layer
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French (fr)
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江艺
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/332,360 priority Critical patent/US20200176485A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the invention relates to the field of display, in particular to an array substrate, a preparation method thereof, and a display device.
  • TFT Thin Film Transistor
  • LCD Liquid Crystal Display
  • AMOLED Active Matrix Organic Light-Emitting
  • LCD Liquid Crystal Display
  • AMOLED Active Matrix Organic Light-Emitting
  • the thin film transistor has various structures, and the materials for preparing the thin film transistor of the corresponding structure also have various types, low temperature polysilicon (Low temperature polysilicon) Poly-silicon (LTPS for short) is one of the more excellent ones.
  • Low temperature polysilicon is polycrystalline silicon (Polycrystalline) Silicon, referred to as a branch of p-Si).
  • Low temperature polysilicon has a high electron mobility, which can effectively reduce the area of the thin film transistor device, thereby improving the aperture ratio of the pixel, increasing the display brightness of the panel and reducing the overall power consumption, which greatly reduces the manufacturing cost of the panel .
  • the current display devices using low-temperature polysilicon technology have the advantages of high resolution, fast response, high brightness, high aperture ratio, low energy consumption, etc., and low-temperature polysilicon can be produced at low temperatures and used to make C- MOS circuit, so it has become a hot technology in the display field.
  • the interlayer dielectric layer usually adopts a double-layer structure design of silicon oxide (SiO) + silicon nitride (SiN), and low-temperature polysilicon will also suffer from deposition and other steps in the subsequent preparation process To destroy and form dangling bonds, so there is usually a step of hydrogenation in the preparation process of the array substrate, in its interlayer dielectric layer (Inter After Level Dielectric (ILD) deposition, rapid thermal annealing (Rapid Thermal Annealing, RTA) is used to break the hydrogen ions (H+) formed after the Si-H bonds of the silicon nitride layer in the interlayer dielectric layer are broken High temperature diffusion, repair into dangling bonds in low temperature polysilicon layer.
  • This preparation method needs a silicon nitride interlayer dielectric layer to hydrogenate and repair dangling bonds, which increases the cost and the preparation process is complicated to breed.
  • the object of the present invention is to provide an array substrate, a method for manufacturing the same, and a display device, to solve the problems of complicated manufacturing and high cost of the array substrate manufacturing industry in the prior art described above.
  • the present invention provides an array substrate including a base layer, a low-temperature polysilicon layer, a gate insulating layer, a gate, and an interlayer dielectric layer.
  • the low-temperature polysilicon layer is provided above the base layer.
  • the gate insulating layer covers the low-temperature polysilicon layer.
  • the gate is provided on the gate insulating layer.
  • the interlayer dielectric layer covers the gate and the gate insulating layer.
  • the low-temperature polysilicon layer has a source region and a drain region.
  • the array substrate further includes contact holes and source and drain electrodes;
  • the contact hole penetrates the gate insulating layer from the interlayer dielectric layer and extends to the low-temperature polysilicon layer, wherein one of the contact holes corresponds to the source region, and the other contact hole corresponds to the Drain region
  • the source electrode and the drain electrode are both provided on the interlayer dielectric layer, and the source electrode is correspondingly connected to the source region through one of the contact holes, and the drain electrode is through the other of the contacts The hole is correspondingly connected to the drain region.
  • the base layer includes a substrate, a light shielding layer, a first buffer layer, and a second buffer layer.
  • the light-shielding layer is provided on the substrate, and the light-shielding layer corresponds to the low-temperature polysilicon layer.
  • the first buffer layer covers the light shielding layer.
  • the second buffer layer covers the second buffer layer, and the low-temperature polysilicon layer is provided on the second buffer layer.
  • the interlayer dielectric layer is a single layer of silicon oxide.
  • the invention also provides a method for preparing an array substrate, which includes the following steps:
  • An interlayer dielectric layer is formed on the gate insulating layer, and the interlayer dielectric layer covers the gate.
  • the step of hydrogenating the low-temperature polysilicon layer includes: adding hydrogen plasma under the condition of a temperature of 300°C-500°C. An electric field is applied, and under the action of the electric field, the hydrogen plasma is dissociated into hydrogen ions so that the hydrogen ions are supplemented and diffused into the low-temperature polysilicon layer.
  • the step of forming the low-temperature polysilicon layer includes: the low-temperature polysilicon layer has a source region and a drain region, and the source region and the drain region are N-type heavily doped or P-type doped .
  • the method further includes the following steps: forming a contact hole, the contact hole penetrates the gate insulating layer from the interlayer dielectric layer and extends to the low-temperature polysilicon layer .
  • the step of manufacturing the base layer includes: providing a substrate.
  • a light shielding layer is formed on the substrate, and the light shielding layer corresponds to the low temperature polysilicon layer.
  • a first buffer layer is formed on the light-shielding layer and covers the light-shielding layer.
  • a second buffer layer is formed on the first buffer layer, and the low-temperature polysilicon layer is provided on the second buffer layer.
  • the invention also provides a display device including the above array substrate.
  • An array substrate in the present invention uses a single-layer interlayer dielectric layer, which reduces the thickness of the array substrate, simplifies the manufacturing process, and saves costs.
  • the low-temperature polysilicon layer is hydrogenated before the interlayer dielectric layer is deposited, and the interlayer dielectric layer is directly deposited in a high-temperature environment after hydrogenation, eliminating the rapid thermal annealing method in the prior art
  • the activation process reduces industrial processes and saves energy and costs.
  • the display device of the present invention has the advantages of high resolution, fast response speed, high brightness, high aperture ratio, low energy consumption, low cost and the like.
  • FIG. 1 is a schematic diagram of a layered structure of an array substrate in an embodiment of the present invention.
  • FIG. 3 is a specific preparation flowchart of the base layer preparation step in the embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a layered structure of a display device in an embodiment of the present invention.
  • Source electrode 70 Drain electrode 80.
  • the component When certain components are described as “on” another component, the component may be placed directly on the other component; there may also be an intermediate component, which is placed on the intermediate component, And the intermediate component is placed on another component.
  • the two When a component is described as “mounted to” or “connected to” another component, the two can be understood to be “installed” or “connected” directly, or a component indirectly “mounted to” or “connected” through an intermediate component To" another part.
  • an embodiment of the present invention provides an array substrate 100, which includes a base layer 10, a low-temperature polysilicon layer 20, a gate insulating layer 30, a gate 40, and an interlayer dielectric layer 50.
  • the base layer 10 includes a substrate 11, a light shielding layer 12, a first buffer layer 13 and a second buffer layer 14.
  • the substrate 11 is an insulating substrate, and the material of the insulating substrate may be an insulating material such as glass or quartz, which is used to protect the overall structure of the array substrate 100.
  • the light shielding layer 12 is provided on the substrate 11, and the light shielding layer 12 corresponds to the low temperature polysilicon layer 20.
  • the orthographic projection center of the light shielding layer 12 on the substrate 11 is The orthographic projection centers of the low-temperature polysilicon layer 20 on the substrate 11 coincide to shield the low-temperature polysilicon layer 20 and prevent light leakage.
  • the light-shielding layer 12 is made of an opaque material, which may be metal or amorphous silicon.
  • the specific material of the light-shielding layer 12 is not specifically limited in this embodiment of the present invention, and other materials may also be used.
  • the material of the first buffer layer 13 is one of silicon nitride, silicon oxide or silicon oxynitride, which covers the substrate 11 and covers the light shielding layer 12.
  • the material of the second buffer layer 14 is one of silicon nitride, silicon oxide or silicon oxynitride, which covers the first buffer layer 13. Both the first buffer layer 13 and the second buffer layer 14 are used to protect the low-temperature polysilicon layer 20, reduce damage caused by movement and vibration of the low-temperature polysilicon layer 20, and also prevent the substrate 11 The metal ions in the diffusion into the array substrate 100, especially into the low-temperature polysilicon layer 20, thereby affecting the electrical performance of the array substrate 100.
  • the low-temperature polysilicon layer 20 is provided on the first buffer layer 13 and has a source region 21 and a drain region 22.
  • the source region 21 and the drain region 22 may be prepared by ion doping technology, such as the N-type heavy doping process, the source region 21 and the drain region 22 are doped with the same type of ions N-type ions or the source region 21 and the drain region 22 are doped with P-type ions of the same type through a P-type heavy doping process. After performing the doping process, the source region 21 and the drain region 22 can reduce the contact resistance between the source 70 and the drain 80 and the low-temperature polysilicon layer 20, and reduce the array substrate 100 leakage current, and improve the electrical performance of the array substrate 100.
  • the gate insulating layer 30 overlies the low-temperature polysilicon layer 20, which may be deposited by an insulating material, and the insulating material may be one of silicon oxide, silicon nitride, or silicon oxynitride.
  • the gate insulating layer 30 is used to protect and isolate the low-temperature polysilicon layer 20.
  • the gate 40 is provided on the gate insulating layer 30, and the gate 40 corresponds to the low-temperature polysilicon layer 20.
  • the grid 40 is made of a conductive material, and the conductive material may be tungsten, chromium, aluminum, copper, or the like.
  • the gate 40 is used to generate an electric field by a voltage, thereby changing the thickness of the conductive channel, so as to control the current of the source 70 and the drain 80.
  • the interlayer dielectric layer 50 overlies the gate electrode 40 and the gate insulating layer 30, which can be deposited by chemical vapor deposition.
  • the interlayer dielectric layer 50 uses a dielectric isolation technology and is made of an insulating dielectric material.
  • the insulating dielectric material may be one of silicon oxide, silicon nitride, or silicon oxynitride.
  • the interlayer dielectric layer 50 is used to isolate metal traces, such as the gate 40, the source 70 and the drain 80.
  • the array substrate 100 further includes a contact hole 60 and a source electrode 70 and a drain electrode 80.
  • the contact hole 60 extends through the gate insulating layer 30 from the interlayer dielectric layer 50 and extends to the low temperature polysilicon layer 20, wherein one of the contact holes 60 corresponds to the source region 21, and the other The contact hole 60 corresponds to the drain region 22.
  • Both the source electrode 70 and the drain electrode 80 are provided on the interlayer dielectric layer 50.
  • the source electrode 70 and the drain electrode 80 may be formed by patterning metal.
  • the source electrode 70 is correspondingly connected to the source region 21 through one contact hole 60
  • the drain electrode 80 is correspondingly connected to the drain region 22 through another contact hole 60.
  • the array substrate 100 adopts a single-layer interlayer dielectric layer structure, which reduces the thickness of the array substrate 100, simplifies the manufacturing process, and saves costs.
  • An embodiment of the present invention also provides a method for manufacturing an array substrate 100.
  • the manufacturing process is shown in FIG. 2.
  • the manufacturing method includes the following steps:
  • Step S10) preparing the base layer 10 includes steps S101)-S104), and the preparation process is shown in FIG. 3.
  • Step S101) Provide a substrate 11: provide an insulating substrate, and the material of the insulating substrate may be an insulating material such as glass or quartz.
  • Step S102) Forming a light-shielding layer 12 depositing the light-shielding layer 12 on the substrate 11 by a chemical vapor deposition method, and then forming the light-shielding layer 12 into a predetermined shape through processes such as exposure or development.
  • the light-shielding layer 12 is made of an opaque material, and the light-shielding material may be metal or amorphous silicon.
  • the specific material of the light-shielding layer 12 is not specifically limited in this embodiment of the present invention, and other materials may be used. material.
  • Step S103) Forming a first buffer layer 13: depositing the first buffer layer 13 on the substrate 11 and covering the light shielding layer 12 with the first buffer layer 13.
  • the material of the first buffer layer 13 is silicon nitride.
  • Step S104) forming a second buffer layer 14 depositing the second buffer layer 14 on the first buffer layer 13, the material of the second buffer layer 14 is silicon oxide.
  • the low-temperature polysilicon layer 20 includes a source region 21 and a drain region 22.
  • the source region 21 and the drain region 22 may be formed by an ion doping technique, and the source region 21 and the drain region 22 may be doped with the same type of ions, and the ions may be doped according to The process selects N-type ions or P-type ions.
  • the gate insulating layer 30 covers the low-temperature polysilicon layer 20.
  • Step S40) forming the gate electrode 40 on the gate insulating layer 30 forming the gate electrode 40 on the gate insulating layer 30 using a conductive material, and the gate electrode 40 corresponds to the low temperature polysilicon layer 20, and then The gate electrode 40 is patterned by an etching process.
  • the conductive material may be tungsten, chromium, aluminum, copper, or the like.
  • Step S50 Hydrogenation of the low-temperature polysilicon layer 20: Under the condition of a temperature of 300° C.-500° C., add hydrogen plasma. An electric field is applied, under the action of the electric field, the hydrogen plasma is dissociated into hydrogen ions, and the hydrogen ions are supplemented and diffused into the low-temperature polysilicon layer 20. The strength of the electric field is set according to actual preparation needs.
  • Step S60 forming an interlayer dielectric layer 50 on the gate insulating layer 30: on the gate insulating layer 30, silicon oxide is deposited on the gate insulating layer 30 by a chemical vapor deposition method to form a single layer An interlayer dielectric layer 50, and the interlayer dielectric layer 50 covers the gate electrode 40.
  • Step S70) forming a contact hole 60 forming the contact hole 60 through an exposure process or a development process, the contact hole 60 penetrates the gate insulating layer 30 from the interlayer dielectric layer 50 and extends to the low-temperature polysilicon layer 20.
  • One contact hole 60 corresponds to the source region 21, and the other contact hole 60 corresponds to the drain region 22.
  • the step of hydrogenating the low-temperature polysilicon layer 20 is carried out before the deposition of the interlayer dielectric layer 50, eliminating the rapid thermal annealing activation process in the prior art, reducing industrial processes, and saving energy And costs.
  • a display device 1000 is also provided in this embodiment, which includes the above-mentioned array substrate 100 and color filter substrate 200 and other panels.
  • the color filter panel 200 is disposed opposite to the array substrate 100.
  • the display device 1000 in this embodiment may also include other structural devices such as polarizers, middle frames, etc.
  • the design points of this embodiment are all in the array substrate 100. Therefore, for the polarizer, medium Frames and other structures will not be repeated one by one.
  • the display device 1000 in this embodiment adopts the array substrate 100 of the present invention, which has the advantages of high resolution, fast response speed, high brightness, high aperture ratio, and low energy consumption.
  • the step of hydrogenating the low-temperature polysilicon layer 20 is completed before the deposition of the interlayer dielectric layer 50, and the interlayer dielectric layer 50 is directly deposited in a high-temperature environment after hydrogenation, which omits the prior art.
  • the rapid thermal annealing activation process simplifies industrial processes and saves energy.
  • only one interlayer dielectric layer 50 is needed in the embodiment of the present invention, which reduces the thickness of the array substrate 100.

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Abstract

本发明提供了一种阵列基板及其制备方法、显示装置。所述低温多晶硅包括基层、低温多晶硅层、栅极绝缘层、栅极以及层间介质层。所述低温多晶硅层设于所述基层上方。所述栅极绝缘层覆于所述低温多晶硅层上。所述栅极设于所述栅极绝缘层上。所述层间介质层覆于所述栅极和所述栅极绝缘层上。所述阵列基板制备方法在沉积层间介质层前对低温多晶硅层进行氢化，在氢化后的高温环境中直接沉积层间介质层，省去了现有技术中快速热退火法活化工艺，减少了工业流程，并且节约了能源及成本。所述显示装置采用了本发明的所述阵列基板，其具有高分辨率、反应速度快、高亮度、高开口率、低耗能等优点。

Description

阵列基板及其制备方法、显示装置 技术领域
本发明涉及显示领域，特别是一种阵列基板及其制备方法、显示装置。
 背景技术
薄膜晶体管（Thin Film Transistor，简称TFT）是目前液晶显示装置（Liquid Crystal Display，简称LCD）和有源矩阵驱动式有机电致发光显示装置（Active Matrix Organic Light-Emitting Diode，简称AMOLED）中的重要驱动元件，直接关系平板显示装置的显示性能。
薄膜晶体管具有多种结构，制备相应结构的薄膜晶体管的材料也具有多种，低温多晶硅(Low temperature poly-silicon，简称LTPS)是其中较为优异的一种。低温多晶硅为多晶硅（Polycrystalline Silicon，简称p-Si）的一个分支。低温多晶硅具有高的电子迁移率，可以有效的减小薄膜晶体管的器件的面积，进而提升像素的开口率，增大面板显示亮度的同时可以降低整体的功耗，使得面板的制造成本大幅度降低。对平板显示而言，目前采用低温多晶硅技术的显示装置具有高分辨率、反应速度快、高亮度、高开口率、低耗能等优点，而且低温多晶硅可在低温下制作，并用于制作C-MOS电路，因此其已成为显示领域炙手可热的技术。
在现有的阵列基板制备方法中，其层间介质层通常采用氧化硅（SiO）+氮化硅（SiN）的双层结构设计，低温多晶硅在后续制备过程中也会因沉积等步骤而遭到破坏，形成悬空键，因此在阵列基板的制备过程中通常设有一步氢化步骤，在其层间介质层（Inter Level Dielectric，简称ILD）沉积完成后，采用快速热退火法（Rapid Thermal Annealing,简称RTA）将层间介质层中氮化硅层的Si-H键断键后所形成的氢离子（H+）经过高温扩散，修补进低温多晶硅层中悬空键中。此制备方法需设置一层氮化硅层间介质层来进行氢化修补悬空键，提高了成本，并且制备工艺繁育复杂。
 技术问题
本发明的目的是提供一种阵列基板及其制备方法、显示装置，以解决上述现有技术中阵列基板的制作工业繁复，成本高等问题。
 技术解决方案
为实现上述目的，本发明提供一种阵列基板，其包括基层、低温多晶硅层、栅极绝缘层、栅极以及层间介质层。所述低温多晶硅层设于所述基层上方。所述栅极绝缘层覆于所述低温多晶硅层上。所述栅极设于所述栅极绝缘层上。所述层间介质层覆于所述栅极和所述栅极绝缘层上。
进一步地，所述低温多晶硅层具有源极区和漏极区。所述阵列基板还包括接触孔以及源极和漏极；
所述接触孔，从所述层间介质层贯穿所述栅极绝缘层并延伸至所述低温多晶硅层，其中一所述接触孔对应所述源极区，另一所述接触孔对应所述漏极区；
所述源极和所述漏极均设于所述层间介质层上，且所述源极通过一所述接触孔对应连接至所述源极区，所述漏极通过另一所述接触孔对应连接至所述漏极区。
进一步地，所述基层包括基板、遮光层、第一缓冲层以及第二缓冲层。所述遮光层设于所述基板上，且所述遮光层对应于所述低温多晶硅层。所述第一缓冲层覆于所述遮光层上。所述第二缓冲层覆于所述第二缓冲层上，所述低温多晶硅层设于所述第二缓冲层上。
进一步地，所述层间介质层为单层氧化硅。
本发明还提供一种阵列基板制备方法，其包括以下步骤：
制作基层；
形成低温多晶硅层于所述基层上；
沉积栅极绝缘层于所述基层上，且所述栅极绝缘层包覆所述低温多晶硅层；
形成栅极于所述栅极绝缘层上；
氢化低温多晶硅层；
形成层间介质层于所述栅极绝缘层上，且所述层间介质层包覆所述栅极。
进一步地，在氢化低温多晶硅层步骤中包括：在温度为300℃-500℃的条件下，加入氢等离子体。施加一电场，在所述电场作用下将氢等离子体解离成氢离子以使氢离子补充扩散至低温多晶硅层中。
进一步地，所述形成低温多晶硅层步骤中包括：所述低温多晶硅层具有源极区和漏极区，对所述源极区和所述漏极区进行N型重掺杂或P型掺杂。
进一步地，所述形成低温多晶硅层于所述基层上之后还包括以下步骤：形成接触孔，所述接触孔从所述层间介质层贯穿所述栅极绝缘层并延伸至所述低温多晶硅层。形成源极和漏极于所述层间介质层上，且所述源极通过一所述接触孔对应连接至所述源极区，所述漏极通过另一所述接触孔对应连接至所述漏极区。
进一步地，所述制作基层步骤包括：提供基板。形成遮光层于所述基板上，且所述遮光层对应于所述低温多晶硅层。形成第一缓冲层于所述遮光层上，且覆于所述遮光层上。形成第二缓冲层于所述第一缓冲层上，所述低温多晶硅层设于所述第二缓冲层上。
本发明还提供一种显示装置，包括上述阵列基板。
 有益效果
本发明中的一种阵列基板，采用了单层结构的层间介质层，减少了阵列基板的厚度，简化了制作工艺，并且节省了成本。
本发明中的一种阵列基板制备方法，在沉积层间介质层前对低温多晶硅层进行氢化，在氢化后的高温环境中直接沉积层间介质层，省去了现有技术中快速热退火法活化工艺，减少了工业流程，并且节约了能源及成本。
本发明中的一种显示装置，具有高分辨率、反应速度快、高亮度、高开口率、低耗能、低成本等优点。
 附图说明
图1为本发明实施例中的阵列基板层状结构示意图；
图2为本发明实施例中的阵列基板制备流程图；
图3为本发明实施例中的制备基层步骤的具体制备流程图；
图4为本发明实施例中的显示装置层状结构示意图。
图中部件表示如下：
显示装置1000；
阵列基板100；彩膜基板200；
基层10；
基板11；遮光层12；
第一缓冲层13；第二缓冲层14；
低温多晶硅层20；
源极区21；漏极区22；
栅极绝缘层30；栅极40；
层间介质层50；接触孔60；
源极70；漏极80。
 本发明的实施方式
以下参考说明书附图介绍本发明的优选发明实施例，证明本发明可以实施，所述发明实施例可以向本领域中的技术人员完整介绍本发明，使其技术内容更加清楚和便于理解。本发明可以通过许多不同形式的发明实施例来得以体现，本发明的保护范围并非仅限于文中提到的发明实施例。
在附图中，结构相同的部件以相同数字标号表示，各处结构或功能相似的组件以相似数字标号表示。附图所示的每一部件的尺寸和厚度是任意示出的，本发明并没有限定每个组件的尺寸和厚度。为了使图示更清晰，附图中有些地方适当夸大了部件的厚度。
此外，以下各发明实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定发明实施例。本发明中所提到的方向用语，例如，“上”、“下”、“前”、“后”、“左”、“右”、“内”、“外”、“侧面”等，仅是参考附加图式的方向，因此，使用的方向用语是为了更好、更清楚地说明及理解本发明，而不是指示或暗指所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”、“第三”等仅用于描述目的，而不能理解为指示或暗示相对重要性。
当某些部件被描述为“在”另一部件“上”时，所述部件可以直接置于所述另一部件上；也可以存在一中间部件，所述部件置于所述中间部件上，且所述中间部件置于另一部件上。当一个部件被描述为“安装至”或“连接至”另一部件时，二者可以理解为直接“安装”或“连接”，或者一个部件通过一中间部件间接“安装至”、或“连接至”另一个部件。
如图1所示，本发明实施例中提供一种阵列基板100，其包括基层10、低温多晶硅层20、栅极绝缘层30、栅极40以及层间介质层50。
所述基层10包括基板11、遮光层12、第一缓冲层13以及第二缓冲层14。
所述基板11为绝缘基板，所述绝缘基板的材料可以为玻璃或石英等绝缘材料，用于保护所述阵列基板100的整体结构。
所述遮光层12设于所述基板11上，并且所述遮光层12对应于所述低温多晶硅层20，本实施例中，所述遮光层12在所述基板11上的正投影中心与所述低温多晶硅层20在所述基板11上的正投影中心重合，用于为所述低温多晶硅层20遮光，防止出现漏光现象。所述遮光层12由不透光材料制成，所述不透光材料可以为金属或非晶硅，本发明实施例对所述遮光层12的具体材料不作具体限制，也可选用其他材料。
所述第一缓冲层13所用材料为氮化硅、氧化硅或氮氧化硅中的一种，其覆于所述基板11上且包覆所述遮光层12。所述第二缓冲层14所用材料为氮化硅、氧化硅或氮氧化硅中的一种，其覆于所述第一缓冲层13上。所述第一缓冲层13以及所述第二缓冲层14均用于保护所述低温多晶硅层20，减少所述低温多晶硅层20由于移动、震荡所产生的损伤，并且还可以防止所述基板11中的金属离子扩散至所述阵列基板100内，特别是扩散至所述低温多晶硅层20中，从而影响所述阵列基板100的电性能。
所述低温多晶硅层20设于所述第一缓冲层13上，其具有源极区21和漏极区22。所述源极区21和所述漏极区22可以通过离子掺杂技术制备而成，如通过N型重掺杂工艺所述源极区21和所述漏极区22掺杂相同类型的离子N型离子或通过P型重掺杂工艺所述源极区21和所述漏极区22掺杂相同类型的离子P型离子。进行掺杂工艺后的所述源极区21和所述漏极区22可以减少所述源极70和所述漏极80与所述低温多晶硅层20之间的接触电阻，降低所述阵列基板100的泄露电流，并提升所述阵列基板100的电性能。
所述栅极绝缘层30覆于所述低温多晶硅层20的上，其可由绝缘材料沉积而成，所述绝缘材料可为氧化硅、氮化硅或氮氧化硅中的一种。所述栅极绝缘层30用于保护以及隔绝所述低温多晶硅层20。
所述栅极40设于所述栅极绝缘层30上，并且所述栅极40对应于所述低温多晶硅层20。所述栅极40由导电材料制备而成，所述导电材料可以为钨、铬、铝、铜等。所述栅极40用于通过电压产生电场，从而改变导电沟道的厚度，以达到控制所述源极70和所述漏极80的电流的目的。
所述层间介质层50覆于所述栅极40和所述栅极绝缘层30上，其可以通过化学气相沉积法沉积而成。所述层间介质层50采用介质隔离技术，由绝缘电介质材料制成，所述绝缘电介质材料可以为氧化硅、氮化硅或氮氧化硅中的一种。所述层间介质层50用于隔离金属走线，如所述栅极40、所述源极70和所述漏极80。
本发明实施例中，所述阵列基板100还包括接触孔60以及源极70和漏极80。
所述接触孔60从所述层间介质层50贯穿所述栅极绝缘层30并延伸至所述低温多晶硅层20，其中一所述接触孔60对应所述源极区21，另一所述接触孔60对应所述漏极区22。
所述源极70和所述漏极80均设于所述层间介质层50上。所述源极70以及所述漏极80可以通过将金属图案化而形成。所述源极70通过一所述接触孔60对应连接至所述源极区21，所述漏极80通过另一所述接触孔60对应连接至所述漏极区22。
在本发明实施例中，所述阵列基板100采用单层的层间介质层结构，减少了所述阵列基板100的厚度，简化了制作工艺，并且节省了成本。
本发明实施例中还提供一种阵列基板100制备方法，其制备流程如图2所示，所述制备方法包括以下步骤：
步骤S10）制备基层10：具体的，步骤S10）中包括步骤S101）-S104），其制备流程如图3所示。
步骤S101）提供基板11：提供一块绝缘基板，所述绝缘基板的材料可以为玻璃或石英等绝缘材料。
步骤S102）形成遮光层12：通过化学气相沉积法在所述基板11上沉积所述遮光层12，然后可以通过曝光或显影等工艺使所述遮光层12形成指定形状。所述遮光层12由不透光材料制成，所述不透光材料可以为金属或非晶硅等材料，本发明实施例对所述遮光层12的具体材料不作具体限制，也可选用其他材料。
步骤S103）形成第一缓冲层13：在所述基板11上沉积所述第一缓冲层13，并且所述第一缓冲层13包覆所述遮光层12。所述第一缓冲层13的材料为氮化硅。
步骤S104）形成第二缓冲层14：在所述第一缓冲层13上沉积所述第二缓冲层14，所述第二缓冲层14的材料为氧化硅。
步骤S20）形成低温多晶硅层20于基层10上：在所述基层10上形成所述低温多晶硅层20，其对应于所述遮光层12。所述低温多晶硅层20包括源极区21和漏极区22。所述源极区21和所述漏极区22可以通过离子掺杂技术形成，并且所述源极区21和所述漏极区22可掺杂相同类型的离子，所述离子可以根据掺杂工艺选择N型离子或P型离子。
步骤S30）沉积栅极绝缘层30于基层10上：在所述基层10上使用绝缘材料沉积栅极所述绝缘层30，所述绝缘材料可以为氧化硅。并且，所述栅极绝缘层30包覆所述低温多晶硅层20。
步骤S40）形成栅极40于栅极绝缘层30上：在所述栅极绝缘层30上使用导电材料形成所述栅极40，并且所述栅极40对应于所述低温多晶硅层20，然后通过蚀刻工艺对所述栅极40进行图案化。所述导电材料可以为钨、铬、铝、铜等。
步骤S50）氢化低温多晶硅层20：在温度为300℃-500℃的条件下，加入氢等离子体。施加一电场，在所述电场作用下将氢等离子体解离成氢离子，并且将氢离子补充扩散至所述低温多晶硅层20中。所述电场的强度根据实际制备需要设定。
步骤S60形成层间介质层50于栅极绝缘层30上：在所述栅极绝缘层30上，将氧化硅通过化学气相沉积法沉积在所述栅极绝缘层30上，形成单层所述层间介质层50，并且所述层间介质层50包覆所述栅极40。
步骤S70）形成接触孔60：通过曝光工艺或显影工艺形成所述接触孔60，所述接触孔60从所述层间介质层50贯穿所述栅极绝缘层30并延伸至所述低温多晶硅层20。一所述接触孔60对应于所述源极区21，另一所述接触孔60对应于所述漏极区22。
步骤S80）形成源极70和漏极80于所述层间介质层50上：在所述层间介质层50上以及所述接触孔60中形成沉积金属导电材料，并在所述层间介质层50上形成金属层。然后通过蚀刻工艺或光刻工艺对所述金属层图案化，形成所述源极70和所述漏极80，其中，所述源极70与所述源极区21连接，所述漏极80与所述漏极区22连接。
本实施例中，将氢化所述低温多晶硅层20步骤提前至沉积所述层间介质层50前进行，省去了现有技术中快速热退火法活化工艺，减少了工业流程，并且节约了能源及成本。
如图4所示，本实施例中还提供一种显示装置1000，其包括以上所述的阵列基板100、彩膜基板200等面板，所述彩膜面板200与所述阵列基板100相对设置。当然，本实施例中的显示装置1000还可以包括其他的，如偏光片、中框等其他的结构器件，而本实施例的设计要点均在所述阵列基板100，因此，对于偏光片、中框等结构不再一一赘述。
本实施例中的所述显示装置1000，采用了本发明的所述阵列基板100，其具有高分辨率、反应速度快、高亮度、高开口率、低耗能等优点。
在本发明实施例中，将氢化所述低温多晶硅层20步骤提前至沉积层间介质层50之前完成，并在氢化后的高温环境中直接沉积层间介质层50，省去了现有技术中快速热退火法活化工艺，简化了工业流程，并且节约了能源。同时，在本发明实施例中只需一层层间介质层50，减小了所述阵列基板100的厚度，在使用本发明的阵列基板100装配显示装置1000后，也同样的减小了所述显示装置1000的厚度。
虽然在本文中参照了特定的实施方式来描述本发明，但是应该理解的是，这些实施例仅仅是本发明的原理和应用的示例。因此应该理解的是，可以对示例性的实施例进行许多修改，并且可以设计出其他的布置，只要不偏离所附权利要求所限定的本发明的精神和范围。应该理解的是，可以通过不同于原始权利要求所描述的方式来结合不同的从属权利要求和本文中所述的特征。还可以理解的是，结合单独实施例所描述的特征可以使用在其他所述实施例中。

Claims (10)

  1. 一种阵列基板，其包括：
    基层；
    低温多晶硅层，设于所述基层上方；
    栅极绝缘层，覆于所述低温多晶硅层上；
    栅极，设于所述栅极绝缘层上；
    层间介质层，覆于所述栅极和所述栅极绝缘层上。
  2. 如权利要求1所述的阵列基板，其中，
    所述低温多晶硅层具有源极区和漏极区；
    所述阵列基板还包括：
    接触孔，从所述层间介质层贯穿所述栅极绝缘层并延伸至所述低温多晶硅层，其中一所述接触孔对应所述源极区，另一所述接触孔对应所述漏极区；以及
    源极和漏极，均设于所述层间介质层上，且所述源极通过一所述接触孔对应连接至所述源极区，所述漏极通过另一所述接触孔对应连接至所述漏极区。
  3. 如权利要求1所述的阵列基板，其中，所述基层包括：
    基板；
    遮光层，设于所述基板上，且所述遮光层对应于所述低温多晶硅层；
    第一缓冲层，覆于所述遮光层上；
    第二缓冲层，覆于所述第二缓冲层上，所述低温多晶硅层设于所述第二缓冲层上。
  4. 如权利要求1所述的阵列基板，其中，所述层间介质层为单层氧化硅。
  5. 一种阵列基板制备方法，其包括以下步骤：
    制作基层；
    形成低温多晶硅层于所述基层上；
    沉积栅极绝缘层于所述基层上，且所述栅极绝缘层包覆所述低温多晶硅层；
    形成栅极于所述栅极绝缘层上；
    氢化低温多晶硅层；
    形成层间介质层于所述栅极绝缘层上，且所述层间介质层包覆所述栅极。
  6. 如权利要求5所述的阵列基板制备方法，其中，在氢化低温多晶硅层步骤中包括：
    在温度为300℃-500℃的条件下，加入氢等离子体；
    施加一电场，在所述电场作用下将氢等离子体解离成氢离子以使氢离子补充扩散至低温多晶硅层中。
  7. 如权利要求6所述的阵列基板制备方法，其中，所述形成低温多晶硅层步骤中：所述低温多晶硅层具有源极区和漏极区，对所述源极区和所述漏极区进行N型重掺杂或P型掺杂。
  8. 如权利要求6所述的阵列基板制备方法，其中，在形成低温多晶硅层于所述基层上之后还包括以下步骤：
    形成接触孔，所述接触孔从所述层间介质层贯穿所述栅极绝缘层并延伸至所述低温多晶硅层；
    形成源极和漏极于所述层间介质层上，且所述源极通过一所述接触孔对应连接至所述源极区，所述漏极通过另一所述接触孔对应连接至所述漏极区。
  9. 如权利要求6所述的阵列基板制备方法，其中，
    在制作基层步骤包括：
    提供基板；
    形成遮光层于所述基板上，且所述遮光层对应于所述低温多晶硅层；
    形成第一缓冲层于所述基板上，且覆于所述遮光层上；
    形成第二缓冲层于所述第一缓冲层上，所述低温多晶硅层设于所述第二缓冲层上。
  10.    一种显示装置，包括如权利要求1任意一项所述的阵列基板。
PCT/CN2019/070021 2018-12-03 2019-01-02 阵列基板及其制备方法、显示装置 Ceased WO2020113747A1 (zh)

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