WO2020113678A1 - 阵列基板的测试方法、装置及存储介质 - Google Patents

阵列基板的测试方法、装置及存储介质 Download PDF

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WO2020113678A1
WO2020113678A1 PCT/CN2018/121889 CN2018121889W WO2020113678A1 WO 2020113678 A1 WO2020113678 A1 WO 2020113678A1 CN 2018121889 W CN2018121889 W CN 2018121889W WO 2020113678 A1 WO2020113678 A1 WO 2020113678A1
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Prior art keywords
test
array substrate
array
curing
pad
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English (en)
French (fr)
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林佩欣
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HKC Co Ltd
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HKC Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/52—Testing for short-circuits, leakage current or ground faults
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133351—Manufacturing of individual cells out of a plurality of cells, e.g. by dicing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing

Definitions

  • the present application relates to the field of thin film transistor array substrates, and in particular, to an array substrate testing method, array substrate testing device, and computer-readable storage media.
  • Each test circuit board may include a plurality of array substrates.
  • the array test pads corresponding to each array substrate are sequentially applied to each array substrate according to the wiring sequence of the array substrate. Signal, and the block-by-block test process of the array substrate results in low efficiency of the array substrate test.
  • the main purpose of the present application is to provide an array substrate test method, an array substrate test device, and a computer-readable storage medium.
  • the present application provides a method for testing an array substrate.
  • the method for testing an array substrate includes the following steps:
  • a curing drive signal is sequentially applied to the curing pad circuits, and at least two array substrates are connected to the curing pad circuits;
  • the method further includes:
  • test pad circuits corresponding to the target array substrate in the test circuit board perform array test on the target array substrate in sequence.
  • the step of sequentially performing array test on the target array substrate according to the arrangement order of the test pad circuits corresponding to the target array substrate in the test circuit board includes:
  • test pad circuits According to the order in which the test pad circuits are arranged in the test circuit board, sequentially apply test drive signals to the test pad circuits;
  • the method further includes:
  • the method further includes:
  • test pad circuits in the test circuit board perform array test on the array substrate in the curing pad circuit.
  • the step of performing array test on the array substrate in the curing pad circuit according to the order in which the test pad circuits are arranged in the test circuit board includes:
  • test pad circuits According to the order in which the test pad circuits are arranged in the test circuit board, sequentially apply test drive signals to the test pad circuits;
  • the method further includes:
  • the method further includes:
  • the present application also provides an array substrate testing device.
  • the array substrate testing device includes:
  • the test device of the array substrate includes a memory, a processor, and a test program of the array substrate stored on the memory and executable on the processor, and the test program of the array substrate is implemented when the processor executes The steps of the above array substrate test method.
  • the present application also provides a computer-readable storage medium on which a test program of an array substrate is stored.
  • the test program of the array substrate is executed by a processor, the array substrate is implemented as described above Of the test method.
  • the array substrate test method, array substrate test device, and computer-readable storage medium provided by the present application sequentially apply curing drive signals to the curing pad circuits according to the order in which the curing pad circuits are arranged in the test circuit board. At least two array substrates are connected to the curing pad circuit; array testing of the array substrate in the curing pad circuit is performed by the curing driving signal. In this way, by using the curing drive signal as an array test signal, at least two array substrates are tested at a time by the array test signal, and the efficiency of performing array test on the array substrate is improved.
  • FIG. 1 is a schematic diagram of a hardware operating environment of a terminal according to an embodiment of the present application
  • FIG. 2 is a schematic flowchart of an embodiment of a method for testing an array substrate of the present application
  • FIG. 3 is a schematic flowchart of another embodiment of a method for testing an array substrate of the present application.
  • FIG. 4 is a schematic flowchart of still another embodiment of a method for testing an array substrate of the present application
  • FIG. 5 is a schematic flowchart of still another embodiment of a method for testing an array substrate of the present application.
  • the present application provides a method for testing an array substrate.
  • the curing drive signal as an array test signal
  • at least two array substrates are tested at a time by the array test signal, and the efficiency of performing array test on the array substrate is improved.
  • FIG. 1 is a schematic diagram of a hardware operating environment of a terminal according to an embodiment of the present application
  • the terminal in the embodiment of the present application may be an array substrate testing device.
  • the terminal may include: a processor 1001, such as a CPU (central processing) unit), memory 1002, communication bus 1003.
  • the communication bus 1003 is configured to implement connection communication between the components in the terminal.
  • the memory 1002 may be a high-speed RAM random access (random-access memory), can also be a stable memory (non-volatile memory), such as disk storage.
  • the memory 1002 may optionally be a storage device independent of the foregoing processor 1001.
  • FIG. 1 does not constitute a limitation on the terminal in the embodiments of the present application, and may include more or fewer components than those illustrated, or combine certain components, or different components Layout.
  • the memory 1002 as a computer storage medium may include a test program of the array substrate.
  • the processor 1001 may be set to call the test program of the array substrate stored in the memory 1002, and perform the following operations:
  • a curing drive signal is sequentially applied to the curing pad circuits, and at least two array substrates are connected to the curing pad circuits;
  • the processor 1001 may call the test program of the array substrate stored in the memory 1002, and also perform the following operations:
  • test pad circuits corresponding to the target array substrate in the test circuit board perform array test on the target array substrate in sequence.
  • the processor 1001 may call the test program of the array substrate stored in the memory 1002, and also perform the following operations:
  • test pad circuits According to the order in which the test pad circuits are arranged in the test circuit board, sequentially apply test drive signals to the test pad circuits;
  • the processor 1001 may call the test program of the array substrate stored in the memory 1002, and also perform the following operations:
  • the processor 1001 may call the test program of the array substrate stored in the memory 1002, and also perform the following operations:
  • test pad circuits in the test circuit board perform array test on the array substrate in the curing pad circuit.
  • the processor 1001 may call the test program of the array substrate stored in the memory 1002, and also perform the following operations:
  • test pad circuits According to the order in which the test pad circuits are arranged in the test circuit board, sequentially apply test drive signals to the test pad circuits;
  • the processor 1001 may call the test program of the array substrate stored in the memory 1002, and also perform the following operations:
  • the processor 1001 may call the test program of the array substrate stored in the memory 1002, and also perform the following operations:
  • the test method of the array substrate includes:
  • Step S10 According to the arrangement order of the curing pad circuits in the test circuit board, sequentially apply curing drive signals to the curing pad circuits, and the curing pad circuits are connected to at least two array substrates.
  • a test circuit board needs to be provided to perform array testing on the array substrate (Array Test, AT) to perform array testing on multiple array substrates, that is, the test circuit board may include multiple array substrates.
  • Array Test AT
  • the test circuit board may include multiple array substrates.
  • a test circuit board including 8 array substrates is formed.
  • Array test is to charge all pixels on the array substrate uniformly, and then find various detection methods of bad electrical.
  • the grid lines, data lines, and common electrode lines on the array substrate can be connected to the array test pad circuit (Array Testing PAD), then according to the arrangement order of the array test pad circuit in the test circuit board, by sequentially applying the test drive signal to the array test pad circuit to use the test drive signal as the array test signal, the array substrate is sequentially tested.
  • Array Testing PAD array test pad circuit
  • the process of performing array testing on the array substrate block by block in this way will result in low test efficiency of the array substrate.
  • test circuit board In the subsequent manufacturing process of the array substrate, it is necessary to pair with the color filter (Color Filter) and perform PSVA Curing polymer vertical alignment curing process (Polymer-stabilized Vertical Alignment Curing), therefore, when the test circuit board is formed, it may be formed by including PSVA Curing set to perform the PSVA Curing curing process PAD polymer vertical alignment curing circuit (Polymer-stabilized Vertical Alignment Curing PAD). That is, in the test circuit board, it can generally include a curing pad circuit.
  • PSVA Curing set to perform the PSVA Curing curing process
  • PAD polymer vertical alignment curing circuit Polymer-stabilized Vertical Alignment Curing PAD
  • each curing pad circuit can be connected to at least two array substrates, it is possible to perform array testing on the array substrate by applying a curing driving signal to the curing pad circuit and using the curing driving signal as an array test signal to improve array testing on the array substrate s efficiency.
  • the curing pad circuit is connected with two array substrates.
  • Step S20 Perform an array test on the array substrate in the curing pad circuit by using the curing driving signal.
  • a curing drive signal is sequentially applied to the curing pad circuits, and the array test is performed on the array substrate by using the curing drive signal as the array test signal. At least two array substrates are connected to the curing pad circuit.
  • the curing pad circuit After the array test signal passes through the curing pad circuit, if there is a difference in signal waveform between the received array test signal and the test signal input before passing through the curing pad circuit, it can be determined that the curing pad circuit is not conductive, that is, the curing At least one array substrate of the pad circuit is open or short-circuited; if there is no signal waveform difference between the received array test signal and the test signal input before passing through the curing pad circuit, it can be determined that the curing pad circuit is conductive, that is, the curing pad The tested array substrates connected in the circuit are all on.
  • a color film corresponding to the test circuit board may be prepared, that is, a color filter (Color Filter), after pairing the test circuit board and the color film, based on the cured circuit of the test circuit board, perform PSVA on the test circuit board and the color film Curing polymer is arranged vertically in the curing process, and the liquid crystal cell is prepared based on the test circuit board and color film after the curing process. In this way, the manufacturing efficiency of the liquid crystal cell can be improved.
  • a color filter Color Filter
  • a whole glass substrate composed of a pair of test circuit boards and color films after a curing process is cut and ground to form individual liquid crystal cells.
  • a glass substrate composed of a test circuit board including eight array substrates eight liquid crystal cells can be cut out.
  • curing drive signals are sequentially applied to the curing pad circuits, and at least two array substrates are connected to the curing pad circuits;
  • the signal performs an array test on the array substrate in the curing pad circuit.
  • Step S30 Acquire all the curing pad circuits that are not conducting through the curing drive signal test.
  • Step S31 Use the array substrate in the solidified pad circuit that is not conductive during the test as the target array substrate.
  • Step S32 Perform array testing on the target array substrate in sequence according to the arrangement order of the test pad circuits corresponding to the target array substrate in the test circuit board.
  • all curing drive signals in the test circuit board are tested to test the non-conducting curing pad circuits, and these tests are not conducted.
  • All the array substrates in the curing pad circuit are used as the target array substrate, and then, according to the arrangement order of the test pad circuits corresponding to the target array substrate in the test circuit board, test drive signals are sequentially applied to each of the test pad circuits, The test drive signal is used as an array test signal to perform array test on all target array substrates in the test circuit board in sequence.
  • the array test result of each target array substrate is obtained.
  • the array test result is open or short circuit, it is determined that the target array substrate test fails; when the array test result is conductive, the target array substrate test is determined to pass.
  • all curing drive signals are obtained to test the non-conducting curing pad circuit; the array substrate in the non-conducting curing pad circuit is used as the target array substrate; according to the test corresponding to the target array substrate The arrangement order of the pad circuits in the test circuit board sequentially performs array test on the target array substrate.
  • the test circuit board after the array test is performed on the array substrate using the curing pad circuit as the basic test unit, all array substrates that are not conductive by the curing pad circuit test are uniformly obtained, and then each array is based on the test pad circuit
  • the substrate is the basic test unit, which performs array testing on the array substrate that is not conductive to the curing pad circuit test, to quickly identify the array substrate that is substantially defective in the target array substrate, and improves the efficiency of array testing on the array substrate.
  • Step S40 When the curing drive signal test is not conducted, obtain a test pad circuit corresponding to the array substrate in the curing pad circuit.
  • Step S41 Perform array test on the array substrate in the curing pad circuit according to the order in which the test pad circuits are arranged in the test circuit board.
  • the test pad circuit corresponding to the array substrate in the curing pad circuit is obtained, and then the Arrangement order of the test pad circuits in the test circuit board, sequentially apply test drive signals to the test pad circuits, and use the test drive signals as array test signals to sequentially perform array test on the array substrate in the cured pad circuit.
  • the array test result of each array substrate in the curing pad circuit is obtained.
  • the array test result is open or short circuit, it is determined that the array substrate test fails; when the array test result is conductive, the array substrate test is determined by.
  • the test pad circuit corresponding to the array substrate in the curing pad circuit is obtained; according to the arrangement order of the test pad circuit in the test circuit board To perform array testing on the array substrate in the curing pad circuit.
  • the test circuit board after performing the array test on the array substrate using the curing pad circuit as the basic test unit, the array substrate that is not conductive by the curing pad circuit test is obtained, and then based on the test pad circuit, the test is not conducted. All array substrates in the curing pad circuit are subjected to array testing.
  • the array test efficiency of the array substrate in the test circuit board is improved.
  • Step S50 When the array test result is on, it is determined that all the array substrates in the curing pad circuit pass the test.
  • all array substrates in the curing pad circuit may be determined to pass the array test.
  • the array can be compared The efficiency of the substrate in the block-by-block test is doubled.
  • the present application also provides an array substrate testing device.
  • the array substrate testing device includes a memory, a processor, and an array substrate test program stored on the memory and executable on the processor.
  • the processor executes The test procedure of the array substrate realizes the steps of the test method of the array substrate as described in the above embodiment.
  • the present application also provides a computer-readable storage medium, the computer-readable storage medium includes a test program of the array substrate, and when the test program of the array substrate is executed by the processor, the array substrate as described in the above embodiment is implemented Of the test method.
  • the methods in the above embodiments can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware.
  • the technical solution of the present application can be embodied in the form of a software product in essence or part that contributes to the existing technology, and the computer software product is stored in a storage medium (such as ROM/RAM as described above) , Disk, CD), including several instructions to make a terminal device (which can be a TV, mobile phone, computer, server, air conditioner, or network equipment, etc.) to perform the method described in each embodiment of the present application.
  • a terminal device which can be a TV, mobile phone, computer, server, air conditioner, or network equipment, etc.

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  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

一种阵列基板的测试方法，包括以下步骤：根据固化垫电路在测试电路板中的排布顺序，依次对固化垫电路施加固化驱动信号，其中，固化垫电路连接有至少两块阵列基板；以及通过固化驱动信号对固化垫电路中的阵列基板进行阵列测试。还提供了一种阵列基板的测试装置以及计算机可读存储介质。

Description

阵列基板的测试方法、装置及存储介质
相关申请
本申请要求2018年12月5日申请的，申请号为201811483443.5，名称为“阵列基板的测试方法、装置及存储介质”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及薄膜晶体管阵列基板领域，尤其涉及一种阵列基板的测试方法、阵列基板的测试装置以及计算机可读存储介质。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。在显示面板生产过程中，在阵列基板制造完成后，需要设置测试电路板以对阵列基板进行阵列测试和固化制程。
每个测试电路板可以包括多块阵列基板，在对阵列基板进行阵列测试时，会根据阵列基板的布线序列，通过与每块阵列基板对应的阵列测试垫，依次给每块阵列基板施加测试驱动信号，而这样阵列基板逐块的测试过程，而导致阵列基板测试效率低下。
申请内容
本申请的主要目的在于提供一种阵列基板的测试方法、阵列基板的测试装置以及计算机可读存储介质，通过实现一次阵列测试信号至少测试两块阵列基板，提高了对阵列基板进行阵列测试的效率。
为实现上述目的，本申请提供一种阵列基板的测试方法，所述阵列基板的测试方法包括以下步骤：
根据固化垫电路在测试电路板中的排布顺序，依次对所述固化垫电路施加固化驱动信号，所述固化垫电路连接有至少两块阵列基板；
通过所述固化驱动信号对所述固化垫电路中的阵列基板进行阵列测试。
可选地，所述通过所述固化驱动信号对所述固化垫电路中的阵列基板进行阵列测试的步骤之后，还包括：
获取所有固化驱动信号测试不导通的固化垫电路；
将所述测试不导通的固化垫电路中的阵列基板作为目标阵列基板；
根据所述目标阵列基板对应的测试垫电路在所述测试电路板中的排布顺序，依次对所述目标阵列基板进行阵列测试。
可选地，所述根据所述目标阵列基板对应的测试垫电路在所述测试电路板中的排布顺序，依次对所述目标阵列基板进行阵列测试的步骤包括：
根据所述测试垫电路在所述测试电路板中的排布顺序，依次对所述测试垫电路施加测试驱动信号；
通过所述测试驱动信号对所述目标阵列基板进行阵列测试。
可选地，所述根据所述目标阵列基板对应的测试垫电路在所述测试电路板中的排布顺序，依次对所述目标阵列基板进行阵列测试的步骤之后，还包括：
在阵列测试结果为开路或短路时，判定所述目标阵列基板测试不通过；
在阵列测试结果为导通时，判定所述目标阵列基板测试通过。
可选地，所述通过所述固化驱动信号对所述固化垫电路中的阵列基板进行阵列测试的步骤之后，还包括：
在固化驱动信号测试不导通时，获取所述固化垫电路中的阵列基板对应的测试垫电路；
根据所述测试垫电路在所述测试电路板中的排布顺序，对所述固化垫电路中的阵列基板进行阵列测试。
可选地，所述根据所述测试垫电路在所述测试电路板中的排布顺序，对所述固化垫电路中的阵列基板进行阵列测试的步骤包括：
根据所述测试垫电路在所述测试电路板中的排布顺序，依次对所述测试垫电路施加测试驱动信号；
通过所述测试驱动信号对所述固化垫电路中的阵列基板进行阵列测试。
可选地，所述根据所述测试垫电路在所述测试电路板中的排布顺序，对所述固化垫电路中的阵列基板进行阵列测试的步骤之后，还包括：
在阵列测试结果为开路或短路时，判定所述阵列基板测试不通过；
在阵列测试结果为导通时，判定所述阵列基板测试通过。
可选地，所述通过所述固化驱动信号对所述固化垫电路中的阵列基板进行阵列测试的步骤之后，还包括：
在阵列测试结果为导通时，判定所述固化垫电路中的所有的阵列基板测试通过。
为实现上述目的，本申请还提供一种阵列基板的测试装置，所述阵列基板的测试装置包括：
所述阵列基板的测试装置包括存储器、处理器及存储在所述存储器上并可在所述处理器上运行的阵列基板的测试程序，所述阵列基板的测试程序被所述处理器执行时实现如上述阵列基板的测试方法的步骤。
为实现上述目的，本申请还提供一种计算机可读存储介质，所述计算机可读存储介质上存储有阵列基板的测试程序，所述阵列基板的测试程序被处理器执行时实现如上述阵列基板的测试方法的步骤。
本申请提供的阵列基板的测试方法、阵列基板的测试装置以及计算机可读存储介质，根据固化垫电路在测试电路板中的排布顺序，依次对所述固化垫电路施加固化驱动信号，所述固化垫电路连接有至少两块阵列基板；通过所述固化驱动信号对所述固化垫电路中的阵列基板进行阵列测试。这样，通过将固化驱动信号作为阵列测试信号，实现一次阵列测试信号至少测试两块阵列基板，提高了对阵列基板进行阵列测试的效率。
附图说明
图1为本申请实施例方案涉及的实施例终端的硬件运行环境示意图；
图2为本申请阵列基板的测试方法的一实施例的流程示意图；
图3为本申请阵列基板的测试方法的另一实施例的流程示意图；
图4为本申请阵列基板的测试方法的又一实施例的流程示意图；
图5为本申请阵列基板的测试方法的又一实施例的流程示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不限定本申请。
本申请提供一种阵列基板的测试方法，通过将固化驱动信号作为阵列测试信号，实现一次阵列测试信号至少测试两块阵列基板，提高了对阵列基板进行阵列测试的效率。
如图1所示，图1是本申请实施例方案涉及的实施例终端的硬件运行环境示意图；
本申请实施例终端可以是阵列基板的测试装置。
如图1所示，该终端可以包括：处理器1001，例如CPU中央处理器（central processing unit），存储器1002，通信总线1003。其中，通信总线1003设置为实现该终端中各组成部件之间的连接通信。存储器1002可以是高速RAM随机存储器（random-access memory），也可以是稳定的存储器（non-volatile memory），例如磁盘存储器。存储器1002可选的还可以是独立于前述处理器1001的存储装置。
本领域技术人员可以理解，图1中示出的终端的结构并不构成对本申请实施例终端的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。
如图1所示，作为一种计算机存储介质的存储器1002中可以包括阵列基板的测试程序。
在图1所示的终端中，处理器1001可以设置为调用存储器1002中存储的阵列基板的测试程序，并执行以下操作：
根据固化垫电路在测试电路板中的排布顺序，依次对所述固化垫电路施加固化驱动信号，所述固化垫电路连接有至少两块阵列基板；
通过所述固化驱动信号对所述固化垫电路中的阵列基板进行阵列测试。
可选地，处理器1001可以调用存储器1002中存储的阵列基板的测试程序，还执行以下操作：
获取所有固化驱动信号测试不导通的固化垫电路；
将所述测试不导通的固化垫电路中的阵列基板作为目标阵列基板；
根据所述目标阵列基板对应的测试垫电路在所述测试电路板中的排布顺序，依次对所述目标阵列基板进行阵列测试。
可选地，处理器1001可以调用存储器1002中存储的阵列基板的测试程序，还执行以下操作：
根据所述测试垫电路在所述测试电路板中的排布顺序，依次对所述测试垫电路施加测试驱动信号；
通过所述测试驱动信号对所述目标阵列基板进行阵列测试。
可选地，处理器1001可以调用存储器1002中存储的阵列基板的测试程序，还执行以下操作：
在阵列测试结果为开路或短路时，判定所述目标阵列基板测试不通过；
在阵列测试结果为导通时，判定所述目标阵列基板测试通过。
可选地，处理器1001可以调用存储器1002中存储的阵列基板的测试程序，还执行以下操作：
在固化驱动信号测试不导通时，获取所述固化垫电路中的阵列基板对应的测试垫电路；
根据所述测试垫电路在所述测试电路板中的排布顺序，对所述固化垫电路中的阵列基板进行阵列测试。
可选地，处理器1001可以调用存储器1002中存储的阵列基板的测试程序，还执行以下操作：
根据所述测试垫电路在所述测试电路板中的排布顺序，依次对所述测试垫电路施加测试驱动信号；
通过所述测试驱动信号对所述固化垫电路中的阵列基板进行阵列测试。
可选地，处理器1001可以调用存储器1002中存储的阵列基板的测试程序，还执行以下操作：
在阵列测试结果为开路或短路时，判定所述阵列基板测试不通过；
在阵列测试结果为导通时，判定所述阵列基板测试通过。
可选地，处理器1001可以调用存储器1002中存储的阵列基板的测试程序，还执行以下操作：
在阵列测试结果为导通时，判定所述固化垫电路中的所有的阵列基板测试通过。
参照图2，在一实施例中，所述阵列基板的测试方法包括：
步骤S10、根据固化垫电路在测试电路板中的排布顺序，依次对所述固化垫电路施加固化驱动信号，所述固化垫电路连接有至少两块阵列基板。
本实施例中，在液晶显示面板生产过程中，在薄膜晶体管阵列基板制造完成后，需要设置测试电路板对阵列基板进行阵列测试（Array Test，AT），以对多块阵列基板进行阵列测试，即所述测试电路板可以包括多块阵列基板。可选地，在形成待测试的测试电路板时，形成包括8块阵列基板的测试电路板。
阵列测试是对阵列基板上所有像素统一充电，进而发现各种电学不良的检测方法。为了实现对一块阵列基板上的所有像素统一充电，可以将阵列基板上的栅线、数据线、公共电极线以短路方式连接到阵列测试垫电路（Array Testing PAD）上，然后根据阵列测试垫电路在测试电路板中的排布顺序，通过向阵列测试垫电路依次施加测试驱动信号，以将测试驱动信号作为阵列测试信号，依次对阵列基板进行阵列测试。但是，这样对阵列基板逐块的进行阵列测试的过程，会导致阵列基板的测试效率低下。
由于在阵列基板后续的制程中，需要与彩膜（Color Filter）进行对组并进行PSVA Curing聚合物垂直排列固化制程（Polymer-stabilized Vertical Alignment Curing），因此，在形成测试电路板时，可以是形成包括设置为进行PSVA Curing固化制程的PSVA Curing PAD聚合物垂直排列固化垫电路（Polymer-stabilized Vertical Alignment Curing PAD）。即在测试电路板中，一般可以是包括固化垫电路的。
由于每个固化垫电路可以连接至少两块阵列基板，因此，可以通过向固化垫电路施加固化驱动信号，将固化驱动信号作为阵列测试信号对阵列基板进行阵列测试，以提高对阵列基板进行阵列测试的效率。
可选地，所述固化垫电路连接有两块阵列基板。
步骤S20、通过所述固化驱动信号对所述固化垫电路中的阵列基板进行阵列测试。
具体地，根据固化垫电路在测试电路板中的排布顺序，依次对所述固化垫电路施加固化驱动信号，将固化驱动信号作为阵列测试信号对阵列基板进行阵列测试。所述固化垫电路连接有至少两块阵列基板。
可选地，在阵列测试信号经过固化垫电路后，若接收到的阵列测试信号与经过固化垫电路前输入的测试信号存在信号波形差异，可判定该固化垫电路不导通，即所述固化垫电路至少有一块阵列基板存在开路或短路的情况；若接收到的阵列测试信号与经过固化垫电路前输入的测试信号不存在信号波形差异，可判定该固化垫电路导通，即该固化垫电路中连接的测试的阵列基板都是导通的。
因此，在通过所述固化驱动信号对所述固化垫电路中的阵列基板进行阵列测试测试之后，在一个固化垫电路测试导通时，可以将该固化垫电路中的所有阵列基板判定为阵列测试通过；在一个固化垫电路测试不导通时，将该固化垫电路中的所有阵列基板依次基于测试垫电路再次进行阵列测试，以甄别出这些阵列基板中，真实存在的阵列测试不通过的阵列基板。
在对阵列基板进行阵列测试后，获取所有测试不通过的阵列基板，即获取所有测试为不良品的阵列基板，对测试不通过的阵列基板进行Array Repair阵列不良修复，利用激光加工的方法，修复测试不通过的阵列基板的阵列电路的异常结构，使阵列基板的阵列电路恢复正常。
可选地，获取所有经过阵列不良修复的阵列基板，根据阵列基板对应的测试垫电路在测试电路板中的排布顺序，对阵列不良修复后的阵列基板再次进行阵列测试，以检验阵列基板是否修复完成。
在对测试电路板中的阵列基板进行阵列测试以及阵列修复后，可以是配制与该测试电路板对应的彩膜，即彩色滤光片（Color Filter），在将测试电路板和彩膜进行对组后，基于该测试电路板的固化垫电路，对测试电路板和彩膜进行PSVA Curing聚合物垂直排列固化制程，并基于进行固化制程后的测试电路板和彩膜制备液晶盒。这样，可以提高液晶盒的制备效率。
当然，若该测试电路板中，所有的阵列基板的阵列测试结果均为测试通过，则可以直接利用该测试电路板，在将测试电路板和彩膜进行对组后，基于该测试电路板的固化垫电路，对测试电路板和彩膜进行PSVA Curing聚合物垂直排列固化制程，并基于进行固化制程后的测试电路板和彩膜制备液晶盒。
具体地，对由测试电路板和彩膜对组后构成的，经过固化制程后的一整块玻璃基板进行切割研磨，以形成一个个液晶盒。比如，对于由一块包括八块阵列基板的测试电路板构成的玻璃基板，可以切割出八个液晶盒。
在一实施例中，根据固化垫电路在测试电路板中的排布顺序，依次对所述固化垫电路施加固化驱动信号，所述固化垫电路连接有至少两块阵列基板；通过所述固化驱动信号对所述固化垫电路中的阵列基板进行阵列测试。这样，通过将固化驱动信号作为阵列测试信号，实现一次阵列测试信号至少测试两块阵列基板，提高了对阵列基板进行阵列测试的效率。
在另一实施例中，如图3所示，在上述图2所示的实施例基础上，所述通过所述固化驱动信号对所述固化垫电路中的阵列基板进行阵列测试的步骤之后，还包括：
步骤S30、获取所有固化驱动信号测试不导通的固化垫电路。
步骤S31、将所述测试不导通的固化垫电路中的阵列基板作为目标阵列基板。
步骤S32、根据所述目标阵列基板对应的测试垫电路在所述测试电路板中的排布顺序，依次对所述目标阵列基板进行阵列测试。
本实施例中，在依次对测试电路板中的固化垫电路施加固化驱动信号后，获取该测试电路板中，所有固化驱动信号测试不导通的固化垫电路，并将这些测试不导通的固化垫电路中的所有阵列基板作为目标阵列基板，然后根据所述目标阵列基板对应的测试垫电路在所述测试电路板中的排布顺序，依次对各个所述测试垫电路施加测试驱动信号，将测试驱动信号作为阵列测试信号对统一对测试电路板中的所有目标阵列基板依次进行阵列测试。
然后获取每块目标阵列基板的阵列测试结果，在阵列测试结果为开路或短路时，则判定该目标阵列基板测试不通过；在阵列测试结果为导通时，则判定该目标阵列基板测试通过。
在其中一实施例中，获取所有固化驱动信号测试不导通的固化垫电路；将所述测试不导通的固化垫电路中的阵列基板作为目标阵列基板；根据所述目标阵列基板对应的测试垫电路在所述测试电路板中的排布顺序，依次对所述目标阵列基板进行阵列测试。这样，在对测试电路板中，先以固化垫电路为基本测试单位对阵列基板进行阵列测试后，统一获取固化垫电路测试不导通的所有阵列基板，再基于测试垫电路，以每块阵列基板为基本测试单位，统一对固化垫电路测试不导通的阵列基板进行阵列测试，实现快速甄别出目标阵列基板中实质为不良品的阵列基板，提高了对阵列基板进行阵列测试的效率。
在又一实施例中，如图4所示，在上述图2至图3的实施例基础上，所述通过所述固化驱动信号对所述固化垫电路中的阵列基板进行阵列测试的步骤之后，还包括：
步骤S40、在固化驱动信号测试不导通时，获取所述固化垫电路中的阵列基板对应的测试垫电路。
步骤S41、根据所述测试垫电路在所述测试电路板中的排布顺序，对所述固化垫电路中的阵列基板进行阵列测试。
本实施例中，在对测试电路板中的固化垫电路施加固化驱动信号后，在固化驱动信号测试不导通时，获取所述固化垫电路中的阵列基板对应的测试垫电路，然后根据所述测试垫电路在所述测试电路板中的排布顺序，依次对所述测试垫电路施加测试驱动信号，将测试驱动信号作为阵列测试信号依次对该固化垫电路中的阵列基板进行阵列测试。
然后获取该固化垫电路中每块阵列基板的阵列测试结果，在阵列测试结果为开路或短路时，则判定该阵列基板测试不通过；在阵列测试结果为导通时，则判定该阵列基板测试通过。
在其中一实施例中，在固化驱动信号测试不导通时，获取所述固化垫电路中的阵列基板对应的测试垫电路；根据所述测试垫电路在所述测试电路板中的排布顺序，对所述固化垫电路中的阵列基板进行阵列测试。这样，在对测试电路板中，先以固化垫电路为基本测试单位对阵列基板进行阵列测试后，获取固化垫电路测试不导通的阵列基板，再基于测试垫电路，对测试不导通的固化垫电路中的所有阵列基板进行阵列测试，通过结合固化垫电路测试和测试垫电路测试对阵列基板进行阵列测试，提高了测试电路板中，阵列基板的阵列测试效率。
在又一实施例中，如图5所示，在上述图2至图4的实施例基础上，所述通过所述固化驱动信号对所述固化垫电路中的阵列基板进行阵列测试的步骤之后，还包括：
步骤S50、在阵列测试结果为导通时，判定所述固化垫电路中的所有的阵列基板测试通过。
本实施例中，在对测试电路板中的固化垫电路施加固化驱动信号后，在一个固化垫电路测试导通时，可以将该固化垫电路中的所有阵列基板判定为阵列测试通过。以一块测试电路板中，一个固化垫电路连接有两块阵列基板为例，若该测试电路板中，每个固化垫电路的测试结果均为导通，即可实现比基于测试垫电路对阵列基板进行逐块测试时的效率提高一倍。
此外，本申请还提出一种阵列基板的测试装置，所述阵列基板的测试装置包括存储器、处理器及存储在存储器上并可在处理器上运行的阵列基板的测试程序，所述处理器执行所述阵列基板的测试程序时实现如以上实施例所述的阵列基板的测试方法的步骤。
此外，本申请还提出一种计算机可读存储介质，所述计算机可读存储介质包括阵列基板的测试程序，所述阵列基板的测试程序被处理器执行时实现如以上实施例所述的阵列基板的测试方法的步骤。
上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在如上所述的一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是电视机，手机，计算机，服务器，空调器，或者网络设备等)执行本申请各个实施例所述的方法。
以上仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种阵列基板的测试方法，其中，所述阵列基板的测试方法包括以下步骤：
    根据固化垫电路在测试电路板中的排布顺序，依次对所述固化垫电路施加固化驱动信号，所述固化垫电路连接有至少两块阵列基板；以及
    通过所述固化驱动信号对所述固化垫电路中的阵列基板进行阵列测试。
  2. 如权利要求1所述的阵列基板的测试方法，其中，所述通过所述固化驱动信号对所述固化垫电路中的阵列基板进行阵列测试的步骤之后，还包括：
    获取所有固化驱动信号测试不导通的固化垫电路；
    将所述测试不导通的固化垫电路中的阵列基板作为目标阵列基板；以及
    根据所述目标阵列基板对应的测试垫电路在所述测试电路板中的排布顺序，依次对所述目标阵列基板进行阵列测试。
  3. 如权利要求2所述的阵列基板的测试方法，其中，所述根据所述目标阵列基板对应的测试垫电路在所述测试电路板中的排布顺序，依次对所述目标阵列基板进行阵列测试的步骤之后，还包括：
    在阵列测试结果为开路或短路时，判定所述目标阵列基板测试不通过；以及
    在阵列测试结果为导通时，判定所述目标阵列基板测试通过。
  4. 如权利要求2所述的阵列基板的测试方法，其中，所述根据所述目标阵列基板对应的测试垫电路在所述测试电路板中的排布顺序，依次对所述目标阵列基板进行阵列测试的步骤包括：
    根据所述测试垫电路在所述测试电路板中的排布顺序，依次对所述测试垫电路施加测试驱动信号；以及
    通过所述测试驱动信号对所述目标阵列基板进行阵列测试。
  5. 如权利要求4所述的阵列基板的测试方法，其中，所述通过所述测试驱动信号对所述目标阵列基板进行阵列测试的步骤之后，还包括：
    在阵列测试结果为开路或短路时，判定所述目标阵列基板测试不通过；以及
    在阵列测试结果为导通时，判定所述目标阵列基板测试通过。
  6. 如权利要求1所述的阵列基板的测试方法，其中，所述通过所述固化驱动信号对所述固化垫电路中的阵列基板进行阵列测试的步骤之后，还包括：
    在固化驱动信号测试不导通时，获取所述固化垫电路中的阵列基板对应的测试垫电路；以及
    根据所述测试垫电路在所述测试电路板中的排布顺序，对所述固化垫电路中的阵列基板进行阵列测试。
  7. 如权利要求6所述的阵列基板的测试方法，其中，所述根据所述测试垫电路在所述测试电路板中的排布顺序，对所述固化垫电路中的阵列基板进行阵列测试的步骤之后，还包括：
    在阵列测试结果为开路或短路时，判定所述阵列基板测试不通过；以及
    在阵列测试结果为导通时，判定所述阵列基板测试通过。
  8. 如权利要求6所述的阵列基板的测试方法，其中，所述根据所述测试垫电路在所述测试电路板中的排布顺序，对所述固化垫电路中的阵列基板进行阵列测试的步骤包括：
    根据所述测试垫电路在所述测试电路板中的排布顺序，依次对所述测试垫电路施加测试驱动信号；以及
    通过所述测试驱动信号对所述固化垫电路中的阵列基板进行阵列测试。
  9. 如权利要求8所述的阵列基板的测试方法，其中，所述通过所述测试驱动信号对所述固化垫电路中的阵列基板进行阵列测试的步骤之后，还包括：
    在阵列测试结果为开路或短路时，判定所述阵列基板测试不通过；以及
    在阵列测试结果为导通时，判定所述阵列基板测试通过。
  10. 如权利要求1所述的阵列基板的测试方法，其中，所述通过所述固化驱动信号对所述固化垫电路中的阵列基板进行阵列测试的步骤之后，还包括：
    在阵列测试结果为导通时，判定所述固化垫电路中的所有的阵列基板测试通过。
  11. 如权利要求1所述的阵列基板的测试方法，其中，所述根据固化垫电路在测试电路板中的排布顺序，依次对所述固化垫电路施加固化驱动信号的步骤之前，还包括：
    形成包括多块所述阵列基板的所述测试电路板。
  12. 如权利要求1所述的阵列基板的测试方法，其中，所述测试电路板包括8块所述阵列基板。
  13. 如权利要求1所述的阵列基板的测试方法，其中，所述固化垫电路连接有两块阵列基板。
  14. 如权利要求1所述的阵列基板的测试方法，其中，所述阵列基板连接有一个测试垫电路。
  15. 如权利要求1所述的阵列基板的测试方法，其中，所述阵列基板的测试方法还包括：
    获取测试不通过的阵列基板，对所述阵列基板进行阵列不良修复。
  16. 如权利要求15所述的阵列基板的测试方法，其中，所述获取测试不通过的阵列基板，对所述阵列基板进行阵列不良修复的步骤之后，还包括：
    获取所有经过阵列不良修复的阵列基板；以及
    根据所述阵列基板对应的测试垫电路在所述测试电路板中的排布顺序，对所述阵列基板进行阵列测试。
  17. 如权利要求1所述的阵列基板的测试方法，其中，所述阵列基板的测试方法还包括：
    在所述测试电路板中的所有阵列基板测试通过时，获取与所述测试电路板对应的彩膜；以及
    将所述测试电路板与所述彩膜进行对组，并基于所述测试电路板的所述测试垫电路进行固化制程。
  18. 如权利要求17所述的阵列基板的测试方法，其中，所述将所述测试电路板与所述彩膜进行对组，并基于所述测试电路板的所述测试垫电路进行固化制程的步骤之后，还包括：
    基于进行固化制程后的测试电路板和彩膜，制备液晶盒。
  19. 一种阵列基板的测试装置，其中，所述阵列基板的测试装置包括存储器、处理器及存储在所述存储器上并可在所述处理器上运行的阵列基板的测试程序，所述阵列基板的测试程序被所述处理器执行时实现如下阵列基板的测试方法的步骤：
    根据固化垫电路在测试电路板中的排布顺序，依次对所述固化垫电路施加固化驱动信号，所述固化垫电路连接有至少两块阵列基板；以及
    通过所述固化驱动信号对所述固化垫电路中的阵列基板进行阵列测试。
  20. 一种计算机可读存储介质，其中，所述计算机可读存储介质上存储有阵列基板的测试程序，所述阵列基板的测试程序被处理器执行时实现如下阵列基板的测试方法的步骤：
    根据固化垫电路在测试电路板中的排布顺序，依次对所述固化垫电路施加固化驱动信号，所述固化垫电路连接有至少两块阵列基板；以及
    通过所述固化驱动信号对所述固化垫电路中的阵列基板进行阵列测试。
PCT/CN2018/121889 2018-12-05 2018-12-19 阵列基板的测试方法、装置及存储介质 Ceased WO2020113678A1 (zh)

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