WO2020107643A1 - 液晶面板及其栅极驱动电路 - Google Patents

液晶面板及其栅极驱动电路 Download PDF

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Publication number
WO2020107643A1
WO2020107643A1 PCT/CN2019/070208 CN2019070208W WO2020107643A1 WO 2020107643 A1 WO2020107643 A1 WO 2020107643A1 CN 2019070208 W CN2019070208 W CN 2019070208W WO 2020107643 A1 WO2020107643 A1 WO 2020107643A1
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Prior art keywords
pull
signal
module
gate
input port
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Ceased
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PCT/CN2019/070208
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English (en)
French (fr)
Inventor
张鑫
肖军城
管延庆
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US16/472,900 priority Critical patent/US10847101B2/en
Publication of WO2020107643A1 publication Critical patent/WO2020107643A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of driving circuits, and in particular to a gate driving circuit of a liquid crystal panel.
  • the liquid crystal display device has been widely used in various electronic products as the display component of electronic equipment, and the array substrate line scan drive (Gate Driver On Array, GOA) circuit is an important part of the liquid crystal display device.
  • GOA is a driving method that uses the existing thin film transistor manufacturing process to make the gate row scanning drive signal circuit on the array substrate to realize the progressive scanning of the pixel array gate.
  • Figures 1 and 2 are a conventional array substrate row scanning drive circuit, and Figure 3 is a timing diagram of the circuit of Figure 2.
  • the existing GOA circuit can be divided into an N-channel metal oxide semiconductor (N-MOS) circuit, a P-channel metal oxide semiconductor (P-MOS) circuit, and a complementary metal oxide semiconductor (CMOS) circuit.
  • N-MOS N-channel metal oxide semiconductor
  • P-MOS P-channel metal oxide semiconductor
  • CMOS complementary metal oxide semiconductor
  • the NMOS circuit omits the P-doping process and the photomask, which is of great benefit for improving the yield and reducing the cost.
  • the stability of the NMOS or PMOS single-type GOA drive circuit is susceptible to interference from the display area, especially in the case of heavy-loaded screens (pixel dot reversal, etc.), it is easy to cause the GOA drive circuit to fail, especially Large horizontal screen.
  • Patent No. CN105261343B discloses a GOA drive circuit, which is provided with a multi-level GOA drive module.
  • Each level of GOA drive module includes: a first drive unit for outputting a line scan signal during a line scan; a second drive unit, an output terminal of which Coupling with the output end of the first driving unit, used to maintain the output signal of the output end during the line scan, and output the scan signal corresponding to the touch scan signal during the touch scan; wake up the drive unit, used for black screen When awakening, the drive modules at all levels can simultaneously output valid line signals.
  • the GOA drive circuit can effectively eliminate the unstable factors existing in the circuit and reduce the risk of circuit function failure. However, it cannot solve the problem that the stability of the single-type GOA is easily interfered by the display area, especially in the case of heavy-loaded pictures (pictures such as Pixel point inversion), which can easily lead to GOA failure.
  • the existing GOA scanning circuit cannot solve the problem that the stability of the single-type GOA is easily interfered by the display area, especially in the case of heavy-loaded pictures (pictures such as pixel inversion), which easily lead to GOA failure.
  • a gate driving circuit of a liquid crystal panel including: a plurality of shift registers.
  • Each of the shift registers includes: a forward and reverse gear module, a low potential line, and a synchronization module.
  • the forward and reverse gear modules have a top-down signal input port and a bottom-up signal input port.
  • the forward and reverse gear modules control the scanning order of the plurality of shift registers according to the signals of the up-to-down signal input port and the down-to-up signal input port.
  • the synchronization module is used for conducting the low potential line, the lower-potential signal input port, and the lower-potential signal input port, which have a lower potential.
  • Each of the shift registers further includes: a gate signal port, a pull-up module, a pull-up switch, a pull-down module, and a pull-down switch.
  • the pull-up module is used to receive a gate signal of the shift register of the previous stage and generate a pull-up signal.
  • the pull-up switch is connected to the pull-up module and the gate signal port for receiving the pull-up signal and a clock signal, and for sending the clock signal to the pull-up signal according to the pull-up signal Gate signal port.
  • the pull-down module is used to receive a gate signal of the shift register of the next stage and generate a pull-down signal.
  • the pull-down switch is connected to the pull-down module, the gate signal port, and the low potential line to receive the pull-down signal, and is used to connect the gate signal port and the low voltage according to the pull-down signal
  • the potential wire is turned on.
  • the forward and reverse gear modules are connected to the pull-up module and the pull-down module and used to control the pull-up module and the pull-down according to the signals of the up-to-down signal input port and the down-to-up signal input port Module.
  • the synchronization module has a first thin film transistor and a second thin film transistor, wherein a gate of the first thin film transistor is connected to the In the up-to-down signal input port, a source is connected to the low-potential line, a drain is connected to the down-to-up signal input port, and a gate of the second thin film transistor is connected to the down-to-up signal input port , A source is connected to the up-to-down signal input port, and a drain is connected to the low potential line.
  • the gate driving circuit of the liquid crystal panel further includes a fully-off module connected to the gate signal port and the low potential line.
  • the gate driving circuit of the liquid crystal panel further includes a fully open module connected to the gate signal port, the pull-down switch, and the low potential line.
  • the gate driving circuit of the liquid crystal panel is an array substrate row scanning driver (Gate Driver On Array, GOA) circuit.
  • GOA Gate Driver On Array
  • the first thin film transistor and the second thin film transistor are both N-channel metal oxide semiconductors.
  • the present disclosure also proposes a gate drive circuit for a liquid crystal panel, including: a plurality of shift registers.
  • Each of the shift registers includes: a forward and reverse gear module, a low potential line, and a synchronization module.
  • the forward and reverse gear modules have a top-down signal input port and a bottom-up signal input port.
  • the forward and reverse gear modules control the scanning order of the plurality of shift registers according to the signals of the up-to-down signal input port and the down-to-up signal input port.
  • the synchronization module is used for conducting the low potential line, the lower-potential signal input port, and the lower-potential signal input port, which have a lower potential.
  • each of the shift registers further includes: a gate signal port, a pull-up module, a pull-up switch, a pull-down module, and a pull-down module Pull the switch.
  • the pull-up module is used to receive a gate signal of the shift register of the previous stage and generate a pull-up signal.
  • the pull-up switch is connected to the pull-up module and the gate signal port for receiving the pull-up signal and a clock signal, and for sending the clock signal to the pull-up signal according to the pull-up signal Gate signal port.
  • the pull-down module is used to receive a gate signal of the shift register of the next stage and generate a pull-down signal.
  • the pull-down switch is connected to the pull-down module, the gate signal port, and the low potential line to receive the pull-down signal, and is used to connect the gate signal port and the low voltage according to the pull-down signal
  • the potential wire is turned on.
  • the forward and reverse gear modules are connected to the pull-up module and the pull-down module and used to control the pull-up module and the pull-down according to the signals of the up-to-down signal input port and the down-to-up signal input port Module.
  • the synchronization module has a first thin film transistor and a second thin film transistor, wherein a gate of the first thin film transistor is connected to the In the up-to-down signal input port, a source is connected to the low-potential line, a drain is connected to the down-to-up signal input port, and a gate of the second thin film transistor is connected to the down-to-up signal input port , A source is connected to the up-to-down signal input port, and a drain is connected to the low potential line.
  • the gate driving circuit of the liquid crystal panel further includes a fully-off module connected to the gate signal port and the low potential line.
  • the gate driving circuit of the liquid crystal panel further includes a fully open module connected to the gate signal port, the pull-down switch, and the low potential line.
  • the gate driving circuit of the liquid crystal panel is an array substrate row scanning driver (Gate Driver On Array, GOA) circuit.
  • GOA Gate Driver On Array
  • the first thin film transistor and the second thin film transistor are both N-channel metal oxide semiconductors.
  • the disclosure also proposes a liquid crystal panel including: a substrate, a pixel array, a gate driving circuit, and a clock signal generator, wherein the pixel array, the gate driving circuit, and the clock signal
  • the generators are all disposed on the substrate
  • the gate drive circuit is used to drive the pixel array
  • the clock signal generator is used to provide a clock signal to the gate drive circuit
  • the gate drive circuit includes : Plural shift registers.
  • Each of the shift registers includes a forward and reverse gear module, a low potential line, and a synchronization module.
  • the forward and reverse gear module has a top-down signal input port and a bottom-up signal input port, the forward and reverse gear module is controlled according to the signals of the top-down signal input port and the bottom-up signal input port The scanning sequence of the plurality of shift registers.
  • the synchronization module is used for conducting the low potential line, the lower-potential signal input port, and the lower-potential signal input port, which have a lower potential.
  • each of the shift registers further includes: a gate signal port, a pull-up module, a pull-up switch, a pull-down module, and a pull-down switch.
  • the pull-up module is used to receive a gate signal of the shift register of the previous stage and generate a pull-up signal.
  • the pull-up switch is connected to the pull-up module, the gate signal port, and the clock signal generator to receive the pull-up signal and the clock signal, and is used to connect the pull-up signal according to the pull-up signal
  • the clock signal is sent to the gate signal port.
  • the pull-down module is used to receive a gate signal of the shift register of the next stage and generate a pull-down signal.
  • the pull-down switch is connected to the pull-down module, the gate signal port, and the low potential line to receive the pull-down signal, and is used to connect the gate signal port and the low voltage according to the pull-down signal
  • the potential wire is turned on.
  • the forward and reverse gear modules are connected to the pull-up module and the pull-down module and used to control the pull-up module and the pull-down according to the signals of the up-to-down signal input port and the down-to-up signal input port Module.
  • the synchronization module has a first thin film transistor and a second thin film transistor, wherein a gate of the first thin film transistor is connected to the up-to-down signal input Port, a source is connected to the low potential line, a drain is connected to the bottom-up signal input port, a gate of the second thin film transistor is connected to the bottom-up signal input port, and a source is connected To the up-to-down signal input port, a drain is connected to the low potential line.
  • the liquid crystal panel further includes a fully-off module connected to the gate signal port and the low potential line.
  • the liquid crystal panel further includes a fully open module connected to the gate signal port, the pull-down switch, and the low potential line.
  • the gate driving circuit of the liquid crystal panel is an array substrate row scan driver (Gate Driver On Array, GOA) circuit.
  • GOA Gate Driver On Array
  • the first thin film transistor and the second thin film transistor of the gate drive circuit of the liquid crystal panel are both N-channel metal oxide semiconductors.
  • the present disclosure provides a single-type GOA driving circuit to realize the line-by-line opening function of the pixel array thin film transistor.
  • the present disclosure improves the stability of the function of the single-type GOA drive circuit under the heavy-load screen through the synchronization module.
  • the disclosure realizes the purpose of synchronizing the down-to-up signal input port and the low-potential line disturbance or the up-to-down signal input port and the low-potential line disturbance, so as to prevent the stability of the gate drive circuit from being disturbed by the display area and reduce the weight of the gate drive circuit Risk of failure.
  • FIG. 1 is a circuit diagram of a gate row scanning driving circuit in the prior art
  • FIG. 2 is a circuit diagram of a gate clock scanning drive circuit with a 4-clock signal in the prior art
  • Figure 3 is a timing diagram of the circuit of Figure 2;
  • FIG. 5 is a circuit diagram of an embodiment of a shift register of the disclosed gate driving circuit.
  • FIG. 6 is a schematic diagram of an embodiment of the disclosed liquid crystal panel.
  • FIG. 4 is a structural block diagram of the gate driving circuit of the present disclosure.
  • a gate driving circuit 100 for a liquid crystal panel which includes: a plurality of shift registers 10, 11, ... 1n.
  • each of the shift registers includes: a forward and reverse gear module 1, a low potential line VGL, and a synchronization module 2.
  • the forward and reverse gear module 1 has a top-down signal input port U2D and a bottom-up signal input port D2U.
  • the forward and reverse gear module 1 controls the scanning order of the plurality of shift registers 10, 11, ... 1n according to the signals of the up-to-down signal input port U2D and the down-to-up signal input port D2U.
  • the synchronization module 2 is used to turn on the lower potential line VGL and the up-to-down signal input port U2D and the down-to-up signal input port D2U, whichever is lower.
  • a gate driving circuit of a liquid crystal panel uses a shift register 11 as an example, wherein each of the shift registers further includes: a gate signal port G1, a pull-up module 3, and a Pull switch SU, pull module 4, and pull switch SD.
  • the pull-up module 3 is used to receive a gate signal GOS of the shift register 10 of the previous stage and generate a pull-up signal.
  • the pull-up switch SU is connected to the pull-up module 3 and the gate signal port G1 for receiving the pull-up signal and a clock signal CK1, and for clocking the clock signal according to the pull-up signal CK1 is sent to the gate signal port G1.
  • the pull-down module 4 is used to receive a gate signal G2S of the shift register 12 of the next stage and generate a pull-down signal.
  • the pull-down switch SD is connected to the pull-down module 4, the gate signal port G1 and the low-potential line VGL to receive the pull-down signal, and to connect the gate signal port according to the pull-down signal G1 is connected to the low potential line VGL.
  • the forward and reverse gear module 1 is connected to the pull-up module 3 and the pull-down module 4, and is used to control the up-down signal input port U2D and the down-up signal input port D2U to control the up Pull module 3 and the pull-down module 4.
  • the basic components of the gate drive circuit depicted in FIGS. 4 and 5 are only embodiments of the present disclosure, and the present disclosure is not limited thereto.
  • the circuit of the shift register may also use other methods such as an interlace driving method (Interlace) or a bilateral array substrate line driving circuit (Bilateral array substrate line driving circuit).
  • Interlace interlace driving method
  • Bilateral array substrate line driving circuit Bilateral array substrate line driving circuit
  • the 4-clock pulse gate drive circuit shown in FIG. 5 can also be adaptively adjusted to have a 6-clock pulse drive circuit or an 8-clock pulse drive circuit, and the disclosure is not limited thereto.
  • FIG. 5 is a circuit diagram of an embodiment of a shift register of a gate driving circuit according to the present disclosure.
  • a gate driving circuit of a liquid crystal panel of an embodiment of the present disclosure uses a shift register 11 as an example, wherein the synchronization module 2 has a first thin film transistor NT3-1 and a second thin film transistor NT4-1, wherein The gate of the first thin film transistor NT3-1 is connected to the up-down signal input port U2D, the source is connected to the low potential line VGL, and the drain is connected to the down-to-up signal input port D2U.
  • the gate of the second thin film transistor NT4-1 is connected to the down-to-up signal input port D2U, the source is connected to the up-to-down signal input port U2D, and the drain is connected to the low potential line VGL.
  • the shift register of the gate driving circuit of the liquid crystal panel of an embodiment of the present disclosure taking the shift register 11 as an example, further includes a fully-off module AGF connected to the gate signal port G1 and the low potential line VGL.
  • the shift register of the gate driving circuit of the liquid crystal panel of an embodiment of the present disclosure further includes a fully open module AGO connected to the gate signal port G1 and the pull-down switch SD (NT10) and the low potential line VGL.
  • the gate driving circuit of the liquid crystal panel according to an embodiment of the present disclosure is a gate driver on array (GOA) circuit.
  • GOA gate driver on array
  • a gate driving circuit of a liquid crystal panel according to an embodiment of the present disclosure wherein the first thin film transistor and the second thin film transistor are both N-channel metal oxide semiconductors.
  • a liquid crystal panel is also provided.
  • FIG. 6 is a schematic diagram of an embodiment of the disclosed liquid crystal panel.
  • An embodiment of a liquid crystal panel 200 of the present disclosure includes: a substrate 210, a pixel array 220, a gate drive circuit 100, and a clock signal generator 230, wherein the pixel array 220 and the gate drive The circuit 100 and the clock signal generator 230 are both disposed on the substrate 100.
  • the gate driving circuit 100 is used to drive the pixel array 220.
  • the clock signal generator 230 is used to provide a clock signal to the gate driving circuit 100.
  • the gate driving circuit 100 includes: a plurality of shift registers 10, 11, ... 1n.
  • each of the shift registers includes: a forward and reverse gear module 1, a low potential line VGL, and a synchronization module 2.
  • the forward and reverse gear module 1 has an up-to-down signal input port U2D and a down-to-up signal input port D2U
  • the forward-reverse gear module 1 is based on the up-to-down signal input port U2D and the down-to-up signal input
  • the signal of the port D2U controls the scanning sequence of the plurality of shift registers 10, 11, ... 1n.
  • the synchronization module 2 is used to turn on the lower potential line VGL and the up-to-down signal input port U2D and the down-to-up signal input port D2U, whichever is lower.
  • the pull-up switch SU includes a thin-film transistor NT9
  • the pull-down switch SD includes thin-film transistors NT5 and NT10.
  • the thin film transistor NT5 is used to turn off the thin film transistor NT9.
  • the thin film transistor NT10 is used to pull the voltage level of the gate signal port G1 to be the same as the voltage level of the low potential line VGL.
  • An embodiment of the forward and reverse gear module 1 includes three thin film transistors NT3, NT4, and NT8, wherein the gate of the thin film transistor NT3 is connected to the lower signal input port U2D, the source is connected to the clock signal CK3, and the thin film transistor The gate of NT4 is connected to the upper signal input port D2U, and the source is connected to the clock signal CK0.
  • the drains of the thin film transistors NT3 and NT4 are both connected to the gate of the thin film transistor NT8.
  • the source of the thin film transistor NT8 is connected to the high potential line VGH, and the drain is connected to the thin film transistors NT5 and NT10 of the pull-down switch SD to control the thin film transistors NT5 and NT10.
  • the pull-up module 3 includes a thin film transistor NT1
  • the pull-down module 4 includes thin film transistors NT2 and NT6.
  • the fully-off module AGF includes a thin film transistor NT14, a source of the thin film transistor NT14 is connected to the gate signal port G1, and a drain of the thin film transistor NT14 is connected to the low potential line VGL.
  • the fully-open module AGO includes a thin film transistor NT11 and a thin film transistor NT12, the drain of the thin film transistor NT11 is connected to the gate signal port G1, the source of the thin film transistor NT12 is connected to the pull-down switch SD, and the drain of the thin film transistor NT12 is connected To the low potential line VGL.
  • the potential of the up-to-down signal input port U2D is High and the potential of the down-to-up signal input port D2U is Low (Low). Therefore, the first thin film transistor NT3-1 in the synchronization module 2 In the on state, the down-to-up signal input port D2U and the low-potential line VGL are conducted through the first thin film transistor NT3-1, so that the down-to-up signal input port D2U and the low-potential line VGL are synchronized in disturbance. Reduce the risk of array substrate row scan drive (GOA) circuit overload failure.
  • GOA array substrate row scan drive
  • the second thin film transistor NT4-1 in the synchronization module 2 In the on state, the up-to-down signal input port U2D and the low-potential line VGL are turned on through the second thin film transistor NT4-1 to realize the up-down signal input port U2D and the low-potential line VGL disturbance synchronization. Reduce the risk of array substrate row scan drive (GOA) circuit overload failure.
  • GAA array substrate row scan drive
  • the pixel array of the display area is connected to the low potential line VGL through the thin film transistor NT10.
  • the low potential line VGL is most affected by the coupling of the signals in the display area.
  • the low-potential line VGL has a larger fluctuation than the bottom-up signal input port D2U, so although the voltage of the low-potential line VGL and the bottom-up signal input port D2U are theoretically the same, there are actually low-potential lines VGL that are Due to the coupling effect, the instantaneous voltage of the low-potential line VGL is higher than the signal input port D2U of the down-to-up signal.
  • the thin-film transistor NT2 in the pull-down module 4 its gate is connected to the gate signal port G2 of the next-stage shift register
  • the shift register of the first stage should be kept closed when the shift register of this stage is turned on. Therefore, its gate signal port G2 is connected to the low potential line VGL through its thin film transistor NT10.
  • the instantaneous voltage of the low potential line VGL is disturbed, there is a risk that the thin film transistor NT2 of this stage will be instantaneously turned on. If the thin film transistor NT2 is turned on, there is a risk that the potential at the Q point will be released, and the high potential cannot be maintained.
  • the Q point When the shift register of this stage is turned on, the Q point should maintain its high (high) potential to enable the thin film transistor NT9 of the pull-up switch SU to turn on, so as to realize the normal stage transfer function. If the Q point potential is released, it will cause the thin film transistor NT9 to turn off, causing the GOA function to fail.
  • a single-type GOA driving circuit designed by the present disclosure realizes the function of opening the gates of the pixel array thin film transistors row by row.
  • the present disclosure improves the stability of the function of the single-type GOA drive circuit under the heavy-load screen through the synchronization module.
  • the disclosure realizes the purpose of synchronizing the down-to-up signal input port and low-potential line disturbance or the up-to-down signal input port and low-potential line disturbance, so as to avoid the stability of the gate drive circuit from being easily interfered by the display area and reduce the gate drive circuit Risk of overload failure.

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  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
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Abstract

一种栅极驱动电路(100)以及具有该栅极驱动电路(100)的液晶面板(200)，所述栅极驱动电路(100)包括：复数个移位寄存器(10, 11, …, 1n)，其中每一个所述移位寄存器(10, 11, …, 1n)包括：一正反档模块(1)、一低电位线(VGL)及一同步模块(2)，其中，所述正反档模块(1)具有一上至下讯号输入端口(U2D)与一下至上讯号输入端口(D2U)，所述正反档模块(1)依所述上至下讯号输入端口(U2D)及所述下至上讯号输入端口(D2U)的讯号来控制所述复数个移位寄存器(10, 11, …, 1n)的扫描顺序；其中所述同步模块(2)用以导通所述低电位线(VGL)与所述上至下讯号输入端口(U2D)及所述下至上讯号输入端口(D2U)之中电位较低者。

Description

液晶面板及其栅极驱动电路 技术领域
本揭示涉及驱动电路领域，特别涉及一种液晶面板的栅极驱动电路。
 背景技术
目前，液晶显示装置作为电子设备的显示部件已经广泛的应用于各种电子产品中，而阵列基板行扫描驱动(Gate Driver On Array, GOA)电路是液晶显示装置中的一个重要组成部分。GOA是利用现有液晶显示器的薄膜晶体管制程将栅极行扫描驱动信号电路制作在阵列基板上，实现对画素阵列栅极逐行扫描的驱动方式。图1、2为一种现有的阵列基板行扫描驱动电路，图3为图2电路的时序示意图。
在现有的GOA电路中，可以分为N沟道金属氧化物半导体(N-MOS)电路、P沟道金属氧化物半导体(P-MOS)电路以及互补型金属氧化半导体(CMOS)电路。由于NMOS电路相比于CMOS电路由于省去P掺杂这一工序及光罩，对于提高良率以及降低成本都大有裨益。
与CMOS GOA驱动电路相比，NMOS或PMOS的单型GOA驱动电路稳定性容易受到显示区域的干扰，尤其在重载画面（Pixel点反转等画面），容易导致GOA驱动电路失效，尤其是中大尺寸横屏。
专利编号CN105261343B公开了一种GOA驱动电路，设置有多级GOA驱动模块，每级GOA驱动模块包括：第一驱动单元，用于在行扫描期间输出行扫描信号；第二驱动单元，其输出端与所述第一驱动单元的输出端耦接，用于在行扫描期间维持输出端的输出信号，以及在触控扫描期间输出与触控扫描信号对应的扫描信号；唤醒驱动单元，用于在黑屏唤醒时使各级驱动模块同时输出有效的行信号。该GOA驱动电路能够有效地消除电路中存在的不稳定因素，降低电路功能失效的风险。但并无法解决单型GOA稳定性容易受到显示区域的干扰，尤其在重载画面（Pixel点反转等画面），容易导致GOA失效的问题。
因此，目前亟需一种显示面板以解决上述问题。
 技术问题
现有的GOA扫描电路无法解决单型GOA稳定性容易受到显示区域的干扰，尤其在重载画面（Pixel点反转等画面），容易导致GOA失效的问题。
 技术解决方案
为解决上述技术问题，本揭示提供一种液晶面板的栅极驱动电路，包括：复数个移位寄存器。每一个所述移位寄存器包括：一正反档模块、一低电位线及一同步模块。所述正反档模块具有一上至下讯号输入端口与一下至上讯号输入端口。所述正反档模块依所述上至下讯号输入端口及所述下至上讯号输入端口的讯号来控制所述复数个移位寄存器的扫描顺序。所述同步模块用以导通所述低电位线与所述上至下讯号输入端口及所述下至上讯号输入端口之中电位较低者。其中每一个所述移位寄存器还包括：一栅极讯号端口、一上拉模块、一上拉开关、一下拉模块、及一下拉开关。其中，所述上拉模块, 用以接收上一级的所述移位寄存器的一栅极讯号并产生一上拉讯号。所述上拉开关, 连接至所述上拉模块及所述栅极讯号端口用以接收所述上拉讯号及一时钟信号, 并用以依所述上拉讯号将所述时钟信号送至所述栅极讯号端口。所述下拉模块, 用以接收下一级的所述移位寄存器的一栅极讯号并产生一下拉讯号。所述下拉开关, 连接至所述下拉模块、所述栅极讯号端口及所述低电位线用以接收所述下拉讯号, 并用以依所述下拉讯号将所述栅极讯号端口与所述低电位线导通。所述正反档模块连接至所述上拉模块与所述下拉模块并用以依所述上至下讯号输入端口及所述下至上讯号输入端口的讯号来控制所述上拉模块与所述下拉模块。
于本揭示其中的一实施例的液晶面板的栅极驱动电路，其中所述同步模块具有一第一薄膜晶体管及一第二薄膜晶体管,其中所述第一薄膜晶体管的一栅极连接至所述上至下讯号输入端口，一源极连接至所述低电位线，一漏极连接至所述下至上讯号输入端口，所述第二薄膜晶体管的一栅极连接至所述下至上讯号输入端口，一源极连接至所述上至下讯号输入端口，一漏极连接至所述低电位线。
于本揭示其中的一实施例的液晶面板的栅极驱动电路，更包括一全关模块连接至所述栅极讯号端口及所述低电位线。
于本揭示其中的一实施例的液晶面板的栅极驱动电路，更包括一全开模块连接至所述栅极讯号端口、所述下拉开关及所述低电位线。
于本揭示其中的一实施例的液晶面板的栅极驱动电路是一种阵列基板行扫描驱动(Gate Driver On Array, GOA)电路。
于本揭示其中的一实施例的液晶面板的栅极驱动电路，其中，所述第一薄膜晶体管及所述第二薄膜晶体管均为N沟道金属氧化物半导体。
本揭示还提出了一种液晶面板的栅极驱动电路，包括：复数个移位寄存器。每一个所述移位寄存器包括：一正反档模块、一低电位线及一同步模块。所述正反档模块具有一上至下讯号输入端口与一下至上讯号输入端口。所述正反档模块依所述上至下讯号输入端口及所述下至上讯号输入端口的讯号来控制所述复数个移位寄存器的扫描顺序。所述同步模块用以导通所述低电位线与所述上至下讯号输入端口及所述下至上讯号输入端口之中电位较低者。
于本揭示其中的一实施例的液晶面板的栅极驱动电路，其中每一个所述移位寄存器还包括：一栅极讯号端口、一上拉模块、一上拉开关、一下拉模块、及一下拉开关。其中，所述上拉模块, 用以接收上一级的所述移位寄存器的一栅极讯号并产生一上拉讯号。所述上拉开关, 连接至所述上拉模块及所述栅极讯号端口用以接收所述上拉讯号及一时钟信号, 并用以依所述上拉讯号将所述时钟信号送至所述栅极讯号端口。所述下拉模块, 用以接收下一级的所述移位寄存器的一栅极讯号并产生一下拉讯号。所述下拉开关, 连接至所述下拉模块、所述栅极讯号端口及所述低电位线用以接收所述下拉讯号, 并用以依所述下拉讯号将所述栅极讯号端口与所述低电位线导通。所述正反档模块连接至所述上拉模块与所述下拉模块并用以依所述上至下讯号输入端口及所述下至上讯号输入端口的讯号来控制所述上拉模块与所述下拉模块。
于本揭示其中的一实施例的液晶面板的栅极驱动电路，其中所述同步模块具有一第一薄膜晶体管及一第二薄膜晶体管,其中所述第一薄膜晶体管的一栅极连接至所述上至下讯号输入端口，一源极连接至所述低电位线，一漏极连接至所述下至上讯号输入端口，所述第二薄膜晶体管的一栅极连接至所述下至上讯号输入端口，一源极连接至所述上至下讯号输入端口，一漏极连接至所述低电位线。
于本揭示其中的一实施例的液晶面板的栅极驱动电路，更包括一全关模块连接至所述栅极讯号端口及所述低电位线。
于本揭示其中的一实施例的液晶面板的栅极驱动电路，更包括一全开模块连接至所述栅极讯号端口、所述下拉开关及所述低电位线。
于本揭示其中的一实施例的液晶面板的栅极驱动电路是一种阵列基板行扫描驱动(Gate Driver On Array, GOA)电路。
于本揭示其中的一实施例的液晶面板的栅极驱动电路，其中，所述第一薄膜晶体管及所述第二薄膜晶体管均为N沟道金属氧化物半导体。
本揭示还提出了一种液晶面板包括：一基板、一画素阵列、一栅极驱动电路、及一时钟信号产生器，其中，所述画素阵列、所述栅极驱动电路、及所述时钟信号产生器均设置于所述基板上，所述栅极驱动电路用以驱动所述画素阵列，所述时钟信号产生器用以提供一时钟信号给所述栅极驱动电路，所述栅极驱动电路包括：复数个移位寄存器。其中每一个所述移位寄存器包括：一正反档模块、一低电位线及一同步模块。其中，所述正反档模块具有一上至下讯号输入端口与一下至上讯号输入端口, 所述正反档模块依所述上至下讯号输入端口及所述下至上讯号输入端口的讯号来控制所述复数个移位寄存器的扫描顺序。所述同步模块用以导通所述低电位线与所述上至下讯号输入端口及所述下至上讯号输入端口之中电位较低者。
于本揭示其中的一实施例的液晶面板，其中每一个所述移位寄存器还包括：一栅极讯号端口、一上拉模块、一上拉开关、一下拉模块、及一下拉开关。其中，所述上拉模块, 用以接收上一级的所述移位寄存器的一栅极讯号并产生一上拉讯号。所述上拉开关, 连接至所述上拉模块、所述栅极讯号端口及所述时钟信号产生器用以接收所述上拉讯号及所述时钟信号, 并用以依所述上拉讯号将所述时钟信号送至所述栅极讯号端口。所述下拉模块, 用以接收下一级的所述移位寄存器的一栅极讯号并产生一下拉讯号。所述下拉开关, 连接至所述下拉模块、所述栅极讯号端口及所述低电位线用以接收所述下拉讯号, 并用以依所述下拉讯号将所述栅极讯号端口与所述低电位线导通。所述正反档模块连接至所述上拉模块与所述下拉模块并用以依所述上至下讯号输入端口及所述下至上讯号输入端口的讯号来控制所述上拉模块与所述下拉模块。
于本揭示其中的一实施例的液晶面板，其中所述同步模块具有一第一薄膜晶体管及一第二薄膜晶体管,其中所述第一薄膜晶体管的一栅极连接至所述上至下讯号输入端口，一源极连接至所述低电位线，一漏极连接至所述下至上讯号输入端口，所述第二薄膜晶体管的一栅极连接至所述下至上讯号输入端口，一源极连接至所述上至下讯号输入端口，一漏极连接至所述低电位线。
于本揭示其中的一实施例的液晶面板，更包括一全关模块连接至所述栅极讯号端口及所述低电位线。
于本揭示其中的一实施例的液晶面板，更包括一全开模块连接至所述栅极讯号端口、所述下拉开关及所述低电位线。
于本揭示其中的一实施例的液晶面板，其中，所述液晶面板的栅极驱动电路是一种阵列基板行扫描驱动(Gate Driver On Array, GOA)电路。
于本揭示其中的一实施例的液晶面板，其中，所述液晶面板的所述栅极驱动电路的所述第一薄膜晶体管及所述第二薄膜晶体管均为N沟道金属氧化物半导体。
 有益效果
相较于现有技术，为解决上述技术问题，本揭示提供一种单型GOA驱动电路，实现画素阵列薄膜晶体管的栅极逐行打开功能。本揭示通过同步模块，提高重载画面下单型GOA驱动电路功能的稳定性。本揭示通过实现下至上讯号输入端口与低电位线扰动同步或上至下讯号输入端口与低电位线扰动同步的目的，避免栅极驱动电路稳定性受到显示区域的干扰，降低栅极驱动电路重载失效的风险。
 附图说明
图1为现有技术的一种栅极行扫描驱动电路的电路图；
图2为现有技术的一种4时钟信号的栅极行扫描驱动电路的电路图；
图3为图2电路的时序示意图；
图4为本揭示栅极驱动电路的结构方块图；
图5为本揭示栅极驱动电路的一种移位寄存器的实施例的电路图；及
图6为本揭示液晶面板的一种实施例的示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本揭示可用以实施的特定实施例。
为了让本揭示的上述及其他目的、特征、优点能更明显易懂，下文将特举本揭示优选实施例，并配合所附图式，作详细说明如下。再者，本揭示所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧层、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。
在图中，结构相似的单元是以相同标号表示。
请参阅图4，图4为本揭示栅极驱动电路的结构方块图。
在本揭示的一种实施例中，提供一种液晶面板的栅极驱动电路100，包括：复数个移位寄存器10、11、…1n。以移位寄存器11为例，每一个所述移位寄存器包括：一正反档模块1、一低电位线VGL及一同步模块2。所述正反档模块1具有一上至下讯号输入端口U2D与一下至上讯号输入端口D2U。所述正反档模块1依所述上至下讯号输入端口U2D及所述下至上讯号输入端口D2U的讯号来控制所述复数个移位寄存器10、11、…1n的扫描顺序。所述同步模块2用以导通所述低电位线VGL与所述上至下讯号输入端口U2D及所述下至上讯号输入端口D2U之中电位较低者。
本揭示的一种实施例的液晶面板的栅极驱动电路，以移位寄存器11为例，其中每一个所述移位寄存器还包括：一栅极讯号端口G1、一上拉模块3、一上拉开关SU、一下拉模块4、及一下拉开关SD。其中，所述上拉模块3, 用以接收上一级的所述移位寄存器10的一栅极讯号G0S并产生一上拉讯号。所述上拉开关SU, 连接至所述上拉模块3及所述栅极讯号端口G1用以接收所述上拉讯号及一时钟信号CK1, 并用以依所述上拉讯号将所述时钟信号CK1送至所述栅极讯号端口G1。所述下拉模块4, 用以接收下一级的所述移位寄存器12的一栅极讯号G2S并产生一下拉讯号。所述下拉开关SD, 连接至所述下拉模块4、所述栅极讯号端口G1及所述低电位线VGL用以接收所述下拉讯号, 并用以依所述下拉讯号将所述栅极讯号端口G1与所述低电位线VGL导通。所述正反档模块1连接至所述上拉模块3与所述下拉模块4,并用以依所述上至下讯号输入端口U2D及所述下至上讯号输入端口D2U的讯号来控制所述上拉模块3与所述下拉模块4。
图4、图5所绘示的栅极驱动电路的基本组件仅为本揭示的实施例，本揭示不限于此。所述移位寄存器的电路还可以使用隔行扫描驱动方式( Interlace)或双边数组基板行驱动电路(Bilateral array substrate line driving circuit)等其他方式。图5所绘示的4时钟脉冲栅极驱动电路也可以适应性调整电路架构为6时钟脉冲驱动电路或8时钟脉冲驱动电路，本揭示不限于此。
请参阅图5，图5为本揭示栅极驱动电路的一种移位寄存器的实施例的电路图。本揭示的一种实施例的液晶面板的栅极驱动电路，以移位寄存器11为例，其中所述同步模块2具有一第一薄膜晶体管NT3-1及一第二薄膜晶体管NT4-1,其中所述第一薄膜晶体管NT3-1的栅极连接至所述上至下讯号输入端口U2D，源极连接至所述低电位线VGL，漏极连接至所述下至上讯号输入端口D2U。所述第二薄膜晶体管NT4-1的栅极连接至所述下至上讯号输入端口D2U，源极连接至所述上至下讯号输入端口U2D，漏极连接至所述低电位线VGL。
本揭示的一种实施例的液晶面板的栅极驱动电路的移位寄存器，以移位寄存器11为例，更包括一全关模块AGF连接至所述栅极讯号端口G1及所述低电位线VGL。
本揭示的一种实施例的液晶面板的栅极驱动电路的移位寄存器，以移位寄存器11为例，更包括一全开模块AGO连接至所述栅极讯号端口G1、所述下拉开关SD(NT10)及所述低电位线VGL。
本揭示的一种实施例的液晶面板的栅极驱动电路是一种阵列基板行扫描驱动(Gate Driver On Array, GOA)电路。
本揭示的一种实施例的液晶面板的栅极驱动电路，其中，所述第一薄膜晶体管及所述第二薄膜晶体管均为N沟道金属氧化物半导体。
根据本揭示的另一个方面，还提供了一种液晶面板。
请参阅图6及图4。图6为本揭示液晶面板的一种实施例的示意图。本揭示的一种液晶面板200的实施例包括：一基板210、一画素阵列220、一栅极驱动电路100、及一时钟信号产生器230，其中，所述画素阵列220、所述栅极驱动电路100、及所述时钟信号产生器230均设置于所述基板100上。所述栅极驱动电路100用以驱动所述画素阵列220。所述时钟信号产生器230用以提供时钟信号给所述栅极驱动电路100。所述栅极驱动电路100包括：复数个移位寄存器10、11、…1n。以移位寄存器11为例，其中每一个所述移位寄存器包括：一正反档模块1、一低电位线VGL及一同步模块2。其中，所述正反档模块1具有一上至下讯号输入端口U2D与一下至上讯号输入端口D2U, 所述正反档模块1依所述上至下讯号输入端口U2D及所述下至上讯号输入端口D2U的讯号来控制所述复数个移位寄存器10、11、…1n的扫描顺序。所述同步模块2用以导通所述低电位线VGL与所述上至下讯号输入端口U2D及所述下至上讯号输入端口D2U之中电位较低者。
请参阅图5,所述上拉开关SU包括一薄膜晶体管NT9，所述下拉开关SD包括薄膜晶体管NT5、NT10。薄膜晶体管NT5用以关闭所述薄膜晶体管NT9。薄膜晶体管NT10用以将所述栅极讯号端口G1的电压准位拉至与低电位线VGL的电压准位相同。
所述正反档模块1的一实施例包括三个薄膜晶体管NT3、NT4、及NT8，其中，薄膜晶体管NT3的栅极连接上至下讯号输入端口U2D，源极连接至时钟信号CK3，薄膜晶体管NT4的栅极连接下至上讯号输入端口D2U，源极连接至时钟信号CK0。薄膜晶体管NT3、NT4的漏极均连接至薄膜晶体管NT8的栅极。薄膜晶体管NT8的源极连接至高电位线VGH，漏极连接至下拉开关SD的薄膜晶体管NT5、NT10以控制薄膜晶体管NT5及NT10。
上拉模块3包括一薄膜晶体管NT1，下拉模块4包括薄膜晶体管NT2及NT6。
全关模块AGF包括薄膜晶体管NT14，薄膜晶体管NT14的源极连接至所述栅极讯号端口G1，薄膜晶体管NT14的漏极连接至所述低电位线VGL。
全开模块AGO包括薄膜晶体管NT11及薄膜晶体管NT12，薄膜晶体管NT11的漏极连接至所述栅极讯号端口G1，薄膜晶体管NT12的源极连接至所述下拉开关SD，薄膜晶体管NT12的漏极连接至所述低电位线VGL。
在正档扫描模式时，上至下讯号输入端口U2D的电位为高(High)，下至上讯号输入端口D2U的电位为低(Low)，因此，同步模块2中的第一薄膜晶体管NT3-1为开启的状态，下至上讯号输入端口D2U与低电位线VGL透过第一薄膜晶体管NT3-1导通，实现下至上讯号输入端口D2U与低电位线VGL扰动同步。降低阵列基板行扫描驱动(GOA)电路重载失效的风险。
在反档扫描模式时，上至下讯号输入端口U2D的电位为低(Low)，下至上讯号输入端口D2U的电位为高(High)，因此，同步模块2中的第二薄膜晶体管NT4-1为开启的状态，上至下讯号输入端口U2D与低电位线VGL透过第二薄膜晶体管NT4-1导通，实现上至下讯号输入端口U2D与低电位线VGL扰动同步。降低阵列基板行扫描驱动(GOA)电路重载失效的风险。
在重载画面下，显示区的画素阵列通过薄膜晶体管NT10与低电位线VGL相连，低电位线VGL受显示区讯号的耦和(Couple)的影响最大。低电位线VGL相对于下至上讯号输入端口D2U，有更大的波动，所以虽然低电位线VGL与下至上讯号输入端口D2U电压理论上相同，但是实际上存在低电位线VGL受显示区讯号的耦和影响使得低电位线VGL瞬间电压高于下至上讯号输入端口D2U，那么对于下拉模块4中的薄膜晶体管NT2，其栅极与下一级移位寄存器的栅极讯号端口G2相连，而下一级移位寄存器在这一级的移位寄存器开启时，应该保持关闭，因此，其栅极讯号端口G2是通过其薄膜晶体管NT10与低电位线VGL相连。当低电位线VGL瞬间电压有扰动时，本级的薄膜晶体管NT2便有被瞬间打开的风险。若薄膜晶体管NT2打开，则Q点电位有被释放的风险，而不能保持其高(high)电位。本级移位寄存器开启时，Q点应保持其高(high)电位而使上拉开关SU的薄膜晶体管NT9开启，从而实现正常的级传功能。若Q点电位被释放，则会导致薄膜晶体管NT9关闭，引起GOA功能失效。
有益效果：本揭示设计的一种单型GOA驱动电路，实现画素阵列薄膜晶体管的栅极逐行打开功能。本揭示通过同步模块，提高重载画面下单型GOA驱动电路功能的稳定性。本揭示通过实现下至上讯号输入端口与低电位线扰动同步或上至下讯号输入端口与低电位线扰动同步的目的，避免栅极驱动电路稳定性容易受到显示区域的干扰，降低栅极驱动电路重载失效的风险。
尽管已经相对于一个或多个实现方式示出并描述了本揭示，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本揭示包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
以上仅是本揭示的优选实施方式，应当指出，对于本领域普通技术人员，在不脱离本揭示原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本揭示的保护范围。

Claims (20)

  1. 一种液晶面板的栅极驱动电路，包括：
    复数个移位寄存器，其中每一个所述移位寄存器包括：
    一正反档模块、一低电位线及一同步模块，其中
    所述正反档模块具有一上至下讯号输入端口与一下至上讯号输入端口, 所述正反档模块依所述上至下讯号输入端口及所述下至上讯号输入端口的讯号来控制所述复数个移位寄存器的扫描顺序；其中
    所述同步模块用以导通所述低电位线与所述上至下讯号输入端口及所述下至上讯号输入端口之中电位较低者;
    其中每一个所述移位寄存器还包括：一栅极讯号端口、一上拉模块、一上拉开关、一下拉模块、及一下拉开关，其中
    所述上拉模块, 用以接收上一级的所述移位寄存器的一栅极讯号并产生一上拉讯号；
    所述上拉开关, 连接至所述上拉模块及所述栅极讯号端口用以接收所述上拉讯号及一时钟信号, 并用以依所述上拉讯号将所述时钟信号送至所述栅极讯号端口；
    所述下拉模块, 用以接收下一级的所述移位寄存器的一栅极讯号并产生一下拉讯号；
    所述下拉开关, 连接至所述下拉模块、所述栅极讯号端口及所述低电位线用以接收所述下拉讯号, 并用以依所述下拉讯号将所述栅极讯号端口与所述低电位线导通；
    所述正反档模块连接至所述上拉模块与所述下拉模块并用以依所述上至下讯号输入端口及所述下至上讯号输入端口的讯号来控制所述上拉模块与所述下拉模块。
  2. 根据权利要求1所述的栅极驱动电路，其中所述同步模块具有一第一薄膜晶体管及一第二薄膜晶体管,其中所述第一薄膜晶体管的一栅极连接至所述上至下讯号输入端口，一源极连接至所述低电位线，一漏极连接至所述下至上讯号输入端口，所述第二薄膜晶体管的一栅极连接至所述下至上讯号输入端口，一源极连接至所述上至下讯号输入端口，一漏极连接至所述低电位线。
  3. 根据权利要求2所述的栅极驱动电路，其中更包括一全关模块连接至所述栅极讯号端口及所述低电位线。
  4. 根据权利要求2所述的栅极驱动电路，其中更包括一全开模块连接至所述栅极讯号端口、所述下拉开关及所述低电位线。
  5. 根据权利要求1所述的栅极驱动电路，其中所述液晶面板的栅极驱动电路是一种阵列基板行扫描驱动(Gate Driver On Array, GOA)电路。
  6. 根据权利要求1所述的栅极驱动电路，其中，所述第一薄膜晶体管及所述第二薄膜晶体管均为N沟道金属氧化物半导体。
  7. 一种液晶面板的栅极驱动电路，包括：
    复数个移位寄存器，其中每一个所述移位寄存器包括：
    一正反档模块、一低电位线及一同步模块，其中，
    所述正反档模块具有一上至下讯号输入端口与一下至上讯号输入端口, 所述正反档模块依所述上至下讯号输入端口及所述下至上讯号输入端口的讯号来控制所述复数个移位寄存器的扫描顺序；其中
    所述同步模块用以导通所述低电位线与所述上至下讯号输入端口及所述下至上讯号输入端口之中电位较低者。
  8. 根据权利要求7所述的栅极驱动电路，其中每一个所述移位寄存器还包括：一栅极讯号端口、一上拉模块、一上拉开关、一下拉模块、及一下拉开关，其中，
    所述上拉模块, 用以接收上一级的所述移位寄存器的一栅极讯号并产生一上拉讯号；
    所述上拉开关, 连接至所述上拉模块及所述栅极讯号端口用以接收所述上拉讯号及一时钟信号, 并用以依所述上拉讯号将所述时钟信号送至所述栅极讯号端口；
    所述下拉模块, 用以接收下一级的所述移位寄存器的一栅极讯号并产生一下拉讯号；
    所述下拉开关, 连接至所述下拉模块、所述栅极讯号端口及所述低电位线用以接收所述下拉讯号, 并用以依所述下拉讯号将所述栅极讯号端口与所述低电位线导通；
    所述正反档模块连接至所述上拉模块与所述下拉模块并用以依所述上至下讯号输入端口及所述下至上讯号输入端口的讯号来控制所述上拉模块与所述下拉模块。
  9. 根据权利要求7所述的栅极驱动电路，其中所述同步模块具有一第一薄膜晶体管及一第二薄膜晶体管,其中所述第一薄膜晶体管的一栅极连接至所述上至下讯号输入端口，一源极连接至所述低电位线，一漏极连接至所述下至上讯号输入端口，所述第二薄膜晶体管的一栅极连接至所述下至上讯号输入端口，一源极连接至所述上至下讯号输入端口，一漏极连接至所述低电位线。
  10. 根据权利要求9所述的栅极驱动电路，其中更包括一全关模块连接至所述栅极讯号端口及所述低电位线。
  11. 根据权利要求9所述的栅极驱动电路，其中更包括一全开模块连接至所述栅极讯号端口、所述下拉开关及所述低电位线。
  12. 根据权利要求7所述的栅极驱动电路，其中所述液晶面板的栅极驱动电路是一种阵列基板行扫描驱动(Gate Driver On Array, GOA)电路。
  13. 根据权利要求7所述的栅极驱动电路，其中，所述第一薄膜晶体管及所述第二薄膜晶体管均为N沟道金属氧化物半导体。
  14. 一种液晶面板包括：一基板、一画素阵列、一栅极驱动电路、及一时钟信号产生器，其中，所述画素阵列、所述栅极驱动电路、及所述时钟信号产生器均设置于所述基板上，所述栅极驱动电路用以驱动所述画素阵列，所述时钟信号产生器用以提供一时钟信号给所述栅极驱动电路，所述栅极驱动电路包括：
    复数个移位寄存器，其中每一个所述移位寄存器包括：
    一正反档模块、一低电位线及一同步模块，其中，
    所述正反档模块具有一上至下讯号输入端口与一下至上讯号输入端口, 所述正反档模块依所述上至下讯号输入端口及所述下至上讯号输入端口的讯号来控制所述复数个移位寄存器的扫描顺序；其中
    所述同步模块用以导通所述低电位线与所述上至下讯号输入端口及所述下至上讯号输入端口之中电位较低者。
  15. 根据权利要求14所述的液晶面板，其中每一个所述移位寄存器还包括：一栅极讯号端口、一上拉模块、一上拉开关、一下拉模块、及一下拉开关，其中，
    所述上拉模块, 用以接收上一级的所述移位寄存器的一栅极讯号并产生一上拉讯号；
    所述上拉开关, 连接至所述上拉模块、所述栅极讯号端口及所述时钟信号产生器用以接收所述上拉讯号及所述时钟信号, 并用以依所述上拉讯号将所述时钟信号送至所述栅极讯号端口；
    所述下拉模块, 用以接收下一级的所述移位寄存器的一栅极讯号并产生一下拉讯号；
    所述下拉开关, 连接至所述下拉模块、所述栅极讯号端口及所述低电位线用以接收所述下拉讯号, 并用以依所述下拉讯号将所述栅极讯号端口与所述低电位线导通；
    所述正反档模块连接至所述上拉模块与所述下拉模块并用以依所述上至下讯号输入端口及所述下至上讯号输入端口的讯号来控制所述上拉模块与所述下拉模块。
  16. 根据权利要求14所述的液晶面板，其中所述同步模块具有一第一薄膜晶体管及一第二薄膜晶体管,其中所述第一薄膜晶体管的一栅极连接至所述上至下讯号输入端口，一源极连接至所述低电位线，一漏极连接至所述下至上讯号输入端口，所述第二薄膜晶体管的一栅极连接至所述下至上讯号输入端口，一源极连接至所述上至下讯号输入端口，一漏极连接至所述低电位线。
  17. 根据权利要求17所述的液晶面板，其中更包括一全关模块连接至所述栅极讯号端口及所述低电位线。
  18. 根据权利要求17所述的液晶面板，其中更包括一全开模块连接至所述栅极讯号端口、所述下拉开关及所述低电位线。
  19. 根据权利要求14所述的栅极驱动电路，其中所述液晶面板的栅极驱动电路是一种阵列基板行扫描驱动(Gate Driver On Array, GOA)电路。
  20. 根据权利要求14所述的栅极驱动电路，其中，所述第一薄膜晶体管及所述第二薄膜晶体管均为N沟道金属氧化物半导体。
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