WO2020107534A1 - 显示面板驱动电路 - Google Patents

显示面板驱动电路 Download PDF

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Publication number
WO2020107534A1
WO2020107534A1 PCT/CN2018/120281 CN2018120281W WO2020107534A1 WO 2020107534 A1 WO2020107534 A1 WO 2020107534A1 CN 2018120281 W CN2018120281 W CN 2018120281W WO 2020107534 A1 WO2020107534 A1 WO 2020107534A1
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Prior art keywords
unit
pixel
field effect
switch
units
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Ceased
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PCT/CN2018/120281
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English (en)
French (fr)
Inventor
黄笑宇
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HKC Co Ltd
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HKC Co Ltd
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Publication date
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Priority to US17/273,317 priority Critical patent/US11410624B2/en
Publication of WO2020107534A1 publication Critical patent/WO2020107534A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
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    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Definitions

  • the present application relates to the field of display technology, and more specifically, to a display panel driving circuit.
  • the data in the thin film transistor liquid crystal display is processed by the timing controller and then output by the control circuit board.
  • the control circuit board is connected to the display panel through the source driving unit and the gate driving unit, respectively.
  • the source driving unit outputs a scan signal
  • the gate driving unit outputs a data signal.
  • the scan signal and the data signal jointly control the pixel unit on the display panel to display light and present an image.
  • the voltage applied to the pixel unit will be switched between positive and negative polarities.
  • the working process of the display panel is to continuously charge the pixel unit from positive polarity to negative polarity, and then from negative polarity to positive polarity, and the voltage of the pixel unit is reversed.
  • the load of the display panel also increases accordingly, resulting in a substantial increase in power consumption. Therefore, how to reduce the power consumption of the display panel has become an urgent problem to be solved.
  • the pixel unit array includes a plurality of pixel unit columns, and each of the pixel unit columns includes a plurality of pixel units connected in series.
  • the gate driving unit is connected to the pixel unit array to charge the pixel unit array.
  • Each pixel unit column is connected to the gate driving unit through one data signal line.
  • the switch control unit is respectively connected to each of the first switch unit and each of the second switch unit.
  • Each first switching unit is connected between the gate driving unit and one pixel unit column through one data signal line.
  • Each of the second switch units includes a first terminal and a second terminal, and the first terminal of each second switch unit is connected to one of the pixel unit columns through one data signal line, and the multiple The second ends of the second switching units are connected to each other.
  • the switch control unit controls the plurality of first switch units to be turned on, the gate driving unit charges the plurality of pixel unit columns through the plurality of data signal lines.
  • the plurality of first switch units are turned off, the plurality of second switch units are turned on, and the pixel unit charges in the plurality of pixel unit columns are neutralized.
  • the switch control unit further includes:
  • a resistor one end of the resistor is connected to the first switch unit and the second switch unit.
  • the trigger includes:
  • a reverse trigger the reverse trigger includes a first reverse input terminal, a second reverse input terminal, and a first reverse output terminal.
  • the first reverse input terminal is connected to the timing controller and receives timing control.
  • the second reverse input terminal is connected to the plurality of first switch units and the plurality of second switch units to obtain a voltage signal.
  • the first reverse output terminal is connected to the first switching unit and the second switching unit, and controls the on and off of the first switching unit and the second switching unit.
  • the first switching unit is a field effect transistor.
  • the gate of the field effect transistor of the first switching unit is connected to the output terminal of the flip-flop, and is used to receive the output voltage of the flip-flop.
  • the source of the field effect transistor of the first switching unit is connected to the gate driving unit through the data signal line, and the drain of the field effect transistor is connected to the pixel unit array through the data signal line Connected to charge the pixel unit.
  • the second switching unit is a field effect transistor.
  • the gate of the field effect transistor of the second switching unit is connected to the output terminal of the flip-flop, and is used to receive the output voltage of the flip-flop.
  • the drain of the field effect transistor is connected to the pixel unit array through the data signal line, and the source of the field effect transistor of the second switch unit is connected to each other to neutralize the plurality of pixel units The pixel cell charges in the column.
  • the field effect transistors of the plurality of first switch units are of the same type.
  • the field effect transistors of the plurality of second switch units are of the same type.
  • the field effect transistor of the first switching unit is different from the field effect transistor of the second switching unit.
  • a display panel driving circuit includes: a pixel unit array, a gate driving unit, a plurality of data signal lines, a timing controller, an inverter, a follow-up flip-flop, a plurality of first switching units and a plurality of second switching units.
  • the pixel unit array includes a plurality of pixel unit columns. Each pixel unit column includes a plurality of pixel units connected in series.
  • the gate driving unit is connected to the pixel unit array to charge the pixel unit array. Each pixel unit column is connected to the gate driving unit through one data signal line.
  • the following trigger includes a first input terminal, a second input terminal, and a first output terminal.
  • the first input terminal is connected to the timing controller and receives timing control.
  • the second input terminal is connected to the plurality of first switch units and the plurality of second switch units to obtain a voltage signal.
  • the first output terminal is connected to the first switching unit and the second switching unit through the inverter, and controls the on and off of the first switching unit and the second switching unit.
  • Each first switching unit is connected between the gate driving unit and one pixel unit column through one data signal line.
  • Each of the second switching units includes a first terminal and a second terminal. The first end of each second switch unit is connected to one pixel unit column through one data signal line. The second ends of the plurality of second switch units are connected to each other.
  • the gate driving unit charges the plurality of pixel unit columns through the plurality of data signal lines.
  • the plurality of second switch units are turned on, and the pixel unit charges in the plurality of pixel unit columns are neutralized.
  • the display panel driving circuit further includes a resistor, and one end of the resistor is connected to the first switch unit and the second switch unit.
  • the second switching unit is a field effect transistor.
  • the gate of the field effect transistor of the second switching unit is connected to the output terminal of the flip-flop, and is used to receive the output voltage of the flip-flop.
  • the drain of the field effect transistor is connected to the pixel unit array through the data signal line, and the source of the field effect transistor of the second switch unit is connected to each other to neutralize the plurality of pixel units The pixel cell charges in the column.
  • the field effect transistor of the first switching unit is different from the field effect transistor of the second switching unit.
  • the field effect transistor of the first switching unit is P-type
  • the field effect transistor of the second switching unit is N-type
  • the other end of the resistor is grounded.
  • Each first switching unit is connected between the gate driving unit and one pixel unit column through one data signal line.
  • Each of the second switch units includes a first terminal and a second terminal, and the first terminal of each second switch unit is connected to one of the pixel unit columns through one data signal line, and the multiple The second ends of the second switching units are connected to each other.
  • the switch control unit controls the plurality of first switch units to be turned on, the gate driving unit charges the plurality of pixel unit columns through the plurality of data signal lines.
  • the plurality of first switch units are turned off, the plurality of second switch units are turned on, and the pixel unit charges in the plurality of pixel unit columns are neutralized.
  • the switch control unit includes a timing controller and a trigger.
  • the input terminal of the trigger is connected to the timing controller, and the output terminal of the trigger is connected to the plurality of first switch units and the plurality of second switch units.
  • the display panel driving circuit includes: a pixel unit array, a plurality of data signal lines, a gate driving unit, a switching control unit, a plurality of first switching units and a plurality of second switching units.
  • the pixel unit array includes a plurality of pixel unit columns. Each pixel unit column includes a plurality of pixel units connected in series. Each pixel unit column is connected to the gate driving unit through one data signal line.
  • the switch control unit is respectively connected to each of the first switch unit and each of the second switch unit. When the switch control unit controls the plurality of first switch units to be turned on, the gate driving unit charges the plurality of pixel unit columns through the plurality of data signal lines.
  • the plurality of first switch units When the plurality of first switch units are turned off, the plurality of second switch units are turned on, and the pixel unit charges in the plurality of pixel unit columns are neutralized.
  • neutralizing the charge of the pixel unit it is possible to reduce the charging voltage difference required for the charge inversion of the pixel unit.
  • the voltage difference required for charging is reduced, the required charging time for the voltage inversion of the pixel unit is shortened, and the power consumption of the display panel is reduced.
  • FIG. 1 is a schematic structural diagram of a display panel driving circuit provided in an embodiment of this application.
  • FIG. 2 is a schematic structural diagram of a display panel driving circuit provided in another embodiment of this application.
  • FIG. 4 is a schematic structural diagram of a display panel provided in an embodiment of the present application.
  • Pixel cell column 210 Pixel cell column 210
  • the voltage applied to the liquid crystal is switched between positive and negative polarities.
  • the working process of the display panel is a process of continuously charging the pixel unit 220 from positive polarity to negative polarity, and then from negative polarity to positive polarity.
  • the gate driving unit 30 reads the data signal from the control panel.
  • the display panel driving circuit 10 controls the plurality of first switch units 90 to be turned off, the plurality of second switch units 100 to be turned on, and the pixel units 220 in the plurality of pixel unit columns 210 are neutralized in charge .
  • the neutralization of the charge of the pixel unit 220 the charging voltage difference required for the charge inversion of the pixel unit 220 is reduced.
  • the voltage difference required for charging is reduced, so that the charging time required for the pixel unit 220 to charge up is shortened, and the overall power consumption of the display panel is reduced.
  • the required charging time is shortened, the display efficiency of the display panel is improved.
  • the display area of the display panel is composed of a plurality of pixel units 220.
  • the pixel units 220 are arranged in an orderly array to form the pixel unit array 20.
  • the gate driving unit 30 transfers charge to the pixel unit column 210 through the plurality of data signal lines 40.
  • the charge on the pixel cell column 210 is the same, that is, the type of charge that the data signal line 40 delivers to the pixel cells 220 connected in series on a single pixel cell column 210 is the same.
  • the charges of the adjacent pixel cell columns 210 may be the same or different.
  • the pixel cell columns 210 in the pixel cell array 20 are arranged in the form of three positive and three negative.
  • each of the data signal lines 40 is connected in series with the first switching unit 90, and the first switching unit 90 can control the gate driving unit 30 and the pixel unit column 210 Is turned on or off, that is, to control whether the gate driving unit 30 charges the pixel unit column 210.
  • the gate driving unit 30 charges the pixel unit column 210; when the first switching unit 90 is turned off, the gate driving unit 30 stops charging The pixel cell column 210 is charged.
  • the pixel cell columns 210 in the pixel cell array 20 are arranged in the form of three positive and three negative, and each of the three positive data signal lines 40 may be connected to one of the first switching cells 90 is connected in series, and every three negative data signal lines 40 can be connected in series with another first switch unit 90, which can realize that the adjacent same-polarity pixel unit column 210 shares one first switch unit 90 Synchronization of charging with the same pole.
  • the charging period for charging the pixel unit array 20 by the gate driving unit 30 includes four time periods, and the four time periods include a first time period, a second time period, and a third time Period and the fourth time period.
  • the gate driving unit 30 negatively charges the n-th, n-th, and n-th pixel unit columns 210 through the data signal line 40, and the gate driving unit 30 Charge the n-th, n+1-th, and n+2th pixel cell columns 210 positively through the data signal line 40.
  • the gate driving unit 30 stops charging the pixel unit column 210 and starts reading data.
  • the process displayed by the display panel is a process realized by countless charging cycles.
  • each second switch unit 100 is connected to one pixel unit column 210 through one data signal line 40, and the second ends 102 of the plurality of second switch units 100 are connected to each other .
  • the second switch unit 100 is turned on, the pixel cell column 210 is turned on by the second off. Since the charges in all the pixel cell columns 210 are different, the positive and negative are arranged in order.
  • the electric charges in the pixel unit 220 move along the pixel unit columns 210, and are collected and neutralized.
  • the voltage of each pixel cell column 210 is neutralized, closer to the voltage to be inverted, the voltage difference is reduced, and the time for voltage inversion is also shortened, which improves the driving efficiency of the gate driving unit 30.
  • the switch control unit 50 includes a timing controller 60 and a trigger 70.
  • the input terminal of the flip-flop 70 is connected to the timing controller 60, and the output terminal of the flip-flop 70 is connected to the plurality of first switch units 90 and the plurality of second switch units 100.
  • the timing controller 60 can provide timing conversion, that is, provide high and low levels in different time periods. When the low level changes to a high level, a rising edge will be generated; when the high level changes to a low level, a falling edge will be generated.
  • the flip-flop 70 has a signal receiving terminal, a voltage input terminal and a voltage output terminal. The signal receiving end of the flip-flop 70 can receive the rising edge and the falling edge. Each time the signal receiving end of the flip-flop 70 receives the rising edge or the falling edge, the voltage input end of the flip-flop 70 will read the voltage once, and the voltage output end will be set internally Output the corresponding voltage. When the high-level and low-level output of the timing controller 60 are changed in an orderly manner, there will be rising and falling edges in order, and the voltage output terminal of the flip-flop 70 will realize the orderly change of the high-low level in order .
  • the voltage output terminal of the flip-flop 70 is connected to the control signal terminals of the plurality of first switch units 90 and the plurality of second switch units 100.
  • the voltage output terminal of the flip-flop 70 outputs a low level
  • the plurality of first switching units 90 are turned on
  • the plurality of second switching units 100 are turned off
  • the gate driving unit 30 gives the pixel unit Column 210 is charged.
  • the gate driving unit 30 stops for three phases Adjacent to the pixel cell column 210 is charged, all the pixel cell columns 210 are connected, and the electric charge in the pixel cell 220 moves along the pixel cell column 210 to be collected and neutralized.
  • the voltage of each pixel cell column 210 is neutralized, closer to the voltage to be inverted, the voltage difference is reduced, and the time for voltage inversion is also shortened, which improves the driving efficiency of the gate driving unit 30.
  • the control signal terminals of the first switch unit 90 and the second switch unit 100 are connected to the voltage output terminal of the flip-flop 70, and the voltage input terminal of the flip-flop 70 is connected to the first switch unit 90 and Between the control signal terminal of the second switch unit 100 and the voltage output terminal of the flip-flop 70.
  • One end of the resistor 80 is connected to the voltage output end of the trigger 70, and the other end is grounded.
  • a current flows through the resistor 80, a voltage difference is formed at both ends of the resistor 80. Since the other end of the resistor 80 is grounded, the pressure value at one end of the resistor 80 is applied to both ends of the resistor 80 Differential pressure value.
  • the voltage at the voltage output terminal of the trigger 70 is equal to the voltage difference across the resistor 80.
  • the resistor 80 can provide an initial voltage to the voltage input terminal of the flip-flop 70.
  • the flip-flop 70 includes a reverse flip-flop 710 including a first reverse input 711, a second reverse input 712, and a first reverse output 713.
  • the first reverse input terminal 711 is connected to the timing controller 60 and receives timing control
  • the second reverse input terminal 712 is connected to the plurality of first switch units 90 and the plurality of second switch units Connect 100 to get the voltage signal.
  • the first reverse output terminal 713 is connected to the first switching unit 90 and the second switching unit 100 to control the on and off of the first switching unit 90 and the second switching unit 100.
  • the reverse flip-flop 710 can realize voltage inversion, that is, when the second reverse input terminal 712 inputs a low level, the first reverse output terminal 713 outputs a high level; the second reverse input terminal 712 inputs a high voltage Normally, the first reverse output terminal 713 outputs a low level.
  • the first switch unit 90, the control signal terminal of the second switch unit 100, and the second reverse input terminal 712 are all low level.
  • the first switch unit 90 is turned on, and the second switch unit 100 is turned off.
  • the gate driving unit 30 charges the plurality of pixel unit columns 210 through the data signal line 40.
  • the timing controller 60 changes from low level to high level, a rising edge occurs.
  • the first inverting input terminal 711 receives the rising edge
  • the first inverting output terminal 713 receives the low level of the second inverting input terminal 712 and inverts to a high level output.
  • the first reverse output terminal 713 is connected to the first switching unit 90 and the second switching unit 100, and the control signal terminals of the plurality of first switching units 90 and the plurality of second switching units 100 High level received.
  • the plurality of first switch units 90 are turned off, and the plurality of second switch units 100 are turned on.
  • the gate driving unit 30 stops charging the pixel unit column 210, all the pixel unit columns 210 are connected, and the charges in the pixel unit 220 move along the pixel unit column 210, and are collected and neutralized.
  • the voltage of each pixel cell column 210 is neutralized, and the pixel cell 220 is 0V.
  • the timing controller 60 changes from high level to low level, a falling edge occurs.
  • the first inverting input terminal 711 receives the falling edge, and the first inverting output terminal 713 receives the high level of the second inverting input terminal 712 and inverts to a low level output.
  • the first reverse output terminal 713 is connected to the first switching unit 90 and the second switching unit 100, and the control signal terminals of the plurality of first switching units 90 and the plurality of second switching units 100 Low level received.
  • the plurality of first switch units 90 are turned on, and the plurality of second switch units 100 are turned off.
  • the gate driving unit 30 charges the pixel unit column 210, and the pixel unit 220 changes from 0V to a set voltage.
  • the flip-flop 70 includes an inverter 720 and a follow-up flip-flop 730.
  • the following trigger 730 includes a first input terminal 731, a second input terminal 732, and a first output terminal 733.
  • the first input terminal 731 is connected to the timing controller 60 and receives timing control.
  • the second input terminal 732 is connected to the plurality of first switch units 90 and the plurality of second switch units 100 to obtain a voltage signal.
  • the first output terminal 733 is connected to the first switching unit 90 and the second switching unit 100 through the inverter 720 to control the conduction of the first switching unit 90 and the second switching unit 100 On and off.
  • the first switch unit 90, the control signal terminal of the second switch unit 100, and the second reverse input terminal 712 are all low level.
  • the first input terminal 731 inputs a rising edge
  • the second input terminal 732 assigns a low level to the first input terminal 733
  • the first input terminal 733 sends a low level to the inverting ⁇ 720.
  • the inverter 720 outputs a high level.
  • the control signal terminals of the plurality of first switch units 90 and the plurality of second switch units 100 receive a high level.
  • the plurality of first switch units 90 are turned off, and the plurality of second switch units 100 are turned on.
  • the gate driving unit 30 stops charging the pixel unit column 210, all the pixel unit columns 210 are connected, and the charges in the pixel unit 220 move along the pixel unit column 210, and are collected and neutralized.
  • the voltage of each pixel cell column 210 is neutralized, and the voltage in the pixel cell 220 is 0V.
  • the plurality of first switching units 90 are field effect transistors, and the gate of the field effect transistor of the first switching unit 90 is connected to the output terminal of the flip-flop 70 for receiving The output voltage of the flip-flop 70 is described.
  • the source of the field effect transistor of the first switching unit 90 is connected to the gate driving unit 30 through the data signal line 40, and the drain of the field effect transistor is connected to the gate through the data signal line 40.
  • the pixel unit array 20 is connected to charge the pixel unit 220.
  • the second switching unit 100 is a field effect transistor, and the gate of the field effect transistor of the second switching unit 100 is connected to the output of the flip-flop 70 for receiving the flip-flop 70 output voltage.
  • the drain of the field effect transistor is connected to the pixel cell array 20 through the data signal line 40, and the source of the field effect transistor of the second switch unit 100 is connected to each other to neutralize the multiple The pixel cells 220 in each pixel cell column 210 are charged.
  • the second ends 102 of all the pixel unit columns 210 are connected, the charge of the electrode unit 220 is neutralized, and the voltage is 0V.
  • the gate of the N-type field effect transistor is at a low level, the N-type field effect transistor is turned off.
  • the second ends 102 of all the pixel cell columns 210 are turned off.
  • the gates of the P-type field effect transistor and the N-type field effect transistor and the second inverting input terminal 712 are all low level.
  • the first input terminal 731 inputs a rising edge
  • the second input terminal 732 assigns a low level to the first input terminal 733
  • the first input terminal 733 sends a low level to the inverting ⁇ 720.
  • the inverter 720 outputs a high level.
  • the gates of the plurality of P-type field effect transistors and the plurality of N-type field effect transistors receive a high level.
  • the plurality of P-type field effect transistors are turned off, and the plurality of N-type field effect transistors are turned on.
  • the gate driving unit 30 stops charging the pixel unit column 210, all the pixel unit columns 210 are connected, and the charges in the pixel unit 220 move along the pixel unit column 210, and are collected and neutralized.
  • the voltage of each pixel cell column 210 is neutralized, and the voltage in the pixel cell 220 is 0V.
  • the timing controller 60 changes from high level to low level, a falling edge occurs.
  • the first input terminal 731 receives the falling edge, and the first output terminal 733 receives the high level of the second input terminal 732 and outputs a high level.
  • the inverter 720 receives a high level and turns it into a low level output.
  • the first reverse output terminal 713 is connected to the P-type field effect transistor and the N-type field effect transistor, the gates of the plurality of P-type field effect transistors and the plurality of N-type field effect transistors The pole received a low level.
  • the plurality of P-type field effect transistors are turned on, and the plurality of N-type field effect transistors are turned off.
  • the gate driving unit 30 charges the pixel unit column 210, and the pixel unit 220 changes from 0V to a set voltage, which shortens the charging time and improves the page display efficiency.
  • the field effect transistor of the first switching unit 90 is N-type
  • the field effect transistor of the second switching unit 100 is P-type
  • the other end of the resistor 80 is at least Describe the threshold voltage of the field effect transistor. Since the initial voltage is the threshold voltage of the field effect transistor, it is a high level.
  • the control signal terminal of the N-type field effect transistor is at a high level, and the N-type field effect transistor is turned on; the control signal terminal of the P-type field effect transistor is at a high level, and the P-type field effect transistor is off Break.
  • the gate driving unit 30 charges the pixel unit column 210.
  • the timing controller 60 changes from low level to high level, a falling edge occurs.
  • the first input terminal 731 receives the falling edge, and the first output terminal 733 receives the low level of the second input terminal 732 and outputs a low level.
  • the inverter 720 receives a low level and turns it into a high level output.
  • the first reverse output terminal 713 is connected to the P-type field effect transistor and the P-type field effect transistor, and the control of the plurality of P-type field effect transistors and the plurality of P-type field effect transistors The signal terminal received a high level.
  • the plurality of P-type field effect transistors are turned on, and the plurality of P-type field effect transistors are turned off.
  • the gate driving unit 30 charges the pixel unit column 210, and the pixel unit 220 changes from 0V to a set voltage, which shortens the charging time and improves the page display efficiency.
  • L1 and L4 are the process curves of the voltage inversion of the pixel unit 220
  • L2 and L3 are the process curves of the voltage inversion of the pixel unit 220 of the present application.
  • the voltage difference of the pixel cell column 210 inversion is 2V
  • the time for the voltage inversion of L1 and L4 is from t2 to t4.
  • the voltage inversion process of the display panel driving circuit 10 is: at time t1, the timing controller 60 changes from low level to high level, and a rising edge occurs.
  • the second input terminal 732 assigns a low level to the first input terminal 733, and the first input terminal 733 sends a low level to the Inverter 720.
  • the inverter 720 outputs a high level.
  • the gates of the plurality of P-type field effect transistors and the plurality of N-type field effect transistors receive a high level.
  • the plurality of P-type field effect transistors are turned off, and the plurality of N-type field effect transistors are turned on.
  • the gate driving unit 30 stops charging the pixel unit column 210, and all the pixel unit columns 210 are connected.
  • the electric charge in the pixel unit 220 moves along the pixel unit column 210, and is collected and neutralized.
  • the pixel unit 220 achieves charge neutralization.
  • L2 and L3 are 0V.
  • the timing controller 60 changes from high level to low level, a falling edge occurs.
  • the first input terminal 731 receives the falling edge, and the first output terminal 733 receives the high level of the second input terminal 732 and outputs a high level.
  • the inverter 720 receives a high level and turns it into a low level output.
  • the first reverse output terminal 713 is connected to the P-type field effect transistor and the N-type field effect transistor, the gates of the plurality of P-type field effect transistors and the plurality of N-type field effect transistors The pole received a low level.
  • the plurality of P-type field effect transistors are turned on, and the plurality of N-type field effect transistors are turned off.
  • the gate driving unit 30 charges the pixel unit column 210, the pixel unit 220 becomes a set voltage within a time period from t2 to t3, and L2 and L3 change from 0V to a set voltage.
  • this application relates to a solution that shortens the time to realize voltage inversion by ⁇ t, shortens the charging time, and improves the page display efficiency.
  • a display panel 101 includes a display panel driving circuit 10.
  • the display panel driving circuit 10 includes: a pixel unit array 20, a gate driving unit 30, a plurality of data signal lines 40, a switching control unit 50, a plurality of first switching units 90, and a plurality of second switching units 100.
  • the pixel cell array 20 includes a plurality of pixel cell columns 210. Each pixel unit column 210 includes a plurality of pixel units 220 connected in series.
  • the gate driving unit 30 is connected to the pixel unit array 20, and the pixel unit array 20 is charged. Each pixel unit column 210 is connected to the gate driving unit 30 through one data signal line 40.
  • the switch control unit 50 is connected to each of the first switch unit 90 and each of the second switch unit 100 respectively.
  • Each first switching unit 90 is connected between the gate driving unit 30 and one pixel unit column 210 through one data signal line 40.
  • Each second switch unit 100 includes a first terminal 101 and a second terminal 102, and the first terminal 101 of each second switch unit 100 is connected to one pixel unit through one data signal line 40 The columns 210 are connected, and the second ends 102 of the plurality of second switch units 100 are connected to each other.
  • the switch control unit 50 controls the plurality of first switch units 90 to be turned on, the gate driving unit 30 charges the plurality of pixel unit columns 210 through the plurality of data signal lines 40.
  • the plurality of first switch units 90 are turned off, the plurality of second switch units 100 are turned on, and the pixel units 220 in the plurality of pixel unit columns 210 are neutralized in charge.
  • the switch control unit 50 includes a timing controller 60 and a trigger 70, an input terminal of the trigger 70 is connected to the timing controller 60, and an output terminal of the trigger 70 is connected to the plurality of first switching units 90 is connected to the plurality of second switching units 100.

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Abstract

一种显示面板驱动电路。显示面板驱动电路包括：像素单元阵列、多条数据信号线、栅极驱动单元、开关控制单元、多个第一开关单元和多个第二开关单元。每个像素单元列通过一条数据信号线与栅极驱动单元连接。开关控制单元分别与每个第一开关单元和每个第二开关单元连接。多个第一开关单元关断时，多个第二开关单元导通，多个像素单元列中的像素单元电荷中和。

Description

显示面板驱动电路
相关申请
本申请要求2018年11月29日申请的，申请号为201821985999.X，名称为“显示面板驱动电路”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及显示技术领域，更具体的说，涉及一种显示面板驱动电路。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
薄膜晶体管液晶显示器中数据经过时序控制器处理后，由控制电路板输出。控制电路板分别通过源级驱动单元和栅极驱动单元与显示面板连接。源级驱动单元输出扫描信号，栅极驱动单元输出数据信号。扫描信号和数据信号共同控制显示面板上的像素单元显示发光，呈现图像。
在液晶显示过程中，为了避免液晶极化，作用于像素单元上的电压会在正极性与负极性之间切换。显示面板的工作个过程是不断地将像素单元由正极性充电至负极性，再由负极性充电至正极性，像素单元的电压实现翻转。随着显示面板尺寸的不断增加，显示面板的负载也相应增加，导致功耗大幅上升。因此，如何降低显示面板的功耗成为亟待解决的问题。
申请内容
有鉴于此，本申请公开一种显示面板驱动电路，以实现随着显示面板尺寸的增加，降低显示面板的功耗。
一种显示面板驱动电路，包括：像素单元阵列、栅极驱动单元、多条数据 信号线、开关控制单元、多个第一开关单元和多个第二开关单元。
所述像素单元阵列包括多个像素单元列，每个所述像素单元列包括多个串联的像素单元。所述栅极驱动单元与所述像素单元阵列连接，为所述像素单元阵列充电。每个所述像素单元列通过一条所述数据信号线与所述栅极驱动单元连接。所述开关控制单元分别与每个所述第一开关单元和每个所述第二开关单元连接。
每个第一开关单元通过一条所述数据信号线连接于所述栅极驱动单元和一个所述像素单元列之间。每个所述第二开关单元包括第一端和第二端，每个所述第二开关单元的所述第一端通过一条所述数据信号线与一个所述像素单元列连接，所述多个第二开关单元的第二端相互连接。所述开关控制单元控制所述多个第一开关单元导通时，所述栅极驱动单元通过所述多条数据信号线给所述多个像素单元列充电。所述多个第一开关单元关断时，所述多个第二开关单元导通，所述多个像素单元列中的所述像素单元电荷中和。
在其中一个实施例中，所述开关控制单元包括时序控制器和触发器，所述触发器的输入端与所述时序控制器连接，所述触发器的输出端与所述多个第一开关单元和所述多个第二开关单元连接。
在其中一个实施例中，所述开关控制单元还包括：
电阻，所述电阻的一端与所述第一开关单元和所述第二开关单元连接。
在其中一个实施例中，所述触发器包括：
反向触发器，所述反向触发器包括第一反向输入端、第二反向输入端和第一反向输出端。所述第一反向输入端与所述时序控制器连接，接受时序控制。所述第二反向输入端与所述多个第一开关单元和所述多个第二开关单元连接，获取电压信号。所述第一反向输出端与所述第一开关单元和所述第二开关单元连接，控制所述第一开关单元和所述第二开关单元的导通和关断。
在其中一个实施例中，所述第一开关单元为场效应晶体管。所述第一开关单元的场效应晶体管的栅极与所述触发器的输出端连接，用于接收所述触发器的输出电压。所述第一开关单元的所述场效应晶体管的源极通过所述数据信号线与所述栅极驱动单元连接，所述场效应晶体管的漏极通过所述数据信号线与所述像素单元阵列连接，用于为所述像素单元充电。
在其中一个实施例中，所述第二开关单元为场效应晶体管。所述第二开关单元的场效应晶体管的栅极与所述触发器的输出端连接，用于接收所述触发器的输出电压。所述场效应晶体管的漏极通过所述数据信号线与所述像素单元阵列连接，所述第二开关单元的所述场效应晶体管的源极相互连接，用于中和所述多个像素单元列中的所述像素单元电荷。
在其中一个实施例中，多个所述第一开关单元的场效应晶体管的类型相同。
在其中一个实施例中，多个所述第二开关单元的场效应晶体管的类型相同。
在其中一个实施例中，所述第一开关单元的场效应晶体管与所述第二开关单元的场效应晶体管的类型不同。
一种显示面板驱动电路，包括：像素单元阵列、栅极驱动单元、多条数据信号线、时序控制器、反相器、跟随触发器、多个第一开关单元和多个第二开关单元。
所述像素单元阵列包括多个像素单元列。每个所述像素单元列包括多个串联的像素单元。所述栅极驱动单元与所述像素单元阵列连接，为所述像素单元阵列充电。每个所述像素单元列通过一条所述数据信号线与所述栅极驱动单元连接。
所述跟随触发器包括第一输入端、第二输入端和第一输出端。所述第一输入端与所述时序控制器连接，接受时序控制。所述第二输入端与所述多个第一开关单元和所述多个第二开关单元连接，获取电压信号。所述第一输出端通过所述反相器与所述第一开关单元和所述第二开关单元连接，控制所述第一开关单元和所述第二开关单元的导通和关断。
每个第一开关单元通过一条所述数据信号线连接于所述栅极驱动单元和一个所述像素单元列之间。每个所述第二开关单元包括第一端和第二端。每个所述第二开关单元的所述第一端通过一条所述数据信号线与一个所述像素单元列连接。所述多个第二开关单元的第二端相互连接。所述多个第一开关单元导通时，所述栅极驱动单元通过所述多条数据信号线给所述多个像素单元列充电。所述多个第一开关单元关断时，所述多个第二开关单元导通，所述多个像素单元列中的所述像素单元电荷中和。
在其中一个实施例中，所述显示面板驱动电路还包括电阻，所述电阻的一 端与所述第一开关单元和所述第二开关单元连接。
在其中一个实施例中，所述第一开关单元为场效应晶体管。所述第一开关单元的场效应晶体管的栅极与所述触发器的输出端连接，用于接收所述触发器的输出电压。所述第一开关单元的所述场效应晶体管的源极通过所述数据信号线与所述栅极驱动单元连接。所述场效应晶体管的漏极通过所述数据信号线与所述像素单元阵列连接，用于为所述像素单元充电。
在其中一个实施例中，所述第二开关单元为场效应晶体管。所述第二开关单元的场效应晶体管的栅极与所述触发器的输出端连接，用于接收所述触发器的输出电压。所述场效应晶体管的漏极通过所述数据信号线与所述像素单元阵列连接，所述第二开关单元的所述场效应晶体管的源极相互连接，用于中和所述多个像素单元列中的所述像素单元电荷。
在其中一个实施例中，多个所述第一开关单元的场效应晶体管的类型相同。
在其中一个实施例中，多个所述第二开关单元的场效应晶体管的类型相同。
在其中一个实施例中，所述第一开关单元的场效应晶体管与所述第二开关单元的场效应晶体管的类型不同。
在其中一个实施例中，所述第一开关单元的所述场效应晶体管为P型，所述第二开关单元的所述场效应晶体管为N型，所述电阻的另一端接地。
在其中一个实施例中，所述第一开关单元的所述场效应晶体管为N型，所述第二开关单元的所述场效应晶体管为P型，所述电阻的另一端为阈值电压。
一种显示面板，包括：显示面板驱动电路。所述显示面板驱动电路包括：包括：像素单元阵列、栅极驱动单元、多条数据信号线、开关控制单元、多个第一开关单元和多个第二开关单元。所述像素单元阵列包括多个像素单元列。每个所述像素单元列包括多个串联的像素单元。所述栅极驱动单元与所述像素单元阵列连接，为所述像素单元阵列充电每个所述像素单元列通过一条所述数据信号线与栅极驱动单元连接。所述开关控制单元分别与每个所述第一开关单元和每个所述第二开关单元连接。
每个第一开关单元通过一条所述数据信号线连接于所述栅极驱动单元和一个所述像素单元列之间。每个所述第二开关单元包括第一端和第二端，每个所述第二开关单元的所述第一端通过一条所述数据信号线与一个所述像素单元列 连接，所述多个第二开关单元的第二端相互连接。所述开关控制单元控制所述多个第一开关单元导通时，所述栅极驱动单元通过所述多条数据信号线给所述多个像素单元列充电。所述多个第一开关单元关断时，所述多个第二开关单元导通，所述多个像素单元列中的所述像素单元电荷中和。
在其中一个实施例中，所述开关控制单元包括时序控制器和触发器。所述触发器的输入端与所述时序控制器连接，所述触发器的输出端与所述多个第一开关单元和所述多个第二开关单元连接。
本申请提供的显示面板驱动电路，包括：像素单元阵列、多条数据信号线、栅极驱动单元、开关控制单元、多个第一开关单元和多个第二开关单元。所述像素单元阵列包括多个像素单元列。每个所述像素单元列包括多个串联的像素单元。每个所述像素单元列通过一条所述数据信号线与所述栅极驱动单元连接。所述开关控制单元分别与每个所述第一开关单元和每个所述第二开关单元连接。所述开关控制单元控制所述多个第一开关单元导通时，所述栅极驱动单元通过所述多条数据信号线给所述多个像素单元列充电。所述多个第一开关单元关断时，所述多个第二开关单元导通，所述多个像素单元列中的所述像素单元电荷中和。通过所述像素单元电荷中和，能够减小所述像素单元电荷翻转所需的充电压差。所需充电的压差减小，缩短了所述像素单元电压翻转的所需充电时间，降低显示面板的功耗。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据公开的附图获得其他的附图。
图1为本申请一个实施例中提供的显示面板驱动电路的结构示意图；
图2为本申请另一个实施例中提供的显示面板驱动电路的结构示意图；
图3为本申请一个实施例中提供的显示面板驱动电路的时间与电压关系图；
图4为本申请一个实施例中提供的显示面板的结构示意图。
附图标记
驱动电路          10
显示面板          101
像素单元阵列      20
像素单元列        210
像素单元          220
数据信号线        230
栅极驱动单元      40
开关控制单元      50
时序控制器        60
触发器            70
电阻              80
第一开关单元      90
第二开关单元      100
反向触发器        710
第一反向输入端    711
第二反向输入端    712
第一反向输出端    713
反相器            720
跟随触发器        730
第一输入端       731
第二输入端       732
第一输出端       733
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例公开了一种显示面板驱动电路，以实现随着显示面板尺寸的增加，降低显示面板的功耗。
请参见图1，申请一实施例提供一种显示面板驱动电路10，包括：像素单元阵列20、栅极驱动单元30、多条数据信号线40、开关控制单元50、多个第一开关单元90和多个第二开关单元100。所述像素单元阵列20包括多个像素单元列210。每个所述像素单元列210包括多个串联的像素单元220。所述栅极驱动单元30与所述像素单元阵列20连接，为所述像素单元阵列20充电每个所述像素单元列210通过一条所述数据信号线40与栅极驱动单元30连接。所述开关控制单元50分别与每个所述第一开关单元90和每个所述第二开关单元100连接。
每个第一开关单元90通过一条所述数据信号线40连接于所述栅极驱动单元30和一个所述像素单元列210之间。每个所述第二开关单元100包括第一端101和第二端102，每个所述第二开关单元100的所述第一端101通过一条所述数据信号线40与一个所述像素单元列210连接，所述多个第二开关单元100的第二端102相互连接。所述开关控制单元50控制所述多个第一开关单元90导通时，所述栅极驱动单元30通过所述多条数据信号线40给所述多个像素单元列210充电。所述多个第一开关单元90关断时，所述多个第二开关单元100导通，所述多个像素单元列210中的所述像素单元220电荷中和。
在液晶显示过程中，为了避免液晶极化，作用于液晶上的电压会在正极性 与负极性之间切换。显示面板的工作过程是不断地将像素单元220由正极性充电至负极性，再由负极性充电至正极性的过程。在所述像素单元220正负极翻转过程中，存在非充电时间。在这段非充电时间里，所述栅极驱动单元30从控制面板读取数据信号。所述显示面板驱动电路10控制所述多个第一开关单元90关断，所述多个第二开关单元100导通，所述多个像素单元列210中的所述像素单元220电荷中和。通过所述像素单元220电荷中和，减小所述像素单元220电荷翻转所需的充电压差。所需充电的压差减小，使得所述像素单元220电荷翻转的所需充电时间缩短，降低显示面板的整体功耗。同时，由于所需充电时间缩短，提高所述显示面板的显示效率。
所述显示面板的显示区域由多个所述像素单元220组成。所述像素单元220以阵列的形式有序排列，形成所述像素单元阵列20。所述栅极驱动单元30通过多条所述数据信号线40将电荷输送给所述像素单元列210。所述像素单元列210上的电荷相同，即所述数据信号线40输送给单个所述像素单元列210上串联的所述像素单元220的电荷种类相同。相邻所述像素单元列210的电荷可以相同，也可以不同。在一个实施例中，所述像素单元阵列20中的所述像素单元列210按照三正三负的形式排布。
在一个实施例中，每个所述数据信号线40上串联一个所述第一开关单元90，所述第一开关单元90能够控制所述栅极驱动单元30与所述像素单元列210之间的通断，即控制所述栅极驱动单元30是否给所述像素单元列210充电。当所述第一开关单元90导通时，所述栅极驱动单元30给所述像素单元列210充电；当所述第一开关单元90关断时，所述栅极驱动单元30停止给所述像素单元列210充电。在一个实施例中，所述像素单元阵列20中的所述像素单元列210按照三正三负的形式排布，每3个正极的所述数据信号线40上可以与一个所述第一开关单元90串联，每3个负极的所述数据信号线40可以与另一个所述第一开关单元90串联，能够实现相邻同极所述像素单元列210共用一个所述第一开关单元90，增加同极充电的同步性。
在一个实施例中，所述栅极驱动单元30为所述像素单元阵列20充电的充电周期包括四个时间段，所述四个时间段包括第一时间段、第二时间段、第三时间段和第四时间段。
当所述第一开关单元90导通时，所述栅极驱动单元30给三个相邻所述像素单元列210充电；当所述第一开关单元90关断时，所述栅极驱动单元30停止给三个相邻所述像素单元列210充电。在第一个时间段内，所述栅极驱动单元30通过所述数据信号线40为第n-3、n-2、n-1所述像素单元列210充正电，所述栅极驱动单元30通过所述数据信号线40为第n、n+1、n+2所述像素单元列210充负电。在第二个时间段内，所述栅极驱动单元30停止为所述像素单元列210充电，开始读取数据。在第三个时间段内，所述栅极驱动单元30通过所述数据信号线40为第n-3、n-2、n-1所述像素单元列210充负电，所述栅极驱动单元30通过所述数据信号线40为第n、n+1、n+2所述像素单元列210充正电。在第四个时间段内，所述栅极驱动单元30停止为所述像素单元列210充电，开始读取数据。所述显示面板显示的过程即为无数个充电周期实现的过程。
每个所述第二开关单元100的所述第一端101通过一条所述数据信号线40与一个所述像素单元列210连接，所述多个第二开关单元100的第二端102相互连接。当所述第二开关单元100导通时，所述像素单元列210通过第二断导通。由于全部所述像素单元列210中的电荷不相同，正负有序排列。当全部所述像素单元列210联通时，所述像素单元220中的电荷沿所述像素单元列210移动，汇集并中和。每个所述像素单元列210的电压被中和，更接近待翻转电压，电压差减小，电压翻转的时间也缩短，提高了所述栅极驱动单元30的驱动效率。
在一个实施例中，所述开关控制单元50包括时序控制器60和触发器70。所述触发器70的输入端与所述时序控制器60连接，所述触发器70的输出端与所述多个第一开关单元90和所述多个第二开关单元100连接。
所述时序控制器60能够提供时序变换，即在不同的时间段内提供高电平和低电平。所述低电平变化为高电平，会产生上升沿；所述高电平变化为低电平，会产生下升沿。所述触发器70具有信号接收端、电压输入端和电压输出端。所述触发器70的所述信号接收端能够接收所述上升沿和所述下降沿。所述触发器70的所述信号接收端每接收一次所述上升沿或所述下降沿，所述触发器70的所述电压输入端会读取一次电压，所述电压输出端会按照内部设置输出相应的电压。当所述时序控制器60输出的高电平和低电平有序变化时，会有序出现上升 沿和下降沿，所述触发器70的电压输出端会顺次实现高低电平的有序变化。
所述触发器70的电压输出端与所述多个第一开关单元90和所述多个第二开关单元100的控制信号端连接。所述触发器70的电压输出端输出低电平时，所述多个第一开关单元90导通，所述多个第二开关单元100关断，所述栅极驱动单元30给所述像素单元列210充电。所述触发器70的电压输出端输出高电平时，所述多个第一开关单元90关断，所述多个第二开关单元100导通，所述栅极驱动单元30停止给三个相邻所述像素单元列210充电，全部所述像素单元列210联通，所述像素单元220中的电荷沿所述像素单元列210移动，汇集并中和。每个所述像素单元列210的电压被中和，更接近待翻转电压，电压差减小，电压翻转的时间也缩短，提高了所述栅极驱动单元30的驱动效率。
在一个实施例中，所述开关控制单元50还包括电阻80。所述电阻80的一端与所述第一开关单元90和所述第二开关单元100连接。所述电阻80能够为所述触发器70的电压输入端提供初始电压。
所述第一开关单元90和所述第二开关单元100的控制信号端与所述触发器70的电压输出端连接，所述触发器70的电压输入端连接于所述第一开关单元90和所述第二开关单元100的控制信号端与所述触发器70的电压输出端之间。所述电阻80的一端与触发器70的电压输出端连接，另一端接地。当有电流通过所述电阻80时，所述电阻80的两端形成压差，由于所述电阻80的另一端接地，则所述电阻80的一端的压力值为施加在所述电阻80两端的压差值。所述触发器70的电压输出端的电压等于所述电阻80两端的压差值。所述电阻80能够为所述触发器70的电压输入端提供初始电压。
在一个实施例中，所述触发器70包括反向触发器710，所述反向触发器710包括第一反向输入端711、第二反向输入端712和第一反向输出端713。所述第一反向输入端711与所述时序控制器60连接，接受时序控制，所述第二反向输入端712与所述多个第一开关单元90和所述多个第二开关单元100连接，获取电压信号。所述第一反向输出端713与所述第一开关单元90和所述第二开关单元100连接，控制所述第一开关单元90和所述第二开关单元100的导通和关断。
所述反向触发器710能够实现电压翻转，即为第二反向输入端712输入低电平时，所述第一反向输出端713输出高电平；第二反向输入端712输入高电 平时，所述第一反向输出端713输出低电平。在一个实施例中，所述第一开关单元90、所述第二开关单元100的控制信号端和所述第二反向输入端712均为低电平。所述第一开关单元90导通，所述第二开关单元100关断。此时，所述栅极驱动单元30给通过所述数据信号线40给所述多个所述像素单元列210充电。当所述时序控制器60由低电平变为高电平时，出现上升沿。所述第一反向输入端711接收到所述上升沿，所述第一反向输出端713接收所述第二反向输入端712的低电平，并翻转为高电平输出。
所述第一反向输出端713与所述第一开关单元90和所述第二开关单元100连接，所述多个第一开关单元90和所述多个第二开关单元100的控制信号端接收到高电平。所述多个第一开关单元90关断，所述多个第二开关单元100导通。所述栅极驱动单元30停止给所述像素单元列210充电，全部所述像素单元列210联通，所述像素单元220中的电荷沿所述像素单元列210移动，汇集并中和。每个所述像素单元列210的电压被中和，所述像素单元220为0V。
当所述时序控制器60由高电平变为低电平时，出现下降沿。所述第一反向输入端711接收到所述下降沿，所述第一反向输出端713接收所述第二反向输入端712的高电平，并翻转为低电平输出。所述第一反向输出端713与所述第一开关单元90和所述第二开关单元100连接，所述多个第一开关单元90和所述多个第二开关单元100的控制信号端接收到低电平。所述多个第一开关单元90导通，所述多个第二开关单元100关断。所述栅极驱动单元30给所述像素单元列210充电，所述像素单元220由0V变为设定电压。
请一并参见图2，在一个实施例中，所述触发器70包括反相器720和跟随触发器730。所述跟随触发器730包括第一输入端731、第二输入端732和第一输出端733。所述第一输入端731与所述时序控制器60连接，接受时序控制。所述第二输入端732与所述多个第一开关单元90和所述多个第二开关单元100连接，获取电压信号。所述第一输出端733通过所述反相器720与所述第一开关单元90和所述第二开关单元100连接，控制所述第一开关单元90和所述第二开关单元100的导通和关断。
所述反相器720和所述跟随触发器730串联实现电压翻转。所述跟随触发器730的所述第二输入端732输入低电平时，所述第一输出端733输出低电平。 所述第二输入端732输入高电平时，所述第一输出端733输出高电平。所述反相器720能够实现电压翻转，即为输入低电平，输出高电平；输入高电平，输出低电平。所述跟随触发器730的所述第一输出端733与所述反相器720连接，实现电压的翻转。
在一个实施例中，所述第一开关单元90、所述第二开关单元100的控制信号端和所述第二反向输入端712均为低电平。第一输入端731输入上升沿时，所述第二输入端732将低电平赋给所述第一输入端733端，所述第一输入端733端将低电平输送给所述反相器720。所述反相器720将高电平输出。所述多个第一开关单元90和所述多个第二开关单元100的控制信号端接收到高电平。所述多个第一开关单元90关断，所述多个第二开关单元100导通。所述栅极驱动单元30停止给所述像素单元列210充电，全部所述像素单元列210联通，所述像素单元220中的电荷沿所述像素单元列210移动，汇集并中和。每个所述像素单元列210的电压被中和，所述像素单元220中的电压为0V。
当所述时序控制器60由高电平变为低电平时，出现下降沿。所述第一输入端731接收到所述下降沿，所述第一输出端733接收所述第二输入端732的高电平，并输出高电平。所述反相器720接收高电平，并翻转为低电平输出。所述第一反向输出端713与所述第一开关单元90和所述第二开关单元100连接，所述多个第一开关单元90和所述多个第二开关单元100的控制信号端接收到低电平。所述多个第一开关单元90导通，所述多个第二开关单元100关断。所述栅极驱动单元30给所述像素单元列210充电，所述像素单元220由0V变为设定电压。
在上一个实施例中，所述多个第一开关单元90为场效应晶体管，所述第一开关单元90的场效应晶体管的栅极与所述触发器70的输出端连接，用于接收所述触发器70的输出电压。所述第一开关单元90的所述场效应晶体管的源极通过所述数据信号线40与所述栅极驱动单元30连接，所述场效应晶体管的漏极通过所述数据信号线40与所述像素单元阵列20连接，用于为所述像素单元220充电。
在一个实施例中，所述第二开关单元100为场效应晶体管，所述第二开关单元100的场效应晶体管的栅极与所述触发器70的输出端连接，用于接收所述 触发器70的输出电压。所述场效应晶体管的漏极通过所述数据信号线40与所述像素单元阵列20连接，所述第二开关单元100的所述场效应晶体管的源极相互连接，用于中和所述多个像素单元列210中的所述像素单元220电荷。
在一个实施例中，多个所述第一开关单元90的场效应晶体管的类型相同，多个所述第二开关单元100的场效应晶体管的类型相同，且与所述第一开关单元90的场效应晶体管的类型不同。
在上一个实施例中，所述第一开关单元90的所述场效应晶体管为P型，所述第二开关单元100的所述场效应晶体管为N型，所述电阻80的另一端接地。P型所述场效应晶体管的栅极为低电平时，所述P型场效应晶体管导通。所述栅极驱动单元30给所述像素单元列210充电。所述P型场效应晶体管的栅极为高电平时，所述P型场效应晶体管关断。所述栅极驱动单元30停止给所述像素单元列210充电。N型所述场效应晶体管的栅极为高电平时，所述N型场效应晶体管导通。全部所述像素单元列210的第二端102联通，所述电极单元220的电荷中和，电压为0V。所述N型场效应晶体管的栅极为低电平时，所述N型场效应晶体管关断。全部所述像素单元列210的第二端102关断。
在初始状态时，P型所述场效应晶体管、N型场效应晶体管的栅极和所述第二反向输入端712均为低电平。第一输入端731输入上升沿时，所述第二输入端732将低电平赋给所述第一输入端733端，所述第一输入端733端将低电平输送给所述反相器720。所述反相器720将高电平输出。所述多个P型所述场效应晶体管和所述多个N型所述场效应晶体管的栅极接收到高电平。所述多个P型所述场效应晶体管关断，所述多个N型场效应晶体管导通。所述栅极驱动单元30停止给所述像素单元列210充电，全部所述像素单元列210联通，所述像素单元220中的电荷沿所述像素单元列210移动，汇集并中和。每个所述像素单元列210的电压被中和，所述像素单元220中的电压为0V。
当所述时序控制器60由高电平变为低电平时，出现下降沿。所述第一输入端731接收到所述下降沿，所述第一输出端733接收所述第二输入端732的高电平，并输出高电平。所述反相器720接收高电平，并翻转为低电平输出。所述第一反向输出端713与P型所述场效应晶体管和所述N型场效应晶体管连接，所述多个P型所述场效应晶体管和所述多个N型场效应晶体管的栅极接收到低 电平。所述多个P型所述场效应晶体管导通，所述多个N型场效应晶体管关断。所述栅极驱动单元30给所述像素单元列210充电，所述像素单元220由0V变为设定电压，缩短了充电时间，提高页面显示效率。
在一个实施例中，所述第一开关单元90的所述场效应晶体管为N型，所述第二开关单元100的所述场效应晶体管为P型，所述电阻80的另一端至少为所述场效应晶体管阈值电压。由于初始电压为所述场效应晶体管阈值电压，为高电平。所述N型场效应晶体管的控制信号端为高电平，所述N型场效应晶体管导通；所述P型场效应晶体管的控制信号端为高电平，所述P型场效应晶体管关断。所述栅极驱动单元30给所述像素单元列210充电。
第一输入端731输入上升沿时，所述第二输入端732将高电平赋给所述第一输入端733端，所述第一输入端733端将高电平输送给所述反相器720。所述反相器720将低电平输出。所述多个P型所述场效应晶体管和所述多个P型所述场效应晶体管的控制信号端接收到低电平。所述多个P型所述场效应晶体管关断，所述多个P型场效应晶体管导通。所述栅极驱动单元30停止给所述像素单元列210充电，全部所述像素单元列210联通，所述像素单元220中的电荷沿所述像素单元列210移动，汇集并中和。每个所述像素单元列210的电压被中和，所述像素单元220中的电压为0V。
当所述时序控制器60由低电平变为高电平时，出现下降沿。所述第一输入端731接收到所述下降沿，所述第一输出端733接收所述第二输入端732的低电平，并输出低电平。所述反相器720接收低电平，并翻转为高电平输出。所述第一反向输出端713与P型所述场效应晶体管和所述P型场效应晶体管连接，所述多个P型所述场效应晶体管和所述多个P型场效应晶体管的控制信号端接收到高电平。所述多个P型所述场效应晶体管导通，所述多个P型场效应晶体管关断。所述栅极驱动单元30给所述像素单元列210充电，所述像素单元220由0V变为设定电压，缩短了充电时间，提高页面显示效率。
请一并参见图3，在一个实施例中，L1、L4为所述像素单元220电压翻转的过程曲线，L2、L3为本申请所述像素单元220电压翻转的过程曲线。在上一个实施例中，所述像素单元列210翻转的电压差为2V，L1、L4电压翻转的时间为t2至t4时间段。所述显示面板驱动电路10的电压翻转过程为：在t1时刻， 所述时序控制器60由低电平变为高电平，出现上升沿。所述第一输入端731输入上升沿时，所述第二输入端732将低电平赋给所述第一输入端733端，所述第一输入端733端将低电平输送给所述反相器720。所述反相器720将高电平输出。所述多个P型所述场效应晶体管和所述多个N型所述场效应晶体管的栅极接收到高电平。所述多个P型所述场效应晶体管关断，所述多个N型场效应晶体管导通。所述栅极驱动单元30停止给所述像素单元列210充电，全部所述像素单元列210联通。所述像素单元220中的电荷沿所述像素单元列210移动，汇集并中和。
在t2时刻，所述像素单元220实现电荷中和。L2、L3为0V。在t2时刻，当所述时序控制器60由高电平变为低电平时，出现下降沿。所述第一输入端731接收到所述下降沿，所述第一输出端733接收所述第二输入端732的高电平，并输出高电平。所述反相器720接收高电平，并翻转为低电平输出。所述第一反向输出端713与P型所述场效应晶体管和所述N型场效应晶体管连接，所述多个P型所述场效应晶体管和所述多个N型场效应晶体管的栅极接收到低电平。所述多个P型所述场效应晶体管导通，所述多个N型场效应晶体管关断。所述栅极驱动单元30给所述像素单元列210充电，所述像素单元220在t2至t3时间段内变为设定电压，L2、L3由0V变为设定电压。与传统技术相比，本申请涉及方案实现电压翻转的时间缩短Δt，充电时间缩短，页面显示效率提高。
请一并参见图4，一种显示面板101包括显示面板驱动电路10。所述显示面板驱动电路10包括：包括：像素单元阵列20、栅极驱动单元30、多条数据信号线40、开关控制单元50、多个第一开关单元90和多个第二开关单元100。所述像素单元阵列20包括多个像素单元列210。每个所述像素单元列210包括多个串联的像素单元220。所述栅极驱动单元30与所述像素单元阵列20连接，为所述像素单元阵列20充电每个所述像素单元列210通过一条所述数据信号线40与栅极驱动单元30连接。所述开关控制单元50分别与每个所述第一开关单元90和每个所述第二开关单元100连接。
每个第一开关单元90通过一条所述数据信号线40连接于所述栅极驱动单元30和一个所述像素单元列210之间。每个所述第二开关单元100包括第一端101和第二端102，每个所述第二开关单元100的所述第一端101通过一条所述 数据信号线40与一个所述像素单元列210连接，所述多个第二开关单元100的第二端102相互连接。所述开关控制单元50控制所述多个第一开关单元90导通时，所述栅极驱动单元30通过所述多条数据信号线40给所述多个像素单元列210充电。所述多个第一开关单元90关断时，所述多个第二开关单元100导通，所述多个像素单元列210中的所述像素单元220电荷中和。
所述开关控制单元50包括时序控制器60和触发器70，所述触发器70的输入端与所述时序控制器60连接，所述触发器70的输出端与所述多个第一开关单元90和所述多个第二开关单元100连接。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语″包括″、″包含″或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句″包括一个......″限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其它实施例中实现。因此，本申请将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (20)

  1. 一种显示面板驱动电路，其特征在于，包括：
    像素单元阵列(20)，包括多个像素单元列(210)，每个所述像素单元列(210)包括多个串联的像素单元(220)；
    栅极驱动单元(30)，与所述像素单元阵列(20)连接，为所述像素单元阵列(20)充电；
    多条数据信号线(40)，每个所述像素单元列(210)通过一条所述数据信号线(40)与所述栅极驱动单元(30)连接；
    开关控制单元(50)、多个第一开关单元(90)和多个第二开关单元(100)，所述开关控制单元(50)分别与每个所述第一开关单元(90)和每个所述第二开关单元(100)连接；
    每个第一开关单元(90)通过一条所述数据信号线(40)连接于所述栅极驱动单元(30)和一个所述像素单元列(210)之间；
    每个所述第二开关单元(100)包括第一端(101)和第二端(102)，每个所述第二开关单元(100)的所述第一端(101)通过一条所述数据信号线(40)与一个所述像素单元列(210)连接，所述多个第二开关单元(100)的第二端(102)相互连接；
    所述开关控制单元(50)控制所述多个第一开关单元(90)导通时，所述栅极驱动单元(30)通过所述多条数据信号线(40)给所述多个像素单元列(210)充电，所述多个第一开关单元(90)关断时，所述多个第二开关单元(100)导通，所述多个像素单元列(210)中的所述像素单元(220)电荷中和。
  2. 如权利要求1所述的显示面板驱动电路，其特征在于，所述开关控制单元(50)包括时序控制器(60)和触发器(70)，所述触发器(70)的输入端与所述时序控制器(60)连接，所述触发器(70)的输出端与所述多个第一开关 单元(90)和所述多个第二开关单元(100)连接。
  3. 如权利要求2所述的显示面板驱动电路，其特征在于，所述开关控制单元(50)还包括：
    电阻(80)，所述电阻(80)的一端与所述第一开关单元(90)和所述第二开关单元(100)连接。
  4. 如权利要求3所述的显示面板驱动电路，其特征在于，所述触发器(70)包括：
    反向触发器(710)，所述反向触发器(710)包括第一反向输入端(711)、第二反向输入端(712)和第一反向输出端(713)，所述第一反向输入端(711)与所述时序控制器(60)连接，接受时序控制，所述第二反向输入端(712)与所述多个第一开关单元(90)和所述多个第二开关单元(100)连接，获取电压信号，所述第一反向输出端(713)与所述第一开关单元(90)和所述第二开关单元(100)连接，控制所述第一开关单元(90)和所述第二开关单元(100)的导通和关断。
  5. 如权利要求4所述的显示面板驱动电路，其特征在于，所述第一开关单元(90)为场效应晶体管，所述第一开关单元(90)的场效应晶体管的栅极与所述触发器(70)的输出端连接，用于接收所述触发器(70)的输出电压，所述第一开关单元(90)的所述场效应晶体管的源极通过所述数据信号线(40)与所述栅极驱动单元(30)连接，所述场效应晶体管的漏极通过所述数据信号线(40)与所述像素单元阵列(20)连接，用于为所述像素单元(220)充电。
  6. 如权利要求5所述的显示面板驱动电路，其特征在于，所述第二开关单元(100)为场效应晶体管，所述第二开关单元(100)的场效应晶体管的栅极与所述触发器(70)的输出端连接，用于接收所述触发器(70)的输出电压，所述场效应晶体管的漏极通过所述数据信号线(40)与所述像素单元阵列(20) 连接，所述第二开关单元(100)的所述场效应晶体管的源极相互连接，用于中和所述多个像素单元列(210)中的所述像素单元(220)电荷。
  7. 如权利要求6所述的显示面板驱动电路，其特征在于，多个所述第一开关单元(90)的场效应晶体管的类型相同。
  8. 如权利要求7所述的显示面板驱动电路，其特征在于，多个所述第二开关单元(100)的场效应晶体管的类型相同。
  9. 如权利要求8所述的显示面板驱动电路，其特征在于，所述第一开关单元(90)的场效应晶体管与所述第二开关单元(100)的场效应晶体管的类型不同。
  10. 一种显示面板驱动电路，其特征在于，包括：
    像素单元阵列(20)，包括多个像素单元列(210)，每个所述像素单元列(210)包括多个串联的像素单元(220)；
    栅极驱动单元(30)，与所述像素单元阵列(20)连接，为所述像素单元阵列(20)充电；
    多条数据信号线(40)，每个所述像素单元列(210)通过一条所述数据信号线(40)与所述栅极驱动单元(30)连接；
    时序控制器(60)、反相器(720)、跟随触发器(730)、多个第一开关单元(90)和多个第二开关单元(100)，
    所述跟随触发器(730)包括第一输入端(731)、第二输入端(732)和第一输出端(733)，所述第一输入端(731)与所述时序控制器(60)连接，接受时序控制，所述第二输入端(732)与所述多个第一开关单元(90)和所述多个第二开关单元(100)连接，获取电压信号，所述第一输出端(733)通过所述反相器(720)与所述第一开关单元(90)和所述第二开关单元(100)连接，控制所述第一开关单元(90)和所述第二开关单元(100)的导通和关断；
    每个第一开关单元(90)通过一条所述数据信号线(40)连接于所述栅极驱动单元(30)和一个所述像素单元列(210)之间；
    每个所述第二开关单元(100)包括第一端(101)和第二端(102)，每个所述第二开关单元(100)的所述第一端(101)通过一条所述数据信号线(40)与一个所述像素单元列(210)连接，所述多个第二开关单元(100)的第二端(102)相互连接；
    所述多个第一开关单元(90)导通时，所述栅极驱动单元(30)通过所述多条数据信号线(40)给所述多个像素单元列(210)充电，所述多个第一开关单元(90)关断时，所述多个第二开关单元(100)导通，所述多个像素单元列(210)中的所述像素单元(220)电荷中和。
  11. 如权利要求10所述的显示面板驱动电路，其特征在于，还包括：
    电阻(80)，所述电阻(80)的一端与所述第一开关单元(90)和所述第二开关单元(100)连接。
  12. 如权利要求11所述的显示面板驱动电路，其特征在于，所述第一开关单元(90)为场效应晶体管，所述第一开关单元(90)的场效应晶体管的栅极与所述触发器(70)的输出端连接，用于接收所述触发器(70)的输出电压，所述第一开关单元(90)的所述场效应晶体管的源极通过所述数据信号线(40)与所述栅极驱动单元(30)连接，所述场效应晶体管的漏极通过所述数据信号线(40)与所述像素单元阵列(20)连接，用于为所述像素单元(220)充电。
  13. 如权利要求12所述的显示面板驱动电路，其特征在于，所述第二开关单元(100)为场效应晶体管，所述第二开关单元(100)的场效应晶体管的栅极与所述触发器(70)的输出端连接，用于接收所述触发器(70)的输出电压，所述场效应晶体管的漏极通过所述数据信号线(40)与所述像素单元阵列(20)连接，所述第二开关单元(100)的所述场效应晶体管的源极相互连接，用于中 和所述多个像素单元列(210)中的所述像素单元(220)电荷。
  14. 如权利要求13所述的显示面板驱动电路，其特征在于，多个所述第一开关单元(90)的场效应晶体管的类型相同。
  15. 如权利要求14所述的显示面板驱动电路，其特征在于，多个所述第二开关单元(100)的场效应晶体管的类型相同。
  16. 如权利要求15所述的显示面板驱动电路，其特征在于，所述第一开关单元(90)的场效应晶体管与所述第二开关单元(100)的场效应晶体管的类型不同。
  17. 如权利要求16所述的显示面板驱动电路，其特征在于，所述第一开关单元(90)的所述场效应晶体管为P型，所述第二开关单元(100)的所述场效应晶体管为N型，所述电阻(80)的另一端接地。
  18. 如权利要求16所述的显示面板驱动电路，其特征在于，所述第一开关单元(90)的所述场效应晶体管为N型，所述第二开关单元(100)的所述场效应晶体管为P型，所述电阻(80)的另一端为阈值电压。
  19. 一种显示面板，其特征在于，包括：
    显示面板驱动电路(10)；
    所述显示面板驱动电路(10)包括：像素单元阵列(20)，包括多个像素单元列(210)，每个所述像素单元列(210)包括多个串联的像素单元(220)；
    栅极驱动单元(30)，与所述像素单元阵列(20)连接，为所述像素单元阵列(20)充电；
    多条数据信号线(40)，每个所述像素单元列(210)通过一条所述数据信号线(40)与所述栅极驱动单元(30)连接；
    开关控制单元(50)、多个第一开关单元(90)和多个第二开关单元(100)，所述开关控制单元(50)分别与每个所述第一开关单元(90)和每个所述第二 开关单元(100)连接；
    每个第一开关单元(90)通过一条所述数据信号线(40)连接于所述栅极驱动单元(30)和一个所述像素单元列(210)之间；
    每个所述第二开关单元(100)包括第一端(101)和第二端(102)，每个所述第二开关单元(100)的所述第一端(101)通过一条所述数据信号线(40)与一个所述像素单元列(210)连接，所述多个第二开关单元(100)的第二端(102)相互连接；
    所述开关控制单元(50)控制所述多个第一开关单元(90)导通时，所述栅极驱动单元(30)通过所述多条数据信号线(40)给所述多个像素单元列(210)充电，所述多个第一开关单元(90)关断时，所述多个第二开关单元(100)导通，所述多个像素单元列(210)中的所述像素单元(220)电荷中和。
  20. 如权利要求19所述的显示面板，其特征在于，所述开关控制单元(50)包括时序控制器(60)和触发器(70)，所述触发器(70)的输入端与所述时序控制器(60)连接，所述触发器(70)的输出端与所述多个第一开关单元(90)和所述多个第二开关单元(100)连接。
PCT/CN2018/120281 2018-11-29 2018-12-11 显示面板驱动电路 Ceased WO2020107534A1 (zh)

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