WO2020103909A1 - 阵列基板、静电放电保护电路和显示装置 - Google Patents

阵列基板、静电放电保护电路和显示装置

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Publication number
WO2020103909A1
WO2020103909A1 PCT/CN2019/119982 CN2019119982W WO2020103909A1 WO 2020103909 A1 WO2020103909 A1 WO 2020103909A1 CN 2019119982 W CN2019119982 W CN 2019119982W WO 2020103909 A1 WO2020103909 A1 WO 2020103909A1
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WIPO (PCT)
Prior art keywords
electrode
signal line
protection device
electrostatic discharge
array substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/119982
Other languages
English (en)
French (fr)
Chinese (zh)
Inventor
龙春平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to JP2020552757A priority Critical patent/JP7510350B2/ja
Priority to US16/956,483 priority patent/US11315920B2/en
Priority to EP19886441.5A priority patent/EP3886164A4/en
Publication of WO2020103909A1 publication Critical patent/WO2020103909A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/911—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using passive elements as protective elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/273—Interconnections for measuring or testing, e.g. probe pads

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate, an electrostatic discharge protection circuit, and a display device.
  • Electrostatic discharge is a relatively common phenomenon in the manufacturing, transportation and use of display devices.
  • ESD Electrostatic Discharge
  • the yield of the display device will be greatly reduced.
  • the electronic circuit in the display device may not work properly, resulting in a decrease in the display effect of the display device.
  • an electrostatic discharge protection circuit is provided in the non-display area (such as the bezel area) of the array substrate in the display device to discharge or balance the high voltage static electricity to protect the display device from electrostatic damage during production, transportation and work .
  • an array substrate in one aspect, includes a base substrate, at least one first signal line, at least one second signal line, and at least one electrostatic discharge protection device.
  • the at least one first signal line and at least one second signal line are disposed on the first side of the base substrate.
  • the at least one electrostatic discharge protection device is disposed on the first side of the base substrate, and each of the at least one electrostatic discharge protection device includes a first electrode, a second electrode, and an insulating medium.
  • the first electrode is coupled to one of the at least one first signal line; the second electrode is coupled to one of the at least one second signal line; insulating medium Provided between the first electrode and the second electrode, the insulating medium is configured such that an electrostatic discharge capacitance is formed between the first electrode and the second electrode.
  • the electrostatic discharge capacitor is configured to discharge the static charge on one of the first signal line and the second signal line to which it is coupled to the other.
  • the array substrate includes: a gate layer, a semiconductor layer, and a gate insulating layer.
  • a gate layer is provided on the first side of the base substrate.
  • the gate layer includes the first electrode of the electrostatic discharge protection device and the gate of the driving transistor.
  • a semiconductor layer is disposed on a side of the gate layer near or away from the base substrate.
  • the semiconductor layer includes a second electrode of the electrostatic discharge protection device and an active layer of the driving transistor.
  • a gate insulating layer is provided between the gate layer and the semiconductor layer, and a portion of the gate insulating layer between the first electrode and the second electrode of the electrostatic discharge protection device serves as the insulating medium .
  • the material of the second electrode is a heavily doped semiconductor material, and the doping concentration of the heavily doped semiconductor material is 10 18 / cm 3 to 10 22 / cm 3 .
  • the gate layer is located on a side of the semiconductor layer away from the base substrate.
  • the array substrate further includes: an interlayer insulating layer and a source-drain electrode layer.
  • the interlayer insulating layer is disposed on a side of the gate layer away from the base substrate.
  • a source-drain electrode layer is disposed on a side of the interlayer insulating layer away from the base substrate, the source-drain electrode layer includes the at least one first signal line, the at least one second signal line, and the The source and drain of the drive transistor.
  • the first electrode of the ESD protection device is provided with a first via hole penetrating the interlayer insulating layer on the side away from the base substrate, and the first electrode of the ESD protection device passes through the first electrode The hole is coupled to the first signal line.
  • the second electrode of the ESD protection device is provided with a second via hole penetrating the gate insulation layer and the interlayer insulation layer on the side away from the base substrate, and the second of the ESD protection device The electrode is coupled to the second signal line through the second via.
  • the second electrode of the ESD protection device is provided with a second via on a side away from the base substrate.
  • the ESD protection device further includes a first connection electrode, one end of the first connection electrode is coupled to the second signal line, and the other end of the first connection electrode passes through the one second via One end of the second electrode close to the second signal line is coupled.
  • the second electrode of the ESD protection device is provided with two second vias on a side away from the base substrate.
  • the ESD protection device further includes a second connection electrode, one end of the second connection electrode is coupled to the second signal line, and the other end of the second connection electrode passes through the two second vias
  • a second via hole is coupled to an end of the second electrode far away from the second signal line, and the portion of the second connection electrode except for its two ends passes through the other of the two second via holes
  • a second via is coupled to an end of the second electrode close to the second signal line.
  • the gate layer is located on a side of the semiconductor layer close to the base substrate.
  • the array substrate further includes a source-drain electrode layer disposed on a side of the semiconductor layer away from the base substrate, the source-drain electrode layer includes the at least one first signal line and the at least one second The signal line and the source and drain of the driving transistor.
  • a third via hole penetrating the gate insulating layer is provided on the side of the first electrode of the ESD protection device that is away from the base substrate, and the first electrode of the ESD protection device passes through the third The hole is coupled to the first signal line.
  • the second electrode of the electrostatic discharge protection device is coupled to the second signal line.
  • the array substrate further includes: at least one test control line and at least one test signal line disposed on the first side of the base substrate, each test control in the at least one test control line The line is configured to transmit a test control signal to the array substrate.
  • Each test signal line in the at least one test signal line is configured to transmit a test signal to the array substrate.
  • the at least one first signal line includes the test control line, and the at least one second signal line includes the test signal line.
  • the array substrate includes: a gate line, a data line, a common voltage signal line, a clock signal line, and a level signal line provided on the first side of the base substrate.
  • the at least one first signal line includes at least one of the gate line, the data line, the common voltage signal line, the clock signal line, and the level signal line.
  • the at least one second signal line includes at least one of the gate line, the data line, the common voltage signal line, the clock signal line, and the level signal line.
  • the first electrode of each of the at least two ESD protection devices is coupled to the same first signal line.
  • a part of the second electrode of the ESD protection device is coupled to one second signal line, and another part of the second electrode of the ESD protection device is coupled to another second signal line.
  • the at least two ESD protection devices are divided into at least one group, and each group includes two ESD protection devices; the two ESD protection devices are a first ESD protection device and a second ESD protection device, respectively Discharge protection device.
  • the array substrate further includes a source-drain electrode layer
  • the array substrate further includes: a passivation layer and a pixel electrode layer.
  • the passivation layer is disposed on the side of the source-drain electrode layer away from the base substrate.
  • the pixel electrode layer is disposed on a side of the passivation layer away from the base substrate.
  • the pixel electrode layer includes at least one third connection electrode and a plurality of pixel electrodes.
  • a fourth via hole penetrating at least the passivation layer is provided on the side of the first electrostatic discharge protection device and the second electrode of the second electrostatic discharge protection device far away from the base substrate.
  • Two ends of one third connection electrode of the at least one third connection electrode respectively pass through the fourth vias corresponding to the first electrostatic discharge protection device and the second electrostatic discharge protection device, and
  • An ESD protection device is coupled to the second electrode of the second ESD protection device.
  • the at least two ESD protection devices are divided into at least one group, and each group includes two ESD protection devices; the two ESD protection devices are a first ESD protection device and a second ESD protection device, respectively Discharge protection device.
  • the first electrode of the first electrostatic discharge protection device and the first electrode of the second electrostatic discharge protection device are coupled to the same first signal line through the same via hole.
  • the orthographic projections of the first ESD protection device and the second ESD protection device on the base substrate are symmetrically located on the first signal line where the two are coupled. Both sides of the orthographic projection on the base substrate.
  • the first electrode includes one first sub-electrode and at least two second sub-electrodes arranged side by side, and the first sub-electrode and the at least two second sub-electrodes are both arranged crosswise.
  • the array substrate has a display area and a non-display area, the non-display area is located at the periphery of the display area, and the at least one ESD protection device is disposed in the non-display area.
  • the array substrate further includes at least one pad provided in the non-display area, and each pad of the at least one pad is coupled to the at least one first signal line and is configured to face the at least one A first signal line transmits electrical signals.
  • an electrostatic discharge protection circuit is provided.
  • the electrostatic discharge protection circuit is provided in the array substrate according to any one of the above.
  • the electrostatic discharge protection circuit includes at least one electrostatic discharge protection device, and the at least one static electricity The first end of each of the electrostatic discharge protection devices in the discharge protection device is coupled to one of the at least one first signal line in the array substrate, and the second end is connected to the One second signal line of at least one second signal line is coupled.
  • the electrostatic discharge protection device is configured to discharge the static charge on one of the first signal line and the second signal line to which it is coupled to the other.
  • the electrostatic discharge protection device is a capacitor.
  • At least two first ends of the ESD protection devices are coupled to the same first signal line, and the second ends of the two ESD protection devices are connected to the same second signal line Or different second signal lines are coupled.
  • a display device including the array substrate as described in any one of the above.
  • FIG. 1 is a structural diagram of an electrostatic discharge protection circuit according to the related art
  • FIG. 2A is a structural diagram of an array substrate according to some embodiments of the present disclosure.
  • FIG. 2B is a cross-sectional view of the array substrate according to the cross-sectional line AA 'in FIG. 2A;
  • FIG. 2C is an enlarged view of the area M in FIG. 2A;
  • 3A is another structural diagram of an array substrate according to some embodiments of the present disclosure.
  • 3B is a cross-sectional view of the array substrate according to the cross-sectional line BB 'in FIG. 3A;
  • FIG. 4A is another structural diagram of an array substrate according to some embodiments of the present disclosure.
  • FIG. 4B is a cross-sectional view of the array substrate according to the cross-sectional line CC 'in FIG. 4A;
  • FIG. 4C is a cross-sectional view of the array substrate according to the cross-sectional line DD 'in FIG. 4A;
  • 5A is another structural diagram of an array substrate according to some embodiments of the present disclosure.
  • 5B is a cross-sectional view of the array substrate according to section line EE 'in FIG. 5A;
  • 6A is another structural diagram of an array substrate according to some embodiments of the present disclosure.
  • FIG. 6B is a cross-sectional view of the array substrate according to the cross-sectional line FF 'in FIG. 6A;
  • 6C is a cross-sectional view of the array substrate according to the cross-sectional line GG 'in FIG. 6A;
  • FIG. 7 is a structural diagram of an electrostatic discharge protection circuit according to some embodiments of the present disclosure.
  • FIG. 8 is another structural diagram of an electrostatic discharge protection circuit according to some embodiments of the present disclosure.
  • FIG. 9 is another structural diagram of an electrostatic discharge protection circuit according to some embodiments of the present disclosure.
  • FIG. 10A is another structural diagram of an array substrate according to some embodiments of the present disclosure.
  • FIG. 10B is another structural diagram of an array substrate according to some embodiments of the present disclosure.
  • FIG. 11 is a structural diagram of a display device according to some embodiments of the present disclosure.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.
  • the features defined as “first” and “second” may explicitly or implicitly include one or more of the features.
  • the meaning of “plurality” is two or more.
  • Coupled and its derivatives may be used.
  • some embodiments may be described using the term “coupled” to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components do not directly contact each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content herein.
  • an electrostatic discharge protection circuit is usually provided in the array substrate in the display device to protect the electronic circuit in the display device from electrostatic interference.
  • the array substrate includes a plurality of signal lines such as a gate line, a data line, a clock signal line, a common voltage signal line, and a level signal line. During the manufacturing, transportation, and use of the display device, the plurality of signal lines may accumulate static electricity. At least one of the plurality of signal lines serves as at least one first signal line, and the other of the plurality of signal lines serves as at least one second signal line.
  • the array substrate further includes at least one ESD protection circuit, and each ESD protection circuit is coupled to at least one first signal line of at least one first signal line and at least one second signal line of at least one second signal line to Discharge or equalize the static electricity on the first signal line or the second signal line.
  • the ESD protection circuit includes at least two thin film transistors.
  • the at least two thin film transistors are a first thin film transistor T 1 and a second thin film transistor T 2 , respectively.
  • Both the first electrode and the control electrode of the first thin film transistor T 1 are coupled to a first signal line 1
  • the first electrode and the control electrode of the second thin film transistor T 2 are coupled to a second signal line 2
  • the first electrode of the first thin film transistor T 1 is coupled to the second electrode of the second thin film transistor T 2
  • the second electrode of the first thin film transistor T 1 is coupled to the first electrode of the second thin film transistor T 2 .
  • the insulating medium between the control electrode (gate) and the first and second electrodes (source and drain electrodes) may break down, thereby Cause the threshold voltage of the thin film transistor to drift or the short circuit between the gate and the source and drain electrodes. Therefore, with the above electrostatic discharge protection circuit, in the case of excessive static charge accumulation, if the thin film transistor encounters a large current or a momentary large charge shock, the gate of the thin film transistor may be broken, resulting in the thin film transistor being burned out. Therefore, the electrostatic discharge protection circuit cannot work normally, and the discharge of static charge cannot be realized.
  • the array substrate 100 includes: a base substrate 3, at least one first signal line 1, at least one second signal line 2, and at least one Electrostatic discharge protection device 4.
  • the at least one first signal line 1 and the at least one second signal line 2 are both provided on the first side A side of the base substrate 3, and the side opposite to the first side A side is the first side of the base substrate 3 Side B side.
  • the at least one first signal line is at least one of a plurality of signal lines (eg, gate lines, data lines, level signal lines) provided on the first side A side of the base substrate 3, and the at least one first signal line
  • the two signal lines are the other of the plurality of signal lines (for example, gate lines, data lines, and level signal lines) provided on the first side A side of the base substrate 3.
  • Static electricity may accumulate on the at least one first signal line 1 and the at least one second signal line 2.
  • Each of the at least one ESD protection device 4 includes a first electrode 41, a second electrode 42, and an insulating medium 43.
  • the first electrode 41 is coupled to one of the at least one first signal line 1.
  • the second electrode 42 is coupled to one of the at least one second signal line 2.
  • the insulating medium 43 is provided between the first electrode 41 and the second electrode 42.
  • the insulating medium 43 is configured such that an electrostatic discharge capacitance C is formed between the first electrode 41 and the second electrode 42; the electrostatic discharge capacitance C is configured to The electrostatic charge on one of the coupled first signal line 1 and second signal line 2 is discharged to the other.
  • the array substrate 100 provided by some embodiments of the present disclosure is provided with at least one ESD protection device 4, and the first electrode 41 included in each ESD protection device 4 is coupled to a first signal line 1, and the second electrode 42 is coupled to a second signal line 2, and an electrostatic discharge capacitor C is formed between the first electrode 41 and the second electrode 42, so that when a large amount of static charge accumulates on the first signal line 1, the device 4 is protected by the electrostatic discharge
  • the electrostatic discharge capacitor C formed in the process discharges static charge from the first signal line 1 to the second signal line 2 to play a role of electrostatic shunt.
  • the electrostatic discharge capacitor C formed in the ESD protection device 4 releases the static charge from the second signal line 2 to the first signal line 1 To electrostatic shunt. In this way, whether a large amount of static charge is accumulated on the first signal line 1 or a large amount of static charge on the second signal line 2, the static charge can be discharged through the electrostatic discharge protection device 4 to avoid the static charge from affecting the electronic circuit ( For example, the normal operation of the pixel drive circuit.
  • an electrostatic discharge capacitor C is formed between the first electrode 41 and the second electrode 42 of each electrostatic discharge protection device 4, and the characteristics of the electrostatic discharge capacitor C are used to achieve electrostatic protection: on the one hand, between the two poles of the capacitor The voltage of will not be abrupt, so the electrostatic discharge capacitor C itself has the effect of suppressing static electricity, especially the circuit provided with a large-capacity capacitor does not even need electrostatic discharge protection.
  • the interference of electrostatic discharge on electronic circuits is mainly conducted interference and radiated interference, and static electricity itself is a wide-band signal.
  • the use of capacitors can provide a better discharge path for electrostatic charges without affecting the generated Is electrostatically coupled to sensitive circuits. Therefore, the use of electrostatic discharge capacitor C for decoupling can improve the decoupling ability of the first signal line 1 and the second signal line 2, and enhance the power of the first signal line 1 and the second signal line 2. Anti-interference ability.
  • the electrostatic discharge capacitor C formed between the first electrode 41 and the second electrode 42 of the electrostatic discharge protection device 4 is used to realize the discharge of electrostatic charges, and no device such as a thin film transistor is used. This avoids the problem that in the related art electrostatic discharge protection circuit, the thin film transistor encounters a large current or a momentary large charge impact, which may cause the gate of the thin film transistor to be broken down, resulting in the problem of the thin film transistor being burned out.
  • the array substrate 100 includes: a gate layer 5, a semiconductor layer 6 and a gate insulating layer 7.
  • the gate layer 5 is provided on the first side A side of the base substrate 3.
  • the gate layer 5 includes the first electrode 41 of the electrostatic discharge protection device 4 and the gate of the driving transistor.
  • the semiconductor layer 6 is disposed on the side of the gate layer 5 near or away from the base substrate 3.
  • the semiconductor layer 6 includes the second electrode 42 of the electrostatic discharge protection device 4 and the active layer of the driving transistor.
  • the gate insulating layer 7 is provided between the gate layer 5 and the semiconductor layer 6, and a portion of the gate insulating layer 7 between the first electrode 41 and the second electrode 42 of the electrostatic discharge protection device 4 serves as an insulating medium 43.
  • the first electrode 41 of the ESD protection device 4 and the gate of the drive transistor are provided in the same layer, so that the first electrode 41 of the ESD protection device can be formed in the same layer when the gate of the drive transistor is formed .
  • the second electrode 42 of the ESD protection device 4 and the active layer of the drive transistor are provided in the same layer, so that the second electrode 42 of the ESD protection device can be formed in the same layer when the active layer of the drive transistor is formed.
  • the array substrate 100 since the first electrode 41 and the second electrode 42 in the ESD protection device 4 are respectively provided in the same layer as the gate electrode and the active layer in the driving transistor, it can be patterned at one time
  • the gate electrode of the driving transistor and the first electrode 41 of the ESD protection device 4 are formed by a process, and the active layer of the driving transistor and the second electrode 42 of the ESD protection device 4 can also be formed through a patterning process, which reduces the array substrate 100
  • the manufacturing process steps reduce the preparation time of the array substrate 100 and improve the preparation efficiency.
  • the same mask can be used when forming the gate and the first electrode 41, and the same mask can be used when forming the active layer and the second electrode 42, the number of masks can be reduced, thereby saving costs .
  • the material of the second electrode 42 is a heavily doped semiconductor material, and the doping concentration of the heavily doped semiconductor material is 10 18 / cm 3 to 10 22 / cm 3 .
  • the material of the second electrode 42 may be a heavily doped low temperature poly-silicon (LTPS) material.
  • the second electrode 42 is formed as follows: an amorphous silicon thin film is formed on the first side A side of the base substrate 3 by a deposition process, through laser annealing (ELA, Excimer Laser Annel) or solid phase crystallization (SPC , Solid Phase Crystallization) process, making amorphous silicon thin film crystallized into polycrystalline silicon thin film. Then, the polysilicon film is etched using a photolithography process to form a plurality of first polysilicon structures having the pattern of the second electrode 42 and a plurality of second polysilicon structures having the pattern of the active layer of the driving transistor.
  • ELA Laser annealing
  • SPC Solid Phase Crystallization
  • High-concentration ion implantation is performed on the plurality of first polysilicon structures.
  • the ions are used as donors or acceptors to provide carriers and are embedded in the polysilicon crystal structure.
  • the concentration of the ions can be selected according to actual needs, for example, 10 18 / cm 3 , 10 19 / cm 3 , 10 20 / cm 3 , 10 21 / cm 3 , 10 22 / cm 3, etc., thereby converting multiple first polysilicon structures into multiple low resistance heavy
  • the doped polysilicon structure, and the plurality of low resistance heavily doped polysilicon structures serve as the second electrode 42.
  • the material of the second electrode 42 is set as a heavily doped semiconductor material. Since the resistance of the heavily doped semiconductor material is much smaller than the resistance of the insulating material and much larger than the resistance of the metal material, the resistance of the second electrode 42 is far Far less than the resistance of the insulating medium 43, and much greater than the resistance of the first signal line 1 and the second signal line 2 (the signal line is generally made of metal material), the resistance value is between the heavy material of the insulating material and the metal material Miscellaneous semiconductor materials can be turned on when high voltage and large current occur.
  • the ESD protection device has a variety of different structures according to the arrangement of each functional film layer included in the array substrate 100, and the present disclosure does not limit this, as long as It is sufficient for the electrostatic discharge protection device to play the role of the aforementioned electrostatic protection.
  • the arrangement of each functional film layer of the array substrate 100 and the structure of the corresponding ESD protection device 4 will be exemplarily introduced below.
  • the array substrate 100 further includes: an interlayer insulating layer 8 and source leakage ⁇ ⁇ 9. 9. Polar layer 9.
  • the interlayer insulating layer 8 is disposed on the side of the gate layer 5 away from the base substrate 3.
  • the source-drain electrode layer 9 is disposed on the side of the interlayer insulating layer 8 away from the base substrate 3, and the source-drain electrode layer 9 includes the at least one first signal line 1, the at least one second signal line 2, and a driving transistor Source and drain.
  • the first electrode 41 of the ESD protection device 4 is provided with a first via a penetrating the interlayer insulating layer 8 on the side away from the base substrate 3, and the first electrode 41 of the ESD protection device 4 passes through the first via a is coupled to the first signal line 1.
  • the second electrode 42 of the ESD protection device 4 is provided with a second via b penetrating the gate insulating layer 7 and the interlayer insulating layer 8 on the side away from the base substrate 3, and the second electrode 42 of the ESD protection device 4 passes through The second via b is coupled to the second signal line 2.
  • the at least one first signal line 1, the at least one second signal line 2 and the source and drain of the driving transistor are arranged in the same layer, so that the source and drain of the driving transistor can be formed At the same time, the at least one first signal line 1 and the at least one second signal line 2 are formed in the same layer, thereby reducing the manufacturing process steps of the array substrate 100, reducing the preparation time of the array substrate 100, and improving the preparation efficiency.
  • the second electrode 42 of each ESD protection device 4 is provided with a second via b on the side away from the base substrate 3.
  • the ESD protection device 4 further includes a first connection electrode 44, one end of the first connection electrode 44 is coupled to the second signal line 2, and the other end of the first connection electrode 44 is close to the second electrode 42 through a second via b One end of the second signal line 2 is coupled.
  • the first connection electrode 44 serves to connect the second signal line 2 and the second electrode 42.
  • the static charge on the first signal line 1 can pass through the first electrode 41.
  • the second electrode 42 and the first connection electrode 44 are discharged onto the second signal line 2, or the static charge on the second signal line 2 can be discharged through the first connection electrode 44, the second electrode 42 and the first electrode 41 To the second signal line 2, it acts as an electrostatic shunt.
  • the second electrode 42 of each electrostatic discharge capacitor C is provided with two second via holes b on the side away from the base substrate 3.
  • the ESD protection device 4 further includes a second connection electrode 45, one end of the second connection electrode 45 is coupled to the second signal line 2, the other end of the second connection electrode 45 passes through one of the two second vias b
  • the via hole b is coupled to the end of the second electrode 42 away from the second signal line 2, and the portion of the second connection electrode 45 except for its two ends passes through the other of the two second via holes b
  • One end of the second electrode 42 near the second signal line 2 is coupled.
  • the orthographic projection of the portion of the second connection electrode 45 other than its two ends on the base substrate 3 and the orthographic projection of the first electrode 41 on the base substrate 3 at least partially overlap.
  • the second connection electrode 45 functions to connect the second signal line 2 and the second electrode 42, and since the portion of the second connection electrode 45 other than its both ends is on the base substrate 3
  • the projection at least partially overlaps the orthographic projection of the first electrode 42 on the base substrate 3, so that a portion of the second connection electrode 45 except for its two ends can form a capacitance between the first electrode 41 and the capacitance can serve as static electricity
  • the discharge capacitance is equivalent to the increase of the electrostatic discharge capacitance formed in the electrostatic discharge protection device 4, and when a large amount of static charge is accumulated on the first signal line 1, the static electricity passing between the first electrode 41 and the second electrode 42
  • a large amount of static charge accumulates on the second
  • the array substrate 100 further includes a source-drain electrode layer 9.
  • the source-drain electrode layer 9 is disposed on the side of the semiconductor layer 6 away from the base substrate 3, the source-drain electrode layer 9 includes the at least one first signal line 1, the at least one second signal line 2, and a driving transistor Source and drain.
  • the first electrode 41 of the electric discharge protection device is provided with a third via c through the gate insulating layer 7 on the side away from the base substrate 3.
  • the first electrode 41 of the electrostatic discharge protection device 4 passes through the third via c and A signal line 1 is coupled.
  • the second electrode 42 of the ESD protection device 4 is coupled to the second signal line 2.
  • the at least one first signal line 1, the at least one second signal line 2 and the source and drain of the driving transistor are arranged in the same layer, so that the source and drain of the driving transistor can be formed At this time, the at least one first signal line 1 and the at least one second signal line 2 are formed in the same layer, thereby reducing the manufacturing process steps of the array substrate 100, reducing the preparation time of the array substrate 100, and improving the preparation efficiency.
  • the second electrode 42 and the second signal line 2 can be directly coupled without coupling via vias, which can simplify the manufacturing process of the array substrate 100.
  • the array substrate 100 has a display area AA and a non-display area BB, and the non-display area BB is disposed around the display area AA.
  • the non-display area BB surrounds the display area AA, or, in the case where the display area AA is rectangular, the non-display area BB is disposed on one side, both sides of the display area AA (the opposite sides, or adjacent Two sides) or three sides.
  • the array substrate needs to test the signal lines in the array substrate before shipping, for example, the gate lines or data lines in the array substrate.
  • the following is an example of testing the data lines of the array substrate.
  • at least one test circuit, at least one test control line, and at least one test signal line need to be arranged in the array substrate.
  • each test circuit 12 is disposed on the first side of the base substrate, and each test circuit 12 of the at least one test circuit 12 is respectively coupled to each data line included in the array substrate .
  • each test circuit 12 includes at least one thin film transistor, and the second electrode (drain) of each of the at least one thin film transistor is coupled to one data line.
  • the at least one test control line 1 ' is disposed on the first side of the base substrate, each test control line 1' of the at least one test control line 1 'is respectively connected to each of the at least one test circuit 12
  • the test circuit 12 is coupled.
  • the test control line 1 ' is configured to transmit a test control signal to the array substrate 100, that is, to transmit the test control signal to the at least one test circuit 12 in the array substrate 100.
  • each test circuit 12 includes at least one thin film transistor
  • each test control line 1 ' respectively coupled to the control electrode (gate) of one thin film transistor in each test circuit 12, so that The test circuit 12 is turned on or off by the test control signal transmitted by the test control line 1 '.
  • the test control signal is transmitted to the at least one test control line through the pad in the array substrate 100, the pad is coupled to the control chip, and the control chip provides the test control signal to the pad.
  • the at least one test signal line 2 ' is disposed on the first side of the base substrate, each test signal line 2' in the at least one test signal line 2 'is respectively connected to each of the at least one test circuit 12
  • the test circuit 12 is coupled.
  • the test signal line 2 ' is configured to transmit a test signal to the array substrate 100, that is, to transmit the test signal to the at least one test circuit 12 in the array substrate 100.
  • each test circuit 12 includes at least one thin film transistor
  • each test signal line 2 ' respectively coupled to the first electrode (source) of one thin film transistor in each test circuit 12, to When the test circuit 12 is turned on, the test signal is transmitted to the data line.
  • the test signal is transmitted to the at least one test signal line through the pad in the array substrate 100, the pad is coupled to the control chip, and the control chip provides the test signal to the pad.
  • the at least one test signal line 2 ′ includes two test signal lines 2 ′, wherein one test signal line 2 ′ is connected to an odd number (eg 1, 3, 5, 7) data lines through the test circuit 12 respectively For coupling, another test signal line 2 'is coupled to an even number (eg, 2, 4, 6, 8) data lines through the test circuit 12 respectively.
  • an odd number eg 1, 3, 5, 7
  • another test signal line 2 ' is coupled to an even number (eg, 2, 4, 6, 8) data lines through the test circuit 12 respectively.
  • the above test process of the array substrate 100 is roughly as follows: under the control of the test control signal transmitted by the at least one test control line 1 ', the at least one test circuit is turned on, and the at least one test signal line 2' is transmitted The test signal is transmitted to the corresponding data line to detect the corresponding data line, for example, to detect whether the corresponding data line is open.
  • the at least one test circuit 12, the at least one test control line 1 'and the at least one test signal line 2' are disposed in the non-display area BB.
  • the at least one first signal line 1 includes a test control line 1 '
  • the at least one second signal line 2 includes a test signal line 2'.
  • the at least one ESD protection device 4 is disposed in the non-display area BB, and each ESD protection device 4 is coupled to one of the at least one first signal line 1 and connected to the at least one One of the second signal lines 2 is coupled.
  • the electrostatic discharge protection device 4 can discharge the static charge onto the test signal line 2', or during the test When a large amount of static charge accumulates on the signal line 2 'momentarily, the electrostatic discharge protection device 4 can discharge the static charge to the test control line 1', thereby avoiding the generated electrostatic coupling into the electronic circuit such as the test circuit 12 , To ensure the normal operation of the array substrate 100 test.
  • the array substrate 100 further includes: a gate line, a data line, a common voltage signal line, a clock signal line, and a level signal line disposed on the first side A side of the base substrate 3.
  • the level signal lines include high level (Vgh) signal lines, low level (Vgl) signal lines, first power supply (Vdd) signal lines, second power supply (Vss) signal lines, and the like.
  • a plurality of pixels in the display area AA and each pixel in the plurality of pixels corresponds to a pixel driving circuit.
  • the pixel driving circuit operates so that The display area AA realizes the display.
  • the gate lines, data lines, common voltage signal lines, clock signal lines, and level signal lines may accumulate static electricity, which may affect the normal operation of electronic circuits (such as pixel driving circuits) in the array substrate.
  • the at least one first signal line 1 includes at least one of the gate line, the data line, the common voltage signal line, the clock signal line, and the level signal line By.
  • the at least one second signal line 2 includes at least one of the gate line, the data line, the common voltage signal line, the clock signal line, and the level signal line.
  • the at least one first signal line 1 includes at least one data line and at least one gate line
  • the at least one second signal line 2 is a common voltage signal line.
  • the at least one ESD protection device 4 is located in the non-display area BB, and each ESD protection device 4 is coupled to a first signal line 1 and a second signal line 2.
  • the at least one first signal line 1 and the at least one second signal line 2 are respectively at least one of multiple signal lines included in the array substrate 100.
  • the electrostatic charge on one of the first signal line 1 and the second signal line 2 to which the electrostatic discharge protection device 4 is coupled can be discharged to
  • the static charge accumulated on the gate line or the data line may be discharged to the common voltage signal line, thereby implementing electrostatic shunting, so that the display operation of the array substrate 100 is protected from static electricity.
  • the array substrate 100 further includes at least one pad disposed in the non-display area BB, each of the at least one pad and at least one first signal line 1 coupled, configured to transmit electrical signals to the at least one first signal line 1.
  • the pad is configured to transmit a test control signal to the test control line 1'; at the at least one first signal line 1 In the case of including the gate line, the pad is configured to transmit the gate scan signal to the gate line.
  • the first electrode 41 of each of the at least two ESD protection devices 4 is coupled to the same first signal line 1.
  • a part of the second electrode 42 of the ESD protection device 4 is coupled to a second signal line 2, and the other part of the second electrode 42 of the ESD protection device 4 is connected to another second The signal line 2 is coupled.
  • the first electrode 41 of each ESD protection device 4 in every two ESD protection devices 4 is coupled to the same first signal line 1.
  • one of the ESD protection devices 4 is coupled to one second signal line 2 and the other ESD protection device 4 is coupled to another second signal Line 2 is coupled.
  • the static charge in the case where a large amount of static charge is momentarily accumulated on the first signal line 1, the static charge can be discharged to different second signal lines 2 through at least two electrostatic discharge protection devices 4, and the static charge on the first signal line 1
  • the path of discharge is increased, which makes the discharge of static charge faster and more efficient, and improves the protection effect of electrostatic discharge.
  • the at least two ESD protection devices 4 are divided into at least one group, and each group includes two ESD protection devices 4.
  • the two ESD protection devices 4 are a first ESD protection device 4 and a second ESD protection device 4, respectively.
  • the array substrate 100 further includes the source-drain electrode layer 9, as shown in FIGS. 4A to 4C and FIGS. 6A to 6C, the array substrate 100 further includes: a passivation layer 10 and a pixel electrode layer 11.
  • the passivation layer 10 is disposed on the side of the source-drain electrode layer 9 away from the base substrate 3.
  • the pixel electrode layer 11 is disposed on the side of the passivation layer 10 away from the base substrate 3.
  • the pixel electrode layer 11 includes at least one third connection electrode 11 a and a plurality of pixel electrodes.
  • the first electrode 42 of the first electrostatic discharge protection device 4 and the second electrode 42 of the second electrostatic discharge protection device 4 are each provided with a fourth via d that penetrates at least the passivation layer 10. Two ends of one third connection electrode 11a of the at least one third connection electrode 11a respectively pass through the fourth via holes d corresponding to the first electrostatic discharge protection device 4 and the second electrostatic discharge protection device 4 respectively , Coupled to the second electrode 42 of the first electrostatic discharge protection device 4 and the second electrostatic discharge protection device 4.
  • the at least two ESD protection devices 4 are divided into four groups, and each group includes two ESD protection devices 4.
  • the two ESD protection devices 4 are a first ESD protection device 4-1 and a second ESD protection device 4-2, respectively.
  • the second electrode 42 of the first electrostatic discharge protection device 4-1 and the second electrode 42 of the second electrostatic discharge protection device 4-2 are both provided with a through gate insulating layer 7 on the side away from the base substrate 3 , The fourth via d of the interlayer insulating layer 8 and the passivation layer 10.
  • the two ends of one third connection electrode 11a of the at least one third connection electrode 11a respectively pass through the first corresponding to the first electrostatic discharge protection device 4-1 and the second electrostatic discharge protection device 4-2
  • the four vias d are coupled to the second electrode 42 of the first ESD protection device 4-1 and the second electrode 42 of the second ESD protection device 4-2.
  • the at least two ESD protection devices 4 are divided into four groups, and each group includes two ESD protection devices 4.
  • the two ESD protection devices 4 are a first ESD protection device 4-1 and a second ESD protection device 4-2, respectively.
  • the first electrode 42 of the first electrostatic discharge protection device 4 and the second electrode 42 of the second electrostatic discharge protection device 4 are each provided with a fourth via d penetrating the passivation layer 10 on a side away from the base substrate 3.
  • the two ends of one third connection electrode 11a of the at least one third connection electrode 11a respectively pass through the first corresponding to the first electrostatic discharge protection device 4-1 and the second electrostatic discharge protection device 4-2
  • the four vias d are coupled to the second electrode 42 of the first ESD protection device 4-1 and the second electrode 42 of the second ESD protection device 4-2.
  • the second electrode 42 of the first ESD protection device 4-1 and the second electrode 42 of the second ESD protection device 4-2 are coupled through the third connection electrode 11a, so that When a large amount of static charge accumulates on the signal line 1 momentarily, the static charge can be discharged through the first electrostatic discharge protection device 4-1 and the second electrostatic discharge protection device 4-2 to the corresponding first positions of the two electrostatic discharge protection devices 4
  • the second signal line 2 and the path of the static charge release on the first signal line 1 are increased, which makes the static charge release faster and more efficient, and improves the electrostatic discharge protection effect.
  • the second electrode 42 of one of the ESD protection devices 4 eg, the first ESD protection device 4-1 and the When the coupling is damaged, the static charge cannot be shunted to the second signal line 2 to which the ESD protection device is coupled.
  • the second ESD protection device 4-2) thereby releasing static electricity, thereby improving the stability of the ESD protection device.
  • the at least two ESD protection devices 4 are divided into at least one group, and each group includes two ESD protection devices 4; the two ESD protection devices 4 are respectively the first ESD protection devices 4 ⁇ ⁇ Electrostatic discharge protection device 4.
  • the first electrode 41 of the first ESD protection device 4 and the first electrode 41 of the second ESD protection device 4 are coupled to the same first signal line 1 through the same via hole.
  • the at least two ESD protection devices 4 are in four groups, and each group includes two ESD protection devices 4.
  • the two ESD protection devices 4 are a first ESD protection device 4-1 and a second ESD protection device 4-2, respectively.
  • the first electrode 41 of the first ESD protection device 4-1 and the first electrode 41 of the second ESD protection device 4-2 are coupled to the same first signal line 1 through the same first via a in between Pick up.
  • the two ESD protection devices 4 in each group are coupled to the same first signal line 1 through the same first via a, which can reduce the number of first vias a, thereby saving
  • the preparation steps of the array substrate 100 improve the preparation efficiency.
  • the first ESD protection device 4-1 and the second ESD in each group of ESD protection devices 4 The orthographic projection of the discharge protection device 4-2 on the base substrate 3 is symmetrically located on both sides of the orthographic projection of the first signal line 1 coupled thereto on the base substrate 3.
  • the first electrode 41 included in the ESD protection device 4 includes one first sub-electrode 41a and at least Two second sub-electrodes 41b, the first sub-electrode 41a and the at least two second sub-electrodes 41b are both arranged crosswise.
  • One end of the first sub-electrode 41a is coupled to the first signal line 1 through the first via a.
  • each ESD protection device 4 includes a first electrode 41, a second electrode 42, an insulating medium 43 disposed between the first electrode 41 and the second electrode 42, and a first connection electrode 44
  • each ESD protection device 4 can be regarded as a thin film transistor, wherein the second electrode 42 can be regarded as an active layer ,
  • the first electrode 41 can be regarded as the gate, the first connection electrode 44 can be regarded as one of the source or the drain, and the other of the source or the drain is suspended, formed by the electrostatic discharge protection device 4
  • the electrostatic discharge capacitor C (an electrostatic discharge capacitor formed between the first electrode 41 and the second electrode 42) realizes the discharge of electrostatic charges.
  • each ESD protection device 4 includes a first electrode 41, a second electrode 42, an insulating medium 43 disposed between the first electrode 41 and the second electrode 42, and a second connection electrode 45
  • each ESD protection device 4 can be regarded as a thin film transistor, wherein the second electrode 42 can be regarded as an active layer ,
  • the first electrode 41 can be regarded as a gate
  • the part of the second connection electrode 45 that is in one of the two second vias b, and the part above the second via b can be Regarded as one of the source electrode or the drain electrode
  • the portion of the second connection electrode 45 that is located in the other second via hole b of the two second via holes b, and the portion above the second via hole b Part can be regarded as the other of the source or the drain, and the source and the drain are connected, through the electrostatic discharge capacitance C formed in the thin film transistor (the electrostatic discharge capacitance C formed in the thin film transistor (the electrostatic discharge capacitor
  • each ESD protection device 4 includes a first electrode 41, a second electrode 42, an insulating medium 43 disposed between the first electrode 41 and the second electrode 42, and a first connection electrode 44
  • each ESD protection device 4 can be regarded as a thin film transistor, wherein the second electrode 42 can be regarded as an active layer ,
  • the first electrode 41 can be regarded as the gate
  • the first connection electrode 44 can be regarded as one of the source or the drain
  • the portion of the third connection electrode 11a in and above the fourth via d can be regarded as
  • the other of the source electrode and the drain electrode realizes the discharge of electrostatic charges through an electrostatic discharge capacitor C formed in the thin film transistor (an electrostatic discharge capacitor formed between the first electrode 41 and the second electrode 42).
  • the first electrode 41 includes one first sub-electrode 41a and at least two second sub-electrodes 41b arranged side by side, which is equivalent to making each ESD protection device 4 be regarded as a thin film transistor
  • the double gate thin film transistor can reduce the leakage current of the ESD protection device 4 (think as a thin film transistor) and make the performance of the ESD protection device more stable.
  • Some embodiments of the present disclosure also provide an electrostatic discharge protection circuit 200 disposed in the array substrate 100 as described above.
  • the array substrate 100 includes a display area AA and a non-display area BB, and the ESD protection circuit 200 is located in the non-display area BB.
  • the ESD protection circuit 200 includes at least one ESD protection device 4.
  • the first end of each ESD protection device 4 in the at least one ESD protection device 4 and the array substrate 100 One first signal line 1 of the at least one first signal line 1 is coupled, and the second end is coupled to one second signal line 2 of the at least one second signal line 2 in the array substrate 100.
  • the ESD protection device 4 is configured to discharge the static charge on one of the first signal line 1 and the second signal line 2 to which it is coupled to the other.
  • the at least one first signal line 1 includes the test control line
  • the at least one A second signal line 2 includes the test signal line.
  • the array substrate 100 includes gate lines, data lines, common voltage signal lines, clock signal lines, and level signal lines.
  • the at least one first signal line 1 includes at least one of a gate line, a data line, a common voltage signal line, a clock signal line, and a level signal line.
  • the at least one second signal line 2 includes at least one of a gate line, a data line, a common voltage signal line, a clock signal line, and a level signal line.
  • the electrostatic discharge protection circuit 200 when no static charge is accumulated on the first signal line 1 and the second signal line 2, the electrostatic discharge protection circuit 200 does not work; when an electrostatic discharge occurs, the first signal line 1 instantly gathers A large amount of static charge will be quickly discharged to the second signal line 2 through the ESD protection device 4 in the ESD protection circuit 200, or a large amount of static charge accumulated momentarily in the second signal line 2 will pass through the ESD protection device in the ESD protection circuit 4 Quickly release to the first signal line 1, so as to avoid the static charge from affecting the normal operation of other electronic circuits such as the pixel driving circuit.
  • the electrostatic discharge protection device 4 is a capacitor.
  • capacitor decoupling can improve the decoupling ability of the first signal line 1 and the second signal line 2 and enhance the anti-interference ability of the first signal line 1 and the second signal line 2. Avoid the influence of static electricity on the normal operation of electronic circuits.
  • the first ends of at least two ESD protection devices 4 are coupled to the same first signal line 1, and the second ends of the two ESD protection devices 4
  • the terminal is coupled to the same second signal line 2 or a different second signal line 2.
  • the static charge in the case where a large amount of static charge is momentarily accumulated on the first signal line 1 coupled to the first ends of the at least two electrostatic discharge protection devices 4, the static charge can be protected by at least two electrostatic discharges
  • the device 4 is released to a different second signal line 2 or to the same second signal line 2, the path of the static charge release on the first signal line 1 is increased, which makes the static charge release faster, more efficient, and improved ESD protection effect.
  • the above-mentioned ESD protection circuit 200 has other ways of setting, and the disclosure does not limit this, as long as it can play the role of ESD protection.
  • an embodiment of the present disclosure also provides a display device 300 including the array substrate 100 as described above.
  • the display device 300 provided in the embodiments of the present disclosure may be a liquid crystal display device (Liquid Crystal Display, referred to as LCD); it may also be an organic electroluminescence display device (Organic Light-Emitting Display, referred to as OLED); or a quantum dot electroluminescence Light-emitting display panel (Quantum Dot Light-Emitting Display, referred to as QLED).
  • LCD Liquid Crystal Display
  • OLED Organic Light-Emitting Display
  • QLED Quantum Dot Light-Emitting Display
  • the display device 300 When the display device 300 is a liquid crystal display device, the display device 300 includes, in addition to the array substrate 100, a counter substrate and a liquid crystal layer provided between the counter substrate and the array substrate 100.
  • the display device 300 further includes an encapsulation layer for encapsulating the array substrate 100.
  • the array substrate 100 further includes a pixel driving circuit and a light emitting device, and the light emitting device includes an anode, a light emitting layer, and a cathode.
  • the encapsulation layer may be a thin-film encapsulation layer or a substrate encapsulation layer.
  • the display device may be any product or component with a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.
  • the beneficial effects that can be achieved by the display device 300 provided by the embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the array substrate 100 provided above, and details are not described herein again.

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PCT/CN2019/119982 2018-11-22 2019-11-21 阵列基板、静电放电保护电路和显示装置 Ceased WO2020103909A1 (zh)

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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN208904019U (zh) * 2018-11-22 2019-05-24 京东方科技集团股份有限公司 显示基板、静电放电保护电路和显示装置
TWI709800B (zh) * 2019-09-25 2020-11-11 友達光電股份有限公司 顯示面板
WO2021102971A1 (zh) * 2019-11-29 2021-06-03 京东方科技集团股份有限公司 显示基板和显示装置
CN111243429B (zh) 2020-02-13 2021-11-09 京东方科技集团股份有限公司 一种显示面板及显示装置
CN112509467B (zh) * 2020-11-27 2022-03-08 合肥维信诺科技有限公司 显示基板、静电释放装置及方法
CN112631470B (zh) * 2021-01-07 2024-01-05 武汉华星光电半导体显示技术有限公司 显示面板及电子设备
CN112992999B (zh) * 2021-02-10 2024-04-16 京东方科技集团股份有限公司 显示母板及显示面板
CN113178443B (zh) * 2021-04-09 2022-06-10 深圳市华星光电半导体显示技术有限公司 一种具有防静电结构的显示屏及其制备方法
US11921943B2 (en) * 2021-11-10 2024-03-05 Lg Display Co., Ltd. Display device
CN114361135A (zh) * 2021-12-31 2022-04-15 昆山国显光电有限公司 阵列基板、显示面板及显示装置
US20240395830A1 (en) * 2022-08-30 2024-11-28 Hefei Boe Joint Technology Co., Ltd. Display substrate, manufacturing method thereof, and display device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100246079A1 (en) * 2009-03-31 2010-09-30 Fujitsu Microelectronics Limited Power supply clamp circuit
CN103972228A (zh) * 2013-01-28 2014-08-06 三星显示有限公司 静电防护电路以及具有该静电防护电路的显示装置
CN104122690A (zh) * 2013-08-23 2014-10-29 深超光电（深圳）有限公司 液晶显示装置以及显示装置
CN207925467U (zh) * 2018-03-29 2018-09-28 京东方科技集团股份有限公司 阵列基板及显示装置
CN208904019U (zh) * 2018-11-22 2019-05-24 京东方科技集团股份有限公司 显示基板、静电放电保护电路和显示装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0166894B1 (ko) * 1995-02-20 1999-03-30 구자홍 액정표시장치
US6175394B1 (en) * 1996-12-03 2001-01-16 Chung-Cheng Wu Capacitively coupled field effect transistors for electrostatic discharge protection in flat panel displays
TWI271847B (en) * 2004-12-08 2007-01-21 Au Optronics Corp Electrostatic discharge protection circuit and method of electrostatic discharge protection
JP2006267545A (ja) * 2005-03-24 2006-10-05 Sanyo Epson Imaging Devices Corp 電気光学装置および電子機器
CN103117285B (zh) * 2013-02-04 2015-12-02 京东方科技集团股份有限公司 一种阵列基板、显示装置及阵列基板的制造方法
KR102145390B1 (ko) * 2013-10-25 2020-08-19 삼성디스플레이 주식회사 정전기 방전 회로를 포함하는 표시 장치
CN106415801B (zh) * 2014-06-03 2019-12-13 夏普株式会社 半导体装置及其制造方法
KR102360010B1 (ko) * 2015-06-05 2022-02-10 삼성디스플레이 주식회사 표시 장치 및 이의 제조 방법
KR102482034B1 (ko) * 2015-07-28 2022-12-29 삼성디스플레이 주식회사 유기전계발광 표시장치 및 그의 리페어 방법
US20170090236A1 (en) * 2015-09-28 2017-03-30 Apple Inc. Bonding Pads for Displays
CN108877650B (zh) * 2017-05-12 2020-12-18 京东方科技集团股份有限公司 像素驱动电路、驱动补偿方法、显示基板和显示装置
CN107807467B (zh) * 2017-11-07 2023-08-22 深圳市华星光电半导体显示技术有限公司 防止面板外围走线发生静电击伤的结构

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100246079A1 (en) * 2009-03-31 2010-09-30 Fujitsu Microelectronics Limited Power supply clamp circuit
CN103972228A (zh) * 2013-01-28 2014-08-06 三星显示有限公司 静电防护电路以及具有该静电防护电路的显示装置
CN104122690A (zh) * 2013-08-23 2014-10-29 深超光电（深圳）有限公司 液晶显示装置以及显示装置
CN207925467U (zh) * 2018-03-29 2018-09-28 京东方科技集团股份有限公司 阵列基板及显示装置
CN208904019U (zh) * 2018-11-22 2019-05-24 京东方科技集团股份有限公司 显示基板、静电放电保护电路和显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3886164A4

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US11315920B2 (en) 2022-04-26
EP3886164A1 (en) 2021-09-29
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