WO2024066716A1 - 显示基板、显示模组及显示装置 - Google Patents

显示基板、显示模组及显示装置 Download PDF

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Publication number
WO2024066716A1
WO2024066716A1 PCT/CN2023/110093 CN2023110093W WO2024066716A1 WO 2024066716 A1 WO2024066716 A1 WO 2024066716A1 CN 2023110093 W CN2023110093 W CN 2023110093W WO 2024066716 A1 WO2024066716 A1 WO 2024066716A1
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Prior art keywords
well
thin film
silicon
film transistor
layer
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PCT/CN2023/110093
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English (en)
French (fr)
Inventor
魏俊波
杨盛际
卢鹏程
黄冠达
杨俊彦
田元兰
Original Assignee
京东方科技集团股份有限公司
云南创视界光电科技有限公司
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Publication of WO2024066716A1 publication Critical patent/WO2024066716A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present disclosure belongs to the field of display technology, and particularly relates to a display substrate, a display module and a display device.
  • OLED organic light-emitting diodes
  • OLED organic light-emitting diodes
  • PPI pixel density
  • the present invention aims to solve at least one of the technical problems existing in the prior art and provide a display substrate, a display module and a display device with high brightness, high contrast and high pixel density.
  • an embodiment of the present disclosure includes a display substrate, which includes a silicon-based substrate and a plurality of pixel units arranged on the silicon-based substrate; the pixel units include a pixel driving circuit and a light-emitting device;
  • the pixel driving circuit includes a first thin film transistor, a second thin film transistor and a third thin film transistor arranged on a silicon substrate;
  • the first thin film transistor includes a first source electrode, a first drain electrode, a first gate electrode and a first active layer;
  • the second thin film transistor includes a second active layer;
  • the third thin film transistor includes a third active layer;
  • the silicon-based substrate comprises a first well and a second well arranged along a first direction; a first deep well is further included between the silicon-based substrate and the second well; the first deep well is arranged around the second well;
  • the first active layer is disposed in the second well; the second active layer and the third active layer are disposed in the first well;
  • a first conductive layer is also provided on the silicon-based substrate; the first conductive layer includes a first source electrode and a first switching electrode; the first source electrode is connected to the source electrode of the first active layer through a first connecting via hole The first switching electrode is connected to the second well region contact area of the second well through a second connecting via hole; and the first source is electrically connected to the first switching electrode.
  • the third active layer and the second active layer are arranged in the same first well.
  • first wells and one second well are arranged along the first direction on the silicon-based substrate; the third active layer and the second active layer are arranged in different first wells; the second well surrounds the first well in which the third active layer is arranged; and the first deep well surrounds the second well.
  • the display substrate further comprises a plurality of repeating units arranged in an array on a silicon-based substrate;
  • the repeating unit includes two pixel units arranged side by side along a first direction;
  • the repeating unit is provided with two second wells in the silicon-based substrate along a first direction and a first well is sandwiched between the two second wells; a first deep well is provided between the second well and the silicon-based substrate, and the first deep well is provided around one of the second wells;
  • two third active layers in the first well sandwich two second active layers.
  • the repeating units arranged along the second direction share the first well.
  • the display substrate further comprises a plurality of repeating units arranged in an array on the base substrate;
  • the repeating unit includes two pixel units arranged side by side along a first direction;
  • the repeating unit is provided with two second wells in the silicon substrate along a first direction and three first wells are sandwiched between the two second wells;
  • the third active layer is arranged in the first well close to the second well; two second active layers are arranged in the first well in the middle along the first direction;
  • the second well surrounds the first well of the third active layer; the first deep well is arranged around one of the second wells;
  • two of the first deep wells sandwich one of the first wells.
  • the repeating units arranged along the second direction share the first well located in the middle.
  • the first conductive layer further includes a first drain electrode; the first drain electrode is electrically connected to the drain contact region of the first active layer through a third connecting via hole;
  • the first drain electrodes of adjacent first thin film transistors are electrically connected in the first conductive layer.
  • the first conductive layer further includes a first conductive pattern; the first conductive pattern at least partially includes a first power signal line; and the first drain is electrically connected to the first conductive pattern.
  • the display substrate also includes a third conductive layer on the side away from the first conductive layer; the third thin film transistor includes a third drain; the third drain is arranged in the third conductive layer; the third drain is electrically connected to the drain contact area of the third active layer through a fourth connecting via; the light-emitting device includes a first electrode, a light-emitting layer and a second electrode; the first electrode is electrically connected to the third drain.
  • the display substrate further comprises:
  • the second conductive layer includes the first gate, the second gate of the second thin film transistor and the third gate of the third thin film transistor;
  • a first gate insulating layer located between the silicon-based substrate and the second conductive layer;
  • a first interlayer insulating layer located between the first conductive layer and the second conductive layer;
  • a second interlayer insulating layer is located on a side of the first conductive layer away from the silicon-based substrate;
  • the first connection via, the second connection via and the third connection via penetrate the first interlayer insulating layer and the first gate insulating layer; the fourth connection via penetrates the second interlayer insulating layer, the first interlayer insulating layer and the first gate insulating layer.
  • the display substrate further comprises a first encapsulation layer, a color filter layer and a second encapsulation layer which are sequentially arranged away from the second electrode of the light-emitting device.
  • the embodiments of the present disclosure further include a display module, wherein the display module includes any of the display substrates described above.
  • the display module also includes a flexible printed circuit board and a cover glass.
  • an embodiment of the present disclosure further includes a display device, wherein the display device includes any of the display modules described above.
  • FIG1 is a circuit diagram provided in an embodiment of the present disclosure.
  • FIG2 is a driving timing diagram of the pixel circuit shown in FIG1 ;
  • FIG3 is a schematic cross-sectional view of a display substrate provided in an embodiment of the present disclosure.
  • FIG4 is a schematic cross-sectional view of another display substrate provided in an embodiment of the present disclosure.
  • FIG5 is a schematic diagram of a transistor arrangement provided in an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of another transistor arrangement provided in an embodiment of the present disclosure.
  • Figure 1 is a circuit diagram provided in an embodiment of the present disclosure.
  • the pixel driving circuit in the embodiment of the present disclosure includes a first thin film transistor N1, a second thin film transistor P1, a third thin film transistor P2, a storage capacitor C and a light-emitting device D;
  • the first thin film transistor N1 includes a first source N11, a first drain N12 and a first gate N13;
  • the second thin film transistor P1 includes a second source, a second drain and a second gate;
  • the third thin film transistor P2 includes a third source, a third drain P22 and a third gate P23;
  • the storage capacitor C includes a first plate and a second plate;
  • the light-emitting device D includes a first electrode.
  • transistors used in the embodiments of the present disclosure may be thin film transistors or Field effect transistors or other devices with the same characteristics, since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain.
  • transistors can be divided into N-type and P-type according to the characteristics of the transistors. When a P-type transistor is used, the source and drain are turned on when a low-level signal is input to the gate; when an N-type transistor is used, the source and drain are turned on when a high-level signal is input to the gate.
  • the first thin film transistor N1 in the pixel circuit is an N-type transistor
  • the second thin film transistor P1 and the third thin film transistor P2 are P-type transistors.
  • the transistors of the embodiments of the present disclosure are not limited to the first thin film transistor N1 using an N-type transistor, and the second thin film transistor P1 and the third thin film transistor P2 using a P-type transistor.
  • Those skilled in the art can also make adjustments according to actual needs, such as the first thin film transistor N1 using a P-type thin film transistor, the second thin film transistor P1 and the third thin film transistor P2 using an N-type transistor, and other different schemes to realize the functions of one or more transistors in the embodiments of the present disclosure.
  • the first thin film transistor N1 is used as a driving transistor in the circuit
  • the second thin film transistor P1 is used as a data writing transistor in the circuit
  • the third thin film transistor P2 is used as a light emitting control transistor in the circuit.
  • the connection point of the first gate electrode N13 of the first thin film transistor N1, the second drain electrode of the second thin film transistor P1 and the first plate of the storage capacitor C is the first node;
  • the first drain electrode N12 of the first thin film transistor N1 is connected to the first power supply voltage signal terminal VDD;
  • the second source electrode of the second thin film transistor P1 is connected to the data signal terminal VData, and the second gate electrode is connected to the scanning signal terminal Gate;
  • the third gate electrode P23 of the third thin film transistor P2 is connected to the first reference voltage signal terminal VSS1, and the third drain electrode P22 is connected to the first electrode of the light emitting device D;
  • the second plate of the storage capacitor C is connected to the second reference voltage signal terminal VSS2;
  • the second electrode of the light emitting device D is connected to the third reference voltage signal terminal VSS3.
  • FIG2 is a driving timing diagram of the pixel circuit shown in FIG1.
  • the working process of the pixel circuit is as follows: the data signal terminal VData inputs a data signal, and at the same time the scanning signal terminal Gate inputs a low-level signal.
  • the second thin-film transistor P1 is turned on under the control of the low-level signal, and the data signal is transmitted to the storage capacitor C, and the storage capacitor C stores the data signal.
  • the first thin-film transistor N1 is turned on under the control of the data signal stored in the storage capacitor C, so that the gate and drain of the first thin-film transistor N1 are connected.
  • the third gate P23 of the third thin-film transistor P2 is connected to the first reference voltage signal terminal VSS1.
  • the first reference voltage signal terminal VSS1 can be a reference ground, so the gate voltage of the third thin-film transistor P2 remains at a low level, and the third thin-film transistor P2 is always in the on state.
  • the first thin film transistor N1 can convert the voltage of the first power supply voltage signal into a driving current, so that the light emitting device D between the first power supply voltage terminal and the third reference voltage signal terminal VSS3 forms a current loop, driving the light emitting device D to emit light.
  • the voltage loaded to the first electrode of the light emitting device D is the voltage input by the data signal terminal VData minus the threshold voltage of the first thin film transistor N1.
  • the design of the pixel driving circuit of the embodiment of the present disclosure can prevent the entire display area from being defective due to the short circuit of the anode and cathode of the OLED device in the individual pixel unit 1.
  • the first source N11 of the first thin film transistor N1 is connected to the substrate where the first active layer of the first thin film transistor N1 is located to eliminate the offset effect.
  • the threshold voltage of the first thin film transistor N1 will increase to about 2.8V.
  • the data signal voltage is 8V
  • the maximum voltage loaded on the first electrode of the light-emitting device D is about 5.2V (8V-2.8V);
  • the first source N11 is connected to the substrate to eliminate the offset effect, so the threshold voltage of the first thin film transistor N1 drops to about 1.1V.
  • the maximum voltage loaded on the first electrode of the light-emitting device D is about 6.9V (8V-1.1V).
  • connecting the first source N11 to the substrate eliminates the offset effect and increases the maximum voltage that can be loaded on the first electrode of the light-emitting device D. Due to the increase in the maximum voltage that can be loaded on the first electrode, the voltage span range of the first electrode is also expanded, and the voltage range that can be loaded on the first point pole is 0.58V ⁇ 6.9V. By expanding the range of the voltage that can be applied to the first electrode, the display contrast is improved.
  • OLED organic light-emitting diodes
  • OLED organic light-emitting diodes
  • PPI pixel density
  • the bias effect mainly comes from the bias between the substrate and the source of the thin film transistor on the thin film crystal.
  • Influence of the threshold voltage of the body tube Taking NMOS as an example, when the source potential of the transistor is higher than the substrate potential, more holes in the surface layer below the gate will be attracted to the substrate, which will increase the number of immobile negative ions left in the depletion layer, increase the width of the depletion layer, and increase the surface charge density Qdep in the depletion layer, which will lead to an increase in the threshold voltage of the thin film transistor, resulting in a lower maximum value of the driving voltage provided to the first electrode of the light-emitting device D in the pixel driving circuit.
  • the present disclosure provides a display substrate, and when manufacturing the display substrate, the source electrode of the first thin film transistor N1 used for driving is connected to the substrate and maintained at the same potential.
  • This method can eliminate the offset effect, prevent the threshold voltage of the thin film transistor from rising, reduce the data signal voltage loss of the pixel driving circuit, and thus increase the maximum voltage provided by the pixel driving circuit to the anode of the light-emitting device D, and increase the voltage span loaded on the anode, so that the maximum brightness of the light-emitting device D is improved, and the brightness range is expanded.
  • the present disclosure provides a display substrate
  • FIG3 is a schematic cross-sectional view of a display substrate provided in an embodiment of the present disclosure
  • FIG4 is a schematic cross-sectional view of another display substrate provided in an embodiment of the present disclosure; as shown in FIGS.
  • the display substrate includes a silicon-based substrate P_SUB and a plurality of pixel units 1 arranged on the silicon-based substrate P_SUB;
  • the pixel unit 1 includes a pixel driving circuit and a light-emitting device D;
  • the pixel driving circuit includes a first thin film transistor N1, a second thin film transistor P1 and a third thin film transistor P2 arranged on the silicon-based substrate P_SUB;
  • the first thin film transistor N1 includes a first source N11, a first drain N12, a first gate N13 and a first active layer;
  • the second thin film transistor P1 includes a second active layer;
  • the third thin film transistor P2 includes a third active layer;
  • the silicon-based substrate P_SUB includes a first well NW and a second well PW arranged along a first direction; a first deep well DNW is also included between the silicon-based substrate P_SUB and the second well PW; the first deep well DNW is arranged around the second well PW;
  • the active layer of the P-type transistor needs to be made in the N-well, and the active layer of the N-type transistor needs to be made in the P-well.
  • the first thin film transistor N1 is an N-type thin film transistor
  • the second thin film transistor P1 and the third thin film transistor P2 are P-type thin film transistors. Therefore, the first well NW in the embodiment of the present disclosure is an N-well, the second well PW is a P-well, and the first deep well DNW is a P-well. It is a deep N-well.
  • the first well NW is an N-well, which is made of a low-concentration N-type material doped;
  • the second well PW is a P-well, which is made of a low-concentration P-type material doped.
  • the first deep well DNW is a deep N-well, which is made of a low-concentration N-type material doped.
  • the silicon-based substrate P_SUB can be a P-type substrate and an N-type substrate. In the present disclosure, the silicon-based substrate P_SUB adopts a P-type substrate.
  • the active layer of the N-type transistor can be directly arranged on the P-type substrate, and the first active layer of the first thin-film transistor N1 corresponding to the present application can be directly arranged on the silicon-based substrate P_SUB, but because the first source N11 of the first thin-film transistor N1 needs to be connected to its substrate, that is, electrically connected to the second well PW where the first active layer is arranged, it is necessary to set a first deep well DNW between the second well PW and the substrate for isolation.
  • the N-type transistors need to be fabricated separately in a P-well and surrounded by a deep N-well to be isolated from the P-type silicon-based substrate P_SUB, thereby preventing noise interference caused by the common substrate.
  • a first conductive layer 21 is also provided on the silicon-based substrate P_SUB; the first conductive layer 21 includes a first source N11 and a first transfer electrode 31; the first source N11 is connected to the source contact area of the first active layer through a first connection via Via1; the first transfer electrode 31 is connected to the second well contact area of the second well PW through a second connection via Via2; the first source N11 is electrically connected to the first transfer electrode 31.
  • the first transfer electrode 31 is directly electrically connected to the second well PW, that is, the area of the low-concentration doped P-type material, through the second connection via Via2.
  • the offset effect can be completely eliminated, the threshold voltage of the thin film transistor can be prevented from rising, and the data signal voltage loss of the pixel driving circuit can be reduced, thereby increasing the maximum voltage provided to the anode of the light-emitting device D by the pixel driving circuit, and increasing the voltage span loaded on the anode, so that the maximum brightness of the light-emitting device D can be improved, and the brightness range is expanded, and the display contrast is increased.
  • the third active layer and the second active layer are arranged in the same first well NW.
  • the second thin film transistor P1 and the third thin film transistor P2 in the embodiment of the present disclosure are both P-type transistors, and there is no need to electrically connect their source electrodes to the substrate during manufacture, so the second active layer of the second thin film transistor P1 and the third active layer of the third thin film transistor P2 can be arranged in the same first well NW.
  • two first wells NW are arranged along the first direction on the silicon-based substrate P_SUB; the third active layer and the second active layer are arranged in different first wells NW; the second well PW surrounds the first well NW in which the third active layer is arranged; and the first deep well DNW surrounds the second well PW.
  • the N-type transistor and the P-type transistor adjacently and separately arranged on the silicon-based substrate P_SUB may generate coupling noise, so the active layer of the second thin film transistor P1 and the active layer of the third thin film transistor P2 are arranged in different first wells NW respectively, and a first well NW and a second well PW are arranged in the first deep well DNW, and the third active layer is arranged in the first well NW of the first deep well DNW.
  • the second well PW is manufactured around the first well NW, and the first deep well DNW is manufactured around the second well PW.
  • analog voltages need to be connected to the silicon-based substrate P_SUB, the first deep well DNW, and the first well NW.
  • the first deep well DNW and the first well NW are connected to the same potential, which can be an analog voltage input from the outside to the pixel driving circuit; the potential in the P-type doped area needs to be lower than that in the N-type doped area, so the silicon-based substrate P_SUB needs to be connected to a lower potential than the first deep well DNW, for example, when the external input voltage is 8V, the silicon-based substrate P_SUB needs to be connected to an analog voltage of -8V, and similarly, when the external input voltage is 6V, the silicon-based substrate P_SUB needs to be connected to an analog voltage of -6V; the reference ground can also be connected to the silicon-based substrate P_SUB.
  • FIG5 is a schematic diagram of a transistor arrangement provided in an embodiment of the present disclosure.
  • the display substrate further includes a plurality of repeating units 11 arranged in an array on a silicon-based substrate P_SUB; the repeating unit 11 includes two pixel units 1 arranged along a first direction; the repeating unit 11 sets two second wells PW on the silicon-based substrate P_SUB along the first direction and sandwiches a first well NW between the two second wells PW; a first deep well DNW is set between the second well PW and the silicon-based substrate P_SUB, and the first deep well DNW is set around a second well PW; in the first direction, two third active layers in the first well NW sandwich two second active layers.
  • the first thin film transistor N1 is set together, and the second thin film transistor P1 and the third thin film transistor P2 are set together; in the first direction, the repeating unit 11 has second wells PW surrounding the first deep well DNW on both sides, and a first well NW is set in the middle, and the second wells PW of adjacent repeating units 11 are arranged on both sides.
  • the wells PW are arranged adjacent to each other; therefore, the first thin film transistor N1 which is an N-type transistor is arranged in a concentrated area on the display substrate, and the active layers of the second thin film transistor P1 and the third thin film transistor P2 which are both P-type transistors can be made in a first well NW which is an N-well.
  • some N-type transistors and some P-type transistors are arranged in a concentrated manner, and a plurality of areas where N-type transistors are arranged and a plurality of areas where P-type transistors are arranged are alternately arranged on the display substrate.
  • This method optimizes the arrangement of transistors on the silicon-based substrate P_SUB, and also realizes a more reasonable arrangement of pixel units 1 on the display substrate.
  • the repeating units 11 arranged along the second direction share the first well NW.
  • the second active layer and the third active layer of the second thin film transistor P1 and the third thin film transistor P2 of the repeating unit 11 arranged along the second direction are arranged in the same first well NW, which further optimizes the arrangement of the transistors of the pixel driving circuit, and also realizes a more reasonable arrangement of the pixel unit 1 on the display substrate.
  • the transistors in the pixel driving circuit of the pixel unit 1 adopt the above arrangement, so that the pixel interval of the pixel unit 1 is 6.3 ⁇ m, the size of the first electrode of the light emitting device D connected to the pixel driving circuit is 4.2 ⁇ mx3.15 ⁇ m, and the area of the first electrode is about 13.23 square microns, which improves the pixel density of the display substrate.
  • Figure 6 is another transistor arrangement schematic diagram provided in an embodiment of the present disclosure.
  • the display substrate also includes a plurality of repeating units 11 arranged in an array on the base substrate; the repeating unit 11 includes two pixel units 1 arranged side by side along the first direction; the repeating unit 11 sets two second wells PW on the silicon-based substrate P_SUB along the first direction and sandwiches three first wells NW between the two second wells PW; the third active layer is set in the first well NW close to the second well PW; in the first well NW located in the middle, two second active layers are set along the first direction; the second well PW surrounds the first well NW in which the third active layer is set; the first deep well DNW is set around a second well PW; in the first direction, two first deep wells DNW sandwich a first well NW.
  • the active layer of the second thin film transistor P1 and the active layer of the third thin film transistor P2 are respectively arranged in different first wells NW, and a first well NW and a second well PW are arranged in the first deep well DNW, and the third active layer is arranged in the first well NW of the first deep well DNW.
  • the first well NW and the first deep well DNW are both N-type material doping regions, in order to separate the two During the manufacturing process, the second well PW is formed around the first well NW, and the first deep well DNW is formed around the second well PW.
  • the first thin film transistor N1 is arranged adjacent to each other, and the second thin film transistor P1 and the third thin film transistor P2 are arranged adjacent to each other; in the first direction, first deep wells DNW surrounding the second well PW are arranged on both sides of the repeating unit 11, wherein the second well PW also surrounds a first well NW with a third active layer, and the first well NW sandwiched by two first deep wells DNW is provided with two second active layers along the first direction; the second wells PW of adjacent repeating units 11 are arranged adjacent to each other; therefore, the first thin film transistor N1 which is an N-type transistor on the display substrate is arranged in a concentrated area, and the active layers of the plurality of second thin film transistors P1 which are all P-type transistors can be made in a first well NW which is an N-well, and in this way, some N-type transistors and some P-type transistors are arranged in a concentrated manner, and
  • the repeating units 11 arranged along the second direction share a first well NW sandwiched between two first deep wells DNW.
  • the second active layer of the second thin film transistor P1 of the repeating unit 11 arranged along the second direction which is a P-type transistor, is arranged in the same first well NW, which further optimizes the arrangement of the transistors of the pixel driving circuit, and also realizes a more reasonable arrangement of the pixel unit 1 on the display substrate.
  • the transistors in the pixel driving circuit of the pixel unit 1 adopt the above arrangement, so that the pixel unit 1 has a pixel spacing of 6.3 ⁇ m, and the size of the first electrode of the light-emitting device D connected to the pixel driving circuit is 4.2 ⁇ mx3.15 ⁇ m, and the area of the first electrode is about 13.23 square microns, which improves the pixel density of the display substrate.
  • the first conductive layer 21 further includes a first drain electrode N12; the first drain electrode N12 is electrically connected to the drain contact region of the first active layer through a third connection via Via3; and the first drain electrodes N12 of adjacent first thin film transistors N1 are electrically connected in the first conductive layer 21.
  • the first thin film transistors N1 of adjacent repeating units 11 are adjacent, so the drain electrodes of adjacent first thin film transistors N1 for driving can be connected to the same power signal line during manufacturing.
  • the first conductive layer 21 further includes a first conductive pattern 32; the first conductive pattern 32 at least partially includes a first power signal line; the first drain N12 is electrically connected to the first conductive pattern 32.
  • the first conductive pattern 32 is formed on the first conductive layer 21, and the first conductive pattern 32 partially includes a first power signal line. It is a first power signal line for providing a driving voltage to the pixel driving circuit, and two adjacent first drain electrodes N12 are connected to the same first power signal line.
  • the display substrate further includes a third conductive layer 23 on a side away from the first conductive layer 21;
  • the third thin film transistor P2 includes a third drain electrode P22;
  • the third drain electrode P22 is arranged in the third conductive layer 23;
  • the third drain electrode P22 is electrically connected to the drain contact area of the third active layer through a fourth connecting via Via4;
  • the light emitting device D includes a first electrode, a light emitting layer, and a second electrode; the first electrode is electrically connected to the third drain electrode P22.
  • the third drain electrode P22 of the third thin film transistor P2 is used as an output terminal, so the third drain electrode P22 is connected to the first electrode of the light emitting device D to drive the light emitting device D to emit light.
  • the stacked structure in the embodiment of the present disclosure is only an exemplary structure, and those skilled in the art can also make adjustments according to actual needs, such as adding other conductive layers, insulating layers or other functional layers (not shown in the figure) to the third conductive layer 23 and the silicon-based substrate P_SUB.
  • the display substrate also includes: a second conductive layer 22, located between the silicon-based substrate P_SUB and the first conductive layer 21; the second conductive layer 22 includes a first gate N13, a second gate of the second thin film transistor P1, and a third gate P23 of the third thin film transistor P2; a first gate insulating layer GI1, located between the silicon-based substrate P_SUB and the second conductive layer 22; a first interlayer insulating layer ILD1, located between the first conductive layer 21 and the second conductive layer 22; a second interlayer insulating layer ILD2, located on the side of the first conductive layer 21 away from the silicon-based substrate P_SUB; a first connecting via Via1, a second connecting via Via2, and a third connecting via Via3 penetrate the first interlayer insulating layer ILD1 and the first gate insulating layer GI1; a fourth connecting via Via4 penetrates the second interlayer insulating layer ILD2, the first interlayer insulating
  • the stacked structure in the embodiment of the present disclosure is only an exemplary structure, and those skilled in the art may also make adjustments according to actual needs, such as adding other conductive layers, insulating layers or other functional layers (not shown in the figure) to the first conductive layer 21 and the silicon-based substrate P_SUB.
  • the display substrate further includes a first encapsulation layer, a color filter layer, and a second encapsulation layer, which are sequentially arranged away from the second electrode of the light-emitting device D.
  • the first electrode of the light-emitting device D is generally made of ITO, which has a high transmittance, a high work function, etc.;
  • the light-emitting layer of the light-emitting device D is generally made of organic materials, and the light-emitting properties of the organic materials are utilized. Under the action of voltage or current, holes and electrons are excited to form excitons to achieve light emission; a second electrode is arranged on the light-emitting layer, and the second electrode is arranged on the second electrode.
  • the second electrode is a transparent structure, which is located below the first encapsulation layer.
  • the second electrode can be made of one or several alloy materials selected from Mg/Ag; the first encapsulation layer is also provided with a color film layer on the side away from the second electrode, and the second encapsulation layer is provided between the second encapsulation layer and the first encapsulation layer, and the color film layer is provided corresponding to the light-emitting layer to realize the color display of the emitted light.
  • the second encapsulation layer is used in combination with the first encapsulation layer to realize the effective encapsulation of the OLED device, realize the effective blocking of water vapor and oxygen, and achieve the purpose of protecting the device and extending the service life.
  • the color film layer matches the light-emitting layer, and the second encapsulation layer is provided on the color film layer to realize the function of protecting the color film layer.
  • the first encapsulation layer and the second encapsulation layer can be made of one or more combinations of organic materials with good sealing properties and inorganic materials, such as silicon oxide, silicon nitride, etc., to protect the OLED device structure and achieve a good sealing effect.
  • the present disclosure does not further limit the materials of the first electrode, the light-emitting layer, the second electrode of the light-emitting device D and the first packaging layer, the color filter layer and the second packaging layer of the display substrate. Those skilled in the art can select appropriate materials according to actual needs.
  • the embodiments of the present disclosure further include a display module, wherein the display module includes any one of the above-mentioned display substrates.
  • the display module also includes a flexible printed circuit board and a cover glass.
  • the cover glass can achieve effective encapsulation of the OLED device, effectively block water vapor and oxygen, protect the device, and extend the life of the device.
  • the cover glass is a transparent material, for example, a high-transmittance plain glass.
  • the flexible printed circuit board is electrically connected to the display substrate to achieve the transmission of external signals, transmit the external voltage to the pixel drive circuit, and provide a driving voltage for the pixel drive circuit.
  • the embodiments of the present disclosure further include a display device, wherein the display device includes any of the above display modules.
  • the display device can be a small display device such as a mobile phone or a watch, or a large display device such as a television or a computer.

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Abstract

本公开提供一种显示基板、显示模组和显示装置，属于显示技术领域。本公开的显示基板包括硅基衬底和硅基衬底上设置的像素单元；像素单元包括像素驱动电路和发光器件；像素驱动电路包括设置在硅基衬底上的第一薄膜晶体管、第二薄膜晶体管和第三薄膜晶体管；硅基衬底包括沿第一方向设置的第一阱和第二阱；硅基衬底和第二阱之间包括第一深阱；第一深阱围绕第二阱设置；第二阱设置第一薄膜晶体管的第一有源层；硅基衬底上设置第一导电层；第一导电层包括第一薄膜晶体管的第一源极和第一转接电极；第一源极通过第一连接过孔与第一有源层的源极接触区连接；第一转接电极通过第二连接过孔与第二阱的第二阱区接触区连接；第一源极与第一转接电极电连接。

Description

显示基板、显示模组及显示装置 技术领域
本公开属于显示技术领域，具体涉及一种显示基板、显示模组及显示装置。
背景技术
随着有机电致发光二极管(Organic Light-Emitting Diode，OLED)的发展，OLED具有自发光、广视角、几乎无穷高的对比度、较低耗电、极高反应速度等优点，越来越多的被用在各种显示装置上。随着市场需求和越来越多的应用场景，对OLED器件的要求越来越高，其中更大的亮度，更高的对比度，更高的像素密度(PPI)成了主要需求之一。如何实现显示基板具有高亮、高对比度和高像素密度成了急需解决的问题。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种具有高亮、高对比度和高像素密度的显示基板、显示模组及显示装置。
第一方面，本公开实施例包括一种显示基板，其包括硅基衬底和在硅基衬底上设置的多个像素单元；所述像素单元包括像素驱动电路和发光器件；
所述像素驱动电路包括设置在硅基衬底上的第一薄膜晶体管、第二薄膜晶体管和第三薄膜晶体管；所述第一薄膜晶体管包括第一源极、第一漏极、第一栅极和第一有源层；所述第二薄膜晶体管包括第二有源层；第三薄膜晶体管包括第三有源层；
所述硅基衬底包括沿第一方向设置的一个第一阱和第二阱；在所述硅基衬底和第二阱之间还包括第一深阱；所述第一深阱围绕所述第二阱设置；
在所述第二阱设置有所述第一有源层；所述第一阱设置有所述第二有源层和所述第三有源层；
在所述硅基衬底上还设置有第一导电层；所述第一导电层包括第一源极和第一转接电极；所述第一源极通过第一连接过孔与所述第一有源层的源极 接触区连接；所述第一转接电极通过第二连接过孔与所述第二阱的第二阱区接触区连接；所述第一源极与所述第一转接电极电连接。
其中，所述第三有源层与所述第二有源层设置在同一个所述第一阱。
其中，所述硅基衬底上沿第一方向设置的两个第一阱和一个第二阱；所述第三有源层与所述第二有源层设置在不同的所述第一阱中；所述第二阱围绕设置第三有源层的第一阱；所述第一深阱围绕所述第二阱。
其中，所述显示基板还包括在硅基衬底上阵列排布的多个重复单元；
所述重复单元包括两个沿第一方向并排设置的像素单元；
所述重复单元沿第一方向在硅基衬底设置两个第二阱以及在两个第二阱之间夹设一个第一阱；所述第二阱与所述硅基衬底之间设置有第一深阱，所述第一深阱围绕一个所述第二阱设置；
在第一方向上，所述第一阱中两个所述第三有源层夹设两个所述第二有源层。
其中，沿第二方向设置的所述重复单元，其共用所述第一阱。
其中，所述显示基板还包括在衬底基板上阵列排布的多个重复单元；
所述重复单元包括两个沿第一方向并排设置的像素单元；
所述重复单元沿第一方向在硅基衬底设置两个第二阱以及在两个第二阱之间夹设三个第一阱；
所述第三有源层设置在靠近所述第二阱的第一阱中；位于中间的第一阱中，沿第一方向设置有两个第二有源层；
所述第二阱围绕设置第三有源层的第一阱；所述第一深阱围绕一个所述第二阱设置；
在第一方向上，两个所述第一深阱夹设一个所述第一阱。
其中，沿第二方向设置的所述重复单元，其共用位于中间的所述第一阱。
其中，所述第一导电层还包括第一漏极；所述第一漏极通过第三连接过孔与所述第一有源层的漏极接触区电连接；
相邻所述第一薄膜晶体管的第一漏极在所述第一导电层电连接。
其中，在所述第一导电层还包括有第一导电图案；所述第一导电图案至少部分包括第一电源信号线；所述第一漏极与所述第一导电图案电连接。
其中，所述显示基板还包括背离所述第一导电层一侧的第三导电层；所述第三薄膜晶体管包括第三漏极；所述第三漏极设置在所述第三导电层；所述第三漏极通过第四连接过孔与所述第三有源层的漏极接触区电连接；所述发光器件包括第一电极、发光层和第二电极；所述第一电极与所述第三漏极电连接。
其中，所述显示基板还包括：
第二导电层，位于所述硅基衬底和第一导电层之间；所述第二导电层包括所述第一栅极、所述第二薄膜晶体管的第二栅极和所述第三薄膜晶体管的第三栅极；
第一栅极绝缘层，位于所述硅基衬底和第二导电层之间；
第一层间绝缘层，位于所述第一导电层和第二导电层之间；
第二层间绝缘层，位于所述第一导电层背离硅基衬底一侧；
所述第一连接过孔、第二连接过孔和第三连接过孔贯穿所述第一层间绝缘层和第一栅极绝缘层；第四连接过孔贯穿所述第二层间绝缘层、第一层间绝缘层和第一栅极绝缘层。
其中，所述显示基板还包括背离所述发光器件的第二电极依次设置的第一封装层、彩膜层和第二封装层。
第二方面，本公开实施例还包括一种显示模组，所述显示模组包括上述任一所述的显示基板。
其中，所述显示模组还包括柔性印刷线路板和盖板玻璃。
第三方面，本公开实施例还包括一种显示装置，所述显示装置包括上述任一所述的显示模组。
附图说明
图1为本公开实施例中提供的一种电路图；
图2为图1所示的像素电路的一种驱动时序图；
图3为本公开实施例中提供的一种显示基板截面示意图；
图4为本公开实施例中提供的另一种显示基板截面示意图；
图5为本公开实施例中提供的一种晶体管排布示意图；
图6为本公开实施例中提供的另一种晶体管排布示意图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为本公开实施例中提供的一种电路图，如图1所示，本公开实施例中的像素驱动电路包括有第一薄膜晶体管N1、第二薄膜晶体管P1、第三薄膜晶体管P2、存储电容C和发光器件D；第一薄膜晶体管N1包括有第一源极N11、第一漏极N12和第一栅极N13；第二薄膜晶体管P1包括有第二源极、第二漏极和第二栅极；第三薄膜晶体管P2包括有第三源极、第三漏极P22和第三栅极P23；存储电容C包括第一极板和第二极板；发光器件D包括第一电极。
需要说明的是，本公开实施例中的所采用的晶体管可以为薄膜晶体管或 场效应管或其他特性的相同器件，由于采用的晶体管的源极和漏极是对称的，所以其源极、漏极是没有区别的。此外按照晶体管的特性区分可以将晶体管分为N型和P型，当采用P型晶体管时，栅极输入低电平信号时，源漏极导通；当采用N型晶体管时，栅极输入高电平信号时，源漏极导通。在本公开实施例及之后的描述中将以像素电路中的第一薄膜晶体管N1为N型晶体管，第二薄膜晶体管P1和第三薄膜晶体管P2为P型晶体管为例进行说明。然而本公开的实施例的晶体管不限于第一薄膜晶体管N1用N型晶体管，第二薄膜晶体管P1和第三薄膜晶体管P2用P型晶体管，本领域技术人员还可以根据实际需要进行调整，例如第一薄膜晶体管N1用P型薄膜晶体管，第二薄膜晶体管P1和第三薄膜晶体管P2用N型晶体管等不同方案实现本公开的实施例中的一个或多个晶体管的功能。
如图1所示，第一薄膜晶体管N1在电路中用作驱动晶体管，第二薄膜晶体管P1在电路中用作数据写入晶体管，第三薄膜晶体管P2在电路中用作发光控制晶体管。第一薄膜晶体管N1的第一栅极N13、第二薄膜晶体管P1的第二漏极和存储电容C的第一极板的连接点为第一节点；第一薄膜晶体管N1的第一漏极N12连接第一电源电压信号端VDD；第二薄膜晶体管P1的第二源极连接数据信号端VData，第二栅极连接扫描信号端Gate；第三薄膜晶体管P2的第三栅极P23连接第一参考电压信号端VSS1，第三漏极P22连接发光器件D的第一电极；存储电容C的第二极板连接第二参考电压信号端VSS2；发光器件D的第二电极连接第三参考电压信号端VSS3。
图2为图1所示的像素电路的一种驱动时序图，如图2所示，像素电路的工作过程为：数据信号端VData输入数据信号，同时扫描信号端Gate输入低电平信号，第二薄膜晶体管P1在低电平信号的控制下打开，将数据信号传输到存储电容C，存储电容C将该数据信号进行存储。第一薄膜晶体管N1在存储电容C存储的数据信号的控制下打开，使得第一薄膜晶体管N1的栅极和漏极连接。第三薄膜晶体管P2的第三栅极P23连接第一参考电压信号端VSS1，第一参考电压信号端VSS1可以为参考地，因此第三薄膜晶体管P2的栅极电压保持低电平，第三薄膜晶体管P2一直处于导通状态，此 时第一薄膜晶体管N1可以将第一电源电压信号的电压转换为驱动电流，使得第一电源电压端与第三参考电压信号端VSS3之间的发光器件D形成电流回路，驱动发光器件D进行发光。加载到发光器件D的第一电极的电压为数据信号端VData输入的电压减去第一薄膜晶体管N1的阈值电压。
进一步的，当OLED器件的第一电极和第二电极发光短路的时候，可能引发闩锁效应导致电路失效或损坏。第三薄膜晶体管P2在OLED器件的第一电极和第二电极发生短路时，其漏极的寄生PN结会发生反偏，进而阻止了闩锁效应的发生。因此本公开实施例的像素驱动电路的设计可以防止因个别像素单元1中OLED器件出现阴阳极短路引发整个显示区域出现不良。
本公开实施例中，将第一薄膜晶体管N1的第一源极N11与第一薄膜晶体管N1的第一有源层所在的衬底进行连接，消除偏衬效应。经过实验测试，在将第一源极N11与衬底连接之前，第一薄膜晶体管N1的阈值电压会增大到约为2.8V，当数据信号电压为8V时，发光器件D的第一电极最大加载的电压约为5.2V(8V-2.8V)；将第一源极N11与衬底连接，消除了偏衬效应，因此第一薄膜晶体管N1的阈值电压下降扫约为1.1V，当数据信号电压为8V时，发光器件D的第一电极最大加载的电压约为6.9V(8V-1.1V)。因此，将第一源极N11与衬底连接消除了偏衬效应，提升了发光器件D第一电极上可加载的最大电压。由于提高了第一电极上可加载的最大电压，第一电极的电压跨度范围也得到扩大，第一点极上可加载的电压范围为0.58V～6.9V。通过扩大第一电极上可加载的电压的范围，提高了显示对比度。
随着有机电致发光二极管(Organic Light-Emitting Diode，OLED)的发展，OLED具有自发光、广视角、几乎无穷高的对比度、较低耗电、极高反应速度等优点，越来越多的被用在各种显示装置上。随着市场需求和越来越多的应用场景，对OLED器件的要求越来越高，其中更大的亮度范围，更高的像素密度(PPI)成了主要需求之一。如何提高像素驱动电路提供OLED器件阳极电压的跨度范围，实现高亮显示、高亮度范围显示，如何减小像素单元1的面积，提高PPI，成了急需解决的问题。
衬偏效应主要是来源于薄膜晶体管的衬底和源极之间的偏压对薄膜晶 体管的阈值电压的影响：以NMOS为例，当晶体管的源极(Source)电势高于衬底(Bulk)电势时，栅极下面的表面层中将有更多的空穴被吸引到衬底，使耗尽层中留下的不能移动的负离子增多，耗尽层宽度增加，耗尽层中的体电荷面密度Qdep也增加，进而导致薄膜晶体管的阈值电压增加，导致像素驱动电路中向发光器件D第一电极提供的驱动电压的最大值变低。
鉴于此，本公开提供了一种显示基板，在制作显示基板时将用于驱动的第一薄膜晶体管N1的源极和衬底连接，并保持相同的电位。通过该方法可以消除偏衬效应，防止薄膜晶体管的阈值电压上升，使像素驱动电路的数据信号电压损失降低，进而提高了像素驱动电路提供给发光器件D阳极的最大电压，并增加了加载在阳极上的电压跨度，使发光器件D的最大亮度得以提升，并且扩大了亮度范围。
以下结合附图和具体实施例对本公开实施例的显示基板进行说明。
第一方面，本公开实施提供了一种显示基板，图3为本公开实施例中提供的一种显示基板截面示意图；图4为本公开实施例中提供的另一种显示基板截面示意图；如图3、4所示，显示基板包括硅基衬底P_SUB和在硅基衬底P_SUB上设置的多个像素单元1；像素单元1包括像素驱动电路和发光器件D；像素驱动电路包括设置在硅基衬底P_SUB上的第一薄膜晶体管N1、第二薄膜晶体管P1和第三薄膜晶体管P2；第一薄膜晶体管N1包括第一源极N11、第一漏极N12、第一栅极N13和第一有源层；第二薄膜晶体管P1包括第二有源层；第三薄膜晶体管P2包括第三有源层；硅基衬底P_SUB包括沿第一方向设置的第一阱NW和第二阱PW；在硅基衬底P_SUB和第二阱PW之间还包括第一深阱DNW；第一深阱DNW围绕第二阱PW设置；在第二阱PW设置有第一有源层；第一阱NW设置有第二有源层和第三有源层。
需要说明的是，P型晶体管的有源层需要制作在N阱中，N型晶体管的有源层需要制作在P阱中，本公开实施中，第一薄膜晶体管N1为N型薄膜晶体管，第二薄膜晶体管P1和第三薄膜晶体管P2为P型薄膜晶体管，因此，本公开实施例中的第一阱NW为N阱，第二阱PW为P阱，第一深阱DNW 为深N阱。第一阱NW为N阱，其由低浓度的N型材料掺杂制成；第二阱PW为P阱，其由低浓度的P型材料掺杂制成。第一深阱DNW为深N阱，其由低浓度的N型材料掺杂制成。硅基衬底P_SUB可以为P型衬底和N型衬底，在本公开中硅基衬底P_SUB采用P型衬底。N型晶体管的有源层可以直接设置在P型衬底上，对应本申请第一薄膜晶体管N1的第一有源层可以直接设置在硅基衬底P_SUB上，但是由于需要将第一薄膜晶体管N1的第一源极N11与其衬底连接，也就是与设置第一有源层的第二阱PW电连接，因此需要在第二阱PW与衬底基板之间设置第一深阱DNW进行隔离。当多个N型晶体管制作在同一P型硅基衬底P_SUB上时，将N型晶体管的源极和衬底连接会对彼此造成影响，因此需要将N型晶体管单独制作在一个P阱中，并且通过深N阱将其包围，与P型硅基衬底P_SUB进行隔离，从而防止共衬底引起的噪声干扰。
进一步的，在硅基衬底P_SUB上还设置有第一导电层21；第一导电层21包括第一源极N11和第一转接电极31；第一源极N11通过第一连接过孔Via1与第一有源层的源极接触区连接；第一转接电极31通过第二连接过孔Via2与第二阱PW的第二阱区接触区连接；第一源极N11与第一转接电极31电连接。第一转接电极31通过第二连接过孔Via2直接与第二阱PW，即低浓度掺杂P型材料的区域进行电连接。通过将用作驱动晶体管的第一薄膜晶体管N1的第一源极N11与衬底连接的方法，可以完全的消除偏衬效应，防止薄膜晶体管的阈值电压上升，使像素驱动电路的数据信号电压损失降低，进而提高了像素驱动电路提供给发光器件D阳极的最大电压，并增加了加载在阳极上的电压跨度，使发光器件D的最大亮度得以提升，并且扩大了亮度范围，增大了显示的对比度。
在一些示例中，第三有源层与第二有源层设置在同一个第一阱NW。本公开实施例中的第二薄膜晶体管P1和第三薄膜晶体管P2均为P型晶体管，且在制作时无需将其源极和衬底进行电连接，因此可以将第二薄膜晶体管P1的第二有源层和第三薄膜晶体管P2的第三有源层设置在同一个第一阱NW中。
在一些示例中，硅基衬底P_SUB上沿第一方向设置的两个第一阱NW；第三有源层与第二有源层设置在不同的第一阱NW中；所述第二阱PW围绕设置第三有源层的第一阱NW；所述第一深阱DNW围绕所述第二阱PW。当接入像素驱动电路的电源电压较大时，例如将8V电压接入像素驱动电路，在硅基衬底P_SUB上相邻且单独设置的N型晶体管和P型晶体管可能产生的耦合噪声，因此将第二薄膜晶体管P1的有源层和第三薄膜晶体管P2的有源层分别设置在不同的第一阱NW中，并且在第一深阱DNW中设置一个第一阱NW和一个第二阱PW，设置在第一深阱DNW的第一阱NW中设置第三有源层。由于第一阱NW和第一深阱DNW同为N型材料掺杂区域，为了将二者分隔开，在制作时，将第二阱PW围绕第一阱NW制作，第一深阱DNW围绕第二阱PW制作。
进一步的，在硅基衬底P_SUB，第一深阱DNW，第一阱NW中，都需接有模拟电压。其中，第一深阱DNW和第一阱NW连接有相同电位，可以是输入从外部输入到像素驱动电路的模拟电压；在P型掺杂区域的电位需要低于N型掺杂的区域，因此硅基衬底P_SUB上相较于第一深阱DNW需要接有低电位，例如在外接输入电压为8V时，其硅基衬底P_SUB上需要接有-8V的模拟电压，同样的，外接输入电压为6V时，硅基衬底P_SUB上需要接有-6V的模拟电压；也可以在硅基衬底P_SUB上接参考地。
在一些示例中，图5为本公开实施例中提供的一种晶体管排布示意图，如图5所示，显示基板还包括在硅基衬底P_SUB上阵列排布的多个重复单元11；重复单元11包括两个沿第一方向设置的像素单元1；重复单元11沿第一方向在硅基衬底P_SUB设置两个第二阱PW以及在两个第二阱PW之间夹设一个第一阱NW；第二阱PW与硅基衬底P_SUB之间设置有第一深阱DNW，第一深阱DNW围绕一个第二阱PW设置；在第一方向上，第一阱NW中两个第三有源层夹设两个第二有源层。为了提高显示基板的像素密度(PPI)，将第一薄膜晶体管N1设置在一起，将第二薄膜晶体管P1和第三薄膜晶体管P2设置在一起；重复单元11在第一方向上，两侧设置围绕有第一深阱DNW的第二阱PW，中间设置第一阱NW，相邻重复单元11其第二 阱PW相邻设置；因此，在显示基板上为N型晶体管的第一薄膜晶体管N1集中区域设置，均为P型晶体管的第二薄膜晶体管P1和第三薄膜晶体管P2的有源层可以制作在一个为N阱的第一阱NW中，通过该方式将部分N型晶体管和部分P型晶体管集中设置，多个设置N型晶体管和多个设置P型晶体管的区域在显示基板上交替设置，通过该方法优化了在硅基衬底P_SUB上晶体管的排布，同时也实现了显示基板上像素单元1的更合理的排布。
进一步的，沿第二方向设置的重复单元11，其共用第一阱NW。沿第二方向上设置的重复单元11其为P型晶体管的第二薄膜晶体管P1和第三薄膜晶体管P2的第二有源层和第三有源层设置在同一个第一阱NW中，进一步优化了像素驱动电路的晶体管的排布，同时也实现了显示基板上像素单元1的更加合理的排布。像素单元1的像素驱动电路中的晶体管采用上述排布方式，可以使像素单元1的像素间隔为6.3μm，与像素驱动电路连接的发光器件D的第一电极的尺寸为4.2μmx3.15μm，第一电极的面积约为13.23平方微米，提高了显示基板的像素密度。
在一些示例中，图6为本公开实施例中提供的另一种晶体管排布示意图，如图6所示，显示基板还包括在衬底基板上阵列排布的多个重复单元11；重复单元11包括两个沿第一方向并排设置的像素单元1；重复单元11沿第一方向在硅基衬底P_SUB设置两个第二阱PW以及在两个第二阱PW之间夹设三个第一阱NW；第三有源层设置在靠近第二阱PW的第一阱NW中；位于中间的第一阱NW中，沿第一方向设置有两个第二有源层；第二阱PW围绕设置第三有源层的第一阱NW；第一深阱DNW围绕一个第二阱PW设置；在第一方向上，两个第一深阱DNW夹设一个第一阱NW。当接入像素驱动电路的电源电压较大时，例如将8V电压接入像素驱动电路，在硅基衬底P_SUB上相邻且单独设置的N型晶体管和P型晶体管可能产生的耦合噪声，因此将第二薄膜晶体管P1的有源层和第三薄膜晶体管P2的有源层分别设置在不同的第一阱NW中，并且在第一深阱DNW中设置一个第一阱NW和一个第二阱PW，设置在第一深阱DNW的第一阱NW中设置第三有源层。由于第一阱NW和第一深阱DNW同为N型材料掺杂区域，为了将二者分 隔开，在制作时，将第二阱PW围绕第一阱NW制作，第一深阱DNW围绕第二阱PW制作。为了提高显示基板的像素密度(PPI)，将第一薄膜晶体管N1相邻设置，将第二薄膜晶体管P1和第三薄膜晶体管P2相邻设置；重复单元11在第一方向上，两侧设置围绕有第二阱PW的第一深阱DNW，其中，第二阱PW还围绕一个设置第三有源层的第一阱NW，被两个第一深阱DNW夹设的第一阱NW沿第一方向设置有两个第二有源层；相邻重复单元11其第二阱PW相邻设置；因此，在显示基板上为N型晶体管的第一薄膜晶体管N1集中区域设置，均为P型晶体管的多个第二薄膜晶体管P1的有源层，可以制作在一个为N阱的第一阱NW中，通过该方式将部分N型晶体管和部分P型晶体管集中设置，多个设置N型晶体管和多个设置P型晶体管的区域在显示基板上交替设置，通过该方法优化了在硅基衬底P_SUB上晶体管的排布，同时也实现了显示基板上像素单元1的更合理的排布。
在一些示例中，沿第二方向设置的重复单元11，其共用位于中间被两个第一深阱DNW夹设的第一阱NW。沿第二方向上设置的重复单元11其为P型晶体管的第二薄膜晶体管P1的第二有源层设置在同一个第一阱NW中，进一步优化了像素驱动电路的晶体管的排布，同时也实现了显示基板上像素单元1的更加合理的排布。像素单元1的像素驱动电路中的晶体管采用上述排布方式，可以使像素单元1的像素间为6.3μm，与像素驱动电路连接的发光器件D的第一电极的的尺寸为4.2μmx3.15μm，第一电极的面积约为13.23平方微米，提高了显示基板的像素密度。
在一些示例中，第一导电层21还包括第一漏极N12；第一漏极N12通过第三连接过孔Via3与第一有源层的漏极接触区电连接；相邻第一薄膜晶体管N1的第一漏极N12在第一导电层21电连接。相邻的重复单元11其第一薄膜晶体管N1相邻，因此在制作时可以将相邻的用于驱动的第一薄膜晶体管N1的漏极连接同一个电源信号线。
在一些示例中，在第一导电层21还包括有第一导电图案32；第一导电图案32至少部分包括第一电源信号线；第一漏极N12与第一导电图案32电连接。在第一导电层21上制作第一导电图案32，第一导电图案32部分 为用于给像素驱动电路提供驱动电压的第一电源信号线，两个相邻的第一漏极N12连接同一个第一电源信号线。
在一些示例中，显示基板还包括背离第一导电层21一侧的第三导电层23；第三薄膜晶体管P2包括第三漏极P22；第三漏极P22设置在第三导电层23；第三漏极P22通过第四连接过孔Via4与第三有源层的漏极接触区电连接；发光器件D包括第一电极、发光层和第二电极；第一电极与第三漏极P22电连接。第三薄膜晶体管P2的第三漏极P22用作输出端，因此第三漏极P22与发光器件D的第一电极连接，实现驱动发光器件D发光。本公开实施例中的叠层结构仅仅为一种示例性的结构，本领域技术人员还可以根据实际需要进行调整，例如在第三导电层23和硅基衬底P_SUB中增加其他导电层、绝缘层或者其他功能层(图中未示出)。
在一些示例中，如图3、图4所示，显示基板还包括：第二导电层22，位于硅基衬底P_SUB和第一导电层21之间；第二导电层22包括第一栅极N13、第二薄膜晶体管P1的第二栅极和第三薄膜晶体管P2的第三栅极P23；第一栅极绝缘层GI1，位于硅基衬底P_SUB和第二导电层22之间；第一层间绝缘层ILD1，位于第一导电层21和第二导电层22之间；第二层间绝缘层ILD2，位于第一导电层21背离硅基衬底P_SUB一侧；第一连接过孔Via1、第二连接过孔Via2和第三连接过孔Via3贯穿第一层间绝缘层ILD1和第一栅极绝缘层GI1；第四连接过孔Via4贯穿第二层间绝缘层ILD2、第一层间绝缘层ILD1和第一栅极绝缘层GI1。本公开实施例中的叠层结构仅仅为一种示例性的结构，本领域技术人员还可以根据实际需要进行调整，例如在第一导电层21和硅基衬底P_SUB中增加其他导电层、绝缘层或者其他功能层(图中未示出)。
在一些示例中，显示基板还包括背离发光器件D的第二电极依次设立的第一封装层、彩膜层和第二封装层。发光器件D的第一电极一般采用ITO制作而成，其具有较高的透过率、高功函数等；发光器件D的发光层通常是由有机材料制成，利用有机材料的发光特性，在电压或者电流的作用，有空穴与电子激发，形成激子，实现发光；在发光层上面设置有第二电极，第 二电极是一种透明的结构，其位于第一封装层的下面，第二电极可以选择Mg/Ag中的一种或几种合金材料制作而成；第一封装层背离第二电极一侧还设置有彩膜层，第二封装层，第二封装层与第一封装层之间设置彩膜层，且对应于发光层设置，实现发射光的彩色化显示。第二封装层，与第一封装层结合使用，实现OLED器件的有效封装，实现水汽、氧气的有效阻挡，达到保护器件，延长寿命的目的，彩膜层与发光层匹配作用，第二封装层设置在彩膜层的上面，可以实现保护彩膜层的功能。第一封装层和第二封装层可以采用密封特性较好的有机材料，无机材料中的一种或者多种结合制作而成，例如氧化硅，氮化硅等，已达到保护OLED器件结构，达到较好的密封作用。
需要说明的是，本公开中不对发光器件D的第一电极、发光层和第二电极以及显示基板的第一封装层、彩膜层和第二封装层的材料做进一步的限定，本领域技术人员可以根据实际需求选用合适的材料。
第二方面，本公开实施例还包括一种显示模组，所述显示模组包括上述任一显示基板。
在一些示例中，显示模组还包括柔性印刷线路板和盖板玻璃。盖板玻璃可以实现OLED器件的有效封装，实现水汽、氧气的有效阻挡，达到保护器件，延长寿命的目的，盖板玻璃是一种透明的材料，例如，采用一种高透过率的素玻璃。柔性印刷线路板与显示基板实现电气连接，实现外部信号的传输，将外部电压传输到像素驱动电路，为像素驱动电路提供驱动电压。
第三方面，本公开实施例还包括一种显示装置，所述显示装置包括上述任一显示模组。显示装置可以是手机、手表等小型显示设备，也可以是电视、电脑等大型显示设备。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (15)

  1. 一种显示基板，其包括硅基衬底和在硅基衬底上设置的多个像素单元；所述像素单元包括像素驱动电路和发光器件；
    所述像素驱动电路包括设置在硅基衬底上的第一薄膜晶体管、第二薄膜晶体管和第三薄膜晶体管；所述第一薄膜晶体管包括第一源极、第一漏极、第一栅极和第一有源层；所述第二薄膜晶体管包括第二有源层；第三薄膜晶体管包括第三有源层；
    所述硅基衬底包括沿第一方向设置的一个第一阱和第二阱；在所述硅基衬底和第二阱之间还包括第一深阱；所述第一深阱围绕所述第二阱设置；
    在所述第二阱设置有所述第一有源层；所述第一阱设置有所述第二有源层和所述第三有源层；
    在所述硅基衬底上还设置有第一导电层；所述第一导电层包括第一源极和第一转接电极；所述第一源极通过第一连接过孔与所述第一有源层的源极接触区连接；所述第一转接电极通过第二连接过孔与所述第二阱的第二阱区接触区连接；所述第一源极与所述第一转接电极电连接。
  2. 根据权利要求1所述的显示基板，其特征在于，所述第三有源层与所述第二有源层设置在同一个所述第一阱。
  3. 根据权利要求1所述的显示基板，其特征在于，所述硅基衬底上沿第一方向设置的两个第一阱和一个第二阱；所述第三有源层与所述第二有源层设置在不同的所述第一阱中；所述第二阱围绕设置第三有源层的第一阱；所述第一深阱围绕所述第二阱。
  4. 根据权利要求1所述的显示基板，其特征在于，所述显示基板还包括在硅基衬底上阵列排布的多个重复单元；
    所述重复单元包括两个沿第一方向并排设置的像素单元；
    所述重复单元沿第一方向在硅基衬底设置两个第二阱以及在两个第二阱之间夹设一个第一阱；所述第二阱与所述硅基衬底之间设置有第一深阱，所述第一深阱围绕一个所述第二阱设置；
    在第一方向上，所述第一阱中两个所述第三有源层夹设两个所述第二有源层。
  5. 根据权利要求4所述的显示基板，其特征在于，沿第二方向设置的所述重复单元，其共用所述第一阱。
  6. 根据权利要求1所述的显示基板，其特征在于，所述显示基板还包括在衬底基板上阵列排布的多个重复单元；
    所述重复单元包括两个沿第一方向并排设置的像素单元；
    所述重复单元沿第一方向在硅基衬底设置两个第二阱以及在两个第二阱之间夹设三个第一阱；
    所述第三有源层设置在靠近所述第二阱的第一阱中；位于中间的第一阱中，沿第一方向设置有两个第二有源层；
    所述第二阱围绕设置第三有源层的第一阱；所述第一深阱围绕一个所述第二阱设置；
    在第一方向上，两个所述第一深阱夹设一个所述第一阱。
  7. 根据权利要求6所述的显示基板，其特征在于，沿第二方向设置的所述重复单元，其共用位于中间的所述第一阱。
  8. 根据权利要求1所述的显示基板，其特征在于，所述第一导电层还包括第一漏极；所述第一漏极通过第三连接过孔与所述第一有源层的漏极接 触区电连接；
    相邻所述第一薄膜晶体管的第一漏极在所述第一导电层电连接。
  9. 根据权利要求1所述的显示基板，其特征在于，在所述第一导电层还包括有第一导电图案；所述第一导电图案至少部分包括第一电源信号线；所述第一漏极与所述第一导电图案电连接。
  10. 根据权利要求1所述的显示基板，其特征在于，所述显示基板还包括背离所述第一导电层一侧的第三导电层；所述第三薄膜晶体管包括第三漏极；所述第三漏极设置在所述第三导电层；所述第三漏极通过第四连接过孔与所述第三有源层的漏极接触区电连接；所述发光器件包括第一电极、发光层和第二电极；所述第一电极与所述第三漏极电连接。
  11. 根据权利要求1所述的显示基板，其特征在于，所述显示基板还包括：
    第二导电层，位于所述硅基衬底和第一导电层之间；所述第二导电层包括所述第一栅极、所述第二薄膜晶体管的第二栅极和所述第三薄膜晶体管的第三栅极；
    第一栅极绝缘层，位于所述硅基衬底和第二导电层之间；
    第一层间绝缘层，位于所述第一导电层和第二导电层之间；
    第二层间绝缘层，位于所述第一导电层背离硅基衬底一侧；
    所述第一连接过孔、第二连接过孔和第三连接过孔贯穿所述第一层间绝缘层和第一栅极绝缘层；第四连接过孔贯穿所述第二层间绝缘层、第一层间绝缘层和第一栅极绝缘层。
  12. 根据权利要求10所述的显示基板，其特征在于，所述显示基板还 包括背离所述发光器件的第二电极依次设置的第一封装层、彩膜层和第二封装层。
  13. 一种显示模组，其特征在于，所述显示模组包括权利要求1-12中任一所述的显示基板。
  14. 根据权利要求13所述的显示模组，其特征在于，所述显示模组还包括柔性印刷线路板和盖板玻璃。
  15. 一种显示装置，其特征在于，所述显示装置包括权利要求13、14中任一所述的显示模组。
PCT/CN2023/110093 2022-09-28 2023-07-31 显示基板、显示模组及显示装置 WO2024066716A1 (zh)

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