WO2020098581A1 - 一种mim电容及其制作方法 - Google Patents

一种mim电容及其制作方法 Download PDF

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Publication number
WO2020098581A1
WO2020098581A1 PCT/CN2019/116996 CN2019116996W WO2020098581A1 WO 2020098581 A1 WO2020098581 A1 WO 2020098581A1 CN 2019116996 W CN2019116996 W CN 2019116996W WO 2020098581 A1 WO2020098581 A1 WO 2020098581A1
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mim capacitor
layer
metal layer
upper plate
dielectric layer
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French (fr)
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金宏峰
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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Priority to US17/263,285 priority Critical patent/US11476324B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/041—Manufacture or treatment of capacitors having no potential barriers
    • H10D1/043—Manufacture or treatment of capacitors having no potential barriers using patterning processes to form electrode extensions, e.g. etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/62—Capacitors having potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/714—Electrodes having non-planar surfaces, e.g. formed by texturisation having horizontal extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H10W20/496—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means

Definitions

  • the present invention relates to the field of semiconductor technology, specifically to a MIM capacitor and a manufacturing method thereof.
  • Capacitors are widely used in semiconductor integrated circuits as storing charge, coupling, and filtering devices.
  • metal-insulator-metal (MIM, Metal-Isolation-Metal) capacitors have gradually become the mainstream in radio frequency integrated circuits, especially in the mixing / RF CMOS manufacturing process.
  • MIM Metal-insulator-metal
  • the reason is that it is usually made in a metal interconnect layer, which is compatible with both integrated circuit technology and the distance between the substrate, which can overcome the large parasitic capacitance of many other types of capacitors, and the device performance increases with frequency Disadvantages of obvious decline.
  • MIM capacitors are usually located in the upper layer of the multi-layer device structure in integrated circuits, and their structure is closer to the typical capacitor, that is, a capacitor with a dielectric between metal electrode plates.
  • the semiconductor device includes a MIM capacitor area and other circuit areas, wherein the MIM capacitor structure includes a lower plate 101, an upper plate 103, and a dielectric layer 102 between the two.
  • the dielectric layer 102 is usually formed of a silicon nitride (SiN) thin film with a high dielectric constant.
  • the lower electrode plate 101 and the upper electrode plate 103 of the MIM capacitor are also connected to the top metal layer 104 through contact holes 105 formed in an intermetal dielectric layer (IMD, Inter Metal) 100.
  • IMD intermetal dielectric layer
  • a metal material for example, copper
  • metal wiring is generally used for wiring, that is, metal wiring.
  • the metal wiring process and the production of the MIM capacitor are two independent process steps, and the MIM capacitor region needs to be defined by a photolithography process dedicated to the production of the MIM capacitor to form the MIM capacitor.
  • Many process steps lead to increased production costs and longer production cycle. Therefore, it is necessary to propose a new MIM capacitor manufacturing method to solve at least one of the above problems.
  • the invention provides a method for manufacturing a MIM capacitor, including the following steps:
  • the anti-reflection layer in is used as the dielectric layer of the MIM capacitor;
  • An upper plate of the MIM capacitor is formed on the anti-reflection layer in the MIM capacitor region.
  • the invention also provides a MIM capacitor, including:
  • the upper plate of the MIM capacitor is formed on the anti-reflection layer in the MIM capacitor region;
  • the first metal layer in the MIM capacitor region serves as a lower electrode plate of the MIM capacitor
  • the anti-reflection layer in the MIM capacitor region serves as a dielectric layer of the MIM capacitor.
  • the anti-reflective layer remaining in the etched area after etching also serves as the dielectric layer of the capacitor, and the metal is continuously filled in the etched area as the upper electrode plate, and no longer needs to be manufactured
  • the additional capacitor dielectric layer also eliminates the need for an additional photolithography process to define the upper plate area, reducing the number of photolithography and etching, thereby reducing process costs and shortening the process cycle.
  • FIG. 1 is a cross-sectional view of an exemplary MIM capacitor.
  • FIG. 2 is a schematic cross-sectional view of a MIM capacitor obtained by a method according to an exemplary embodiment of the present invention.
  • FIG. 3 is a schematic flowchart of a method for manufacturing a MIM capacitor according to an exemplary embodiment of the present invention.
  • first element, component, region, layer, or section discussed below can be represented as a second element, component, region, layer, or section.
  • Spatial relationship terms such as “below”, “below”, “below”, “above”, “above”, etc. It can be used here for the convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then elements or features described as “below” or “below” or “below” the elements or features would be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “below” can include both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
  • FIG. 2 is a schematic cross-sectional view of a MIM capacitor obtained according to the method of an exemplary embodiment of the present invention
  • FIG. 3 is a method of manufacturing a MIM capacitor according to an exemplary embodiment of the present invention Schematic flow chart.
  • the present invention provides a method for manufacturing a MIM capacitor. As shown in FIG. 3, the main steps of the manufacturing method include:
  • Step S301 providing a semiconductor substrate, and forming a first metal layer on the semiconductor substrate;
  • Step S302 forming an anti-reflection layer on the first metal layer
  • Step S303 lithography and etch the first metal layer and the anti-reflection layer to define a MIM capacitor region, and the first metal layer in the MIM capacitor region serves as a lower plate of the MIM capacitor, the The anti-reflection layer in the MIM capacitor area serves as a dielectric layer of the MIM capacitor;
  • Step S304 forming an upper plate of the MIM capacitor on the anti-reflection layer in the MIM capacitor region.
  • step S301 is performed, as shown in FIG. 2, a semiconductor substrate is provided, and a metal layer is formed on the semiconductor substrate.
  • the semiconductor substrate may be at least one of the materials mentioned below: single crystal silicon, silicon on insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator (S -SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.
  • An isolation structure (not shown in FIG. 2) is also formed in the semiconductor substrate.
  • the isolation structure is a shallow trench isolation (STI) structure or a local silicon oxide (LOCOS) isolation structure.
  • the isolation structure divides the substrate into different Various semiconductor devices can be formed in the source area and the active area, such as NMOS and PMOS.
  • the metal wiring includes forming a plurality of metal layers and interconnect structures on the semiconductor substrate.
  • the number of metal layers formed during the metal wiring of semiconductor devices has gradually increased.
  • only the formation of the four metal layers and the interconnection structure are described, including the bottom metal layer 2011, the first metal layer 2012, the second metal layer 2013, and the top metal layer 2014 that are sequentially formed from bottom to top.
  • an underlying metal layer 2011 is formed according to a conventional metal wiring process, where the underlying metal layer 2011 may be formed by a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, or an atomic layer deposition (ALD)
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • LPCVD low-pressure chemical vapor deposition
  • LAD laser ablation deposition
  • SEG selective epitaxial growth
  • the underlying metal layer Materials for 2011 include but are not limited to copper (Cu) or aluminum (Al).
  • an underlying anti-reflective layer is formed on the underlying metal layer 2011, wherein the deposition method of the underlying anti-reflective layer may be selected from chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), etc
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • LPCVD low pressure chemical vapor deposition
  • LAD laser ablation deposition
  • SEG selective epitaxial growth
  • CVD chemical vapor deposition
  • the material of the bottom anti-reflection layer includes, but is not limited to, silicon oxynitride (SION).
  • a photolithography process is used to form a photoresist layer (not shown in FIG. 2) that defines the circuit pattern of the bottom metal layer 2011 on the bottom anti-reflection layer.
  • the photoresist layer with the circuit pattern of the bottom metal layer 2011 may be a photoresist formed through a spin coating process, and then formed through processes such as exposure, development, and cleaning. Then, using the photoresist layer as a mask, the bottom metal layer 2011 and the bottom anti-reflection layer are etched, thereby forming a bottom metal layer 2011 circuit pattern.
  • the bottom metal layer 2011 and the bottom anti-reflection layer may be etched by dry methods. Dry etching includes but is not limited to: reactive ion etching (RIE), ion beam etching and plasma etching.
  • a bottom inter-metal dielectric layer is deposited, the bottom inter-metal dielectric layer fills the gap between the bottom metal layer 2011 and covers the bottom metal layer 2011 and the bottom anti-reflection layer.
  • the deposition method of the underlying intermetal dielectric layer can be selected from chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or atomic layer deposition (ALD) method.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • the material of the underlying inter-metal dielectric layer includes but is not limited to silicon dioxide (SiO 2 ).
  • a first metal layer 2012 is formed on the bottom intermetal dielectric layer, the method and material for forming the first metal layer 2012 and the method and material for forming the bottom metal layer 2011 The same, no more details here.
  • step S302 is performed to form a first anti-reflection layer on the first metal layer.
  • a first anti-reflection layer is formed on the first metal layer 2012.
  • the formation method and material of the first anti-reflection layer are the same as the formation method and material of the above-mentioned bottom anti-reflection layer. Repeat again.
  • step S303 is performed, as shown in FIG. 2, the first metal layer 2012 and the first anti-reflection layer are lithographically and etched to define a MIM capacitor region, and the MIM capacitor region
  • the first metal layer serves as the lower plate 201 of the MIM capacitor
  • the first anti-reflection layer in the MIM capacitor region serves as the dielectric layer 202 of the MIM capacitor.
  • a photoresist layer (not shown in FIG. 2) covering the first anti-reflection layer is formed, and then the photoresist layer is patterned using a photolithography process to define a MIM capacitor region. Using the patterned photoresist layer as a mask, the first metal layer 2012 and the first anti-reflection layer are etched. After etching, the first metal layer in the MIM capacitor region is used as the MIM capacitor. The lower electrode plate 201 and the first anti-reflection layer in the MIM capacitor region serve as the dielectric layer 202 of the MIM capacitor.
  • a photoresist layer (not shown in FIG. 2) covering the first anti-reflection layer is formed, and then the photoresist layer is patterned using a photolithography process to define a MIM capacitor region. Using the patterned photoresist layer as a mask, the first metal layer 2012 and the first anti-reflection layer are etched. After etching, the first metal layer in the MIM capacitor region is used as the MIM capacitor
  • the photoresist layer is patterned using a photolithography process, and simultaneously defining the MIM capacitor region and other The pattern of the circuit area.
  • the first metal layer in the MIM capacitor region serves as the lower plate 201 of the MIM capacitor
  • the first anti-reflection layer in the MIM capacitor region serves as the dielectric layer 202 of the MIM capacitor.
  • the MIM capacitor area and other circuit areas are defined at the same time, so that the mutually independent metal wiring process and the production of the MIM capacitor are combined in the same step.
  • the thickness of the lower plate 201 of the MIM capacitor is 2000 to 5000 angstroms
  • the thickness of the dielectric layer 202 of the MIM capacitor is 200 angstroms to 500 angstroms.
  • step S304 is performed to form the upper plate 203 of the MIM capacitor on the first anti-reflection layer in the MIM capacitor region.
  • the steps include: forming a first intermetal dielectric on the first anti-reflection layer Layer, lithography and etch a first intermetal dielectric layer, forming an upper plate opening in the first intermetal dielectric layer, the upper plate opening exposes a portion of the first anti-reflective layer, ie the upper The plate opening exposes part of the dielectric layer 202 of the MIM capacitor; the upper plate opening is filled with metal to form the upper plate 203 of the MIM capacitor.
  • the first contact hole opening exposes a portion of the first metal layer, that is, the first contact hole opening exposes a portion of the lower plate 201 of the MIM capacitor
  • the first contact hole realizes interconnection between multiple metal layers of metal wiring.
  • the first contact hole opening is located around the opening of the upper plate.
  • the upper electrode plate opening of the MIM capacitor and the at least one first contact hole opening are formed, and light is also emitted from other circuit regions Carve and etch to form contact hole openings in at least one other circuit area, so that the mutually independent metal wiring process and MIM capacitor fabrication are combined in the same step.
  • the filling material of the upper plate 203 of the MIM capacitor and the first contact hole includes but is not limited to tungsten, and the method of forming the upper plate 203 of the MIM capacitor and the first contact hole may use chemical vapor Deposition (CVD) method, physical vapor deposition (PVD) method or atomic layer deposition (ALD) method, etc.
  • CVD chemical vapor Deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • the area of the upper plate is 10E2um 2 to 10E6um 2
  • the thickness of the upper plate of the MIM capacitor is 5000 to 8000 angstroms.
  • the upper plate opening of the MIM capacitor, the first contact hole opening and the contact hole opening of other circuit areas are simultaneously filled, and the upper plate of the MIM capacitor, the first contact hole and the contact hole of other circuit areas are simultaneously formed , Can further shorten the process cycle.
  • the method further includes: forming a second metal layer 2013 and performing photolithography and etching to pattern The second metal layer 2013.
  • the forming method and material of the layer 2013 and the forming method and material of the bottom metal layer 2011 are the same, and will not be repeated here.
  • the method further includes: forming a second intermetal dielectric layer, and between the second metal layers At least one second contact hole is formed in the dielectric layer.
  • the second contact hole 205 is electrically connected to the second metal layer 2013, and the second contact hole 205 is located above the second metal layer 2013 in the MIM capacitance region.
  • a second anti-reflection layer is also formed between the second metal layer 2013 and the second intermetal dielectric layer.
  • a top metal layer 2014 is formed on the second intermetal dielectric layer and lithographically and etched to pattern the top metal layer 2014. Specifically, the formation method and material of the top metal layer 2014 and the formation method and material of the bottom metal layer 2011 are the same, which will not be repeated here.
  • the upper plate 203 of the MIM capacitor and the lower plate 201 of the MIM capacitor are led out to the top metal layer 2014 respectively.
  • the upper plate 203 of the MIM capacitor is sequentially led out to the first top metal layer through the second metal layer 2013 in the MIM capacitor region and the second contact hole 205 in the MIM capacitor region.
  • the lower electrode plate 201 of the MIM capacitor is sequentially led out to the second top metal layer through the first contact hole, the second metal layer 2013 in the MIM capacitor region, and the second contact hole in the MIM capacitor region.
  • the MIM capacitor area and other circuit areas are defined at the same time, so that the mutually independent metal wiring process and the production of the MIM capacitor are combined in the same step; during etching
  • the anti-reflective layer remaining in the engraved area at the same time serves as the dielectric layer of the capacitor.
  • the present invention also provides a MIM capacitor, which includes:
  • An anti-reflection layer is formed on the first metal layer
  • the semiconductor substrate includes a MIM capacitor region and other circuit regions, the first metal layer in the MIM capacitor region serves as a lower plate of the MIM capacitor, and the anti-reflection layer in the MIM capacitor region serves as a MIM capacitor Medium layer
  • An upper plate of MIM capacitor is formed on the anti-reflection layer in the MIM capacitor region.
  • the semiconductor substrate may be at least one of the materials mentioned below: single crystal silicon, silicon on insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator (S -SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.
  • An isolation structure (not shown in FIG. 2) is also formed in the semiconductor substrate.
  • the isolation structure is a shallow trench isolation (STI) structure or a local silicon oxide (LOCOS) isolation structure.
  • the isolation structure divides the substrate into different Various semiconductor devices can be formed in the source area and the active area, such as NMOS and PMOS.
  • the metal wiring includes forming a plurality of metal layers and interconnect structures on the semiconductor substrate.
  • the number of metal layers formed during the metal wiring of semiconductor devices has gradually increased.
  • the material of the metal layer includes but is not limited to copper (Cu) or aluminum (Al).
  • the semiconductor substrate includes a MIM capacitor region and other circuit regions, wherein the first metal layer 2012 located in the MIM capacitor region serves as the lower plate 201 of the MIM capacitor.
  • the thickness of the lower plate 201 of the MIM capacitor is 2000 angstroms to 5000 angstroms.
  • a bottom anti-reflection layer, a first anti-reflection layer, and a second anti-reflection layer are formed on the bottom metal layer 2011, the first metal layer 2012, and the second metal layer 2013, respectively.
  • the material of the anti-reflection layer includes silicon oxynitride (SION).
  • a first anti-reflection layer is formed above the first metal layer 2012, and the first anti-reflection layer in the MIM capacitor region serves as the dielectric layer 202 of the MIM capacitor.
  • the thickness of the dielectric layer of the MIM capacitor is 200 angstroms to 500 angstroms.
  • the bottom metal layer 2011 and the first metal layer 2012 are electrically connected by the bottom contact hole
  • the first metal layer 2012 and the second metal layer 2013 are electrically connected by the first contact hole
  • the second metal layer 2013 is
  • the top metal 2014 is electrically connected by the second contact hole
  • interconnection between multiple metal layers is realized.
  • the material of the contact hole includes tungsten.
  • an upper plate 203 of the MIM capacitor is formed above the dielectric layer 202 of the MIM capacitor.
  • the material of the upper plate 203 of the MIM capacitor includes tungsten.
  • the area of the upper plate is 10E2um 2 to 10E6um 2
  • the thickness of the upper plate of the MIM capacitor is 5000 to 8000 angstroms.
  • a second metal layer 2013 is formed on the upper plate 203 of the MIM capacitor.
  • the area of the lower plate 201 of the MIM capacitor is equal to the area of the dielectric layer 202 of the MIM capacitor, and the area of the upper plate 203 of the MIM capacitor is less than or equal to the area of the dielectric layer 202 of the MIM capacitor.
  • a top metal layer 2014 is also formed above the second metal layer 2013.
  • the upper plate 203 of the MIM capacitor and the lower plate 201 of the MIM capacitor are respectively led out to the top metal layer 2014. Specifically, the upper plate 203 of the MIM capacitor is led out to the first top metal layer through the second metal layer 2013 and the second contact hole 205. The lower plate 201 of the MIM capacitor is led out to the second top metal layer through the first contact hole, the second metal layer 2013 and the second contact hole. The first top metal layer and the second top metal layer are separated by a third intermetal dielectric layer.

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Abstract

一种MIM电容及其制作方法，所述制作方法包括：提供半导体衬底，在所述半导体衬底上形成第一金属层；在所述第一金属层上形成抗反射层；光刻并刻蚀所述第一金属层和所述抗反射层，以定义MIM电容区域，所述MIM电容区域中的所述第一金属层作为MIM电容的下极板，所述MIM电容区域中的所述抗反射层作为MIM电容的介质层；在所述MIM电容区域中的所述抗反射层上形成MIM电容的上极板。

Description

一种MIM电容及其制作方法 技术领域
本发明涉及半导体技术领域，具体而言涉及一种MIM电容及其制作方法。
背景技术
电容作为存储电荷、耦合以及滤波器件被广泛应用在半导体集成电路中。现有的集成电路电容中，金属-绝缘体-金属型(MIM，Metal-Isolation-Metal)电容逐渐成为射频集成电路中的主流，尤其在混频/射频CMOS制程上的应用已非常普遍。原因在于，其通常制作在金属互连层中，既与集成电路工艺相兼容，又与衬底间距离较远，可以克服许多其他类型的电容具有的寄生电容大、器件性能随频率增大而明显下降的缺点。
MIM电容在集成电路中通常位于多层器件结构的上层，其结构更接近于典型意义的电容，即在金属电极板之间具有电介质的电容。如图1所示，半导体器件包括MIM电容区域和其他电路区域，其中，MIM电容结构包括下极板101、上极板103以及位于二者之间的介质层102，该结构能实现电荷存储功能。其中，介质层102通常采用高介电常数的氮化硅(SiN)薄膜形成。另外，MIM电容的下极板101和上极板103还分别通过在金属间介电层(IMD，Inter Metal Dielectric)100内形成的接触孔105连接至顶层金属层104。
在半导体器件的后段制作过程中，为了连接各个部件构成集成电路，通常使用具有相对高导电率的金属材料(例如铜)进行布线，即金属布线。在示例性的方案中，金属布线工艺和MIM电容的制作是两个彼此独立的工艺步骤，需要通过专门用于制作MIM电容的光刻工艺来定义MIM电容区域，才能形成MIM电容。工艺步骤较多导致生产成本增加、制作周期延长。因此，有必要提出一种新的MIM电容制作方法，以解决上述至少一个问题。
发明内容
在发明内容部分中引入了一系列简化形式的概念，这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。
本发明提供一种MIM电容的制作方法，包括以下步骤：
提供半导体衬底，在所述半导体衬底上形成第一金属层；
在所述第一金属层上形成抗反射层；
光刻并刻蚀所述第一金属层和所述抗反射层，以定义MIM电容区域，所述MIM电容区域中的所述第一金属层作为MIM电容的下极板，所述MIM电容区域中的所述抗反射层作为MIM电容的介质层；
在所述MIM电容区域中的所述抗反射层上形成MIM电容的上极板。
本发明还提供一种MIM电容，包括：
半导体衬底；
第一金属层，形成于所述半导体衬底上；
抗反射层，形成于所述第一金属层上；以及
MIM电容的上极板，形成于MIM电容区域中的所述抗反射层上；
其中，所述MIM电容区域中的所述第一金属层作为MIM电容的下极板，所述MIM电容区域中的所述抗反射层作为MIM电容的介质层。根据本发明提供的MIM电容的制作方法，在刻蚀后的刻开区域中保留下来的抗反射层同时作为电容的介质层，继续在刻开区域中填充金属作为上极板，不再需要制作额外的电容的介质层，也不再需要额外的光刻工艺来定义上极板区域，减少了光刻和刻蚀的次数，从而降低了工艺成本，缩短了工艺周期。
附图说明
通过结合附图对本发明实施例进行更详细的描述，本发明的上述以及其它目的、特征和优势将变得更加明显。附图用来提供对本发明实施例的进一步理解，并且构成说明书的一部分，与本发明实施例一起用于解释本发明，并不构成对本发明的限制。在附图中，相同的参考标号通常代表相同部件或步骤。
附图中：
图1是一种示例性的MIM电容的剖面图。
图2是根据本发明示例性实施例的方法所获得的MIM电容的示意性剖面图。
图3是根据本发明示例性实施例的一种MIM电容的制作方法的示意性流程图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下” 元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本发明，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
参照图2和图3，其中图2是根据本发明示例性实施例的方法所获得的MIM电容的示意性剖面图；图3是根据本发明示例性实施例的一种MIM电容的制作方法的示意性流程图。
本发明提供一种MIM电容的制作方法，如图3所示，该制作方法的主要步骤包括：
步骤S301：提供半导体衬底，在所述半导体衬底上形成第一金属层；
步骤S302：在所述第一金属层上形成抗反射层；
步骤S303：光刻并刻蚀所述第一金属层和所述抗反射层，以定义MIM电容区域，所述MIM电容区域中的所述第一金属层作为MIM电容的下极板，所述MIM电容区域中的所述抗反射层作为MIM电容的介质层；
步骤S304：在所述MIM电容区域中的所述抗反射层上形成MIM电容的上极板。
下面，对本发明的半导体器件的制作方法的具体实施方式做详细的说明。
首先，执行步骤S301，如图2所示，提供半导体衬底，在所述半导体衬底上形成金属层。
示例性地，所述半导体衬底可以是以下所提到的材料中的至少一种：单 晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。在半导体衬底中还形成有隔离结构(图2未示出)，所述隔离结构为浅沟槽隔离(STI)结构或者局部氧化硅(LOCOS)隔离结构，隔离结构将基底分为不同的有源区，有源区中可以形成各种半导体器件，例如NMOS和PMOS等。
示例性地，金属布线包括在半导体衬底上形成多个金属层及互连结构。随着技术的进步，半导体器件金属布线过程中形成的金属层数逐渐增加。在本实施例中，仅介绍其中四层金属层及互连结构的形成，包括由下至上依次形成的底层金属层2011、第一金属层2012、第二金属层2013和顶层金属层2014。
首先，参照图2，按照常规金属布线的过程形成底层金属层2011，其中底层金属层2011的形成方法可以为化学气相沉积(CVD)法、物理气相沉积(PVD)法或原子层沉积(ALD)法等形成的低压化学气相沉积(LPCVD)、激光烧蚀沉积(LAD)以及选择外延生长(SEG)中的一种，在本发明中优选为物理气相沉积(PVD)法，所述底层金属层2011的材料包括但不限于铜(Cu)或铝(Al)。
接下来，在底层金属层2011上形成底层抗反射层，其中底层抗反射层的淀积方法可以选用化学气相沉积(CVD)法、物理气相沉积(PVD)法或原子层沉积(ALD)法等形成的低压化学气相沉积(LPCVD)、激光烧蚀沉积(LAD)以及选择外延生长(SEG)中的一种。本发明中优选化学气相沉积(CVD)法，所述底层抗反射层的材料包括但不限于氮氧化硅(SION)。
接下来，采用光刻工艺在底层抗反射层上形成具有定义底层金属层2011电路图形的光刻胶层(图2未示出)。该具有底层金属层2011电路图形的光刻胶层可以是通过旋涂工艺形成的光刻胶，然后经曝光、显影、清洗等工艺形成的。然后，以该光刻胶层为掩膜，刻蚀底层金属层2011和底层抗反射层，从而形成底层金属层2011电路图形。可以采用干法刻蚀所述底层金属层2011和底层抗反射层，干法刻蚀包括但不限于：反应离子刻蚀(RIE)、离子束刻蚀和等离子体刻蚀。
接下来，沉积底层金属间介电层，所述底层金属间介电层填充底层金属层2011之间的空隙并覆盖所述底层金属层2011和底层抗反射层。底层金属 间介电层的淀积方法可以选用化学气相沉积(CVD)法、物理气相沉积(PVD)法或原子层沉积(ALD)法等。本发明中优选化学气相沉积(CVD)法，所述底层金属间介电层的材料包括但不限于二氧化硅(SiO 2)。
接下来，对所述底层金属间介电层执行化学机械抛光以实现平整化，并在部分底层金属层2011上方的底层金属间介电层和底层抗反射层中刻蚀形成底层接触孔开口，在底层接触孔开口中填充金属以形成底层接触孔(CT)，以实现金属布线的多个金属层之间的互连。
在本实施例中，如图2所示，在底层金属间介电层上方形成第一金属层2012，所述第一金属层2012形成方法与材料与所述底层金属层2011的形成方法与材料相同，在此不再赘述。
接下来，执行步骤S302，在所述第一金属层上形成第一抗反射层。
在本实施例中，在所述第一金属层2012上形成第一抗反射层，所述第一抗反射层的形成方法与材料与上述底层抗反射层的形成方法与材料相同，在此不再赘述。
接下来，执行步骤S303，如图2所示，光刻并刻蚀所述第一金属层2012和所述第一抗反射层，以定义MIM电容区域，以所述MIM电容区域中的所述第一金属层作为MIM电容的下极板201，以所述MIM电容区域中的所述第一抗反射层作为MIM电容的介质层202。
示例性地，形成覆盖所述第一抗反射层的光刻胶层(图2未示出)，然后采用光刻工艺图案化所述光刻胶层，以定义MIM电容区域。以所述图案化后的光刻胶层为掩模，刻蚀所述第一金属层2012和所述第一抗反射层，刻蚀后，MIM电容区域中的第一金属层作为MIM电容的下极板201，MIM电容区域中的第一抗反射层作为MIM电容的介质层202。在其他实施例中，形成覆盖所述第一抗反射层的光刻胶层(图2未示出)，然后采用光刻工艺图案化所述光刻胶层，同时形成定义MIM电容区域和其他电路区域的图案。以所述图案化的光刻胶层为掩模，刻蚀所述第一金属层2012和所述第一抗反射层，MIM电容区域中的第一金属层作为MIM电容的下极板201，MIM电容区域中的第一抗反射层作为MIM电容的介质层202。在金属布线过程中，同时定义 MIM电容区域和其他电路区域，从而将彼此独立的金属布线工艺和MIM电容的制作结合在同一步骤中完成。作为一个实例，所述MIM电容的下极板201的厚度为2000埃至5000埃，所述MIM电容的介质层202的厚度为200埃至500埃。
接下来，执行步骤S304，在所述MIM电容区域中的所述第一抗反射层上形成MIM电容的上极板203，其步骤包括：在第一抗反射层上形成第一金属间介电层，光刻并刻蚀第一金属间介电层，在所述第一金属间介电层中形成上极板开口，所述上极板开口暴露部分所述第一抗反射层，即上极板开口暴露MIM电容的部分介质层202；在所述上极板开口中填充金属以形成所述MIM电容的上极板203。其中，在所述MIM电容区域中，在所述第一金属间介电层中形成上极板开口的同时，还进行光刻和刻蚀，形成依次贯穿所述第一金属间介电层和所述第一抗反射层的至少一个第一接触孔开口(CT)，所述第一接触孔开口暴露部分所述第一金属层，即第一接触孔开口暴露MIM电容的部分下极板201，第一接触孔实现金属布线的多个金属层之间的互连。第一接触孔开口位于上极板开口的周围。在其他实施例中，在同时具有MIM电容区域和其他电路区域的半导体器件的制作过程中，形成MIM电容的上极板开口和至少一个第一接触孔开口的同时，还在其他电路区域进行光刻并刻蚀，形成至少一个其他电路区域的接触孔开口，从而将彼此独立的金属布线工艺和MIM电容的制作结合在同一步骤中完成。
进一步，所述MIM电容的上极板203和所述第一接触孔的填充材料包括但不限于钨，形成所述MIM电容的上极板203和所述第一接触孔的方法可以选用化学气相沉积(CVD)法、物理气相沉积(PVD)法或原子层沉积(ALD)法等。作为一个实例，所述上极板的面积为10E2um 2至10E6um 2，所述MIM电容的上极板的厚度为5000埃至8000埃。在其他实施例中，同时填充MIM电容的上极板开口、第一接触孔开口及其他电路区域的接触孔开口，同时形成MIM电容的上极板、第一接触孔及其他电路区域的接触孔，可进一步缩短工艺周期。
通过上述方法，采用钨填充形成接触孔的同时进行钨填充形成MIM电容的上极板，不再需要额外的光刻工艺来定义上极板区域，从而减少了光刻工 艺的次数，降低了工艺成本，缩短了工艺周期。
接下来，在所述MIM电容区域中的所述第一抗反射层上形成MIM电容的上极板203的步骤之后，还包括：形成第二金属层2013并光刻及刻蚀，以图形化所述第二金属层2013。
在本实施例中，光刻及刻蚀前的第二金属层2013所述MIM电容的上极板203、所述第一接触孔以及所述第一金属间介电层，所述第二金属层2013的形成方法与材料和所述底层金属层2011的形成方法与材料相同，在此不再赘述。
接下来，在形成第二金属层并光刻及刻蚀，以图形化所述第二金属层的步骤之后，还包括：形成第二金属间介电层，并在所述第二金属层间介电层中形成至少一个第二接触孔。示例性地，如图2所示，第二接触孔205与第二金属层2013电连接，第二接触孔205位于MIM电容区域中的第二金属层2013上方。在其他实施例中，在第二金属层2013与第二金属间介电层之间还形成有第二抗反射层。
接下来，在第二金属间介电层上形成顶层金属层2014并光刻及刻蚀，以图形化所述顶层金属层2014。具体地，所述顶层金属层2014的形成方法与材料和所述底层金属层2011的形成方法与材料相同，在此不再赘述。
如图2所示，所述MIM电容的上极板203和所述MIM电容的下极板201分别引出至顶层金属层2014。具体地，MIM电容的上极板203依次通过MIM电容区域中的第二金属层2013、MIM电容区域中的第二接触孔205引出至第一顶层金属层。MIM电容的下极板201依次通过第一接触孔、MIM电容区域中的第二金属层2013和MIM电容区域中的第二接触孔引出至第二顶层金属层。
根据本发明提供的MIM电容的制作方法，在金属布线过程中，同时定义MIM电容区域和其他电路区域，从而将彼此独立的金属布线工艺和MIM电容的制作结合在同一步骤中完成；在刻蚀后的刻开区域中保留下来的抗反射层同时作为电容的介质层，继续在刻开区域中填充金属作为上极板，不再需 要制作额外的电容的介质层，也不再需要额外的光刻工艺来定义上极板区域，减少了光刻和刻蚀的次数，从而降低了工艺成本，缩短了工艺周期。
参照图2，本发明还提供了一种MIM电容，其包括：
半导体衬底，所述半导体衬底上形成有第一金属层；
所述第一金属层上形成有抗反射层；
所述半导体衬底包括MIM电容区域和其他电路区域，所述MIM电容区域中的所述第一金属层作为MIM电容的下极板，所述MIM电容区域中的所述抗反射层作为MIM电容的介质层；
所述MIM电容区域中的所述抗反射层上形成有MIM电容的上极板。
示例性地，所述半导体衬底可以是以下所提到的材料中的至少一种：单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。在半导体衬底中还形成有隔离结构(图2未示出)，所述隔离结构为浅沟槽隔离(STI)结构或者局部氧化硅(LOCOS)隔离结构，隔离结构将基底分为不同的有源区，有源区中可以形成各种半导体器件，例如NMOS和PMOS等。
示例性地，金属布线包括在半导体衬底上形成多个金属层及互连结构。随着技术的进步，半导体器件金属布线过程中形成的金属层数逐渐增加。在本实施例中，仅介绍其中四层金属层及互连结构的形成，包括由下至上依次形成的底层金属层2011、第一金属层2012、第二金属层2013和顶层金属层2014。进一步，上述金属层的材料包括但不限于铜(Cu)或铝(Al)。
在本实施例中，半导体衬底包括MIM电容区域和其他电路区域，其中，位于MIM电容区域中的第一金属层2012作为MIM电容的下极板201。作为一个实例，所述MIM电容的下极板201的厚度为2000埃至5000埃。
示例性地，在底层金属层2011、第一金属层2012、第二金属层2013上分别形成有底层抗反射层、第一抗反射层和第二抗反射层。进一步，上述抗反射层的材料包括氮氧化硅(SION)。
在本实施例中，所述第一金属层2012上方形成有第一抗反射层，MIM 电容区域中的第一抗反射层作为MIM电容的介质层202。作为一个实例，所述MIM电容的介质层的厚度为200埃至500埃。
示例性地，在底层金属层2011与第一金属层2012间由底层接触孔电连接、第一金属层2012与第二金属层2013之间由第一接触孔电连接，第二金属层2013与顶层金属2014之间由第二接触孔电连接，最终实现多个金属层之间的互连。进一步，上述接触孔的材料包括钨。
示例性地，所述MIM电容的介质层202的上方形成有MIM电容的上极板203。进一步，所述MIM电容的上极板203的材料包括钨。作为一个实例，所述上极板的面积为10E2um 2至10E6um 2，所述MIM电容的上极板的厚度为5000埃至8000埃。
示例性地，所述MIM电容的上极板203上形成有第二金属层2013。进一步，MIM电容的下极板201的面积等于MIM电容的介质层202的面积，MIM电容的上极板203的面积小于或等于MIM电容的介质层202的面积。
示例性地，在第二金属层2013的上方还形成有顶层金属层2014。
进一步，所述MIM电容的上极板203和所述MIM电容的下极板201分别引出至顶层金属层2014。具体地，MIM电容的上极板203通过第二金属层2013、第二接触孔205引出至第一顶层金属层。MIM电容的下极板201通过第一接触孔、第二金属层2013和第二接触孔引出至第二顶层金属层。所述第一顶层金属层和所述第二顶层金属层由第三金属间介电层隔开。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (15)

  1. 一种MIM电容的制作方法，包括以下步骤：
    提供半导体衬底，在所述半导体衬底上形成第一金属层；
    在所述第一金属层上形成抗反射层；
    光刻并刻蚀所述第一金属层和所述抗反射层，以定义MIM电容区域，所述MIM电容区域中的所述第一金属层作为MIM电容的下极板，所述MIM电容区域中的所述抗反射层作为MIM电容的介质层；及
    在所述MIM电容区域中的所述抗反射层上形成MIM电容的上极板。
  2. 如权利要求1所述的制作方法，其中，所述在所述MIM电容区域中的所述抗反射层上形成所述MIM电容的上极板的步骤包括：
    形成第一金属间介电层并光刻及刻蚀，在所述第一金属间介电层中形成上极板开口，所述上极板开口暴露部分所述抗反射层；
    在所述上极板开口中填充金属以形成所述MIM电容的上极板。
  3. 如权利要求2所述的制作方法，其中，所述在所述第一金属间介电层中形成上极板开口，所述上极板开口暴露部分所述抗反射层的步骤还包括：
    在所述上极板开口的区域外、所述MIM电容区域中光刻并刻蚀所述第一金属间介电层和所述抗反射层，形成依次贯穿所述第一金属间介电层和所述抗反射层的至少一个第一接触孔开口，所述第一接触孔开口暴露部分所述第一金属层；
    所述在所述上极板开口中填充金属以形成所述MIM电容的上极板的步骤还包括：
    在所述第一接触孔开口中填充金属以形成第一接触孔。
  4. 如权利要求3所述的制作方法，其中，所述在所述MIM电容区域中的所述抗反射层上形成MIM电容的上极板的步骤之后，还包括：
    形成第二金属层并光刻及刻蚀，以图形化所述第二金属层。
  5. 如权利要求4所述的制作方法，其中，所述在形成第二金属层并光刻及刻蚀，以图形化所述第二金属层的步骤之后，还包括：
    形成第二金属间介电层，并在所述第二金属层间介电层中形成至少一个第二接触孔；
    在第二金属间介电层上形成顶层金属层并光刻及刻蚀，以图形化所述顶层金属层。
  6. 如权利要求5所述的制作方法，其中，所述MIM电容的上极板和所述MIM电容的下极板分别引出至顶层金属层。
  7. 如权利要求6所述的制作方法，其中，所述MIM电容的上极板依次通过所述MIM电容区域中的第二金属层、MIM电容区域中的第二接触孔引出至所述顶层金属层；
    所述MIM电容的下极板依次通过所述第一接触孔、所述MIM电容区域中的第二金属层和所述MIM电容区域中的第二接触孔引出至所述顶层金属层。
  8. 如权利要求3所述的制作方法，其中，所述形成第一金属间介电层并光刻及刻蚀，在所述第一金属间介电层中形成上极板开口的步骤，以及在所述上极板开口的区域外、所述MIM电容区域中光刻并刻蚀所述第一金属间介电层和所述抗反射层，形成依次贯穿所述第一金属间介电层和所述抗反射层的至少一个第一接触孔开口的步骤的同时，还在MIM电容所在半导体器件的其他电路区域进行光刻并刻蚀，形成至少一个其他电路区域的接触孔开口。
  9. 如权利要求3所述的制作方法，其中，所述上极板的尺寸大于所述第一接触孔的尺寸。
  10. 如权利要求1所述的制作方法，其中，所述MIM电容的介质层材料包括氮氧化硅。
  11. 如权利要求1所述的制作方法，其中，所述MIM电容的介质层的厚度为200埃至500埃。
  12. 一种MIM电容，包括：
    半导体衬底；
    第一金属层，形成于所述半导体衬底上；
    抗反射层，形成于所述第一金属层上；以及
    MIM电容的上极板，形成于MIM电容区域中的所述抗反射层上；
    其中，所述MIM电容区域中的所述第一金属层作为MIM电容的下极板，所述MIM电容区域中的所述抗反射层作为MIM电容的介质层。
  13. 如权利要求12所述的MIM电容，其中，所述上极板的面积为10E2 um 2至10E6um 2。
  14. 如权利要求12所述的MIM电容，其中，所述MIM电容的上极板的厚度为5000埃至8000埃，所述MIM电容的下极板的厚度为2000埃至5000埃，所述MIM电容的介质层的厚度为200埃至500埃。
  15. 如权利要求12所述的MIM电容，其中，所述MIM电容的介质层材料包括氮氧化硅。
PCT/CN2019/116996 2018-11-16 2019-11-11 一种mim电容及其制作方法 Ceased WO2020098581A1 (zh)

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