WO2020098349A1 - 一种基于时钟周期的脉宽调制信号占空比倍增电路 - Google Patents

一种基于时钟周期的脉宽调制信号占空比倍增电路 Download PDF

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WO2020098349A1
WO2020098349A1 PCT/CN2019/104383 CN2019104383W WO2020098349A1 WO 2020098349 A1 WO2020098349 A1 WO 2020098349A1 CN 2019104383 W CN2019104383 W CN 2019104383W WO 2020098349 A1 WO2020098349 A1 WO 2020098349A1
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width modulation
pulse width
modulation signal
multiplication
clock
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PCT/CN2019/104383
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English (en)
French (fr)
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朱金桥
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上海客益电子有限公司
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Publication of WO2020098349A1 publication Critical patent/WO2020098349A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation

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  • the invention relates to the field of integrated circuits, and in particular to a duty cycle multiplier circuit for a pulse width modulation signal based on a clock cycle in the field of signal processing.
  • Pulse width modulation (PWM) signal is a very common type of signal in electronic systems. It has the dual properties of analog and digital signals, and plays an important role in signal acquisition and transmission, signal conditioning, sensors, signal isolation and other fields. Many traditional pulse-width modulation (PWM) signals are generated by analog circuits. Once generated, they cannot be effectively signal-conditioned, resulting in greater limitations in applications.
  • PWM pulse width modulation
  • the object of the present invention is to provide a duty cycle multiplier circuit for a pulse width modulation signal based on a clock cycle.
  • the duty ratio in the present invention refers to the ratio of the high-level pulse width or the low-level pulse width of the pulse width modulation signal to the period of the pulse width modulation signal.
  • the high-level pulse duty ratio refers to the ratio of the high-level pulse width of the pulse width modulation signal to the period of the pulse width modulation signal.
  • the low-level pulse duty cycle refers to the ratio of the low-level pulse width of the pulse-width modulation signal to the period of the pulse-width modulation signal.
  • the present invention provides a duty cycle multiplier circuit for a pulse width modulation signal based on a clock cycle, and a clock signal CLK and an original pulse width modulation signal PWM1 are input to the input terminal; the high power of the original pulse width modulation signal PWM1
  • the flat duration is the sum of the clock cycles of the N clock signals CLK
  • the low-level duration of the original pulse width modulation signal PWM1 is the sum of the clock cycles of the M clock signals CLK
  • the output terminal outputs the duty cycle
  • the pulse width modulation signal PWM2 after the multiplication, the high level and the low level duration of the pulse width modulation signal PWM2 after the duty cycle multiplication are the sum of an integer number of clock cycles of the clock signal CLK, the duty
  • the period of the pulse width modulation signal PWM2 after the ratio multiplication is equal to the period of the original pulse width modulation signal PWM1; the high level duration of the pulse width modulation signal PWM2 after the duty ratio multiplication is K * N clock signals
  • the parameter K is equal to 2.
  • the duty cycle multiplying circuit of the pulse width modulation signal based on the clock period includes:
  • the duty cycle multiplication enables the pulse generation circuit, and the input terminal inputs the clock signal CLK and the original pulse width modulation signal PWM1, the duration of the high level and low level of the original pulse width modulation signal PWM1 are both integers of the clock signal CLK
  • Duty cycle multiplication circuit its input terminal inputs the PWM multiplication start enable pulse signal Pulse1 and the PWM multiplication end enable pulse signal Pulse2, and its output end outputs the duty cycle doubled pulse width modulation signal PWM2
  • the pulse width of the pulse width modulation signal PWM2 after the duty ratio multiplication is adapted to the PWM multiplication start enable pulse signal Pulse1 and the PWM multiplication end enable pulse signal Pulse2, and the pulse after the duty ratio multiplication
  • the wide modulation signal PWM2 performs signal synchronization through the clock signal CLK to ensure that the high-level and low-level durations of the pulse width modulation signal PWM2 after the duty cycle is doubled are the sum of an integer number of clock cycles of the clock signal CLK.
  • the duty ratio doubling enable pulse generating circuit includes:
  • a duty cycle multiplication start enable pulse generating circuit the input terminal inputs the clock signal CLK and the original pulse width modulation signal PWM1, and the output end outputs the PWM multiplication start enable pulse signal Pulse1;
  • the duty cycle multiplication end enable pulse generation circuit has the input terminal input the clock signal CLK and the original pulse width modulation signal PWM1, and the output end thereof outputs the PWM multiplication end enable pulse signal Pulse2.
  • the duty cycle multiplying end enable pulse generating circuit further includes:
  • a first counter whose input terminal inputs the clock signal CLK and the original pulse width modulation signal PWM1 for counting the number of cycles of the clock signal CLK corresponding to the pulse duration of the original pulse width modulation signal PWM1; the first The counter starts counting after the pulse of the original pulse width modulation signal PWM1 starts, and holds and outputs the first count value after the end of the pulse of the original pulse width modulation signal PWM1;
  • the second counter whose input terminal inputs the clock signal CLK and the original pulse width modulation signal PWM1, is used to count the period of the original pulse width modulation signal PWM1 pulse at any end until the next end of the corresponding clock signal CLK Number of cycles; the second counter starts counting after the end of the original pulse width modulation signal PWM1 pulse, and continuously counts, and outputs the second count value;
  • the input terminal inputs the first count value and the second count value, when the values of the first count value and the second count value are not equal, the output remains at a low level, When the first count value and the second count value are equal, the PWM multiplication end enable pulse Pulse2 is output.
  • the PWM multiplication start enable pulse signal Pulse1 may be high level or low level
  • the PWM multiplication end enable pulse signal Pulse2 may be high level or low level.
  • the rising and falling edges of the original pulse width modulation signal PWM1 are synchronized with the rising edges of the clock signal CLK, or the rising and falling edges of the original pulse width modulation signal PWM1 are synchronized with the clock signal CLK The falling edge is synchronized.
  • the duty cycle multiplication circuit is further implemented:
  • the falling edge of the clock signal CLK is used to trigger the rising or falling edge of the pulse width modulation signal PWM2 after the duty ratio is doubled;
  • the falling edge of the clock signal CLK is used to trigger the falling edge or the rising edge of the pulse width modulation signal PWM2 after the duty ratio is doubled.
  • the duty cycle multiplication circuit is further implemented:
  • the rising edge of the clock signal CLK is used to trigger the rising or falling edge of the pulse width modulation signal PWM2 after the duty cycle is doubled;
  • the falling edge or rising edge of the pulse width modulation signal PWM2 after the duty ratio multiplication is triggered by the rising edge of the clock signal CLK.
  • the present invention also provides a pulse width modulation signal duty cycle multiplication method using a clock cycle-based pulse width modulation signal duty cycle multiplication circuit as described above.
  • the method includes the following processes:
  • Duty cycle multiplication enable pulse generation circuit outputs PWM multiplication start enable pulse signal Pulse1 and PWM multiplication end enable pulse signal Pulse2;
  • the duty ratio doubling circuit inputs the PWM multiplication start enable pulse signal Pulse1 and the PWM multiplication end enable pulse signal Pulse2, and triggers by the rising or falling edge of the clock signal CLK to form the duty ratio multiplication The pulse width modulation signal PWM2.
  • the beneficial effects of the present invention are as follows: the present invention can easily double the duty cycle of the PWM signal by synchronizing the original pulse width modulation signal PWM1 based on the clock cycle and cooperate with the corresponding control circuit Features.
  • FIG. 1 is a circuit diagram of a pulse width modulation signal duty cycle multiplication circuit based on a clock cycle of the present invention
  • FIG. 2 is a schematic diagram of a duty-doubling enable pulse generating circuit of the present invention
  • 3 is a timing diagram of the operation of the pulse width modulation signal high-level pulse duty cycle multiplication circuit of the present invention
  • FIG. 4 is a timing diagram of the operation of the pulse width modulation signal low-level pulse duty cycle multiplication circuit of the present invention.
  • a duty cycle multiplying circuit of a pulse width modulation signal based on a clock cycle includes a duty cycle multiplying enable pulse generating circuit 101 and a duty cycle multiplying circuit 102.
  • the duty cycle multiplication enables the input terminal of the pulse generation circuit 101 to input the clock signal CLK and the original pulse width modulation signal PWM1, and the original pulse width modulation signal PWM1 performs signal synchronization through the clock signal CLK to ensure the high level and low power of the PWM1 signal
  • the flat duration is the sum of an integer number of clock cycles of the clock signal CLK.
  • the rising edge and falling edge of the original pulse width modulation signal PWM1 are synchronized with the rising edge of the clock signal CLK, or the rising edge and falling edge of the original pulse width modulation signal PWM1 are synchronized with the falling edge of the clock signal CLK; wherein, the original pulse
  • the duration of the high level of the wide modulation signal PWM1 is the sum of the clock cycles of the N clock signals CLK
  • the duration of the low level of the original pulse width modulation signal PWM1 is the sum of the clock cycles of the M clock signals CLK
  • parameter N , M are integers greater than 0.
  • the output terminal of the duty ratio multiplication enable pulse generation circuit 101 outputs the PWM multiplication start enable pulse signal Pulse1 and the PWM multiplication end enable pulse signal Pulse2 and sends it to the duty ratio multiplication circuit 102.
  • the input terminal of the duty ratio doubling circuit 102 inputs the PWM multiplication start enable pulse signal Pulse1 and the PWM multiplication end enable pulse signal Pulse2, and the output end thereof outputs the pulse width modulation signal PWM2 after the duty ratio multiplication.
  • the PWM multiplication start enable pulse signal Pulse1 may be a high level or a low level
  • the PWM multiplication start enable pulse signal Pulse2 may be a high level or a low level.
  • the duty cycle multiplication enable pulse generation circuit 101 includes a duty cycle multiplication start enable pulse generation circuit 201 and a duty cycle multiplication end enable pulse generation circuit 202.
  • a clock signal CLK and an original pulse width modulation signal PWM1 are input to the input terminal of the duty cycle multiplication start enable pulse generation circuit 201, and its output terminal outputs the PWM multiplication start enable pulse Pulse1.
  • the input terminal of the duty multiplication end enable pulse generating circuit 202 inputs the clock signal CLK and the original pulse width modulation signal PWM1, and the output end thereof outputs the PWM multiplication end enable pulse Pulse2.
  • the duty multiplication end enable pulse generation circuit 202 includes a first counter 203, a second counter 204 and a count value comparison circuit 205.
  • the input terminal of the first counter 203 inputs the clock signal CLK and the original pulse width modulation signal PWM1.
  • the first counter 203 is used to count the number of cycles of the CLK signal corresponding to the pulse duration of the original pulse width modulation signal PWM1.
  • the first counter 203 is in PWM1 Counting starts after the start of the pulse, and holds and outputs the first count value Count1 after the end of the PWM1 pulse.
  • the input terminal of the second counter 204 inputs the clock signal CLK and the original pulse width modulation signal PWM1.
  • the second counter 204 is used to count the corresponding clock signal CLK during the period from the end of the original pulse width modulation signal PWM1 pulse to the end of the next In the number of cycles, the second counter 204 starts counting after the end of the PWM1 pulse and continuously counts, and outputs the second count value Count2.
  • the first count value Count1 and the second count value Count2 are input to the input terminal of the count value comparison circuit 205.
  • the output is kept at a low level, and when the two values are equal, the output PWM multiplication end is enabled Pulse2.
  • the pulse width modulation signal duty ratio doubling circuit of the present invention can double the duty ratio of the high level pulse of the original pulse width modulation signal PWM1 or can double the duty ratio of the low level pulse of the original pulse width modulation signal PWM1.
  • the PWM multiplication start enable pulse signal Pulse1 and the PWM multiplication end enable pulse signal Pulse2 determine the pulse width of the pulse width modulation signal PWM2 after the duty ratio multiplication, and the pulse width modulation signal after the duty ratio multiplication PWM2 performs signal synchronization through the clock signal CLK to ensure that the duration of the high level and low level of the pulse width modulation signal PWM2 after the duty cycle is doubled is still the sum of an integer number of clock cycles of the clock signal CLK.
  • the duty ratio doubling circuit 102 may further realize that the pulse of the pulse signal Pulse1 at the start of the PWM multiplication start continues During the period, the falling edge of the clock signal CLK triggers the rising or falling edge of the pulse width modulation signal PWM2 after the duty cycle multiplication; when the pulse duration of the enable pulse Pulse2 ends at the PWM multiplication end, the falling of the clock signal CLK is used Edge triggering generates a falling or rising edge of the pulse width modulation signal PWM2 after the duty cycle is doubled.
  • the high-level duration of the pulse width modulation signal PWM2 after the duty ratio is doubled is the sum of the clock cycles of the K * N clock signals CLK or the low-level duration of the pulse width modulation signal PWM2 after the duty ratio is doubled It is the sum of the clock cycles of K * M clock signals CLK, and the period of the pulse width modulation signal PWM2 after the duty ratio is doubled is equal to the period of the original pulse width modulation signal PWM1.
  • the parameter K represents the multiplication factor and is an integer greater than 1 .
  • the duty cycle multiplication circuit 102 further realizes that the pulse of the pulse signal Pulse1 at the start of the PWM multiplication start continues During the period, the rising edge of the clock signal CLK is used to trigger the rising or falling edge of the pulse width modulation signal PWM2 after the duty cycle is doubled; when the pulse duration of the enable pulse Pulse2 ends at the PWM multiplication end, the rising of the clock signal CLK is used Edge triggering generates a falling or rising edge of the pulse width modulation signal PWM2 after the duty cycle is doubled.
  • the present invention also provides a duty cycle multiplication method based on the above-mentioned clock cycle-based pulse width modulation signal duty cycle multiplication circuit, which includes the following processes:
  • the duty ratio multiplication enable pulse generation circuit 101 outputs the PWM multiplication start enable pulse signal Pulse1 and the PWM multiplication end enable pulse signal Pulse2;
  • the duty ratio doubling circuit 102 inputs the PWM multiplication start enable pulse signal Pulse1 and the PWM multiplication end enable pulse signal Pulse2, and triggers by the rising or falling edge of the clock signal CLK to form a pulse width after the duty ratio multiplication Modulation signal PWM2.
  • the multiplication factor is 2 times, the clock signal CLK period is T, the original pulse width
  • the rising edge of the signal PWM1 triggers the duty cycle doubling start enable pulse generation circuit 201 to output the PWM doubling start enable pulse Pulse1 whose pulse width is T.
  • the first count value Count1 output by the first counter 203 is reset to 0 at the rising edge of the signal PWM1, and then is counted twice after being counted twice during the high level period of the signal PWM1, and the first count value Count1 is after the falling edge of the signal PWM1 Keep count value 2.
  • the second count value Count2 output by the second counter 204 is reset to 0 at the falling edge of the signal PWM1, and then continuously counts during the low level of the signal PWM1, when the value of the second count value Count2 is equal to that of the first count value Count1
  • the count value comparison circuit 205 outputs the PWM multiplication end enable pulse Pulse2.
  • the falling edge of the clock signal CLK is used to trigger the rising edge of the pulse width modulation signal PWM2 (which may be referred to as the signal PWM2 hereinafter) after the duty cycle multiplication.
  • the falling edge of the clock signal CLK is used to trigger the falling edge of the pulse width modulation signal PWM2 after the duty cycle is doubled.
  • the multiplication factor is 2 times, the clock signal CLK period is T, the original pulse
  • the falling edge of the signal PWM1 triggers the duty cycle doubling start enable pulse generation circuit 201 to output the PWM doubling start enable pulse Pulse1 whose pulse width is T.
  • the first count value Count1 output by the first counter 203 is reset to 0 at the falling edge of the signal PWM1, and then counted twice after two counts during the low level period of the signal PWM1, and the first count value Count1 is after the rising edge of the signal PWM1 Keep count value 2.
  • the second count value Count2 output by the second counter 204 is reset to 0 at the rising edge of the signal PWM1, and then continuously counts during the high level of the signal PWM1, when the value of the second count value Count2 is equal to the first count value Count1
  • the count value comparison circuit 205 outputs the PWM multiplication end enable pulse Pulse2.
  • the falling edge of the clock signal CLK is used to trigger the falling edge of the pulse width modulation signal PWM2 (which may be referred to as the signal PWM2 hereinafter) after the duty cycle multiplication.
  • the falling edge of the clock signal CLK is used to trigger the rising edge of the pulse width modulation signal PWM2 after the duty cycle is doubled.

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Abstract

一种基于时钟周期的脉宽调制信号占空比倍增电路，包含：占空比倍增使能脉冲产生电路（101），输入端输入时钟信号（CLK）和原始脉宽调制信号（PWM1），原始脉宽调制信号（PWM1）的高电平和低电平的持续时间都是时钟信号（CLK）的整数个时钟周期之和，输出端输出PWM倍增起始使能脉冲信号（Pulse1）和PWM倍增结束使能脉冲信号（Pulse2）；占空比倍增电路（102），输入端输入PWM倍增起始使能脉冲信号（Pulse1）和PWM倍增结束使能脉冲信号（Pulse2），输出端输出占空比倍增后的脉宽调制信号（PWM2），其中，占空比倍增后的脉宽调制信号（PWM2）的脉冲宽度与PWM倍增起始使能脉冲信号（Pulse1）和PWM倍增结束使能脉冲信号（Pulse2）相适配，且占空比倍增后的脉宽调制信号（PWM2）通过时钟信号（CLK）进行信号同步，保证占空比倍增后的脉宽调制信号（PWM2）的高电平和低电平持续时间都是时钟信号（CLK）的整数个时钟周期之和。通过将原始脉宽调制信号（PWM1）同步化并基于时钟周期，并配合相应的控制电路，十分便利地实现PWM信号的占空比倍增功能。

Description

一种基于时钟周期的脉宽调制信号占空比倍增电路 技术领域
本发明涉及集成电路领域，尤其涉及在信号处理领域中的一种基于时钟周期的脉宽调制信号占空比倍增电路。
背景技术
脉宽调制(PWM)信号是电子系统中非常常用的一类信号，它具有模拟信号和数字信号的双重属性，在信号采集与传输、信号调理、传感器、信号隔离等领域都发挥着重要作用。传统的脉宽调制(PWM)信号很多通过模拟电路产生，一旦产生便无法对其进行有效地信号调理，从而导致在应用中产生较大的局限性。
在电路系统的实践中，需要对已有PWM信号进行占空比倍增处理，从而可以实现精确的模拟量加倍的功能，便于系统进行精确控制，传统的方法却无法实现这一功能。
基于上述原因，需要提出一种基于时钟周期的脉宽调制信号占空比倍增电路实为必要。
发明的公开
本发明的目的在于提供一种基于时钟周期的脉宽调制信号占空比倍增电路，通过将原始脉宽调制信号PWM1同步化以及基于时钟周期，并配合相应的控制电路，从而可以十分便利地实现PWM信号的占空比倍增功能。本发明中的占空比是指脉宽调制信号的高电平脉冲宽度或者低电平脉冲宽度与脉宽调制信号周期的比值。高电平脉冲占空比是指脉宽调制信号的高电平脉冲宽度与脉宽调制信号周期的比值。低电平脉冲占空比是指脉宽调制信号的低电平脉冲宽度与脉宽调制信号周期的比值。
为了达到上述目的，本发明提供一种基于时钟周期的脉宽调制信号占空比倍增电路，其输入端输入时钟信号CLK和原始脉宽调制信号PWM1；所述原始脉宽调制信号PWM1的高电平的持续时间是N个时钟信号CLK的时钟周期之和，所述原始脉宽调制信号PWM1的低电平的持续时间是M个时钟信号CLK的时钟周期之和；其输出端输出占空比倍增后的脉宽调制信号PWM2，所述占空比倍增后的脉宽调制信号PWM2的高电平和低电平持续时间都是所述时钟信号CLK的整数个时钟周期之和，所述占空比倍增后的脉宽调制信号PWM2的周期与所述原始脉宽调制信号PWM1的周期相等；所述占空比倍增后的脉宽调制信号PWM2的高电平持续时间是K*N个时钟信号CLK的时钟周期之和，或者所述占空比倍增后的脉宽调制信号PWM2的低电平持续时间是K*M个时钟信号CLK的时钟周期之和；其中，参数N、M均为大于0的整数，参数K为大于1的整数。
优选地，所述参数K等于2。
优选地，基于时钟周期的脉宽调制信号占空比倍增电路包含：
占空比倍增使能脉冲产生电路，其输入端输入时钟信号CLK和原始脉宽调制信号PWM1，所述原始脉宽调制信号PWM1的高电平和低电平的持续时间都是时钟信号CLK的整数个时钟周期之和，其输出端输出PWM倍增起始使能脉冲信号Pulse1和PWM倍增结束使能脉冲信号Pulse2；
占空比倍增电路，其输入端输入所述PWM倍增起始使能脉冲信号Pulse1和所述PWM倍增结束使能脉冲信号Pulse2，其输出端输出占空比倍增后的脉宽调制信号PWM2；所述占空比倍增后的脉宽调制信号PWM2的脉冲宽度与所述PWM倍增起始使能脉冲信号Pulse1和PWM倍增结束使能脉冲信号Pulse2相适配，且所述占空比倍增后的脉宽调制信号PWM2通过所述时钟信号CLK进行信号同步，保证占空比倍增后的脉宽调制信号PWM2的高电平和低电平持续时间是所述时钟信号CLK的整数个时钟周期之和。
优选地，所述占空比倍增使能脉冲产生电路包含：
占空比倍增起始使能脉冲产生电路，其输入端输入所述时钟信号CLK和所述原始脉宽调制信号PWM1，其输出端输出所述PWM倍增起始使能脉冲信号Pulse1；
占空比倍增结束使能脉冲产生电路，其输入端输入所述时钟信号CLK 和所述原始脉宽调制信号PWM1，其输出端输出PWM倍增结束使能脉冲信号Pulse2。
优选地，所述占空比倍增结束使能脉冲产生电路进一步包含：
第一计数器，其输入端输入所述时钟信号CLK和所述原始脉宽调制信号PWM1，用于统计原始脉宽调制信号PWM1的脉冲持续时间所对应的时钟信号CLK的周期数；所述第一计数器在原始脉宽调制信号PWM1脉冲开始后开始计数，并且在原始脉宽调制信号PWM1脉冲结束后保持并输出第一计数值；
第二计数器，其输入端输入所述时钟信号CLK和所述原始脉宽调制信号PWM1，用于统计原始脉宽调制信号PWM1脉冲任意一次结束直至下一次结束的期间内所对应的时钟信号CLK的周期数；所述第二计数器在原始脉宽调制信号PWM1脉冲结束后开始计数，并连续进行计数，输出第二计数值；
计数值比较电路，其输入端输入所述第一计数值和所述第二计数值，当所述第一计数值和所述第二计数值的数值不相等时，输出保持为低电平，当所述第一计数值和所述第二计数的数值相等时，输出所述PWM倍增结束使能脉冲Pulse2。
优选地，所述PWM倍增起始使能脉冲信号Pulse1可为高电平或者低电平，所述PWM倍增结束使能脉冲信号Pulse2可为高电平或者低电平。
优选地，所述原始脉宽调制信号PWM1的上升沿和下降沿与所述时钟信号CLK的上升沿同步，或者，所述原始脉宽调制信号PWM1的上升沿和下降沿与所述时钟信号CLK的下降沿同步。
优选地，当所述原始脉宽调制信号PWM1的上升沿和下降沿与所述时钟信号CLK的上升沿同步时，所述占空比倍增电路中进一步实现：
在所述PWM倍增起始使能脉冲信号Pulse1的脉冲持续期间时，用时钟信号CLK的下降沿触发产生占空比倍增后的脉宽调制信号PWM2的上升沿或者下降沿；
在所述PWM倍增结束使能脉冲Pulse2的脉冲持续期间时，用时钟信号CLK的下降沿触发产生占空比倍增后的脉宽调制信号PWM2的下降沿或者上升沿。
优选地，当所述原始脉宽调制信号PWM1的上升沿和下降沿与所述时钟 信号CLK的下降沿同步时，所述占空比倍增电路中进一步实现：
在所述PWM倍增起始使能脉冲信号Pulse1的脉冲持续期间时，用时钟信号CLK的上升沿触发产生占空比倍增后的脉宽调制信号PWM2的上升沿或者下降沿；
在所述PWM倍增结束使能脉冲Pulse2的脉冲持续期间时，用时钟信号CLK的上升沿触发产生占空比倍增后的脉宽调制信号PWM2的下降沿或者上升沿。
本发明还提供一种采用如上文所述的基于时钟周期的脉宽调制信号占空比倍增电路的脉宽调制信号占空比倍增方法，该方法包含以下过程：
确定所述脉宽调制信号占空比倍增电路对原始脉宽调制信号PWM1的高电平脉冲进行占空比倍增，或者对原始脉宽调制信号PWM1的低电平脉冲进行占空比倍增，并预设占空比倍增的倍数以及时钟信号CLK的周期；
设置原始脉宽调制信号PWM1与时钟信号CLK进行信号同步的方式；
设定所述原始脉宽调制信号PWM1的高电平以及低电平的脉冲宽度；
占空比倍增使能脉冲产生电路输出PWM倍增起始使能脉冲信号Pulse1和PWM倍增结束使能脉冲信号Pulse2；
占空比倍增电路输入所述PWM倍增起始使能脉冲信号Pulse1和所述PWM倍增结束使能脉冲信号Pulse2，并通过时钟信号CLK的上升沿或者下降沿进行触发，以形成占空比倍增后的脉宽调制信号PWM2。
与现有技术相比，本发明的有益效果为：本发明通过将原始脉宽调制信号PWM1同步化并基于时钟周期，并配合相应的控制电路，可以十分便利地实现PWM信号的占空比倍增功能。
附图的简要说明
图1为本发明的一种基于时钟周期的脉宽调制信号占空比倍增电路的电路图；
图2为本发明的占空比倍增使能脉冲产生电路示意图；
图3为本发明的脉宽调制信号高电平脉冲占空比倍增电路工作的时序图；
图4为本发明的脉宽调制信号低电平脉冲占空比倍增电路工作的时序图。
实现本发明的最佳方式
为了使本发明更加明显易懂，以下结合附图和具体实施方式对本发明做进一步说明。
如图1所示，本发明提供的一种基于时钟周期的脉宽调制信号占空比倍增电路包含有占空比倍增使能脉冲产生电路101和占空比倍增电路102。
占空比倍增使能脉冲产生电路101的输入端输入时钟信号CLK和原始脉宽调制信号PWM1，并且原始脉宽调制信号PWM1通过时钟信号CLK进行信号同步，以保证PWM1信号的高电平和低电平的持续时间都是时钟信号CLK的整数个时钟周期之和。具体地，原始脉宽调制信号PWM1的上升沿和下降沿与时钟信号CLK的上升沿同步，或者原始脉宽调制信号PWM1的上升沿和下降沿与时钟信号CLK的下降沿同步；其中，原始脉宽调制信号PWM1的高电平的持续时间是N个时钟信号CLK的时钟周期之和，原始脉宽调制信号PWM1的低电平的持续时间是M个时钟信号CLK的时钟周期之和，参数N、M均为大于0的整数。
占空比倍增使能脉冲产生电路101的输出端输出PWM倍增起始使能脉冲信号Pulse1和PWM倍增结束使能脉冲信号Pulse2并发送至占空比倍增电路102。
占空比倍增电路102的输入端输入PWM倍增起始使能脉冲信号Pulse1和PWM倍增结束使能脉冲信号Pulse2，其输出端输出占空比倍增后的脉宽调制信号PWM2。示例地，PWM倍增起始使能脉冲信号Pulse1可为高电平或者低电平，PWM倍增结束使能脉冲信号Pulse2可为高电平或者低电平。
如图2所示，所述的占空比倍增使能脉冲产生电路101包含占空比倍增起始使能脉冲产生电路201和占空比倍增结束使能脉冲产生电路202。
占空比倍增起始使能脉冲产生电路201的输入端输入时钟信号CLK和原始脉宽调制信号PWM1，其输出端输出PWM倍增起始使能脉冲Pulse1。
占空比倍增结束使能脉冲产生电路202的输入端输入时钟信号CLK和原始脉宽调制信号PWM1，其输出端输出PWM倍增结束使能脉冲Pulse2。
如图2所示，所述的占空比倍增结束使能脉冲产生电路202包含第一计数器203、第二计数器204和计数值比较电路205。
第一计数器203的输入端输入时钟信号CLK和原始脉宽调制信号 PWM1，第一计数器203用于统计原始脉宽调制信号PWM1脉冲持续时间所对应的CLK信号的周期数，第一计数器203在PWM1脉冲开始后开始计数，并且在PWM1脉冲结束后保持并输出第一计数值Count1。
第二计数器204的输入端输入时钟信号CLK和原始脉宽调制信号PWM1，第二计数器204用于统计原始脉宽调制信号PWM1脉冲每一次结束直至下一次结束的期间内所对应的时钟信号CLK的周期数，第二计数器204在PWM1脉冲结束后开始计数，并连续进行计数，输出第二计数值Count2。
计数值比较电路205的输入端输入第一计数值Count1和第二计数值Count2，当这两者数值不相等时，输出保持为低电平，当两者数值相等时，输出PWM倍增结束使能脉冲Pulse2。
本发明的脉宽调制信号占空比倍增电路可对原始脉宽调制信号PWM1的高电平脉冲进行占空比倍增或者可对原始脉宽调制信号PWM1的低电平脉冲进行占空比倍增。
本发明中，PWM倍增起始使能脉冲信号Pulse1和PWM倍增结束使能脉冲信号Pulse2决定了占空比倍增后的脉宽调制信号PWM2的脉冲宽度，并且占空比倍增后的脉宽调制信号PWM2通过时钟信号CLK进行信号同步，保证占空比倍增后的脉宽调制信号PWM2的高电平和低电平持续时间依然是时钟信号CLK的整数个时钟周期之和。具体地，当原始脉宽调制信号PWM1的上升沿和下降沿与时钟信号CLK的上升沿同步时，占空比倍增电路102中可进一步实现：在PWM倍增起始使能脉冲信号Pulse1的脉冲持续期间时，用时钟信号CLK的下降沿触发产生占空比倍增后的脉宽调制信号PWM2的上升沿或者下降沿；在PWM倍增结束使能脉冲Pulse2的脉冲持续期间时，用时钟信号CLK的下降沿触发产生占空比倍增后的脉宽调制信号PWM2的下降沿或者上升沿。其中，占空比倍增后的脉宽调制信号PWM2的高电平持续时间是K*N个时钟信号CLK的时钟周期之和或者占空比倍增后的脉宽调制信号PWM2的低电平持续时间是K*M个时钟信号CLK的时钟周期之和，且占空比倍增后的脉宽调制信号PWM2的周期与原始脉宽调制信号PWM1的周期相等，参数K表示倍增倍数且为大于1的整数。
另，当原始脉宽调制信号PWM1的上升沿和下降沿与时钟信号CLK的下降沿同步时，所述占空比倍增电路102中进一步实现：在PWM倍增起始 使能脉冲信号Pulse1的脉冲持续期间时，用时钟信号CLK的上升沿触发产生占空比倍增后的脉宽调制信号PWM2的上升沿或者下降沿；在PWM倍增结束使能脉冲Pulse2的脉冲持续期间时，用时钟信号CLK的上升沿触发产生占空比倍增后的脉宽调制信号PWM2的下降沿或者上升沿。
本发明还提供了一种基于上述的基于时钟周期的脉宽调制信号占空比倍增电路的占空比倍增方法，该方法包含以下过程：
确定脉宽调制信号占空比倍增电路对原始脉宽调制信号PWM1的高电平脉冲进行占空比倍增，或者，对原始脉宽调制信号PWM1的低电平脉冲进行占空比倍增，并预设占空比倍增的倍数以及时钟信号CLK的周期；
设置原始脉宽调制信号PWM1与时钟信号CLK进行信号同步的方式；
设定原始脉宽调制信号PWM1的高电平以及低电平的脉冲宽度；
占空比倍增使能脉冲产生电路101输出PWM倍增起始使能脉冲信号Pulse1和PWM倍增结束使能脉冲信号Pulse2；
占空比倍增电路102输入PWM倍增起始使能脉冲信号Pulse1和PWM倍增结束使能脉冲信号Pulse2，并通过时钟信号CLK的上升沿或者下降沿进行触发，以形成占空比倍增后的脉宽调制信号PWM2。
实施例一：
如图3所示，在本发明的一个实施例中，以对脉宽调制信号的高电平脉冲进行占空比倍增为目的，倍增倍数为2倍，时钟信号CLK周期为T，原始脉宽调制信号PWM1(后文可简称信号PWM1)的上升沿和下降沿与时钟信号CLK的上升沿同步，并且信号PWM1的高电平脉冲宽度为2T，信号PWM1的低电平脉冲宽度为6T，即信号PWM1的高电平脉冲占空比为2T/(2T+6T)＝1/4。
信号PWM1的上升沿触发占空比倍增起始使能脉冲产生电路201输出PWM倍增起始使能脉冲Pulse1，其脉冲宽度为T。
第一计数器203输出的第一计数值Count1在信号PWM1的上升沿被复位到0，之后在信号PWM1的高电平期间进行两次计数后为2，第一计数值Count1在信号PWM1下降沿之后保持计数值2。
第二计数器204输出的第二计数值Count2在信号PWM1的下降沿被复位到0，之后在信号PWM1的低电平期间进行连续计数，当第二计数值Count2 的数值等于第一计数值Count1的数值时(例如本实施例中两者均为2时)，计数值比较电路205输出PWM倍增结束使能脉冲Pulse2。
在PWM倍增起始使能脉冲Pulse1为高时，用时钟信号CLK的下降沿触发产生占空比倍增后的脉宽调制信号PWM2(后文可简称信号PWM2)的上升沿，在PWM倍增结束使能脉冲Pulse2为高时，用时钟信号CLK的下降沿触发产生占空比倍增后的脉宽调制信号PWM2的下降沿，此方法所得到的信号PWM2的高电平时间为4T，低电平时间为4T，则信号PWM2的高电平占空比为4T/(4T+4T)＝1/2。此方法成功实现了基于时钟周期的脉宽调制信号的占空比倍增，倍增倍数为2倍，DUTY PWM2＝2*DUTY PWM1。
实施例二：
如图4所示，在本发明的另一个实施例中，以对脉宽调制信号的低电平脉冲进行占空比倍增为目的，倍增倍数为2倍，时钟信号CLK周期为T，原始脉宽调制信号PWM1(后文可简称信号PWM1)的上升沿和下降沿与时钟信号CLK的上升沿同步，并且信号PWM1的低电平脉冲宽度为2T，信号PWM1的高电平脉冲宽度为6T，即信号PWM1的低电平脉冲占空比为2T/(2T+6T)＝1/4。
信号PWM1的下降沿触发占空比倍增起始使能脉冲产生电路201输出PWM倍增起始使能脉冲Pulse1，其脉冲宽度为T。
第一计数器203输出的第一计数值Count1在信号PWM1的下降沿被复位到0，之后在信号PWM1的低电平期间进行两次计数后为2，第一计数值Count1在信号PWM1上升沿之后保持计数值2。
第二计数器204输出的第二计数值Count2在信号PWM1的上升沿被复位到0，之后在信号PWM1的高电平期间进行连续计数，当第二计数值Count2的数值等于第一计数值Count1的数值时(例如本实施例中两者均为2时)，计数值比较电路205输出PWM倍增结束使能脉冲Pulse2。
在PWM倍增起始使能脉冲Pulse1为高时，用时钟信号CLK的下降沿触发产生占空比倍增后的脉宽调制信号PWM2(后文可简称信号PWM2)的下降沿，在PWM倍增结束使能脉冲Pulse2为高时，用时钟信号CLK的下降沿触发产生占空比倍增后的脉宽调制信号PWM2的上升沿，此方法所得到的信号PWM2的低电平时间为4T，高电平时间为4T，则信号PWM2的低电 平占空比为4T/(4T+4T)＝1/2。此方法成功实现了基于时钟周期的脉宽调制信号的占空比倍增，倍增倍数为2倍，DUTY PWM2＝2*DUTY PWM1。
尽管本发明的内容已经通过上述优选实施例作了详细介绍，但应当认识到上述的描述不应被认为是对本发明的限制。在本领域技术人员阅读了上述内容后，对于本发明的多种修改和替代都将是显而易见的。因此，本发明的保护范围应由所附的权利要求来限定。

Claims (10)

  1. 一种基于时钟周期的脉宽调制信号占空比倍增电路，其特征在于，
    其输入端输入时钟信号CLK和原始脉宽调制信号PWM1；所述原始脉宽调制信号PWM1的高电平的持续时间是N个时钟信号CLK的时钟周期之和，所述原始脉宽调制信号PWM1的低电平的持续时间是M个时钟信号CLK的时钟周期之和；
    其输出端输出占空比倍增后的脉宽调制信号PWM2，所述占空比倍增后的脉宽调制信号PWM2的高电平和低电平持续时间都是所述时钟信号CLK的整数个时钟周期之和，所述占空比倍增后的脉宽调制信号PWM2的周期与所述原始脉宽调制信号PWM1的周期相等；所述占空比倍增后的脉宽调制信号PWM2的高电平持续时间是K*N个时钟信号CLK的时钟周期之和，或者所述占空比倍增后的脉宽调制信号PWM2的低电平持续时间是K*M个时钟信号CLK的时钟周期之和；
    其中，参数N、M均为大于0的整数，参数K为大于1的整数。
  2. 如权利要求1所述的基于时钟周期的脉宽调制信号占空比倍增电路，其特征在于，
    所述参数K等于2。
  3. 如权利要求1所述的基于时钟周期的脉宽调制信号占空比倍增电路，其特征在于，包含：
    占空比倍增使能脉冲产生电路(101)，其输入端输入时钟信号CLK和原始脉宽调制信号PWM1，所述原始脉宽调制信号PWM1的高电平和低电平的持续时间都是时钟信号CLK的整数个时钟周期之和，其输出端输出PWM倍增起始使能脉冲信号Pulse1和PWM倍增结束使能脉冲信号Pulse2；
    占空比倍增电路(102)，其输入端输入所述PWM倍增起始使能脉冲信号Pulse1和所述PWM倍增结束使能脉冲信号Pulse2，其输出端输出占空比倍增后的脉宽调制信号PWM2；所述占空比倍增后的脉宽调制信号PWM2的脉冲宽度与所述PWM倍增起始使能脉冲信号Pulse1和PWM 倍增结束使能脉冲信号Pulse2相适配，且所述占空比倍增后的脉宽调制信号PWM2通过所述时钟信号CLK进行信号同步，保证占空比倍增后的脉宽调制信号PWM2的高电平和低电平持续时间都是所述时钟信号CLK的整数个时钟周期之和。
  4. 如权利要求3所述的基于时钟周期的脉宽调制信号占空比倍增电路，其特征在于，
    所述占空比倍增使能脉冲产生电路(101)包含：
    占空比倍增起始使能脉冲产生电路(201)，其输入端输入所述时钟信号CLK和所述原始脉宽调制信号PWM1，其输出端输出所述PWM倍增起始使能脉冲信号Pulse1；
    占空比倍增结束使能脉冲产生电路(202)，其输入端输入所述时钟信号CLK和所述原始脉宽调制信号PWM1，其输出端输出PWM倍增结束使能脉冲信号Pulse2。
  5. 如权利要求4所述的基于时钟周期的脉宽调制信号占空比倍增电路，其特征在于，
    所述占空比倍增结束使能脉冲产生电路(202)进一步包含：
    第一计数器(203)，其输入端输入所述时钟信号CLK和所述原始脉宽调制信号PWM1，用于统计原始脉宽调制信号PWM1的脉冲持续时间所对应的时钟信号CLK的周期数；所述第一计数器(203)在原始脉宽调制信号PWM1脉冲开始后开始计数，并且在原始脉宽调制信号PWM1脉冲结束后保持并输出第一计数值；
    第二计数器(204)，其输入端输入所述时钟信号CLK和所述原始脉宽调制信号PWM1，用于统计原始脉宽调制信号PWM1脉冲任意一次结束直至下一次结束的期间内所对应的时钟信号CLK的周期数；所述第二计数器(204)在原始脉宽调制信号PWM1脉冲结束后开始计数，并连续进行计数，输出第二计数值；
    计数值比较电路(205)，其输入端输入所述第一计数值和所述第二计数值，当所述第一计数值和所述第二计数值的数值不相等时，输出保持为低电平，当所述第一计数值和所述第二计数的数值相等时，输出所述PWM倍增结束使能脉冲Pulse2。
  6. 如权利要求3所述的基于时钟周期的脉宽调制信号占空比倍增电路，其特征在于，
    所述PWM倍增起始使能脉冲信号Pulse1可为高电平或者低电平，所述PWM倍增结束使能脉冲信号Pulse2可为高电平或者低电平。
  7. 如权利要求3所述的基于时钟周期的脉宽调制信号占空比倍增电路，其特征在于，
    所述原始脉宽调制信号PWM1的上升沿和下降沿与所述时钟信号CLK的上升沿同步，或者，所述原始脉宽调制信号PWM1的上升沿和下降沿与所述时钟信号CLK的下降沿同步。
  8. 如权利要求7所述的基于时钟周期的脉宽调制信号占空比倍增电路，其特征在于，
    当所述原始脉宽调制信号PWM1的上升沿和下降沿与所述时钟信号CLK的上升沿同步时，所述占空比倍增电路(102)中进一步实现：
    在所述PWM倍增起始使能脉冲信号Pulse1的脉冲持续期间时，用时钟信号CLK的下降沿触发产生占空比倍增后的脉宽调制信号PWM2的上升沿或者下降沿；
    在所述PWM倍增结束使能脉冲Pulse2的脉冲持续期间时，用时钟信号CLK的下降沿触发产生占空比倍增后的脉宽调制信号PWM2的下降沿或者上升沿。
  9. 如权利要求7所述的基于时钟周期的脉宽调制信号占空比倍增电路，其特征在于，
    当所述原始脉宽调制信号PWM1的上升沿和下降沿与所述时钟信号CLK的下降沿同步时，所述占空比倍增电路(102)中进一步实现：
    在所述PWM倍增起始使能脉冲信号Pulse1的脉冲持续期间时，用时钟信号CLK的上升沿触发产生占空比倍增后的脉宽调制信号PWM2的上升沿或者下降沿；
    在所述PWM倍增结束使能脉冲Pulse2的脉冲持续期间时，用时钟信号CLK的上升沿触发产生占空比倍增后的脉宽调制信号PWM2的下降沿或者上升沿。
  10. 一种采用如权利要求1-9中任意一项所述的基于时钟周期的脉宽调制信 号占空比倍增电路的脉宽调制信号占空比倍增方法，其特征在于，该方法包含以下过程：
    确定所述脉宽调制信号占空比倍增电路对原始脉宽调制信号PWM1的高电平脉冲进行占空比倍增，或者对原始脉宽调制信号PWM1的低电平脉冲进行占空比倍增，并预设占空比倍增的倍数以及时钟信号CLK的周期；
    设置原始脉宽调制信号PWM1与时钟信号CLK进行信号同步的方式；
    设定所述原始脉宽调制信号PWM1的高电平以及低电平的脉冲宽度；
    占空比倍增使能脉冲产生电路(101)输出PWM倍增起始使能脉冲信号Pulse1和PWM倍增结束使能脉冲信号Pulse2；
    占空比倍增电路(102)输入所述PWM倍增起始使能脉冲信号Pulse1和所述PWM倍增结束使能脉冲信号Pulse2，并通过时钟信号CLK的上升沿或者下降沿进行触发，以形成占空比倍增后的脉宽调制信号PWM2。
PCT/CN2019/104383 2018-11-14 2019-09-04 一种基于时钟周期的脉宽调制信号占空比倍增电路 WO2020098349A1 (zh)

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