WO2020098024A1 - 一种阵列基板的制造方法及显示面板 - Google Patents

一种阵列基板的制造方法及显示面板 Download PDF

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WO2020098024A1
WO2020098024A1 PCT/CN2018/119706 CN2018119706W WO2020098024A1 WO 2020098024 A1 WO2020098024 A1 WO 2020098024A1 CN 2018119706 W CN2018119706 W CN 2018119706W WO 2020098024 A1 WO2020098024 A1 WO 2020098024A1
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layer
metal layer
array substrate
exposed area
photoresist
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French (fr)
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付婷婷
葛邦同
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HKC Co Ltd
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HKC Co Ltd
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Definitions

  • the present application relates to the technical field of displays, and in particular, to an array substrate manufacturing method and a display panel.
  • the lithography mask is a key component in the lithography process. Using ultraviolet light and the lithography mask to expose the pattern coated with the photoresist, the lithography mask can be The electronic device pattern is transferred to the substrate, and the electronic device is formed through development, etching, stripping and other processes.
  • An object of the present application is to provide a method of manufacturing an array substrate, including but not limited to solving the phenomenon that the size deviation between the photoresist and the metal layer in the photolithography process affects the electrical properties of the array panel.
  • An array substrate manufacturing method includes the following steps:
  • Coating photoresist on the metal layer forming an unexposed area, a partially exposed area, and a fully exposed area through exposure and development;
  • wet etching is performed to etch the metal layer in part of the exposed area to form metal layer pits and leak out the semiconductor layer;
  • Dry etching is performed to form a channel region pattern of the thin film transistor.
  • Another object of the present application is to provide a method for manufacturing an array substrate, including the following steps:
  • Coating a layer of photoresist on the metal layer forming an unexposed area, a partially exposed area, and a fully exposed area through exposure and development;
  • Both the first ashing process and the second ashing process are etched with sulfur hexafluoride gas.
  • Still another object of the present application is to provide a display panel including an array substrate and a color filter substrate.
  • the array substrate includes a substrate, and a gate electrode, a gate insulating layer, a semiconductor layer, and a metal that are sequentially stacked on the substrate A layer and a photoresist, the photoresist is provided with a channel, and the metal layer is provided with a pit connecting the channel and leaking out of the semiconductor layer; both side walls of the pit and the channel The two side walls are flush.
  • the manufacturing method of the array substrate uses the second ashing process to etch away the remaining photoresist that has not been etched away in the pit area of the metal layer after the first ashing process. That is, by reducing the coverage of the photoresist that has not been etched off by the first ashing process in the lateral direction, the edge of the photoresist and the metal layer is ensured to be flush, and the size deviation between the metal layer and the photoresist is reduced , To provide guarantee for the subsequent etching process to achieve the alignment of the subsequent semiconductor layer and the metal layer.
  • FIG. 2 is a schematic structural diagram of a gate metal thin film layer deposited on a substrate provided by an embodiment of the present application;
  • FIG. 3 is a schematic structural view of a gate insulating layer deposited on a substrate provided by an embodiment of the present application;
  • FIG. 4 is a schematic structural view of depositing a semiconductor layer on a substrate provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural view of depositing a metal layer on a substrate provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of the structure after the first ashing process and wet etching provided by the embodiment of the present application;
  • FIG. 7 is a schematic structural view of a second ashing process provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a deposited passivation layer and a conductive film provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • an embodiment of the present application provides a method for manufacturing an array substrate, including the following steps:
  • the gate electrode 2, the gate insulating layer 3, the semiconductor layer 4 and the metal layer 5 are sequentially formed on the substrate 1; corresponding to step a and step b in FIG. 1;
  • a layer of photoresist 6 is coated on the metal layer 5; an unexposed area A, a partially exposed area B, and a fully exposed area C are formed through exposure and development steps; corresponding to step c in FIG.
  • wet etching is performed to etch the metal layer 6 of the partially exposed area B to form a metal layer pit 50, which leaks out the semiconductor layer 4; corresponding to step e in FIG. 1;
  • a halftone or gray tone mask exposure is used to make the photoresist 6 form a fully exposed area (photoresist completely removed area) C, and a partially exposed area B (light The partially removed area of the photoresist), and the unexposed area A (the area where the photoresist is completely retained), so that by using the first ashing process, the photoresist 6 of the partially exposed area B is removed to expose the corresponding partially exposed area
  • the metal layer 5 of B by wet etching, the metal layer 5 of the partially exposed area B is etched to form a metal layer pit 50, which leaks out of the semiconductor layer 4; after the first ashing process, it is not completely
  • the photoresist 6 above the pit 50 of the metal layer is completely removed, so the second ashing process is needed to remove the remaining residue that has not been etched away in the region of the pit 50 of the metal layer after the first ashing process
  • the photoresist 6 is etched away, that is, by reducing
  • X in the figure represents the lateral direction of the photoresist 6 described above.
  • the second ashing process may be etched with oxygen or sulfur hexafluoride gas, so that the photoresist 6 can be etched away better.
  • the above-mentioned first ashing treatment may also be etched with oxygen or sulfur hexafluoride gas, so that the above-mentioned photoresist 6 can be etched away better.
  • the first ashing process or the second ashing process may also be etched by other gases, which is not limited here.
  • the semiconductor layer 4 includes a silicon-based thin film layer 41 and an ohmic contact layer 42, and the ohmic contact layer 42 is deposited on the silicon-based thin film 41.
  • the ohmic contact layer 42 may be deposited on the silicon-based thin film layer 41 by chemical vapor deposition, of course, in this embodiment, the ohmic contact layer 42 may also be deposited on the silicon-based thin film by physical vapor deposition method On layer 41, there is no unique limitation here.
  • the step of etching away the remaining photoresist corresponding to the region of the metal layer pit 50 further includes the following steps:
  • Dry etching is performed to etch away the ohmic contact layer 42 exposed in the metal layer recess 50, so that part of the exposed region B leaks out of the silicon-based thin film layer 41, thereby forming a thin film transistor channel region pattern.
  • the excess photoresist 6 in the metal layer pit 50 is etched away, and when the dry etching is performed, the leaked metal layer pit 50 can be removed
  • the semiconductor layer 4 in is completely etched away, so that the edges of the semiconductor layer 4 and the metal layer 5 are flush with each other, thereby reducing the electrical performance of the array substrate due to the size deviation.
  • Table 1 shows the influence of different gases on the etching of the ohmic contact layer in the metal pit during the ashing process. It can be clearly seen from the comparison that under the same conditions, the ashing treatment can make the residual amount of the ohmic contact layer 42 in the metal layer pit 50 less; in addition, under the same conditions, relative to oxygen etching The sulfur hexafluoride gas etching makes the residual amount of the ohmic contact layer 42 in the metal layer recess 50 less, which in turn makes the display panel have better display characteristics.
  • Table 1 Effect of different gases on the etching of the ohmic contact layer in the pits of the metal layer during the ashing process
  • Table 2 shows the effects of oxygen etching on semiconductor etching in metal pits at different times. It can be clearly seen from the comparison that under the same conditions, when the etching time is longer, the residual amount of the ohmic contact layer 42 in the metal layer pit 50 gradually decreases. When the ventilation time reaches 60 seconds, the effect is better. The residual amount of the ohmic contact layer 42 can reach 0.0769 micrometers, and the edge of the ohmic contact layer 42 can be almost flush with the edge of the metal layer 5 to prevent the residual amount of the ohmic contact layer 42 from affecting the electrical characteristics of the array substrate.
  • Table 3 shows the effects of different times on the etching of the ohmic contact layer in the metal pit under the etching of sulfur hexafluoride gas. It can be clearly seen from the comparison that under the same conditions, when the etching time is longer, the residual amount of the ohmic contact layer 42 in the metal layer pit 50 gradually decreases. When the ventilation time reaches 20 seconds, the effect is better. The residual amount of the ohmic contact layer 42 can reach 0.0992 ⁇ m, which provides a guarantee that the edge of the ohmic contact layer 42 can be flush with the edge of the metal layer 5.
  • Table 3 The effect of different time on the etching of the ohmic contact layer in the pit of the metal layer under sulfur hexafluoride gas etching
  • the steps of setting a photoresist on the metal layer and forming an unexposed area, a partially exposed area, and a fully exposed area and the first ashing process to remove the partially exposed area of the photoresist further includes the following steps:
  • a wet etching process is used to etch the fully exposed area C, and the metal layer 5 of the fully exposed area C is etched away;
  • the ohmic contact layer 42 of the fully exposed area C is etched using a dry etching process to form data lines, source electrodes, and drain electrodes.
  • the source electrode and the drain electrode material may be any one or more of metals such as chromium, aluminum, or copper, which is not limited herein.
  • the step of etching away the remaining photoresist corresponding to the region of the metal layer pit 50 during the second ashing process further includes the following steps:
  • a layer of passivation layer 7 is deposited on the fully exposed area C, and via holes are formed on the passivation layer 7 by dry etching.
  • a layer of passivation layer 7 is deposited by plasma enhanced chemical vapor deposition, the passivation layer 7 is made of silicon nitride material, so that the passivation layer 7 is prepared by using silicon nitride material Therefore, it can prevent water vapor, sodium ions and oxygen impurities from intruding into the device.
  • the above-mentioned passivation layer 7 can also be prepared by other organic insulating materials, which is not limited herein.
  • the step of etching away the remaining photoresist corresponding to the metal layer pit 50 region further includes the following steps:
  • a layer of photoresist 6 is coated on the above-mentioned passivation layer 7, a common mask plate is used, and after exposure and development, a dry etching process is used to form in the pixel area
  • the passivation layer pit ie, via pattern
  • the passivation layer 7 in the passivation layer pit is completely etched away, so that part of the drain electrode can be exposed.
  • a layer of conductive film 8 is deposited by magnetron sputtering or thermal evaporation.
  • the conductive film 8 may be made of indium tin oxide or indium zinc oxide.
  • the pixel electrode is formed by dry etching , And the pixel electrode can be electrically connected to the drain electrode through the pit of the passivation layer.
  • the stripping process is used to remove the remaining photoresist 6 and the conductive film 8 overlying the remaining photoresist 6, so that the conductive film 8 deposited in the pits of the passivation layer remains.
  • both the gate insulating layer 3 and the semiconductor layer 4 are deposited on the substrate 1 by chemical vapor deposition, and the metal layer 5 is deposited on the semiconductor layer 4 by vapor deposition method.
  • the material of the gate insulating layer 3 may be oxide, nitride, or oxynitride.
  • the gate insulating layer 3 may also be prepared from other materials , Not limited here.
  • a method for manufacturing an array substrate is also provided.
  • the method for manufacturing an array substrate is substantially the same as the method for manufacturing an array substrate described above.
  • the first ashing process and the second ash process described above The chemical treatment adopts sulfur hexafluoride gas etching.
  • the array substrate manufactured by the above method can ensure that the edge of the metal layer 5 and the photoresist 6 are flush, so that the etched ohmic contact layer 42 is flush with the edge of the metal layer 5 to avoid Dimensional deviations caused by uneven edges affect the electrical characteristics of the display panel.
  • the display panel 9 includes an array substrate 91 and a color filter substrate 92, wherein the array substrate 91 includes a substrate 1, and on the substrate 1
  • the gate electrode 2, the gate insulating layer 3, the semiconductor layer 4, the metal layer 5, and the photoresist 6 are stacked in this order, and the photoresist 6 is provided with a channel 60, and at the same time, the metal layer 5 is provided with
  • the metal layer dimple 50 communicates with the channel 60, and the two side walls of the metal layer dimple 50 are flush with the two side walls of the channel 60.
  • the semiconductor layer 4 can be exposed to form a thin film transistor channel region pattern; by the two sidewalls of the metal layer recess 50 and the sidewalls of the channel 60 Set to be flush, thereby reducing the size deviation between the metal layer 5 and the photoresist 6, and providing guarantee for the subsequent etching process, so as to achieve the subsequent alignment of the semiconductor layer 4 and the metal layer 5.
  • the size deviation between the metal layer 5 and the photoresist 6 can be reduced, so that the etched ohmic contact layer 42 and the metal layer The edge of 5 is flush and provides a guarantee.
  • sulfur hexafluoride gas to etch the photoresist 6, a better etching of the photoresist 6 can be achieved in a shorter time, which improves the etching The production efficiency reduces the production cost.

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Abstract

一种阵列基板的制造方法及显示面板，其中，该阵列基板的制造方法包括沉淀栅电极、沉积栅绝缘层、半导体层、金属层、光刻胶，通过曝光、显影形成未曝光区域、部分曝光区域以及完全曝光区域，随后，通过第一次灰化处理及湿刻蚀形成金属层凹坑，并通过第二次灰化处理将第一次灰化处理未刻蚀掉的残余的所述光刻胶刻蚀掉，最后通过干蚀刻形成沟道区域图形。

Description

一种阵列基板的制造方法及显示面板
本申请要求于2018年11月14日提交中国专利局，申请号为201811352465.8，发明名称为“一种阵列基板的制造方法、显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示器技术领域，尤其涉及一种阵列基板的制造方法及显示面板。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然构成现有技术。随着科学技术的发展，电子设备(例如智能手机、笔记本电脑、数码相机等)越来越普及，使得作为电子设备的重要部件的液晶显示装置的需求量也大大提升，从而推动了液晶显示面板行业的快速发展。
显示面板制造行业中，光刻掩膜版是在光刻工艺的关键部件，利用紫外光和光刻掩膜版对涂布有光刻胶的图形进行曝光，可将光刻掩膜版上的电子器件图案转写到基板上，并经过显影、刻蚀、剥离等工艺形成电子器件。
然而，在光刻工艺过程中，由于光刻胶与沉积于基板上的金属层之间存在特征尺寸偏差(即设计值与实际值之间的偏差)，影响了后续的刻蚀工艺，进而影响了阵列面板的电性表现。
申请内容
本申请的一个目的在于提供一种阵列基板的制造方法，包括但不限于解决光刻工艺中因光刻胶与金属层之间存在尺寸偏差而影响阵列面板电性的现象。
一种阵列基板的制造方法，包括如下步骤：
在基板上依次形成栅电极、栅绝缘层、半导体层以及金属层；
在所述金属层上涂覆光刻胶；通过曝光、显影形成未曝光区域、部分曝光区域以及完全曝光区域；
进行第一次灰化处理，去除部分曝光区域的光刻胶，暴露出对应所述部分曝光区域的金属层；
进行湿蚀刻，对部分曝光区域的所述金属层进行刻蚀，形成金属层凹坑，漏出半导体层；
进行第二次灰化处理，将所述金属层凹坑区域内经过第一次灰化处理未刻蚀掉的残余的所述光刻胶刻蚀掉；以及
进行干蚀刻，形成薄膜晶体管沟道区域图形。
本申请的另一目的在于提供一种阵列基板的制造方法，包括如下步骤：
在基板上依次形成栅电极、栅绝缘层、半导体层以及金属层；
在所述金属层上涂覆一层光刻胶；通过曝光、显影形成未曝光区域、部分曝光区域以及完全曝光区域；
进行第一次灰化处理去除部分曝光区域的光刻胶，暴露出对应所述部分曝光区域的金属层；
进行湿蚀刻对部分曝光区域的所述金属层进行刻蚀，形成金属层凹坑，漏出半导体层；
进行第二次灰化处理，将所述金属层凹坑区域内经过第一次灰化处理未刻蚀掉的残余的所述光刻胶刻蚀掉；以及
进行干蚀刻，形成薄膜晶体管沟道区域图形；
所述第一次灰化处理与所述第二次灰化处理均采用六氟化硫气体刻蚀。
本申请的再一目的在于提供一种显示面板，包括阵列基板和彩膜基板，所述阵列基板包括基板、以及呈层叠依次设置于所述基板上的栅电极、栅绝缘层、半导体层、金属层、及光刻胶，所述光刻胶上开设有通道，所述金属层上开设有连通所述通道并漏出所述半导体层的凹坑，所述凹坑的两侧壁与所述通道的两侧壁相齐平。
本申请实施例提供的阵列基板的制造方法，通过采用第二次灰化处理，将金属层凹坑区域内经过第一次灰化处理未刻蚀掉的的残余的光刻胶刻蚀掉，即通过在横向方向上减少第一次灰化处理未刻蚀掉光刻胶的覆盖量，保证光刻胶与金属层的边缘相齐平，降低了金属层与光刻胶之间的尺寸偏差，为后续的刻蚀工艺提供保证，以实现后续的半导体层与金属层对齐。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1是本申请实施例提供的一种阵列基板制造方法的流程图；
图2是本申请实施例提供的在基板上沉积栅金属薄膜层的结构示意图；
图3是本申请实施例提供的在基板上沉积栅绝缘层的结构示意图；
图4是本申请实施例提供的在基板上沉积半导体层的结构示意图；
图5是本申请实施例提供的在基板上沉积金属层的结构示意图；
图6是本申请实施例提供的经过第一次灰化处理及湿蚀刻后的结构示意图；
图7是本申请实施例提供的经过第二次灰化处理的结构示意图；
图8是本申请实施例提供的沉积钝化层与导电薄膜的结构示意图；
图9是本申请实施例提供的显示面板的结构示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不设置为限定本申请。
需说明的是，当部件被称为“固定于”或“设置于”另一个部件，它可以直接在另一个部件上或者间接在该另一个部件上。当一个部件被称为是“连接于”另一个部件，它可以是直接或者间接连接至该另一个部件上。术语“上”、“下”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本专利的限制，对于本领域的普通技术人员而言，可以根据具体情况理解上述术语的具体含义。术语“第一”、“第二”仅设置为便于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明技术特征的数量。“多个”的含义是两个或两个以上，除非另有明确具体的限定。
为了说明本申请所述的技术方案，以下结合具体附图及实施例进行详细说明。
如图1～8所示，本申请实施例提供了一种阵列基板的制造方法，包括如下步骤：
在基板1上依次形成栅电极2、栅绝缘层3、半导体层4以及金属层5；对应图1中的步骤a与步骤b；
在金属层5上涂覆一层光刻胶6；通过曝光、显影步骤形成未曝光区域A、 部分曝光区域B以及完全曝光区域C；对应图1中的步骤c；
进行第一次灰化处理去除部分曝光区域B的光刻胶6，暴露出对应所述部分曝光区域B的金属层5；对应图1中的步骤d；
进行湿蚀刻对部分曝光区域B的金属层6进行刻蚀，形成金属层凹坑50，漏出半导体层4；对应图1中的步骤e；
进行第二次灰化处理，将上述金属层凹坑50区域内经过第一次灰化处理未刻蚀掉的残余的光刻胶6刻蚀掉；对应图1中的步骤f；
进行干蚀刻，形成薄膜晶体管沟道区域图形；对应图1中的步骤g。
在本实施例中，请参阅图6与图7，采用半色调或灰色调掩膜版曝光，使光刻胶6形成完全曝光区域(光刻胶完全去除区域)C、部分曝光区域B(光刻胶部分去除区域)、以及未曝光区域A(光刻胶完全保留区域)，这样，通过采用第一次灰化处理，从而去除部分曝光区域B的光刻胶6，暴露出对应部分曝光区域B的金属层5；通过进行湿蚀刻，从而对部分曝光区域B的金属层5进行刻蚀，形成金属层凹坑50，漏出半导体层4；由于经过第一次灰化处理后，未能完全将金属层凹坑50上方的光刻胶6完全去除掉，故而需通过采用第二次灰化处理，将金属层凹坑50区域内经过第一次灰化处理未刻蚀掉的的残余的光刻胶6刻蚀掉，即通过在横向方向上减少第一次灰化处理未刻蚀掉光刻胶6的覆盖量，保证光刻胶6与金属层5的边缘相齐平，降低了金属层5与光刻胶6之间的尺寸偏差，为后续的刻蚀工艺提供保证。当然，在本实施例中，该制备方法不限于上述顺序，此处不作唯一限定。
在一个实施例中，如图7所示，图中的X代表的是上述所述的光刻胶6的横向方向。
在一个实施例中，上述第二次灰化处理可采用氧气或六氟化硫气体刻蚀， 从而可较好的将上述光刻胶6刻蚀掉。
可选地，上述第一次灰化处理也可采用氧气或六氟化硫气体刻蚀，从而可较好的将上述光刻胶6刻蚀掉。
当然，在本实施例中，上述第一灰化处理或第二次灰化处理也可以通过其他气体来刻蚀，此处不作唯一限定。
在一个实施例中，上述半导体层4包括硅基薄膜层41和欧姆接触层42，该欧姆接触层42沉积于上述硅基薄膜41上。可选地，上述欧姆接触层42可通过化学气相沉积法沉积于硅基薄膜层41上，当然，在本实施例中，上述欧姆接触层42也可通过物理气相沉积法沉积于上述硅基薄膜层41上，此处不作唯一限定。
在一个实施例中，在进行第二次灰化处理，将金属层凹坑50区域对应的残余的光刻胶刻蚀掉的步骤之后还包括如下步骤：
进行干蚀刻，将暴露在所述金属层凹坑50中的所述欧姆接触层42刻蚀掉，使得部分曝光区域B漏出所述硅基薄膜层41，以此形成薄膜晶体管沟道区域图形。这样，通过在干蚀刻之前设置第二次灰化处理，从而将金属层凹坑50中的多余的光刻胶6刻蚀掉，当进行干蚀刻时，从而可将漏出的金属层凹坑50中的半导体层4完全刻蚀掉，使得半导体层4与金属层5的边缘相齐平，减少了因出现尺寸偏差而影响阵列基板的电性表现。
可选地，请参照表一，表一为灰化处理中不同气体对金属凹坑中的欧姆接触层刻蚀的影响。通过对比能够明显的看出，在同等条件下，通过灰化处理可使得金属层凹坑50中的残留量的欧姆接触层42较少；此外，在同等条件下，相对于氧气刻蚀来讲，六氟化硫气体刻蚀使得金属层凹坑50中的欧姆接触层42残留量较少，进而使得显示面板具有较好的显示特性。
表一：灰化处理中不同气体对金属层凹坑中的欧姆接触层刻蚀的影响
Figure PCTCN2018119706-appb-000001
可选地，请参照表二，表二为氧气刻蚀下不同时间对金属凹坑中的半导体刻蚀的影响。通过对比能够明显的看出，在同等条件下，当刻蚀的时间越长时，金属层凹坑50中的欧姆接触层42残留量逐渐减少，当通气时间达到60秒时，效果较佳，可使得欧姆接触层42残留量达到0.0769微米，几乎能够实现欧姆接触层42与金属层5的边缘相齐平，避免了因欧姆接触层42出现残留量而影响阵列基板的电学特性。
表二：氧气刻蚀下不同时间对金属层凹坑中的欧姆接触层刻蚀的影响
Figure PCTCN2018119706-appb-000002
可选地，请参照表三，表三为六氟化硫气体刻蚀下不同时间对金属凹坑中的欧姆接触层刻蚀的影响。通过对比能够明显的看出，在同等条件下，当刻蚀的时间越长时，金属层凹坑50中的欧姆接触层42残留量逐渐减少，当通气时间达到20秒时，效果较佳，可使得欧姆接触层42残留量达到0.0992微米，为欧姆接触层42的边缘能够与金属层5的边缘相齐平提供了保证。
表三：六氟化硫气体刻蚀下不同时间对金属层凹坑中的欧姆接触层刻蚀的影响
Figure PCTCN2018119706-appb-000003
可选地，通过表二与表三对比能够看出，当采用氧气刻蚀，通气时长为40秒时，此时欧姆接触层42的残留量达到0.09178微米，当采用六氟化硫气体刻蚀，通气时长为20秒时，此时欧姆接触层42的残留量达到0.0992微米，通过对比能够发现，采用六氟化硫气体刻蚀能够在较短的时间内，使得欧姆接触层42的残留量达到与氧气刻蚀在40秒的残留量，即通过采用六氟化硫气体刻蚀，可大大提高刻蚀的效率，进而节约了生产成本。
在一个实施例中，在所述金属层上设置光刻胶并形成未曝光区域、部分曝光区域以及完全曝光区域的步骤与所述进行第一次灰化处理去除部分曝光区域的光刻胶，暴露出对应所述部分曝光区域的金属层的步骤还包括如下步骤：
采用湿蚀刻工艺对完全曝光区域C进行刻蚀，将完全曝光区域C的金属层5刻蚀掉；
对完全曝光区域C的欧姆接触层42采用干蚀刻工艺进行蚀刻以形成数据线、源电极及漏电极。
这样，通过湿蚀刻及干蚀刻，从而可在基板1上形成数据线、源电极及漏电极。在本实施例中，上述源电极及漏电极材料可选用铬、铝或铜等金属中的任意一种或多种，此处不作唯一限定。
在一个实施例中，请参阅图8，在进行第二次灰化处理，将金属层凹坑50区域对应的残余的光刻胶刻蚀掉的步骤中还包括如下步骤：
在完全曝光区域C上沉积一层钝化层7，通过干蚀刻在所述钝化层7上制作出过孔。
可选地，在本实施例中，采用等离子体增强化学气相沉积法沉积一层钝化层7，钝化层7采用氮化硅材料制备，这样，通过采用氮化硅材料制备钝化层7，从而可起到防止水汽、钠离子和氧气杂质侵入到器件中，当然，在本实施例中，上述钝化层7也可通过其他有机绝缘材料制备，此处不作唯一限定。
在一个实施例中，请参阅图8，在沉积所述钝化层7之后，将所述金属层凹坑50区域对应的残余的所述光刻胶刻蚀掉的步骤中还包括如下步骤：
在所述钝化层7上沉积一层导电薄膜8，通过干蚀刻使所述导电薄膜8形成像素电极，所述像素电极通过所述过孔与所述漏电极电性连接；
剥离剩余的光刻胶6。
可选地，在本实施例中，通过在上述钝化层7上涂覆一层光刻胶6，采用普通掩膜版通过曝光和显影后，采用干法刻蚀工艺，在像素区域内形成钝化层凹坑(即过孔图形)，钝化层凹坑内的钝化层7被完全刻蚀掉，从而可暴露出部分漏电极。
可选地，在本实施例中，采用磁控溅射或热蒸发的方法沉积一层导电薄膜8，该导电薄膜8可采用氧化铟锡或氧化铟锌，这样，通过进行干蚀刻形成像素电极，且该像素电极可通过钝化层凹坑与漏电极电性相连。最后，利用带膜剥离工艺去除剩余的光刻胶6和覆盖在剩余光刻胶6上的导电薄膜8，从而使得沉积在钝化层凹坑中的导电薄膜8保留下来。
可选地，上述栅绝缘层3与半导体层4均采用化学气相沉积沉积于上述基板1上，且上述金属层5通过气相沉积法沉积于上述半导体层4上。
可选地，在本实施例中，上述栅绝缘层3的材料可为氧化物、氮化物或者氧氮化物等材料，当然，在本实施例中，上述栅绝缘层3也可通过其他材料制备，此处不作唯一限定。
在本申请中，还提供了一种阵列基板的制造方法，该阵列基板的制造方法与上述所述的阵列基板制造方法大致相同，可选地，上述第一次灰化处理与第二次灰化处理均采用六氟化硫气体刻蚀。这样，通过采用上述方法制造的阵列基板，从而可保证金属层5与光刻胶6的边缘相齐平，从而使得后续刻蚀的欧姆接触层42与金属层5的边缘相齐平，避免了因边缘不齐而引起尺寸偏差，从而影响了显示面板的电学特性。
在本申请中，还提供了一种显示面板，请参阅图7与图9，该显示面板9包括阵列基板91和彩膜基板92，其中，该阵列基板91包括基板1，在该基板1上依次呈层叠设置的栅电极2、栅绝缘层3、半导体层4、金属层5、及光刻胶6，上述光刻胶6上开设有通道60，与此同时，上述金属层5上开设有金属层凹坑50，该金属层凹坑50与上述通道60相连通，且上述金属层凹坑50的两侧壁与上述通道60的两侧壁相齐平。这样，通过设置金属层凹坑50，从而可使得上述半导体层4裸露在外，以此形成薄膜晶体管沟道区域图形；通过将上述金属层凹坑50的两侧壁与上述通道60的两侧壁设置为相齐平，从而降低了金属层5与光刻胶6之间的尺寸偏差，为后续的刻蚀工艺提供保证，以实现后续的半导体层4与金属层5对齐。
在本申请中，通过在采用干蚀刻之前，增加第二次灰化处理，从而可降低金属层5与光刻胶6之间的尺寸偏差，从而为后续刻蚀的欧姆接触层42与金属层5的边缘相齐平提供了保证，此外，通过使用六氟化硫气体来对光刻胶6蚀刻，可实现在较短的时间内对光刻胶6进行较好的蚀刻，提高了刻蚀的生产效率，降低了生产成本。
以上仅为本申请的可选实施例而已，并不设置为限制本申请。对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之 内，所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (17)

  1. 一种阵列基板的制造方法，其中，包括如下步骤：
    在基板上依次形成栅电极、栅绝缘层、半导体层以及金属层；
    在所述金属层上涂覆光刻胶；通过曝光、显影形成未曝光区域、部分曝光区域以及完全曝光区域；
    进行第一次灰化处理，去除部分曝光区域的光刻胶，暴露出对应所述部分曝光区域的金属层；
    进行湿蚀刻，对部分曝光区域的所述金属层进行刻蚀，形成金属层凹坑，漏出半导体层；
    进行第二次灰化处理，将所述金属层凹坑区域内经过第一次灰化处理未刻蚀掉的残余的所述光刻胶刻蚀掉；以及
    进行干蚀刻，形成薄膜晶体管沟道区域图形。
  2. 根据权利要求1所述的一种阵列基板的制造方法，其中，所述第二次灰化处理采用氧气刻蚀。
  3. 根据权利要求1所述的一种阵列基板的制造方法，其中，所述第二次灰化处理采用六氟化硫气体刻蚀。
  4. 根据权利要求1所述的一种阵列基板的制造方法，其中，所述半导体层包括硅基薄膜层和沉积于所述硅基薄膜层上的欧姆接触层。
  5. 根据权利要求4所述的一种阵列基板的制造方法，其中，所述欧姆接触层通过化学气相沉积于所述硅基薄膜层上。
  6. 根据权利要求4所述的一种阵列基板的制造方法，其中，在进行所述第二次灰化处理，将所述金属层凹坑区域对应的残余的所述光刻胶刻蚀掉的步 骤之后还包括如下步骤：
    进行干蚀刻，将暴露在所述金属层凹坑中的所述欧姆接触层刻蚀掉，漏出所述硅基薄膜层，以此形成薄膜晶体管沟道区域图形。
  7. 根据权利要求6所述的一种阵列基板的制造方法，其中，在所述金属层上设置光刻胶并形成未曝光区域、部分曝光区域以及完全曝光区域的步骤与所述进行第一次灰化处理去除部分曝光区域的光刻胶，暴露出对应所述部分曝光区域的金属层的步骤之间还包括如下步骤：
    采用湿蚀刻工艺对所述完全曝光区域进行刻蚀，将所述完全曝光区域的金属层刻蚀掉；以及
    对所述完全曝光区域的欧姆接触层采用干蚀刻工艺进行蚀刻以形成数据线、源电极及漏电极。
  8. 根据权利要求7所述的一种阵列基板的制造方法，其中，所述源电极或漏电极采用铬、铝和铜中的任意一种材料制备。
  9. 根据权利要求7所述的一种阵列基板的制造方法，其中，在进行第二次灰化处理，将所述金属层凹坑区域对应的残余的所述光刻胶刻蚀掉的步骤中还包括如下步骤：
    在所述完全曝光区域内沉积一层钝化层，通过干蚀刻在所述钝化层上制作出过孔。
  10. 根据权利要求9所述的一种阵列基板的制造方法，其中，所述钝化层通过等离子体增强化学气相沉积法沉积于所述完全曝光区域内。
  11. 根据权利要求9所述的一种阵列基板的制造方法，其中，在沉积所述钝化层之后，将所述金属层凹坑区域对应的残余的所述光刻胶刻蚀掉的步骤中还包括如下步骤：
    在所述钝化层上沉积导电薄膜，通过干蚀刻使所述导电薄膜形成像素电极，所述像素电极通过所述过孔与所述漏电极电性连接；以及
    剥离剩余的光刻胶。
  12. 根据权利要求11所述的一种阵列基板的制造方法，其中，所述导电薄膜通过磁控溅射或热蒸发法沉积于所述钝化层上。
  13. 根据权利要求11所述的一种阵列基板的制造方法，其中，所述导电薄膜为氧化铟锡和氧化铟锌中的任意一种材料制备。
  14. 根据权利要求1所述的一种阵列基板的制造方法，其中，所述栅绝缘层及所述半导体层通过化学气相沉积法依次沉积于所述基板上，所述金属层通过物理气相沉积法沉积于所述半导体层上。
  15. 根据权利要求14所述的一种阵列基板的制造方法，其中，所述栅绝缘层的材料为氧化物、氮化物或者氧氮化物。
  16. 一种阵列基板的制造方法，包括如下步骤：
    在基板上依次形成栅电极、栅绝缘层、半导体层以及金属层；
    在所述金属层上涂覆一层光刻胶；通过曝光、显影形成未曝光区域、部分曝光区域以及完全曝光区域；
    进行第一次灰化处理去除部分曝光区域的光刻胶，暴露出对应所述部分曝光区域的金属层；
    进行湿蚀刻对部分曝光区域的所述金属层进行刻蚀，形成金属层凹坑，漏出半导体层；
    进行第二次灰化处理，将所述金属层凹坑区域内经过第一次灰化处理未刻蚀掉的残余的所述光刻胶刻蚀掉；以及
    进行干蚀刻，形成薄膜晶体管沟道区域图形；
    所述第一次灰化处理与所述第二次灰化处理均采用六氟化硫气体刻蚀。
  17. 显示面板，包括阵列基板和彩膜基板，其中，所述阵列基板包括基板、以及呈层叠依次设置于所述基板上的栅电极、栅绝缘层、半导体层、金属层、及光刻胶，所述光刻胶上开设有通道，所述金属层上开设有连通所述通道并漏出所述半导体层的凹坑，所述凹坑的两侧壁与所述通道的两侧壁相齐平。
PCT/CN2018/119706 2018-11-14 2018-12-07 一种阵列基板的制造方法及显示面板 Ceased WO2020098024A1 (zh)

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