WO2020097993A1 - 显示面板及其制作方法和显示装置 - Google Patents

显示面板及其制作方法和显示装置 Download PDF

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WO2020097993A1
WO2020097993A1 PCT/CN2018/118158 CN2018118158W WO2020097993A1 WO 2020097993 A1 WO2020097993 A1 WO 2020097993A1 CN 2018118158 W CN2018118158 W CN 2018118158W WO 2020097993 A1 WO2020097993 A1 WO 2020097993A1
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Prior art keywords
layer
insulating layer
metal layer
display panel
semiconductor layer
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Ceased
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PCT/CN2018/118158
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English (en)
French (fr)
Inventor
杨春辉
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HKC Co Ltd
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HKC Co Ltd
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Priority to US16/349,597 priority Critical patent/US20200292891A1/en
Publication of WO2020097993A1 publication Critical patent/WO2020097993A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present application relates to the field of display technology, in particular to a display panel, a manufacturing method and a display device.
  • the display panel has many advantages such as a thin body, power saving, no radiation, etc., and is widely used.
  • Most of the liquid crystal displays on the market are backlight type liquid crystal displays, which include a liquid crystal panel and a backlight module (Backlight Module).
  • Thin film transistor liquid crystal display (Thin Film Transistor-Liquid Crystal) (TFT-LCD) manufacturing process includes array engineering, color film engineering and LCD cell manufacturing engineering.
  • Array engineering includes cleaning technology, CVD film formation technology, sputter film formation technology, photoresist overlay, development and stripping technology, exposure technology, etching technology, dry etching technology, etc.
  • four to five thin film patterns are formed on the surface of the glass substrate.
  • Examples of four processes include: first metal layer engineering (referred to as G project) and protective layer engineering (referred to as I project), second metal layer project (referred to as D project), passivation layer project (referred to as C project) ), Transparent conductive film project (referred to as PI project).
  • G project first metal layer engineering
  • I project protective layer engineering
  • D project second metal layer project
  • C project passivation layer project
  • PI project Transparent conductive film project
  • the switch structure formed by the example four processes has a problem of short-circuit connection.
  • the technical problem to be solved by the present application is to provide a display panel, a manufacturing method and a display device that can prevent a short circuit of a switch structure in the display panel.
  • the present application provides a display panel, a manufacturing method, and a display device that prevent short-circuiting of the switch structure in the display panel.
  • a display panel includes: a first substrate; a first metal layer, a first insulating layer, and a semiconductor layer, which are stacked on the first substrate, and the first metal layer, the first The insulating layer and the semiconductor layer have the same shape; the second metal layer; and the second insulating layer cover the stacked first metal layer, the first insulating layer, and the semiconductor layer, and are formed on the first metal layer and the first Between two metal layers.
  • the second insulating layer is a black color resistor.
  • the second insulating layer is made of insulating material.
  • the first metal layer is a gate
  • the second metal layer includes separate source and drain
  • the first insulating layer is a gate insulating layer
  • the gate is formed on the first liner
  • the gate insulating layer is formed on the gate
  • the semiconductor layer is formed on the gate insulating layer
  • the second insulating layer is formed on the semiconductor layer
  • the second insulating layer partially covers the semiconductor layer, A part of it does not cover the semiconductor layer
  • the source electrode and the drain electrode are provided in the region where the semiconductor layer is not covered by the second insulating layer.
  • the second insulating layer is formed with an opening to expose the semiconductor layer, the opening is formed in a non-edge region of the second insulating layer, and the source electrode and the drain electrode are connected to the semiconductor layer through the opening through.
  • the distance from the periphery of the opening to the edge of the second insulating layer is greater than 0, and the distance from the opening to the gate edge is greater than 0.
  • the length of the source is d5
  • the length of the drain is d6
  • the length of the opening is d7
  • the length of the source d5 and the length of the drain d6 are equal to the length of the opening d7 .
  • the first metal layer is a scan line
  • the second metal layer is a data line; a portion where the scan line and the data line overlap each other is provided with a second insulating layer.
  • the first substrate is a glass substrate.
  • the first metal layer is a gate
  • the second metal is an independent source and drain.
  • the first insulating layer and the semiconductor layer are formed by exposure and development of the same photomask, and their shapes are consistent.
  • the application also discloses a method for manufacturing a display panel.
  • the method includes the following steps:
  • the first metal layer, the first An insulating layer and a semiconductor layer have the same shape;
  • the second insulating layer covers the stacked first metal layer, first insulating layer, and semiconductor layer;
  • a second metal layer is formed on the second insulating layer; the second insulating layer is formed between the first metal layer and the second metal layer.
  • the method further includes the steps of:
  • a transparent conductive layer is formed, and the transparent conductive layer is connected to the second metal layer through the via hole.
  • the second insulating layer is formed with an opening to expose the semiconductor layer, the opening is formed in a non-edge area of the second insulating layer, and the source and drain Conducting with the semiconductor layer through the opening.
  • the present application also discloses a display device including a display panel.
  • the display panel includes: a first substrate; a first metal layer, a first insulating layer, and a semiconductor layer, which are stacked on the first On the substrate, the shapes of the first metal layer, the first insulating layer and the semiconductor layer are consistent;
  • a second metal layer and a second insulating layer covering the stacked first metal layer, first insulating layer, and semiconductor layer, and formed between the first metal layer and the second metal layer.
  • the first metal layer, the first insulating layer and the semiconductor layer are formed by exposure and development of the same photomask.
  • the shape is consistent, which can reduce the corresponding process steps and save the manufacturing cost, but the edges of the first metal layer, the first insulating layer and the semiconductor layer are flush, and the bottom part of the first metal layer is exposed, it is easy to In the subsequent manufacturing process, it will cause a short circuit with other conductive devices, or even burn the display panel; this solution isolates the first metal layer and the second metal layer through the second insulating layer, and the second insulating layer covers the stacked first metal layer, The first insulating layer and the semiconductor layer ensure the normal display of the display panel.
  • FIG. 1 is a schematic diagram of a manufacturing process of a display panel according to an embodiment of the present application
  • FIG. 2 is a schematic diagram of a display panel structure according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a structure of a second insulating layer according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of the comparison between the gate and the semiconductor layer according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a first metal layer, a semiconductor layer, and a second insulating layer according to an embodiment of the present application;
  • FIG. 6 is a schematic diagram of a data line and source and drain structures according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of the source and drain and the mouth structure of an embodiment of the present application.
  • FIG. 8 is a schematic diagram of data line and scan line structures of another embodiment of the present application.
  • FIG. 9 is a schematic diagram of a region where data lines and scan lines overlap in another embodiment of the present application.
  • FIG. 10 is a flowchart of a method for manufacturing a display panel according to another embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a display device according to another embodiment of the present application.
  • first and second are used only for descriptive purposes and cannot be understood as indicating relative importance, or implicitly indicating the number of indicated technical features.
  • the features defined as “first” and “second” may expressly or implicitly include one or more of the features; “multiple” means two or more.
  • the term “comprising” and any variations thereof are meant to be non-exclusive and one or more other features, integers, steps, operations, units, components, and / or combinations thereof may be present or added.
  • connection should be understood in a broad sense, such as fixed connection, detachable connection, or integral connection; may be mechanical connection It can also be an electrical connection; it can be directly connected, indirectly connected through an intermediary, or connected within two components.
  • an embodiment of the present application discloses a display panel 100, a manufacturing method, and a display device 10.
  • a display panel 100 includes:
  • the first substrate 110, the first metal layer 120, the first insulating layer 130, and the semiconductor layer 140 are stacked on the first substrate 110, respectively.
  • the first metal layer 120, the first insulating layer 130 and the semiconductor layer 140 have the same shape; the second metal layer 160; and the second insulating layer 150 cover the stacked first metal layer 120, the first insulating layer 130 and the semiconductor layer 140. Formed between the first metal layer 120 and the second metal layer 160.
  • the first metal layer 120, the first insulating layer 130, and the semiconductor layer 140 pass the same light
  • the mask is developed by exposure and development, and its shape is consistent, which can reduce the corresponding process steps and save the manufacturing cost, but the edges of the first metal layer 120, the first insulating layer 130, and the semiconductor layer 140 are flush, the first The bottom part of the metal layer 120 is exposed, it is easy to cause a short circuit with other conductive devices in the subsequent process, and even burn the display panel 100; this solution isolates the first metal layer 120 and the second metal layer 160 by the second insulating layer 150 Insulation, the second insulation layer 150 covers the stacked first metal layer 120, the first insulation layer 130, and the semiconductor layer 140, which ensures the normal display of the display panel 100.
  • a glass substrate is used for the first substrate 110 case.
  • the second insulating layer 150 is a black color resist.
  • the second insulating layer 150 is made of black color resistance, which can effectively block the light incident from the backlight, prevent the light from entering the semiconductor layer 140, and prevent the semiconductor layer 140 from being exposed to light A current is generated under the influence to improve the performance of the display panel 100.
  • the second insulating layer 150 may also use other insulating layer materials, as long as the insulation between the first metal layer 120 and the second metal layer 160 is achieved.
  • the first metal layer 120 is the gate 121
  • the second metal layer 160 includes the separated source 161 and drain 162
  • the first insulating layer 130 is the gate 121 insulating layer
  • the gate 121 is formed on the first substrate 110, the gate 121 insulating layer is formed on the gate 121, the semiconductor layer 140 is formed on the gate 121 insulating layer; the second insulating layer 150 is formed on the semiconductor layer 140;
  • a part of the second insulating layer 150 covers the semiconductor layer 140, and a part of it does not cover the semiconductor layer 140; the source electrode 161 and the drain electrode 162 are provided in a region where the semiconductor layer 140 is not covered by the second insulating layer 150.
  • This scheme forms a switching structure such as a thin film transistor (Thin Film Transistor, TFT) to improve the performance of the thin film transistor.
  • the first metal layer 120 forms the gate 121 of the thin film transistor
  • the second metal layer 160 forms the source 161 and the drain 162 of the thin film transistor
  • the first insulating layer 130 is the insulating layer of the gate 121 of the thin film transistor
  • the second insulating layer 150 Formed on the semiconductor layer 140, a part of the second insulating layer 150 covers the semiconductor layer 140, a part does not cover the semiconductor layer 140, the source electrode 161 and the drain electrode 162 are provided in the region of the semiconductor layer 140 not covered by the second insulating layer 150, such a source
  • the electrode 161 and the drain 162 can be connected to the semiconductor layer 140 in contact, which ensures that the switch structure formed by the gate 121, the source 161 and the drain 162 can work normally after the panel process is completed.
  • the gate 121, the source 161, and the drain 162 may have a certain thickness due to the gate 121 insulating layer and the second insulating layer 150 between them. Therefore, the gate 121, the source 161 and the drain 162 cannot work normally, which affects the performance of the display panel 100.
  • the second insulating layer 150 is formed with an opening 151 to expose the semiconductor layer 140.
  • the opening 151 is formed in the non-edge area of the second insulating layer 150.
  • the source 161 and the drain 162 pass through the opening 151 and the semiconductor Layer 140 is on.
  • the second insulating layer 150 is provided with an opening 151, and the opening 151 is provided in a region not at the edge of the second insulating layer 150. Since the shape of the semiconductor layer 140 and the gate 121 are the same, then the gate 121 The backlight on one side may be incident on the semiconductor layer 140 to generate current to the semiconductor layer 140, which may cause light leakage or uneven display in the display panel 100.
  • the second insulating layer 150 When the opening 151 is disposed in the non-edge area of the second insulating layer 150, the distance from the periphery of the opening 151 to the edge of the second insulating layer 150 is greater than 0, and the distance from the opening 151 to the edge of the gate 121 is greater than 0; the second insulating layer 150 is not The area of the opening 151 can block the light incident from the backlight, thereby preventing the semiconductor layer 140 from generating photocurrent, and avoiding light leakage or uneven display brightness of the display panel 100.
  • the length of the source electrode 161 is d5
  • the length of the drain electrode 162 is d6
  • the length of the opening 151 is d7
  • the length d5 of the source electrode 161 and the length d6 of the drain electrode 162 are equal to the opening 151 The length d7.
  • the length d5 of the source electrode 161 and the length d6 of the drain electrode 162 are equal to the length d7 of the opening 151, so that the source electrode 161 and the drain electrode 162 can shield the semiconductor layer 140 from external light sources.
  • the first metal layer 120 is the scan line 300
  • the second metal layer 160 is the data line 200; the portion where the scan line 300 and the data line 200 overlap each other is provided with second insulation ⁇ 150 ⁇ Layer 150.
  • This solution is mainly aimed at the part where the data lines 200 and the scanning lines 300 overlap and overlap. Because of the manufacturing accuracy of the display panel 100, the data lines 200 and the scanning lines 300 may be connected. If the scanning lines 300 and the data lines are not connected The second insulating layer 150 is provided in the area where 200 overlaps and overlaps, which may cause a short circuit in the display panel 100 and burn the display panel 100. After the second insulating layer 150 is provided, the area where the second insulating layer 150 overlaps the data line 200 and the scanning line 300 can prevent the data line 200 and the scanning line 300 from being connected to cause a short circuit, thereby ensuring the display panel 100 Can be displayed normally.
  • a manufacturing method of a display panel 100 includes the following steps:
  • S10 Provide a first substrate 110 covering the first metal layer 120, the first insulating layer 130 and the semiconductor layer 140, and after a single exposure, development and etching, form the first metal layer 120, the first insulating layer 130 and the semiconductor layer 140 ;
  • the shapes of the first metal layer 120, the first insulating layer 130, and the semiconductor layer 140 are consistent;
  • the shapes of the first metal layer 120, the first insulating layer 130, and the semiconductor layer 140 are the same. These three layers can be manufactured through the same mask, which can reduce the corresponding process steps and save the manufacturing Cost, but the subsequent process needs to provide the second metal layer 160, if the first metal layer 120 and the second metal layer 160 are not insulated, then the first metal layer 120 and the second metal layer 160 may be connected after all processes are completed , which in turn causes a short circuit, which may even burn the display panel 100.
  • a second insulating layer 150 is provided between the first metal layer 120 and the second metal layer 160, so as to isolate and insulate the first metal layer 120 and the second metal layer 160, thus ensuring the normal display of the display panel 100 .
  • a glass substrate may be used for the first substrate 110, and other suitable materials may also be used.
  • the second metal layer 160 is deposited, and after exposure, development, and etching to form the second metal layer 160, the method further includes the steps of:
  • a transparent conductive layer 190 is formed, and the transparent conductive layer 190 is connected to the second metal layer 160 through the via 180.
  • This scheme forms a switching structure such as a thin film transistor (Thin Film Transistor, TFT), the first metal layer 120 forms the gate 121, the second insulating layer 150 forms the gate 121 insulating layer, and the second metal forms the source electrode 161 and the drain isolated from each other Electrode 162, a passivation layer 170 is formed on the source electrode 161 and the drain electrode 162, and a via 180 is formed on the passivation layer 170, and finally a transparent electrode layer is formed, thus forming a complete switch structure.
  • TFT Thin Film Transistor
  • the first insulating layer 130 does not completely surround the gate 121, and part of the gate 121 is exposed, and the source 161 and the drain are formed later At 162, the gate 121 may communicate with the source 161 and the drain 162, which may cause a short circuit or even burn the panel. Therefore, a second insulating layer 150 is provided between the gate 121 and the source 161 and the drain 162.
  • the isolation and insulation treatment between the gate electrode 121 and the source electrode 161 and the drain electrode 162 can make the display panel 100 work normally, and ensure the performance that the display surface cannot.
  • This scheme can of course also form the data line 200 and the scan line 300, the first metal layer 120 forms the scan line 300, and the second metal layer 160 forms the data line 200, because of the manufacturing accuracy of the display panel 100, the data line 200 and the scan line 300 may be connected. If the second insulating layer 150 is not provided in the area where the scan line 300 and the data line 200 overlap each other, a short circuit may occur in the display panel 100 and the display panel 100 may be burned. After the second insulating layer 150 is provided, the area where the second insulating layer 150 overlaps the data line 200 and the scanning line 300 can prevent the data line 200 and the scanning line 300 from being connected to cause a short circuit, thereby ensuring the display panel 100 Can be displayed normally.
  • the second insulating layer 150 is formed with an opening 151 to expose the semiconductor layer 140, the opening 151 is formed in the non-edge area of the second insulating layer 150, the source 161 and the drain 162 The semiconductor layer 140 is electrically connected through the opening 151.
  • the opening 151 of the second insulating layer 150 only needs to be provided with a light-shielding pattern corresponding to the opening 151 on the photomask used in the exposure process. After corresponding development, the opening 151 can be thought of as the opening 151. No process steps are added to the process of the second insulating layer 150, and the process is simple and easy.
  • a display device 10 is disclosed.
  • the display device 10 is the display panel 100 described above.
  • the second insulating layer 150 isolates and insulates the first metal layer 120 and the second metal layer 160, and the second insulating layer 150 covers the stacked first metal layer 120 and the first
  • the insulating layer 130 and the semiconductor layer 140 ensure the normal display of the display panel 100 in this way.
  • the first metal layer 120 may be the source electrode 121 or the scanning line 200
  • the second metal layer 160 is the source electrode 161 and the drain electrode 162, or may be the data line 300.
  • TN-type display panel full name Twisted Nematic, namely twisted nematic panel
  • IPS-type display panel In-Plane Switching, plane conversion
  • VA-type display Panel Vertical Alignment, vertical alignment technology
  • MVA type display panel Multi-domain Vertical Alignment, multi-quadrant vertical alignment technology
  • OLED display panel organic light-emitting diode

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Abstract

一种显示面板（100）、制作方法和显示装置（10）。显示面板（100）包括：第一衬底（110）；第一金属层（120）、第一绝缘层（130）和半导体层（140），分别堆叠设置在第一衬底（110）上，第一金属层（120）、第一绝缘层（130）以及半导体层（140）的形状一致；第二金属层（160）；以及第二绝缘层（150），覆盖堆叠设置的第一金属层（120）、第一绝缘层（130）以及半导体层（140）、且形成于第一金属层（120）和第二金属层（160）之间。

Description

显示面板及其制作方法和显示装置
本申请要求于2018年11月12日提交中国专利局，申请号为CN201811338861.5，申请名称为“一种显示面板、制作方法和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板、制作方法和显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
显示面板具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶面板及背光模组(Backlight Module)。薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)制程包括阵列工程、彩膜工程及液晶盒制造工程。阵列工程包括洗净技术、CVD成膜技术、sputter成膜技术、光刻胶覆盖、显影与剥离技术、曝光技术、蚀刻技术、干刻技术等。最终在玻璃基板表面形成四至五道薄膜图案。
示例的四道工艺(简称4mask)包括：第一金属层工程(简称G工程)和保护层工程(简称I工程)、第二金属层工程(简称D工程)、钝化层工程(简称C工程)、透明导电薄膜工程(简称PI工程)。经过示例的四道工艺形成的开关结构存在连通短路的问题。
技术解决方案
本申请所要解决的技术问题是提供一种可以防止显示面板内开关结构短路的显示面板、制作方法和显示装置。
为实现上述目的，本申请提供了一种防止显示面板内开关结构短路的显示面板、制作方法和显示装置。
一种显示面板，所述显示面板包括：第一衬底；第一金属层、第一绝缘层和半导体层，分别堆叠设置在所述第一衬底上，所述第一金属层、第一绝缘层以及半导体层的形状一致；第二金属层；以及第二绝缘层，覆盖所述堆叠设置的第一金属层、第一绝缘层以及半导体层、且形成于所述第一金属层和第二金属层之间。
可选的，所述第二绝缘层为黑色色阻。
可选的，所述第二绝缘层为绝缘材料制成。
可选的，所述第一金属层为栅极，所述第二金属层包括分离的源极和漏极，所述第一绝缘层为栅极绝缘层；所述栅极形成于第一衬底上，所述栅极绝缘层形成于栅极上，所述半导体层形成于栅极绝缘层上；所述第二绝缘层形成在半导体层上；所述第二绝缘层一部分覆盖半导体层，一部分不覆盖半导体层；所述源极和漏极设置在半导体层未被第二绝缘层覆盖的区域。
可选的，所述第二绝缘层形成有开口以暴露所述半导体层，所述开口形成在第二绝缘层非边缘区域，所述源极和漏极通过所述开口与所述半导体层导通。
可选的，开口四周距离第二绝缘层的边缘的距离均大于0，开口距离栅极边缘的距离大于0。
可选的，所述源极的长度为d5，所述漏极的长度为d6，所述开口的长度为d7，所述源极的长度d5与漏极的长度d6等于所述开口的长度d7。
可选的，所述第一金属层为扫描线，所述第二金属层为数据线；所述扫描 线与数据线交错互叠的部分设置有第二绝缘层。
可选的，所述第一衬底为玻璃基板。
可选的，所述第一金属层为栅极，所述第二金属为相互独立的源极和漏极。
可选的，第一绝缘层以及半导体层通过同一道光罩曝光显影而成，其形状是一致的。
本申请还公开了一种显示面板的制作方法，所述制作方法包括步骤：
提供第一衬底，覆盖第一金属层，第一绝缘层以及半导体层，经过一次曝光、显影以及蚀刻，形成第一金属层、第一绝缘层以及半导体层；所述第一金属层、第一绝缘层以及半导体层的形状一致；
形成第二绝缘层；所述第二绝缘层覆盖所述堆叠设置的第一金属层、第一绝缘层以及半导体层；
在所述第二绝缘层上形成第二金属层；所述第二绝缘层形成于所述第一金属层和第二金属层之间。
可选的，所述沉积第二金属层，经过曝光、显影以及蚀刻，形成第二金属层步骤之后，还包括步骤：
在所述第二金属层上形成钝化层，并在所述钝化层上形成过孔；
形成透明导电层，所述透明导电层通过所述过孔连接第二金属层。
可选的，所述形成第二绝缘层步骤中，所述第二绝缘层形成有开口以暴露所述半导体层，所述开口形成在第二绝缘层非边缘区域，所述源极和漏极通过所述开口与所述半导体层导通。
本申请还公开了一种显示装置，所述显示装置包括显示面板，所述显示面板包括：第一衬底；第一金属层、第一绝缘层和半导体层，分别堆叠设置在所述第一衬底上，所述第一金属层、第一绝缘层以及半导体层的形状一致；
第二金属层；以及第二绝缘层，覆盖所述堆叠设置的第一金属层、第一绝缘层以及半导体层、且形成于所述第一金属层和所述第二金属层之间。
本申请相对于使用同一道光罩制程形成第一金属层，第一绝缘层以及半导体层的显示面板来说，第一金属层，第一绝缘层以及半导体层通过同一道光罩曝光显影而成，其形状是一致的，样可以减少了对应的制程步骤，节约了制作成本，但第一金属层，第一绝缘层以及半导体层边缘是平齐的，第一金属层的底部部分裸露，就容易在后续制程中与其他导电器件造成短路，甚至会烧毁显示面板；本方案通过第二绝缘层对第一金属层和第二金属层进行隔离绝缘，第二绝缘层覆盖堆叠设置的第一金属层、第一绝缘层以及半导体层，这样确保了显示面板的正常显示。
附图说明
所包括的附图用来提供对本申请实施例的具体的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请的一实施例的一种显示面板的制程的示意图；
图2是本申请的一实施例的一种显示面板结构的示意图；
图3是本申请的一实施例的第二绝缘层结构的示意图；
图4是本申请的一实施例的栅极与半导体层对比的示意图；
图5是本申请的一实施例的第一金属层、半导体层以及第二绝缘层示意图；
图6是本申请的一实施例的数据线与源极以及漏极结构的示意图；
图7是本申请的一实施例的源极和漏极以及靠口结构的示意图；
图8是本申请的另一实施例的数据线和扫描线结构的示意图；
图9是本申请的另一实施例的数据线与扫描线交错重叠区域的示意图；
图10是本申请的另一实施例的一种显示面板的制作方法流程图；
图11是本申请的另一实施例的一种显示装置的结构示意图。
具体实施方式
需要理解的是，这里所使用的术语、公开的具体结构和功能细节，仅仅是为了描述具体实施例，是代表性的，但是本申请可以通过许多替换形式来具体实现，不应被解释成仅受限于这里所阐述的实施例。
在本申请的描述中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示相对重要性，或者隐含指明所指示的技术特征的数量。由此，除非另有说明，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征；“多个”的含义是两个或两个以上。术语“包括”及其任何变形，意为不排他的包含，可能存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
另外，“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系的术语，是基于附图所示的方位或相对位置关系描述的，仅是为了便于描述本申请的简化描述，而不是指示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
此外，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如可以是固定连接，也可以是可拆卸连接，或一体地连接；可以 是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，或是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
下面参考附图和可选的实施例对本申请作具体说明。
如图1至图11所示，本申请实施例公布了一种显示面板100、制作方法和显示装置10。
一种显示面板100，包括：
第一衬底110、第一金属层120、第一绝缘层130和半导体层140，第一金属层120、第一绝缘层130和半导体层140分别堆叠设置在第一衬底110上。第一金属层120、第一绝缘层130以及半导体层140的形状一致；第二金属层160；以及第二绝缘层150，覆盖堆叠设置的第一金属层120、第一绝缘层130以及半导体层140、形成于第一金属层120和第二金属层160之间。
本方案相对于使用同一道光罩制程形成第一金属层120，第一绝缘层130以及半导体层140的显示面板100来说，第一金属层120，第一绝缘层130以及半导体层140通过同一道光罩曝光显影而成，其形状是一致的，样可以减少了对应的制程步骤，节约了制作成本，但第一金属层120，第一绝缘层130以及半导体层140边缘是平齐的，第一金属层120的底部部分裸露，就容易在后续制程中与其他导电器件造成短路，甚至会烧毁显示面板100；本方案通过第二绝缘层150对第一金属层120和第二金属层160进行隔离绝缘，第二绝缘层150覆盖堆叠设置的第一金属层120、第一绝缘层130以及半导体层140，这样确保了显示面板100的正常显示。
另外，第一衬底110壳采用玻璃基板。
在一实施例中，第二绝缘层150为黑色色阻。
本方案中，由于第一金属层120，第一绝缘层130以及半导体层140的形状是一致的，在第一金属层120的背光源入射时，入射光源可能照射到半导体层140中，导致半导体层140有电流产生，影响显示面板100性能；本方案第二绝缘层150采用黑色色阻制作成，能有效的遮挡背光源入射的光线，防止光线入射到半导体层140，避免半导体层140因为光照影响下产生电流，提升显示面板100性能。当然，的第二绝缘层150也可以采用其他的绝缘层材料，只要实现对第一金属层120和第二金属层160之间的绝缘，都是可以的。
在一实施例中，参考图1、图3、图4、图5，由于第一金属层，半导体层第一绝缘层一道光罩制成，故此为了区别三者，所以三者图示形状表示为不一致，以方便观察和理解。第一金属层120为栅极121，第二金属层160包括分离的源极161和漏极162，第一绝缘层130为栅极121绝缘层；
栅极121形成于第一衬底110上，栅极121绝缘层形成于栅极121上，半导体层140形成于栅极121绝缘层上；第二绝缘层150形成在半导体层140上；
第二绝缘层150一部分覆盖半导体层140，一部分不覆盖半导体层140；源极161和漏极162设置在半导体层140未被第二绝缘层150覆盖的区域。
这种方案形成的是开关结构如薄膜晶体管(Thin Film Transistor,TFT)，以改进薄膜晶体管的性能。第一金属层120形成薄膜晶体管的栅极121，第二金属层160形成薄膜晶体管的源极161和漏极162，第一绝缘层130为薄膜晶体管的栅极121绝缘层；第二绝缘层150形成在半导体层140上，第二绝缘层150一部分覆盖半导体层140，一部分不覆盖半导体层140，源极161和漏极162设置在半导体层140未被第二绝缘层150覆盖的区域，这样源极161和漏极162可以与半导体层140连接接触连接，这样保证了在完成面板制程后，栅极121，源极161与漏极162三者形成的开关结构可以正常工作。而若第二绝缘层150 全部覆盖半导体层140，那么栅极121，源极161和漏极162由于之间存在栅极121绝缘层和第二绝缘层150，两层都具有一定的厚度可能导致了栅极121、源极161和漏极162之间无法正常工作，影响显示面板100的性能。
在一实施例中，参考图5，第二绝缘层150形成有开口151以暴露半导体层140，开口151形成在第二绝缘层150非边缘区域，源极161和漏极162通过开口151与半导体层140导通。
本方案中，第二绝缘层150设置有开口151，开口151的设置在区域不处于第二绝缘层150的边缘部分，由于半导体层140与栅极121的形状是一致的，那么在栅极121一侧的背光源有可能入射到半导体层140进而使半导体层140产生电流，这样会导致显示面板100出现漏光或者显示不均匀的情况发生。在开口151设置在第二绝缘层150非边缘区域时，开口151四周距离第二绝缘层150的边缘的距离均大于0，开口151距离栅极121边缘的距离大于0；第二绝缘层150非开口151区域可以遮挡背光源入射的光线，进而防止半导体层140产生光电流，避免显示面板100出现漏光或者显示亮度不均匀。
本实施例可选的，参考图7，源极161的长度为d5，漏极162的长度为d6，开口151的长度为d7，源极161的长度d5与漏极162的长度d6等于开口151的长度d7。
本方案中，源极161的长度d5与漏极162的长度d6等于开口151的长度d7，这样源极161和漏极162可以遮蔽半导体层140，防止外部光源照射。
本实施例可选的，参考图8、9，第一金属层120为扫描线300，第二金属层160为数据线200；扫描线300与数据线200交错互叠的部分设置有第二绝缘层150。
本方案主要针对数据线200和扫描线300交错互叠的部分来说，因为显示 面板100制程精度的原因，数据线200和扫描线300就可能出现连通的情况，若不在扫描线300和数据线200交错互叠的区域设置第二绝缘层150，，可能造成显示面板100内出现短路的情况进而烧毁显示面板100。在设置第二绝缘层150后，第二绝缘层150对数据线200和扫描线300的交错互叠的区域，可以防止数据线200和扫描线300连通造成短路的情况发生，确保了显示面板100可以正常显示。
如图10所示，作为本申请的另一实施例，公开了一种显示面板100的制作方法，制作方法包括步骤：
S10:提供第一衬底110，覆盖第一金属层120，第一绝缘层130以及半导体层140，经过一次曝光、显影以及蚀刻，形成第一金属层120、第一绝缘层130以及半导体层140；第一金属层120、第一绝缘层130以及半导体层140的形状一致；
S11:形成第二绝缘层150；第二绝缘层150覆盖堆叠设置的第一金属层120、第一绝缘层130以及半导体层140；
S12：在第二绝缘层150上形成第二金属层160；第二绝缘层150形成于第一金属层120和第二金属层160之间。
本方案中，第一金属层120，第一绝缘层130以及半导体层140的形状是一致的，这三层可以通过同一道光罩便可以制作完成，这样可以减少了对应的制程步骤，节约了制作成本，但后续制程需要设置第二金属层160，若不对第一金属层120和第二金属层160进行隔离绝缘，那么在完成所有制程后第一金属层120和第二金属层160有可能连通，进而造成短路的情况，甚至会烧毁显示面板100。在第一金属层120和第二金属层160之间设置第二绝缘层150，这样对第一金属层120和第二金属层160起到隔离绝缘的作用，这样确保了显示 面板100的正常显示。
另外，第一衬底110的可以采用玻璃基板，其他适用材料也是可以采用的。
本实施例可选的，沉积第二金属层160，经过曝光、显影以及蚀刻，形成第二金属层160步骤之后，还包括步骤：
S13:在第二金属层160上形成钝化层170，并在钝化层170上形成过孔180；
S14:形成透明导电层190，透明导电层190通过过孔180连接第二金属层160。
这种方案形成开关结构如薄膜晶体管(Thin FilmTransistor,TFT)，第一金属层120形成栅极121，第二绝缘层150形成栅极121绝缘层，第二金属形成相互隔离的源极161和漏极162，在源极161和漏极162形成钝化层170，并在钝化层170上形成过孔180，最后形成透明电极层，这样就形成了完整的开关结构，由于这种开关结构的栅极121、第一绝缘层130与半导体是一次光罩形成的，第一绝缘层130没有完全包裹栅极121，栅极121有部分的是裸露在外的，在后形成源极161与漏极162时，栅极121有可能与源极161和漏极162连通，进而导致短路甚至烧毁面板，所以在栅极121与源极161、漏极162之间设置第二绝缘层150，这样可以对栅极121与源极161、漏极162之间进行隔离绝缘处理，可以使的显示面板100正常工作，保障了显示面不能的性能。
这种方案当然也可以形成数据线200和扫描线300，第一金属层120形成扫描线300，第二金属层160形成数据线200，因为显示面板100制程精度的原因，数据线200和扫描线300就可能出现连通的情况，若不在扫描线300和数据线200交错互叠的区域设置第二绝缘层150，，可能造成显示面板100内出现短路的情况进而烧毁显示面板100。在设置第二绝缘层150后，第二绝缘层150对数据线200和扫描线300的交错互叠的区域，可以防止数据线200和扫描线 300连通造成短路的情况发生，确保了显示面板100可以正常显示。
当然，其他开光结构也是可以适用的。
在一实施例中，形成第二绝缘层150步骤中，第二绝缘层150形成有开口151以暴露半导体层140，开口151形成在第二绝缘层150非边缘区域，源极161和漏极162通过开口151与半导体层140导通。
本方案中，第二绝缘层150的开口151，只需要在在曝光过程中所使用的光掩模上设置与开口151对应的遮光图案，经过相应显影后便可以想成开口151，在制作第二绝缘层150的制程中不增加制程步骤，制程简单易行。
如图11所示，作为本申请的另一实施例，公开了一种显示装置10，显示装置10上述显示面板100。
本方案中，显示面板内的开关结构中，第二绝缘层150对第一金属层120和第二金属层160进行隔离绝缘，第二绝缘层150覆盖堆叠设置的第一金属层120、第一绝缘层130以及半导体层140，这样确保了显示面板100的正常显示。
当然第一金属层120可以是源极121或者扫描线200，第二金属层160是源极161和漏极162，也可以是数据线300.
需要说明的是，本方案中涉及到的各步骤的限定，在不影响具体方案实施的前提下，并不认定为对步骤先后顺序做出限定，写在前面的步骤可以是在先执行的，也可以是在后执行的，甚至也可以是同时执行的，只要能实施本方案，都应当视为属于本申请的保护范围。
本申请的技术方案可以广泛运用于各种显示面板，如TN型显示面板(全称为Twisted Nematic，即扭曲向列型面板)、IPS型显示面板(In-Plane Switching，平面转换)、VA型显示面板(Vertical Alignment，垂直配向技术)、MVA型显示面板(Multi-domain Vertical Alignment，多象限垂直配向技术)，当然， 也可以是其他类型的显示面板，如有机发光显示面板(organic light-emitting diode，简称OLED显示面板)，均可适用上述方案。
以上内容是结合具体的可选实施方式对本申请所作的具体详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (13)

  1. 一种显示面板，所述显示面板包括：
    第一衬底；
    第一金属层、第一绝缘层和半导体层，分别堆叠设置在所述第一衬底上，所述第一金属层、第一绝缘层以及半导体层的形状一致；
    第二金属层；以及
    第二绝缘层，覆盖所述堆叠设置的第一金属层、第一绝缘层以及半导体层、且形成于所述第一金属层和所述第二金属层之间。
  2. 如权利要求1所述一种显示面板，其中，所述第二绝缘层为黑色色阻。
  3. 如权利要求2所述一种显示面板，其中，所述第二绝缘层为绝缘材料制成。
  4. 如权利要求1所述一种显示面板，其中，所述第一金属层为栅极，所述第二金属层包括分离的源极和漏极，所述第一绝缘层为栅极绝缘层；
    所述栅极形成于第一衬底上，所述栅极绝缘层形成于栅极上，所述半导体层形成于栅极绝缘层上；所述第二绝缘层形成在所述半导体层上；
    所述第二绝缘层一部分覆盖所述半导体层，一部分不覆盖所述半导体层；所述源极和漏极设置在所述半导体层未被第二绝缘层覆盖的区域。
  5. 如权利要求3所述一种显示面板，其中，所述第二绝缘层形成有开口以暴露所述半导体层，所述开口形成在所述第二绝缘层非边缘区域，所述源极和所述漏极通过所述开口与所述半导体层导通。
  6. 如权利要求3所述一种显示面板，其中，开口四周距离第二绝缘层的边缘的距离均大于0，开口距离栅极边缘的距离大于0。
  7. 如权利要求4所述一种显示面板，其中，所述源极的长度为d5，所述漏极的长度为d6，所述开口的长度为d7，所述源极的长度d5与漏极的长度d6等于所述开口的长度d7。
  8. 如权利要求1所述一种显示面板，其中，所述第一金属层为扫描线，所述第二金属层为数据线；所述扫描线与数据线交错互叠的部分设置有第二绝缘层。
  9. 如权利要求1所述一种显示面板，其中，所述第一衬底为玻璃基板。
  10. 如权利要求1所述一种显示面板，其中，所述第一金属层为栅极，所述第二金属为相互独立的源极和漏极。
  11. 如权利要求1所述一种显示面板，其中，第一金属层，第一绝缘层以及半导体层通过同一道光罩曝光显影而成，其形状是一致的。
  12. 一种显示面板的制作方法，所述制作方法包括步骤：
    提供第一衬底，覆盖第一金属层，第一绝缘层以及半导体层，经过一次曝光、显影以及蚀刻，形成第一金属层、第一绝缘层以及半导体层；所述第一金属层、第一绝缘层以及半导体层的形状一致；
    形成第二绝缘层；所述第二绝缘层覆盖所述堆叠设置的第一金属层、第一绝缘层以及半导体层；以及
    在所述第二绝缘层上形成第二金属层；所述第二绝缘层形成于所述第一金属层和第二金属层之间。
  13. 如权利要求13所述一种显示面板的制作方法，其中，所述沉积第二金属层，经过曝光、显影以及蚀刻，形成第二金属层步骤之后，还包括步骤：
    在所述第二金属层上形成钝化层，并在所述钝化层上形成过孔；
PCT/CN2018/118158 2018-11-12 2018-11-29 显示面板及其制作方法和显示装置 Ceased WO2020097993A1 (zh)

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