WO2020095142A1 - 表示装置および電子機器 - Google Patents

表示装置および電子機器 Download PDF

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Publication number
WO2020095142A1
WO2020095142A1 PCT/IB2019/059206 IB2019059206W WO2020095142A1 WO 2020095142 A1 WO2020095142 A1 WO 2020095142A1 IB 2019059206 W IB2019059206 W IB 2019059206W WO 2020095142 A1 WO2020095142 A1 WO 2020095142A1
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WO
WIPO (PCT)
Prior art keywords
transistor
circuit
electrode
display device
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2019/059206
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English (en)
French (fr)
Japanese (ja)
Inventor
豊高耕平
齋藤元晴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to KR1020217016002A priority Critical patent/KR102932698B1/ko
Priority to US17/285,603 priority patent/US11663990B2/en
Priority to CN201980073616.2A priority patent/CN112955946B/zh
Priority to JP2020556357A priority patent/JP7441176B2/ja
Publication of WO2020095142A1 publication Critical patent/WO2020095142A1/ja
Anticipated expiration legal-status Critical
Priority to US18/134,054 priority patent/US12039952B2/en
Priority to JP2024021729A priority patent/JP2024050929A/ja
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • One embodiment of the present invention relates to a display device.
  • one embodiment of the present invention is not limited to the above technical field.
  • the technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method.
  • one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, more specifically, as technical fields of one embodiment of the present invention disclosed in this specification, a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, and the like.
  • An operation method or a manufacturing method thereof can be given as an example.
  • a semiconductor device generally means a device that can function by utilizing semiconductor characteristics.
  • a transistor and a semiconductor circuit are one mode of a semiconductor device.
  • the memory device, the display device, the imaging device, and the electronic device may include a semiconductor device.
  • Patent Document 1 and Patent Document 2 disclose a technique in which a transistor including zinc oxide or an In—Ga—Zn-based oxide is used for a switching element of a pixel of a display device.
  • Patent Document 3 discloses a memory device having a configuration in which a transistor having an extremely low off-state current is used for a memory cell.
  • a driver that supplies data to pixels of a display device has a logic portion and an amplifier portion and is designed so that respective operations are appropriate.
  • the logic section is designed to be high-speed and suppress power consumption
  • the amplifier section is designed to be capable of outputting high withstand voltage and high voltage. Therefore, it is necessary to arrange transistors and the like having different configurations in one chip, which requires many manufacturing steps, which is one of the causes of cost increase.
  • the power supply voltage is different between the logic section and the amplifier section, a circuit that outputs at least two voltages is required. If the voltage output can be unified, the power supply circuit can be simplified and the cost can be reduced. If the power supply voltage of the amplifier unit can be reduced, the power consumption of the driver as a whole can be reduced.
  • a display device including a driver with low power consumption. Another object is to provide a display device which includes a driver with low power consumption and boosts an output voltage of the driver by a pixel. Another object is to provide a display device that can supply a voltage higher than the output voltage of a source driver to a display device. Another object is to provide a display device capable of increasing the brightness of a display image.
  • Another object is to provide a display device with low power consumption. Alternatively, it is another object to provide a highly reliable display device. Another object is to provide a new display device or the like. Another object is to provide a method for driving the above display device. Another object is to provide a novel semiconductor device or the like.
  • One embodiment of the present invention relates to a display device including a driver with low power consumption.
  • One embodiment of the present invention is a display device including a driver circuit and a pixel circuit, in which the driver circuit includes a shift register circuit and an amplifier circuit, and the pixel circuit is output from the amplifier circuit.
  • the display device has a function of adding the first data and the second data to generate the third data, and has the configuration in which the same power supply voltage is supplied to the shift register circuit and the amplifier circuit.
  • the shift register circuit and the amplifier circuit can have a structure in which the same power supply circuit is electrically connected.
  • the power supply voltage supplied to the driver circuit can be 3.3 V or less.
  • the driver circuit further includes one or more circuits selected from an input interface circuit, a serial-parallel conversion circuit, a latch circuit, a level shift circuit, a PTL (pass transistor logic), a digital-analog conversion circuit, and a bias generation circuit.
  • the circuit may be configured to be supplied with the same power supply voltage as the shift register circuit and the amplifier circuit.
  • Another embodiment of the present invention is a display device including a driver circuit and a pixel circuit, wherein the driver circuit includes a shift register circuit and an amplifier circuit, and the pixel circuit outputs from the amplifier circuit.
  • the shift register circuit has a first transistor
  • the amplifier circuit has a second transistor.
  • the first transistor and the second transistor when the gate insulating film of one transistor has a region of thickness a, the other transistor has a gate insulating film of 0.9a or more and 1.1a or less.
  • the display device has the following regions.
  • the driver circuit further includes one or more circuits selected from an input interface circuit, a serial-parallel conversion circuit, a latch circuit, a level shift circuit, a PTL, a digital-analog conversion circuit, and a bias generation circuit.
  • the transistor included can have a region where the thickness of the gate insulating film is 0.9 a or more and 1.1 a or less.
  • the pixel circuit includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, a second capacitor, a light emitting device, And one of the source and drain of the third transistor is electrically connected to one electrode of the first capacitor, and the other electrode of the first capacitor is connected to the source or drain of the fourth transistor.
  • One of the source and the drain of the fourth transistor is electrically connected to one of the sources and the drain of the fifth transistor, and one electrode of the first capacitor is connected to the sixth electrode.
  • one of the source and the drain of the sixth transistor is the source or the drain of the seventh transistor
  • One of the source and the drain of the seventh transistor is electrically connected to one electrode of the light-emitting device, and the one electrode of the light-emitting device is electrically connected to one electrode of the second capacitor.
  • the second electrode of the second capacitor which is electrically connected to the second capacitor can be electrically connected to the gate of the seventh transistor.
  • the pixel circuit includes a third transistor, a fourth transistor, a fifth transistor, a first capacitor, a second capacitor, and a liquid crystal device, and a source of the third transistor.
  • one of the drains is electrically connected to one electrode of the first capacitor, and the other electrode of the first capacitor is electrically connected to one of the source and the drain of the fourth transistor.
  • One of a source and a drain of the transistor is electrically connected to one of a source and a drain of the fifth transistor, and one electrode of the first capacitor is electrically connected to one electrode of the second capacitor.
  • One electrode of the second capacitor can be electrically connected to one electrode of the liquid crystal device.
  • the other of the source and the drain of the third transistor may be electrically connected to the other of the source and the drain of the fourth transistor.
  • a transistor included in a pixel circuit includes a metal oxide in a channel formation region, and the metal oxide includes In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, or Nd). Or Hf).
  • a display device including a driver with low power consumption can be provided.
  • a display device which includes a driver with low power consumption and boosts an output voltage of the driver by a pixel can be provided.
  • a display device that can supply a voltage higher than the output voltage of the source driver to the display device can be provided.
  • a display device capable of increasing the brightness of a display image can be provided.
  • a display device with low power consumption can be provided.
  • a highly reliable display device can be provided.
  • a new display device or the like can be provided.
  • a method for driving the above display device can be provided.
  • a novel semiconductor device or the like can be provided.
  • FIG. 1 is a diagram illustrating a display device.
  • FIG. 2 is a diagram illustrating a pixel circuit.
  • 3A to 3C are diagrams illustrating a pixel circuit.
  • FIG. 4 is a diagram illustrating a pixel circuit.
  • FIG. 5 is a timing chart explaining the operation of the pixel circuit.
  • 6A to 6C are diagrams illustrating a pixel circuit.
  • FIG. 7 is a diagram illustrating a pixel circuit.
  • FIG. 8 is a diagram illustrating a pixel circuit.
  • FIG. 9 is a diagram illustrating a pixel circuit.
  • 10A to 10C are diagrams illustrating a pixel layout.
  • FIG. 11A is a diagram illustrating a source driver.
  • 11B and 11C are diagrams illustrating a transistor.
  • FIG. 11A is a diagram illustrating a source driver.
  • 11B and 11C are diagrams illustrating a transistor.
  • FIG. 11A is a diagram illustrating a source driver
  • 12A is a diagram illustrating a source driver.
  • 12B and 12C are diagrams illustrating a transistor.
  • 13A to 13C are diagrams illustrating a display device.
  • 14A and 14B are diagrams illustrating a touch panel.
  • 15A and 15B are diagrams illustrating a display device.
  • FIG. 16 is a diagram illustrating a display device.
  • 17A and 17B are diagrams illustrating a display device.
  • 18A and 18B are diagrams illustrating a display device.
  • 19A to 19E are diagrams illustrating a display device.
  • 20A1 to 20C2 are diagrams illustrating transistors.
  • 21A1 to 21C2 are diagrams illustrating a transistor.
  • 22A1 to 22C2 are diagrams illustrating transistors.
  • 23A1 to 23C2 are diagrams illustrating transistors.
  • FIG. 24A to 24F are diagrams illustrating electronic devices.
  • 25A and 25B are diagrams illustrating the I D -V G characteristics of a transistor.
  • FIG. 26A is a diagram illustrating an EL pixel circuit.
  • FIG. 26B is a timing chart.
  • 27A and 27B are diagrams illustrating a liquid crystal pixel circuit.
  • FIG. 28 is a block diagram of the source driver.
  • 29A and 29B are diagrams for explaining simulation results of power consumption of the source driver.
  • FIG. 30 is a diagram for explaining the actual measurement result of the power consumption of the panel.
  • FIG. 31A is a diagram illustrating the transmittance of a liquid crystal device.
  • FIG. 31B is a diagram illustrating the brightness of the liquid crystal display panel.
  • FIG. 32A is a display image photograph of an EL display panel.
  • FIG. 32B is a display image photograph of the liquid crystal display panel.
  • the element may be composed of a plurality of elements.
  • a plurality of transistors which operate as switches may be connected in series or in parallel.
  • a capacitor also referred to as a capacitor
  • a capacitor may be divided and placed at a plurality of positions.
  • one conductor may have a plurality of functions such as a wiring, an electrode, and a terminal in some cases, and in this specification, a plurality of names may be used for the same element.
  • a plurality of names may be used for the same element.
  • the elements may actually be connected via a plurality of conductors, and In the book, such a configuration is included in the category of direct connection.
  • One embodiment of the present invention is a display device including a low power consumption source driver and a pixel having a function of adding data.
  • the source driver has a configuration in which the logic section and the amplifier section properly operate with the same power supply voltage. Since the power supply voltage of the logic unit that operates with low power consumption is used as a reference, the voltage that can be output by the amplifier unit is small, but the power consumption of the entire source driver can be suppressed.
  • the pixel has a function of holding the first data, a function of adding the second data to the first data to generate third data, and supplying the third data to the display device.
  • a display device with extremely low power consumption can be realized by combining a source driver with low power supply voltage and a pixel capable of boosting operation.
  • FIG. 1 is a diagram illustrating a display device of one embodiment of the present invention.
  • the display device includes a pixel array 11, a source driver 20, and a gate driver 30.
  • the pixel array 11 has the pixels 10 arranged in the column direction and the row direction.
  • the wiring is illustrated in a simplified manner, and details will be described later.
  • the source driver 20 can be configured to include a logic unit 21 and an amplifier unit 22.
  • a power supply circuit 25 is electrically connected to the logic unit 21 and the amplifier unit 22.
  • the number of power supply circuits 25 is not limited to one, but the voltages supplied to the logic unit 21 and the amplifier unit 22 can be the same.
  • a method of attaching an IC chip by a COF (chip on film) method, a COG (chip on glass) method, a TCP (tape carrier package) method, or the like can be used.
  • a transistor manufactured by using the same process as the pixel array 11 may be used and the transistor may be formed on the same substrate as the pixel array 11.
  • FIG. 1 shows an example in which the gate driver 30 is arranged on one side of the pixel array 11, two gate drivers 30 may be arranged so as to face each other with the pixel array 11 interposed therebetween, and the drive row may be divided.
  • the pixel 10 includes a transistor 101, a transistor 102, a transistor 103, a transistor 104, a transistor 105, a capacitor 106, a capacitor 107, and a light emitting device 108.
  • One of a source and a drain of the transistor 101 is electrically connected to one electrode of the capacitor 106.
  • the other electrode of the capacitor 106 is electrically connected to one of a source and a drain of the transistor 102.
  • One of a source and a drain of the transistor 102 is electrically connected to one of a source and a drain of the transistor 103.
  • One electrode of the capacitor 106 is electrically connected to the gate of the transistor 104.
  • One of a source and a drain of the transistor 104 is electrically connected to one of a source and a drain of the transistor 105.
  • One of a source and a drain of the transistor 105 is electrically connected to one electrode of the light emitting device 108.
  • One electrode of the light emitting device 108 is electrically connected to one electrode of the capacitor 107.
  • the other electrode of the capacitor 107 is electrically connected to the gate of the transistor 104.
  • the connection between the elements of the pixel 10 and various wirings will be described.
  • the gate of the transistor 101 is electrically connected to the wiring 125.
  • the gate of the transistor 102 is electrically connected to the wiring 126.
  • the gate of the transistor 103 is electrically connected to the wiring 125.
  • the gate of the transistor 105 is electrically connected to the wiring 127.
  • the other of the source and the drain of the transistor 101 is electrically connected to the wiring 121.
  • the other of the source and the drain of the transistor 102 is electrically connected to the wiring 122.
  • the other of the source and the drain of the transistor 103 is electrically connected to the wiring 124.
  • the other of the source and the drain of the transistor 104 is electrically connected to the wiring 123.
  • the other of the source and the drain of the transistor 105 is electrically connected to the wiring 124.
  • the other electrode of the light emitting device 108 is electrically connected to the wiring 129.
  • the wirings 125, 126, 127 have a function as a gate line and can be electrically connected to the gate driver 30 (see FIG. 1).
  • the wirings 121 and 122 have a function as a source line and can be electrically connected to the source driver 20.
  • the wirings 123 and 129 can have a function as power supply lines. For example, by supplying a high potential to the wiring 123 and a low potential to the wiring 129, the light emitting device 108 can be forward-biased (emitted).
  • the wiring 124 can have a function of being supplied with a reference potential (V ref ).
  • V ref a reference potential
  • 0V, GND potential or the like can be used.
  • the specific potential may be “V ref ”.
  • a wiring connecting one of the source and the drain of the transistor 101, one electrode of the capacitor 106, the other electrode of the capacitor 107, and the gate of the transistor 104 is referred to as a node NM.
  • a wiring that connects one of a source and a drain of the transistor 102, the other electrode of the capacitor 106, and one of a source and a drain of the transistor 103 is referred to as a node NA.
  • the transistor 101 can have a function of writing the potential of the wiring 121 in the node NM.
  • the transistor 102 can have a function of writing the potential of the wiring 122 in the node NA.
  • the transistor 103 can have a function of supplying the reference potential (V ref ) to the node NA.
  • the transistor 104 can have a function of controlling a current flowing to the light emitting device 108 according to the potential of the node NM.
  • the transistor 105 can have a function of fixing the source potential of the transistor 104 at the time of writing data to the node NM and a function of controlling the operation timing of the light emitting device 108.
  • the node NM is connected to the node NA via the capacitor 106. Therefore, when the node NM is in a floating state, the potential change of the node NA can be added by capacitive coupling. The addition of potentials at the node NM will be described below.
  • the first data (weight: “W”) is written in the node NM.
  • the reference potential “V ref ” is supplied to the node NA, and the capacitor 106 holds “W ⁇ V ref ”.
  • the node NA is made floating, and the second data (data: “D”) is supplied to the node NA.
  • the potential of the node NM is W + (C 106 / (C 106 + C NM )) ⁇ (D ⁇ V ref ). ..
  • the potential of the node NM can be regarded as "W + D-V ref" .
  • V ref is “ ⁇ W” or “ ⁇ D”
  • the potential of the node NM can be close to “3D”.
  • the node NM and the node NA act as holding nodes. Data can be written to each node by making a transistor connected to each node conductive. By turning off the transistor, the data can be held in each node. By using a transistor with extremely low off-state current as the transistor, leakage current can be suppressed and the potential of each node can be held for a long time.
  • a transistor in which a metal oxide is used for a channel formation region hereinafter referred to as an OS transistor is preferably used.
  • an OS transistor it is preferable to apply an OS transistor to any or all of the transistors 101, 102, and 103.
  • OS transistors may be applied to all the transistors included in the pixel 10.
  • a transistor having Si in a channel formation region hereinafter referred to as a Si transistor
  • an OS transistor and a Si transistor may be used together.
  • the Si transistor include a transistor including amorphous silicon, a transistor including crystalline silicon (microcrystalline silicon, low-temperature polysilicon, single crystal silicon), and the like.
  • a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used.
  • an oxide semiconductor containing indium or the like can be used, and for example, CAAC-OS or CAC-OS described later can be used.
  • the CAAC-OS has stable atoms forming a crystal and is suitable for a transistor in which reliability is important. Further, since the CAC-OS exhibits high mobility characteristics, it is suitable for a transistor or the like which drives at high speed.
  • the OS transistor Since the OS transistor has a large energy gap in the semiconductor layer, it can exhibit extremely low off-current characteristics of several yA / ⁇ m (current value per 1 ⁇ m of channel width). Further, the OS transistor has characteristics different from those of the Si transistor such that impact ionization, avalanche breakdown, short channel effect, and the like do not occur, and a highly reliable circuit can be formed. Further, variations in electrical characteristics due to non-uniformity of crystallinity, which is a problem in Si transistors, are less likely to occur in OS transistors.
  • the semiconductor layer included in the OS transistor is an In-M-Zn-based semiconductor layer containing indium, zinc, and M (M is a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). It can be a film represented by an oxide.
  • M is a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium.
  • M is a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium.
  • M is a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or
  • the atomic ratio of the metal elements of the sputtering target used for forming the In-M-Zn-based oxide by a sputtering method preferably satisfies In? M and Zn? M.
  • the atomic ratio of the semiconductor layers to be formed includes a fluctuation of ⁇ 40% in the atomic ratio of the metal elements contained in the sputtering target.
  • an oxide semiconductor having a low carrier density is used for the semiconductor layer.
  • the semiconductor layer has a carrier density of 1 ⁇ 10 17 / cm 3 or less, preferably 1 ⁇ 10 15 / cm 3 or less, more preferably 1 ⁇ 10 13 / cm 3 or less, and more preferably 1 ⁇ 10 11 / cm 3. cm 3 or less, more preferably less than 1 ⁇ 10 10 / cm 3 , and 1 ⁇ 10 ⁇ 9 / cm 3 or more of an oxide semiconductor can be used.
  • Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. It can be said that the oxide semiconductor has low density of defect states and stable characteristics.
  • the composition is not limited to these, and a material having an appropriate composition may be used depending on required semiconductor characteristics and electrical characteristics of a transistor (field-effect mobility, threshold voltage, or the like). Further, in order to obtain the required semiconductor characteristics of the transistor, it is preferable that the carrier density, the impurity concentration, the defect density, the atomic ratio of the metal element and oxygen, the interatomic distance, the density, and the like of the semiconductor layer be appropriate. ..
  • the concentration of silicon or carbon in the semiconductor layer is 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3. / Cm 3 or less.
  • the concentration of alkali metal or alkaline earth metal (concentration obtained by SIMS) in the semiconductor layer is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • the nitrogen concentration (concentration obtained by SIMS) in the semiconductor layer is preferably 5 ⁇ 10 18 atoms / cm 3 or less.
  • the transistor when hydrogen is contained in the oxide semiconductor included in the semiconductor layer, oxygen reacts with oxygen which is bonded to a metal atom to be water, which might cause oxygen deficiency in the oxide semiconductor.
  • the channel formation region in the oxide semiconductor contains oxygen vacancies, the transistor might have normally-on characteristics.
  • a defect in which hydrogen is contained in an oxygen vacancy may function as a donor and an electron which is a carrier may be generated.
  • part of hydrogen may be bonded to oxygen which is bonded to a metal atom to generate an electron which is a carrier. Therefore, a transistor including an oxide semiconductor which contains a large amount of hydrogen is likely to have normally-on characteristics.
  • the defect in which hydrogen is contained in oxygen vacancies can function as a donor of the oxide semiconductor.
  • defects may be evaluated by carrier concentration instead of donor concentration. Therefore, in this specification and the like, a carrier concentration which is assumed to be a state where no electric field is applied may be used as a parameter of the oxide semiconductor, instead of the donor concentration. That is, the “carrier concentration” described in this specification and the like can be called the “donor concentration” in some cases.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , and more preferably 5 ⁇ 10 18 atoms / cm 3. It is less than 3 , and more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • the semiconductor layer may have a non-single crystal structure, for example.
  • the non-single-crystal structure includes, for example, a CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having a c-axis oriented crystal, a polycrystalline structure, a microcrystalline structure, or an amorphous structure.
  • CAAC-OS C-Axis Aligned Crystalline Oxide Semiconductor
  • the amorphous structure has the highest defect level density and the CAAC-OS has the lowest defect level density.
  • the oxide semiconductor film having an amorphous structure has disordered atomic arrangement and no crystalline component, for example.
  • the oxide film having an amorphous structure has, for example, a completely amorphous structure and has no crystal part.
  • the semiconductor layer may be a mixed film including two or more kinds of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region.
  • the mixed film may have, for example, a single-layer structure or a laminated structure including any two or more kinds of the above-mentioned regions.
  • CAC Cloud-Aligned Composite
  • the CAC-OS is a structure of a material in which an element included in an oxide semiconductor is unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof.
  • an oxide semiconductor one or more metal elements are unevenly distributed and a region including the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm or less, or a size in the vicinity thereof.
  • the state of being mixed with is also called a mosaic shape or a patch shape.
  • the oxide semiconductor preferably contains at least indium. It is particularly preferable to contain indium and zinc. In addition to them, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. One kind or a plurality of kinds selected from may be contained.
  • CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS may be particularly referred to as CAC-IGZO) means indium oxide (hereinafter, InO).
  • InO indium oxide
  • X1 X1 is a real number larger than 0
  • In X2 Zn Y2 O Z2 X2, Y2, and Z2 are real numbers larger than 0
  • gallium indium oxide (hereinafter, InO).
  • GaO X3 (X3 is a real number larger than 0)) or gallium zinc oxide (hereinafter, Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers larger than 0)) to.) and the like, the material becomes mosaic by separate into, mosaic InO X1 or in X2 Zn Y2 O Z2, is a configuration in which uniformly distributed in the film (hereinafter Also referred to as a cloud-like.) A.
  • the CAC-OS is a composite oxide semiconductor having a structure in which a region containing GaO X3 as a main component and a region containing In X2 Zn Y2 O Z2 or InO X1 are mixed.
  • the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the region of No. 2.
  • IGZO is a common name and may refer to one compound of In, Ga, Zn, and O.
  • InGaO 3 (ZnO) m1 (m1 is a natural number) or In (1 + x0) Ga (1-x0) O 3 (ZnO) m0 (-1 ⁇ x0 ⁇ 1, m0 is an arbitrary number) is represented. Crystalline compounds may be mentioned.
  • the crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure.
  • the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals has c-axis orientation and is connected without being oriented in the ab plane.
  • CAC-OS relates to a material structure of an oxide semiconductor.
  • CAC-OS is a region that is observed in the form of nanoparticles mainly containing Ga as a main component and nanoparticles mainly containing In as a main component in a material configuration containing In, Ga, Zn, and O.
  • the regions that are observed in a pattern are each randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.
  • the CAC-OS does not include a stacked structure of two or more kinds of films having different compositions.
  • a structure having two layers of a film containing In as a main component and a film containing Ga as a main component is not included.
  • the CAC-OS has a partly observed region in the form of nanoparticles mainly containing the metal element and a part mainly containing In as a main component. The areas observed in the form of particles are randomly dispersed in a mosaic shape.
  • the CAC-OS can be formed by a sputtering method under the condition that the substrate is not heated intentionally, for example.
  • any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as a film formation gas.
  • an inert gas typically argon
  • oxygen gas typically argon
  • a nitrogen gas may be used as a film formation gas.
  • the flow rate ratio of the oxygen gas is 0% or more and less than 30%, preferably 0% or more and 10% or less. ..
  • the CAC-OS is characterized in that no clear peak is observed when it is measured using a ⁇ / 2 ⁇ scan by the Out-of-plane method, which is one of the X-ray diffraction (XRD: X-ray diffraction) measurement methods. Have. That is, it can be seen from the X-ray diffraction measurement that orientations in the ab plane direction and the c-axis direction of the measurement region are not seen.
  • XRD X-ray diffraction
  • the electron beam diffraction pattern of the CAC-OS which is obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam electron beam), a ring-shaped region with high brightness (ring region) and the ring Multiple bright spots are observed in the area. Therefore, it can be seen from the electron beam diffraction pattern that the crystal structure of CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.
  • nc nano-crystal
  • GaO X3 is a main component by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy). It can be confirmed that the region and the region containing In X2 Zn Y2 O Z2 or InO X1 as main components are unevenly distributed and mixed.
  • the CAC-OS has a structure different from that of the IGZO compound in which the metal element is uniformly distributed, and has a property different from that of the IGZO compound. That is, the CAC-OS is phase-separated into a region containing GaO X3 or the like as a main component and a region containing In X2 Zn Y2 O Z2 or InO X1 as a main component, and a region containing each element as a main component. Has a mosaic structure.
  • the region containing In X2 Zn Y2 O Z2 or InO X1 as a main component is a region having higher conductivity than a region containing GaO X3 or the like as a main component. That is, the carriers flow in the region containing In X2 Zn Y2 O Z2 or InO X1 as a main component, so that conductivity as an oxide semiconductor is developed. Therefore, a region containing In X2 Zn Y2 O Z2 or InO X1 as a main component is distributed in a cloud shape in the oxide semiconductor, whereby high field-effect mobility ( ⁇ ) can be realized.
  • a region containing GaO X3 or the like as a main component has a higher insulating property than a region containing In X2 Zn Y2 O Z2 or InO X1 as a main component. That is, the region containing GaO X3 or the like as a main component is distributed in the oxide semiconductor, whereby leakage current can be suppressed and favorable switching operation can be realized.
  • the CAC-OS when used for a semiconductor device, the insulating property due to GaO X3 or the like and the conductivity due to In X2 Zn Y2 O Z2 , or InO X1 are high due to complementary action.
  • On-current (I on ) and high field-effect mobility ( ⁇ ) can be realized.
  • the semiconductor device using the CAC-OS has high reliability. Therefore, the CAC-OS is suitable as a constituent material of various semiconductor devices.
  • one electrode of the light emitting device 108 is electrically connected to the wiring 123 and the other electrode of the light emitting device 108 is connected to the electrode 123. It may be electrically connected to the other of the source and the drain of the transistor 104.
  • the transistor 109 may be provided between one of a source and a drain of the transistor 104 and one electrode of the light emitting device 108.
  • the timing of light emission can be controlled arbitrarily.
  • the configurations shown in FIGS. 3A and 3B may be combined.
  • the circuit 40 can be electrically connected to the wiring 124 connected to the transistor 105.
  • the circuit 40 can have one or more of a supply source of a reference potential (V ref ), a function of acquiring electric characteristics of the transistor 104, and a function of generating correction data.
  • the gate line may be shared by two pixels adjacent in the vertical direction (direction in which the source lines (wirings 121 and 122) extend).
  • FIG. 4 illustrates the pixel 10 [n, m] arranged in the nth row and the mth column (n and m are natural numbers of 1 or more) and the pixel 10 [n + 1, m] arranged in the n + 1th row and the mth column.
  • FIG. 4 illustrates the pixel 10 [n, m] arranged in the nth row and the mth column (n and m are natural numbers of 1 or more) and the pixel 10 [n + 1, m] arranged in the n + 1th row and the mth column.
  • the gate of the transistor 102 of the pixel 10 [n, m] is electrically connected to the wiring 125 [n + 1].
  • the gate of the transistor 101 and the gate of the transistor 103 of the pixel 10 [n + 1, m] are electrically connected to the wiring 125 [n + 1].
  • the gate of the transistor 102 of the pixel 10 [n + 1, m] is electrically connected to the wiring 125 [n + 2].
  • the gate of the transistor 101 and the gate of the transistor 103 of the pixel 10 [n + 2, m] are electrically connected to the wiring 125 [n + 2].
  • the pixel 10 of one embodiment of the present invention there are two writing operations of writing first data (weight) and writing second data (data). Since the weight and the data are supplied from different source lines, the timing of writing the data of one pixel and the timing of the weight writing of the other pixel can be overlapped in two vertically adjacent pixels. Therefore, the gate lines connected to the gates of the transistors that perform these operations can be shared.
  • the number of gate lines per pixel can be reduced from three to substantially two, and the aperture ratio of the pixel can be increased. Moreover, the operation of the gate driver can be simplified. Moreover, since the number of gate wirings that need to be charged and discharged is reduced, power consumption can be reduced.
  • the high potential is represented by “H” and the low potential is represented by “L”.
  • the weight supplied to the pixel 10 [n, m] is “W1”
  • the image data is “D1”
  • the weight supplied to the pixel 10 [n + 1, m] is “W2”
  • the image data is “D2”.
  • V ref for example, 0V, GND potential or a specific potential can be used.
  • the wiring 123 is constantly supplied with a high potential
  • the wiring 129 is constantly supplied with a low potential
  • the wiring 124 is constantly supplied with a reference potential (V ref ). Note that there may be a period during which these potentials are not supplied as long as the operation is not hindered.
  • “W1” is supplied to the wiring 121 from time T1 to time T2.
  • the transistor 101 is turned on, and the potential of the wiring 121 [m] is written to the node NM [n, m].
  • the operation is a weight writing operation in the pixel 10 [n, m], and the potential “W1” is written in the node NM [n, m].
  • the transistor 105 is turned on and the source potential of the transistor 104 becomes “V ref ”. Therefore, the light emitting device 108 does not emit light even when the transistor 104 is turned on.
  • the potential of the wiring 125 [n] is “L”
  • the potential of the wiring 127 [n] is “H”
  • the potential of the wiring 125 [n + 1] is “H”
  • the potential of the wiring 127 [n + 1] is “H”.
  • the transistor 101 becomes non-conductive.
  • “W1” is held in the node NM [n, m]. Further, “W1-V ref ” is held in the capacitor 106.
  • the transistor 103 is turned off, the transistor 102 is turned on, and the potential of the node NA [n, m] becomes the potential “D1” of the wiring 122 [m].
  • “(D1 ⁇ V ref ) ′” according to the capacitance ratio between the capacitor 106 and the node NM [n, m] is added to the node NM [n, m].
  • This operation is an addition operation in the pixel 10 [n, m], and the potential of the node NM [n, m] becomes “W1 + (D1-V ref ) ′”.
  • the source potential of the transistor 104 is “V ref ”, and the potential “W1 + D1 ′” can be written to the node NM [n, m] while the source potential of the transistor 104 is stable.
  • This operation is a reset operation for performing the subsequent addition operation (capacitive coupling operation).
  • the transistor 101 is turned on, and the potential of the wiring 121 [m] is written to the node NM [n + 1, m].
  • the operation is a weight writing operation in the pixel 10 [n + 1, m], and the potential “W2” is written in the node NM [n + 1, m].
  • the transistor 105 is turned on and the source potential of the transistor 104 becomes “V ref ”. Therefore, the light emitting device 108 does not emit light even when the transistor 104 is turned on.
  • “D2” is supplied to the wiring 122 from time T3 to time T4.
  • the potential of the wiring 127 [n] is “L”
  • the potential of the wiring 125 [n + 1] is “L”
  • the potential of the wiring 127 [n + 1] is “H”
  • the potential of the wiring 125 [n + 2] is “H”.
  • the transistor 103 is non-conductive and the transistor 102 is conductive, so that the potential of the node NA [n + 1, m] becomes the potential “D2” of the wiring 122 [m].
  • “(D2-V ref ) ′” according to the capacitance ratio between the capacitor 106 and the node NM [n + 1, m] is added to the node NM [n + 1, m].
  • This operation is an addition operation in the pixel 10 [n + 1, m], and the potential of the node NM [n + 1, m] becomes “W2 + (D2-V ref ) ′”.
  • the source potential of the transistor 104 is “V ref ”, and the potential “W1 + D2 ′” can be written to the node NM [n + 1, m] while the source potential of the transistor 104 is stable.
  • the transistor 105 When the potential of the wiring 127 [n + 1] is set to “L” and the potential of the wiring 125 [n + 2] is set to “L” at time T4, the transistor 105 is turned off in the pixel 10 [n + 1, m] and the node NM [n + 1, m]. A current flows from the transistor 104 to the light emitting device 108 according to the potential of [m], and the light emitting device 108 emits light.
  • FIG. 6A is a circuit diagram of a pixel 10 using a liquid crystal device as a display device.
  • One electrode of the liquid crystal device 110 is electrically connected to the node NM, and the other electrode of the liquid crystal device 110 is electrically connected to the wiring 130.
  • the other electrode of the capacitor 107 is electrically connected to the wiring 131.
  • the wiring 130 and the wiring 131 may be electrically connected to each other.
  • the wirings 130 and 131 have a function of supplying power.
  • the wirings 130 and 131 can supply a reference potential such as GND or 0 V or an arbitrary potential.
  • the wiring 131 can be used as illustrated in FIG. 6B.
  • the wiring 130 may be used.
  • the capacitor 107 may be omitted.
  • the OS transistor can be used as the transistor connected to the node NM. Since the leakage current of the OS transistor is extremely small, display can be maintained for a relatively long time even if the capacitor 107 which functions as a storage capacitor is omitted. Further, not limited to the configuration of the transistor, it is effective to omit the capacitor 107 even when the display period can be shortened by high-speed operation such as field sequential driving. By omitting the capacitor 107, the aperture ratio can be improved. Alternatively, the transmittance of the pixel can be improved.
  • the gate line can be shared by two pixels in the vertical direction as in FIG. As shown in FIG. 7, when a liquid crystal device is used, the number of gate lines can be reduced from two to substantially one per pixel by sharing a gate line between two pixels.
  • the operation when a light-emitting device is used can be referred to.
  • a transistor may be provided with a back gate as illustrated in FIG. FIG. 8 shows a configuration in which the back gate is electrically connected to the front gate, which has the effect of increasing the on-current.
  • the back gate may be electrically connected to a wiring which can supply a constant potential. With this structure, the threshold voltage of the transistor can be controlled.
  • the pixel 10 of one embodiment of the present invention may have a single source line as shown in FIG.
  • the source line for supplying them can be shared.
  • FIG. 10A, 10B, and 10C are examples of layout diagrams of the pixel 10 when a light emitting device is used as a display device.
  • FIG. 10A is a diagram illustrating an arrangement and a configuration of a transistor and a capacitor, and shows a stack including a gate wiring, a semiconductor layer (metal oxide layer), and a source-drain wiring.
  • the transistors 101 to 105 have a top-gate self-aligned structure and have a back gate.
  • the back gate also functions as a gate wiring.
  • the capacitors 106 and 107 are formed in the same step as the conductive layer formed in the same step as the gate wiring, the insulating layer formed in the same step as the gate insulating film of the back gate, and the semiconductor layer (metal oxide layer) of the transistor. And a conductive layer (conductive metal oxide layer).
  • the conductive metal oxide layer can be formed with high carrier concentration by introducing impurities or the like into the metal oxide layer, similarly to the source region and the drain region of the transistor. Note that the conductive metal oxide layer which serves as one electrode of the capacitor is likely to have variations in resistance value and its resistance is not as low as that of the metal layer; It is preferable that the function of the wiring is assisted by conducting the conductive layer.
  • FIG. 10B shows a structure in which a wiring layer (source wiring and power supply line) is provided on the stack of FIG. 10A.
  • FIG. 10C shows a configuration in which the pixel electrode 111 is provided on the stack of FIG. 10B.
  • the light emitting device can be configured by using the pixel electrode 111 as one electrode and a light emitting layer or the like provided between the pixel electrode 111 and the common electrode facing the pixel electrode 111.
  • FIG. 11A is a block diagram illustrating a conventional source driver
  • FIGS. 11B and 11C are diagrams illustrating a cross section in the channel length direction of a transistor.
  • the source driver has a logic section and an amplifier section.
  • the logic portion 21 is provided with circuits 21_1 to 21_n (n is a natural number of 2 or more).
  • the amplifier 22 is provided with circuits 22_1 to 22_m (m is a natural number of 2 or more). Note that the source driver may be provided with other circuits.
  • circuits 21_1 to 21_n for example, an input interface circuit, a serial / parallel conversion circuit, a shift register circuit, a latch circuit, or the like can be provided.
  • circuits 22_1 to 22_m for example, a level shift circuit, a PTL, an amplifier circuit, or the like can be provided.
  • the logic unit 21 includes a circuit such as a shift register circuit that requires high-speed operation. Therefore, as shown in FIG. 11B, the thickness (t GI ) of the gate insulating film of the transistor 151 included in the logic portion 21 is set to a relatively small film thickness a. Further, as shown by Pelgrom Plot, in a transistor having a relatively thin gate insulating film, there is little variation in operation, so that the channel length (L) of the transistor can be set to a relatively short length c. Therefore, low voltage operation is possible, and the power consumption of the logic section 21 is relatively small.
  • the amplifier unit 22 includes a circuit that outputs a relatively high voltage, such as an amplifier circuit.
  • a relatively high voltage such as an amplifier circuit.
  • the thickness (t GI ) of the gate insulating film of the transistor 152 included in the amplifier unit 22 needs to be set to a relatively large film thickness b (a ⁇ b) to increase the breakdown voltage. is there.
  • Pelgrom Plot since the operation variation is large in a transistor having a relatively thick gate insulating film, the channel length (L) of the transistor is relatively long, and the length d (c ⁇ d) is set. It is necessary to reduce variations.
  • the logic unit 21 and the amplifier unit 22 have different transistor configurations.
  • transistors having different gate insulating film thicknesses are mixed in one chip (or on the same substrate), the number of manufacturing steps is increased, which causes a cost increase.
  • the power supply voltage is different between the logic section and the amplifier section. Therefore, as shown in FIG. 11A, for example, the power supply circuit 25a that outputs a low voltage is connected to the logic unit 21, and the power supply circuit 25b that outputs a high voltage is connected to the amplifier unit 22.
  • the circuit configuration that outputs a plurality of voltages in this manner is one of the factors that increase the cost.
  • the fin type transistor formed on the silicon substrate is illustrated in FIGS. 11B and 11C, it may be a planar type or an SOI type.
  • a transistor which is provided over an insulating substrate and includes single crystal silicon or polycrystalline silicon in a channel formation region may be used.
  • a transistor which is provided over an insulating substrate and includes a metal oxide in a channel formation region may be used. Any transistor has the above-mentioned problems.
  • FIG. 12A is a block diagram illustrating the source driver 20 of one embodiment of the present invention
  • FIGS. 12B and 12C are cross-sectional views of a transistor in a channel length direction.
  • the type of circuit provided in the source driver 20 can have a logic section 21, an amplifier section 22 and other circuits, as in the conventional source driver shown in FIG. 11A.
  • the source driver 20 of one embodiment of the present invention is different from the conventional source driver in that at least the amplifier 22 is connected to the power supply circuit 25a which outputs a low voltage.
  • the power supply circuit 25a may be connected to all circuits included in the source driver 20. Alternatively, all the circuits included in the source driver 20 may be configured to operate at the same low voltage.
  • the transistor used in the amplifier unit 22 can be a transistor having a thin gate insulating film and a short channel length, like the logic unit 21. Therefore, the power consumption of the amplifier unit 22 can be reduced.
  • the same transistor can also be used for a digital-analog conversion circuit and a bias generation circuit included in the source driver 20. Therefore, the power consumption of the source driver 20 as a whole can be made extremely small.
  • the gate insulating film having the same thickness can be used for the transistors included in the logic portion 21 and the amplifier portion 22, manufacturing steps can be significantly reduced and manufacturing cost can be reduced.
  • a plurality of power supply circuits 25a may be connected to the source driver 20.
  • the gate insulating film having the same thickness for the transistor included in the logic section 21 and the transistor included in the amplifier section 22 is a great advantage in the manufacturing process.
  • the same thickness means a thickness obtained as a result of not separately making.
  • the thickness of the gate insulating film is, for example, several nm to several tens nm. Alternatively, it may be 1 nm or less. At such a film thickness level, there is a certain variation even if they are manufactured in the same process due to the influence of the unevenness of the base on which the gate insulating film is provided. They can be confirmed by cross-sectional TEM observation or the like.
  • one of the logic portion and the amplifier portion has a region where the thickness of the gate insulating film of the transistor is a and the thickness of the gate insulating film of the other transistor is 0.8a.
  • the gate insulating film is not separately formed as in one embodiment of the present invention. If a more stable process is used, the gate insulating film of one transistor has a region of a and the gate insulating film of the other transistor has a region of 0.9a or more and 1.1a or less. It can also be manufactured as follows.
  • the above is the description of the source driver 20 of one embodiment of the present invention.
  • the logic section and the amplifier section of the source driver 20 can be operated at 3.3 V or less, for example.
  • the source driver 20 can operate with low power consumption, but its output voltage is small, so that it is difficult to properly operate the display device with normal pixels.
  • a display device with extremely low power consumption can be realized.
  • the larger the display unit the greater the effect of reducing power consumption.
  • the larger the number of pixels the larger the number of times of writing in one frame period, and the larger the size of the display portion, the higher the power consumed for charging / discharging the source line.
  • Embodiment 2 In this embodiment mode, a structural example of a display device using a liquid crystal device and a structural example of a display device using a light emitting device will be described. In the present embodiment, description of the elements, operations and functions of the display device described in Embodiment 1 will be omitted.
  • the pixel described in Embodiment 1 can be used for the display device described in this embodiment.
  • the scanning line driver circuit described below corresponds to a gate driver
  • the signal line driver circuit corresponds to a source driver.
  • the source driver described in Embodiment 1 can be used for the signal line driver circuit.
  • FIGS. 13A to 13C are diagrams illustrating a structure of a display device in which one embodiment of the present invention can be used.
  • a sealant 4005 is provided so as to surround the display portion 215 provided over the first substrate 4001 and the display portion 215 is sealed by the sealant 4005 and the second substrate 4006.
  • the scan line driver circuit 221a, the signal line driver circuit 231a, the signal line driver circuit 232a, and the common line driver circuit 241a each include a plurality of integrated circuits 4042 provided over the printed circuit board 4041.
  • the integrated circuit 4042 is formed using a single crystal semiconductor or a polycrystalline semiconductor.
  • the common line driver circuit 241a has a function of supplying a prescribed potential to the wirings 123, 124, 129, 130, 131, and the like described in Embodiment 1.
  • the integrated circuit 4042 included in the scan line driver circuit 221a and the common line driver circuit 241a has a function of supplying a selection signal to the display portion 215.
  • the integrated circuit 4042 included in the signal line driver circuit 231a and the signal line driver circuit 232a has a function of supplying image data to the display portion 215.
  • the integrated circuit 4042 is mounted on a region of the first substrate 4001 which is different from the region surrounded by the sealant 4005.
  • the method for connecting the integrated circuit 4042 is not particularly limited and a wire bonding method, a COF method, a COG method, a TCP method, or the like can be used.
  • FIG. 13B shows an example in which the integrated circuit 4042 included in the signal line driver circuit 231a and the signal line driver circuit 232a is mounted by a COG method.
  • part or all of the driver circuit can be formed over the same substrate as the display portion 215, so that a system-on-panel can be formed.
  • FIG. 13B shows an example in which the scan line driver circuit 221a and the common line driver circuit 241a are formed over the same substrate as the display portion 215.
  • the sealant 4005 is provided so as to surround the display portion 215 provided over the first substrate 4001, the scan line driver circuit 221a, and the common line driver circuit 241a.
  • a second substrate 4006 is provided over the display portion 215, the scan line driver circuit 221a, and the common line driver circuit 241a. Therefore, the display portion 215, the scan line driver circuit 221a, and the common line driver circuit 241a are sealed together with the display device by the first substrate 4001, the sealant 4005, and the second substrate 4006.
  • FIG. 13B illustrates an example in which the signal line driver circuit 231a and the signal line driver circuit 232a are separately formed and mounted on the first substrate 4001; however, the invention is not limited to this structure.
  • the scan line driver circuit may be separately formed and then mounted, or part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted.
  • the signal line driver circuit 231a and the signal line driver circuit 232a may be formed over the same substrate as the display portion 215.
  • the display device may include a panel in which a display device is sealed and a module in which an IC including a controller is mounted on the panel.
  • the display portion and the scan line driver circuit which are provided over the first substrate include a plurality of transistors.
  • the transistor the Si transistor or the OS transistor described in Embodiment 1 can be applied.
  • the structure of the transistor included in the peripheral driver circuit and the structure of the transistor included in the pixel circuit of the display portion may be the same or different.
  • the transistors included in the peripheral driver circuit may all have the same structure, or may have two or more types of structures.
  • the transistors included in the pixel circuit may all have the same structure, or may have two or more types of structures.
  • the input device 4200 can be provided over the second substrate 4006.
  • the structure in which the input device 4200 is provided in the display device illustrated in FIGS. 13A to 13C can function as a touch panel.
  • a detection device also referred to as a sensor element
  • Various sensors that can detect the proximity or contact of a detection target such as a finger or a stylus can be applied as the detection device.
  • a sensor system various systems such as a capacitance system, a resistance film system, a surface acoustic wave system, an infrared system, an optical system, and a pressure sensitive system can be used.
  • a touch panel having a capacitance type detection device will be described as an example.
  • the electrostatic capacity method there are a surface type electrostatic capacity method, a projection type electrostatic capacity method and the like. Further, as the projection type electrostatic capacity method, there are a self capacity method, a mutual capacity method and the like. The use of the mutual capacitance method is preferable because simultaneous multipoint detection is possible.
  • the touch panel of one embodiment of the present invention has a structure in which a display device and a detection device which are separately manufactured are attached to each other, a structure in which an electrode or the like included in the detection device is provided on one or both of a substrate supporting the display device and a counter substrate, or the like. , Various configurations can be applied.
  • FIG. 14A and 14B show an example of a touch panel.
  • FIG. 14A is a perspective view of touch panel 4210.
  • FIG. 14B is a schematic perspective view of the input device 4200. Note that only representative components are shown for clarity.
  • the touch panel 4210 has a configuration in which a display device and a detection device that are separately manufactured are attached to each other.
  • the touch panel 4210 includes an input device 4200 and a display device, which are provided in an overlapping manner.
  • the input device 4200 includes a substrate 4263, an electrode 4227, an electrode 4228, a wiring 4237, a wiring 4238, and a wiring 4239.
  • the electrode 4227 can be electrically connected to the wiring 4237 or the wiring 4239.
  • the electrode 4228 can be electrically connected to the wiring 4238.
  • the FPC 4272b is electrically connected to each of the wiring 4237, the wiring 4238, and the wiring 4239.
  • An IC 4273b can be provided in the FPC 4272b.
  • a touch sensor may be provided between the first substrate 4001 and the second substrate 4006 of the display device.
  • a touch sensor is provided between the first substrate 4001 and the second substrate 4006, an optical touch sensor using a photoelectric conversion element may be used as well as a capacitance touch sensor.
  • FIG. 15A and FIG. 15B are cross-sectional views of a portion indicated by a chain line N1-N2 in FIG. 13B.
  • the display device illustrated in FIGS. 15A and 15B includes an electrode 4015, and the electrode 4015 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive layer 4019.
  • the electrode 4015 is electrically connected to the wiring 4014 in the openings formed in the insulating layer 4112, the insulating layer 4111, and the insulating layer 4110.
  • the electrode 4015 is formed using the same conductive layer as the first electrode layer 4030, and the wiring 4014 is formed using the same conductive layer as the source and drain electrodes of the transistor 4010 and the transistor 4011.
  • the display portion 215 and the scan line driver circuit 221a provided over the first substrate 4001 each include a plurality of transistors.
  • the transistor 4010 included in the display portion 215 and the scan line are included.
  • the transistor 4011 included in the driver circuit 221a is illustrated. Note that although bottom-gate transistors are illustrated as the transistors 4010 and 4011 in FIGS. 15A and 15B, top-gate transistors may be used.
  • the insulating layer 4112 is provided over the transistor 4010 and the transistor 4011. Further, in FIG. 15B, a partition 4510 is formed over the insulating layer 4112.
  • the transistors 4010 and 4011 are provided over the insulating layer 4102.
  • the transistor 4010 and the transistor 4011 each include an electrode 4017 formed over the insulating layer 4111.
  • the electrode 4017 can function as a back gate electrode.
  • the display device illustrated in FIGS. 15A and 15B includes a capacitor 4020.
  • the capacitor 4020 shows an example including an electrode 4021 formed in the same step as a gate electrode of the transistor 4010, an insulating layer 4103, and an electrode formed in the same step as a source electrode and a drain electrode.
  • the structure of the capacitor 4020 is not limited to this, and the capacitor 4020 may be formed using another conductive layer and an insulating layer.
  • the capacitance value of a capacitor provided in a pixel portion of a display device is set in consideration of leakage current of a transistor provided in the pixel portion and the like so that charge can be held for a predetermined period.
  • the capacitance value of the capacitor may be set in consideration of off-state current of a transistor electrically connected to the capacitor and the like.
  • FIG. 15A is an example of a liquid crystal display device using a liquid crystal device as a display device.
  • a liquid crystal device 4013 which is a display device includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008.
  • an insulating layer 4032 and an insulating layer 4033 which function as alignment films are provided so as to sandwich the liquid crystal layer 4008.
  • the second electrode layer 4031 is provided on the second substrate 4006 side, and the first electrode layer 4030 and the second electrode layer 4031 overlap with each other with the liquid crystal layer 4008 interposed therebetween.
  • liquid crystal devices to which various modes are applied can be used.
  • a VA Very Alignment
  • a TN Transmission Nematic
  • an IPS In-Plane-Switching
  • ASM Analy Symmetrical Integrated Micro-cells
  • OCB Optical Aligned Micro-cell
  • AFLC Anti-ferroelectric Liquid Crystal
  • ECB Electrode Controlled Birefringence
  • VA-IPS mode guest-host mode, etc.
  • a normally black liquid crystal display device for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode may be applied to the liquid crystal display device described in this embodiment.
  • VA vertical alignment
  • MVA Multi-Domain Vertical Alignment
  • PVA Plasma Vertical Alignment
  • ASV Advanced Super View
  • the liquid crystal device is an element that controls transmission or non-transmission of light by an optical modulation action of liquid crystal.
  • the optical modulation action of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, and an oblique electric field).
  • thermotropic liquid crystal low molecular liquid crystal
  • polymer liquid crystal polymer dispersed liquid crystal
  • PDLC Polymer Dispersed Liquid Crystal
  • ferroelectric liquid crystal antiferroelectric liquid crystal, etc.
  • These liquid crystal materials show a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on the conditions.
  • FIG. 15A illustrates an example of a liquid crystal display device including a vertical electric field liquid crystal device
  • a liquid crystal display device including a horizontal electric field liquid crystal device can be applied to one embodiment of the present invention.
  • liquid crystal exhibiting a blue phase for which an alignment film is not used may be used.
  • the blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the temperature of the cholesteric liquid crystal is increased. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which 5 wt% or more of a chiral agent is mixed is used for the liquid crystal layer 4008 in order to improve the temperature range.
  • a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and shows optical isotropy.
  • a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent does not require alignment treatment and has small viewing angle dependence. Further, since it is not necessary to provide an alignment film, rubbing treatment is unnecessary, and thus electrostatic breakdown caused by the rubbing treatment can be prevented and defects or damage of the liquid crystal display device during a manufacturing process can be reduced. ..
  • the spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer, and is provided to control the distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. ing. A spherical spacer may be used.
  • an optical member such as a black matrix (light-shielding layer), a coloring layer (color filter), a polarizing member, a retardation member, and an antireflection member may be appropriately provided.
  • an optical member such as a black matrix (light-shielding layer), a coloring layer (color filter), a polarizing member, a retardation member, and an antireflection member
  • circularly polarized light using a polarizing substrate and a retardation substrate may be used.
  • a backlight, a sidelight or the like may be used as the light source.
  • a micro LED or the like may be used as the backlight and the side light.
  • a light-blocking layer 4132, a coloring layer 4131, and an insulating layer 4133 are provided between the second substrate 4006 and the second electrode layer 4031.
  • the light-shielding layer may be a film containing a resin material or a thin film of an inorganic material such as metal.
  • a stacked film of films including a material used for the coloring layer can be used for the light-blocking layer.
  • a stacked structure of a film containing a material used for a colored layer which transmits light of a certain color and a film containing a material used for a colored layer which transmits light of another color can be used. It is preferable to use the same material for the colored layer and the light-shielding layer because the device can be used in common and the process can be simplified.
  • Examples of the material that can be used for the colored layer include a metal material, a resin material, and a resin material containing a pigment or a dye.
  • the light-shielding layer and the colored layer can be formed using, for example, an inkjet method.
  • the display device illustrated in FIGS. 15A and 15B includes an insulating layer 4111 and an insulating layer 4104.
  • an insulating layer 4111 and the insulating layer 4104 an insulating layer which does not easily transmit an impurity element is used. By sandwiching the semiconductor layer of the transistor with the insulating layer 4111 and the insulating layer 4104, entry of impurities from the outside can be prevented.
  • a light emitting device can be used as a display device included in the display device.
  • an EL device utilizing electroluminescence can be applied.
  • the EL device has a layer containing a light-emitting compound (also referred to as an “EL layer”) between a pair of electrodes.
  • a potential difference larger than the threshold voltage of the EL device is generated between the pair of electrodes, holes are injected into the EL layer from the anode side and electrons are injected from the cathode side. The injected electrons and holes are recombined in the EL layer, and the light emitting compound contained in the EL layer emits light.
  • an organic EL device for example, an organic EL device or an inorganic EL device can be used.
  • an LED including a micro LED
  • a compound semiconductor as a light emitting material
  • the organic EL device In the organic EL device, electrons are injected from one electrode and holes are injected into the EL layer from the other electrode by applying a voltage. When the carriers (electrons and holes) are recombined, the light-emitting organic compound forms an excited state, and when the excited state returns to the ground state, the organic compound emits light. Due to such a mechanism, such a light emitting device is called a current excitation type light emitting device.
  • the EL layer includes a substance having a high hole-injecting property, a substance having a high hole-transporting property, a hole-blocking material, a substance having a high electron-transporting property, a substance having a high electron-injecting property, or a bipolar substance in addition to the light-emitting compound.
  • Substance a substance having a high electron-transporting property and a high hole-transporting property
  • the like may be included.
  • the EL layer can be formed by an evaporation method (including a vacuum evaporation method), a transfer method, a printing method, an inkjet method, a coating method, or the like.
  • the inorganic EL device is classified into a dispersion type inorganic EL device and a thin film type inorganic EL device depending on the element configuration.
  • the dispersion-type inorganic EL device has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light emission mechanism is donor-acceptor recombination light emission that utilizes a donor level and an acceptor level.
  • the thin-film type inorganic EL device has a structure in which a light emitting layer is sandwiched by dielectric layers and further sandwiched by electrodes, and the light emission mechanism is localized type light emission utilizing the core electron transition of metal ions. Note that, here, an organic EL device will be described as a light emitting device.
  • the light emitting device at least one of the pair of electrodes needs to be transparent in order to extract light emission. Then, a transistor and a light emitting device are formed over a substrate, and a top emission (top emission) structure in which light is emitted from a surface opposite to the substrate, or a bottom emission (bottom emission) structure in which light is emitted from a surface on the substrate side, There is a light emitting device with a dual emission (dual emission) structure that takes out light emission from both sides, and any light emitting device with an emission structure can be applied.
  • FIG. 15B is an example of a light-emitting display device (also referred to as an “EL display device”) using a light-emitting device as a display device.
  • the light emitting device 4513 which is a display device is electrically connected to the transistor 4010 provided in the display portion 215. Note that the light-emitting device 4513 has a stacked-layer structure of the first electrode layer 4030, the light-emitting layer 4511, and the second electrode layer 4031, but is not limited to this structure.
  • the structure of the light emitting device 4513 can be changed as appropriate in accordance with the direction of light extracted from the light emitting device 4513, or the like.
  • the partition 4510 is formed using an organic insulating material or an inorganic insulating material.
  • a photosensitive resin material be used and an opening be formed over the first electrode layer 4030 so that a side surface of the opening is an inclined surface having a continuous curvature.
  • the light emitting layer 4511 may be formed of a single layer or a plurality of layers stacked.
  • the emission color of the light emitting device 4513 can be white, red, green, blue, cyan, magenta, yellow, or the like depending on the material forming the light emitting layer 4511.
  • a method of realizing color display there are a method of combining a light emitting device 4513 having a white emission color and a coloring layer, and a method of providing a light emitting device 4513 having a different emission color for each pixel.
  • the former method is more productive than the latter method.
  • the latter method it is possible to obtain a luminescent color having a higher color purity than in the former method.
  • the color purity can be further increased by providing the light emitting device 4513 with a microcavity structure.
  • the light emitting layer 4511 may include an inorganic compound such as a quantum dot.
  • quantum dots in the light emitting layer, they can function as a light emitting material.
  • a protective layer may be formed over the second electrode layer 4031 and the partition 4510 so that oxygen, hydrogen, moisture, carbon dioxide, and the like do not enter the light-emitting device 4513.
  • the protective layer silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, DLC (Diamond Like Carbon), or the like can be formed.
  • a filler 4514 is provided and sealed in the space sealed by the first substrate 4001, the second substrate 4006, and the sealant 4005. In this way, it is preferable to package (enclose) a protective film (bonding film, UV-curable resin film, etc.) or a cover material that has high airtightness and little degassing so as not to be exposed to the outside air.
  • an ultraviolet curable resin or a thermosetting resin can be used in addition to an inert gas such as nitrogen or argon.
  • PVC polyvinyl chloride
  • acrylic resin polyimide
  • epoxy resin epoxy resin
  • silicone resin silicone resin
  • PVB polyvinyl butyral
  • EVA ethylene vinyl acetate
  • the filler 4514 may include a desiccant.
  • sealant 4005 a glass material such as a glass frit, a curable resin that cures at room temperature such as a two-liquid mixed resin, a photocurable resin, or a thermosetting resin can be used. Further, the sealant 4005 may contain a desiccant.
  • a polarizing plate or an optical film such as a circular polarizing plate (including an elliptical polarizing plate), a retardation plate ( ⁇ / 4 plate, ⁇ / 2 plate), a color filter, etc. is provided on the emission surface of the light emitting device. You may provide suitably. Further, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, it is possible to perform anti-glare treatment that diffuses reflected light due to unevenness on the surface and can reduce glare.
  • the light emitting device into a microcavity structure
  • light with high color purity can be extracted.
  • the microcavity structure and the color filter glare can be reduced and the visibility of the displayed image can be improved.
  • first electrode layer and the second electrode layer also referred to as a pixel electrode layer, a common electrode layer, a counter electrode layer, or the like
  • Translucency and reflectivity may be selected depending on the pattern structure of the electrode layer.
  • the first electrode layer 4030 and the second electrode layer 4031 are formed of indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, and indium containing titanium oxide.
  • a light-transmitting conductive material such as tin oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can be used.
  • the first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta). , Chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), and the like, or alloys thereof. It can be formed using one or more kinds of metal nitrides.
  • the first electrode layer 4030 and the second electrode layer 4031 can be formed using a conductive composition containing a conductive high molecule (also referred to as a conductive polymer).
  • a conductive high molecule also referred to as a conductive polymer.
  • a so-called ⁇ -electron conjugated conductive high molecule can be used. Examples thereof include polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer or a derivative thereof including two or more kinds of aniline, pyrrole and thiophene.
  • the protection circuit is preferably constructed by using a non-linear element.
  • a stack structure may be employed in which transistors and capacitors have regions overlapping in the height direction.
  • transistors and capacitors have regions overlapping in the height direction.
  • the transistor 4011 and the transistor 4022 included in the driver circuit so as to overlap with each other, a display device with a narrow frame can be obtained.
  • the aperture ratio and the resolution can be improved by arranging the transistor 4010, the transistor 4023, the capacitor 4020, and the like included in the pixel circuit so that there is a region where they partially overlap with each other.
  • FIG. 16 shows an example in which the stack structure is applied to the liquid crystal display device shown in FIG. 15A, it may be applied to the EL display device shown in FIG. 15B.
  • the transmittance of light in a pixel can be increased and the aperture ratio can be substantially improved. it can.
  • the semiconductor layer also has a light-transmitting property, so that the aperture ratio can be further increased.
  • the display device may be configured by combining the liquid crystal display device and the light emitting device.
  • the light emitting device is arranged on the opposite side of the display surface or at the end of the display surface.
  • the light emitting device has a function of supplying light to the display device.
  • the light emitting device can also be called a backlight.
  • the light emitting device can include a plate-shaped or sheet-shaped light guide unit (also referred to as a light guide plate) and a plurality of light emitting devices that emit light of different colors.
  • a plate-shaped or sheet-shaped light guide unit also referred to as a light guide plate
  • the light guide portion has a mechanism for changing the optical path (also referred to as a light extraction mechanism), which allows the light emitting device to uniformly illuminate the pixel portion of the display panel with light.
  • the light-emitting device may be provided directly below the pixel without providing the light guide portion.
  • the light emitting device preferably has three color light emitting devices of red (R), green (G) and blue (B). Further, a white (W) light emitting device may be included. It is preferable to use a light emitting diode (LED: Light Emitting Diode) as these light emitting devices.
  • RGB red
  • G green
  • B blue
  • W white
  • LED Light Emitting Diode
  • the light emitting device has a full width at half maximum (FWHM: Full Width at Half Maximum) of 50 nm or less, preferably 40 nm or less, more preferably 30 nm or less, further preferably 20 nm or less, and extremely high color purity. It is preferably a light emitting device.
  • the full width at half maximum of the emission spectrum is preferably as small as possible, but can be set to 1 nm or more, for example. This makes it possible to perform vivid display with high color reproducibility when performing color display.
  • the red light emitting device it is preferable to use an element having a peak wavelength of the emission spectrum in the range of 625 nm to 650 nm.
  • the green light emitting device it is preferable to use an element having a peak wavelength of the emission spectrum in the range of 515 nm to 540 nm.
  • the blue light emitting device it is preferable to use an element having a peak wavelength of the emission spectrum in the range of 445 nm or more and 470 nm or less.
  • the display device can sequentially turn on and off the light emitting devices of three colors, drive the pixels in synchronization with the light emitting devices, and perform color display based on the successive additive color mixing method.
  • the driving method can also be called field sequential driving.
  • Field-sequential driving can display vivid color images. Moreover, a smooth moving image can be displayed. Further, by using the above driving method, one pixel does not need to be formed with a plurality of sub-pixels of different colors, and an effective reflection area (also referred to as an effective display area or aperture ratio) of one pixel can be increased, which is bright. The display can be done. Further, since it is not necessary to provide a color filter for each pixel, it is possible to improve the transmissivity of each pixel, and it is possible to perform brighter display. In addition, the manufacturing process can be simplified and the manufacturing cost can be reduced.
  • 17A and 17B are examples of schematic cross-sectional views of a display device capable of field sequential driving.
  • a backlight unit capable of emitting light of each color of RGB is provided on the first substrate 4001 side of the display device.
  • the color is represented by time-divisional light emission of each color of RGB, so that the color filter is not necessary.
  • a backlight unit 4340a illustrated in FIG. 17A has a structure in which a plurality of light emitting devices 4342 are provided immediately below a pixel with a diffusion plate 4352 provided therebetween.
  • the diffusion plate 4352 has a function of diffusing light emitted from the light emitting device 4342 to the first substrate 4001 side and uniformizing the luminance within the surface of the display portion.
  • a polarizing plate may be provided between the light emitting device 4342 and the diffusion plate 4352, if necessary. Further, the diffusion plate 4352 may be omitted if it is unnecessary. Further, the light shielding layer 4132 may be omitted.
  • the backlight unit 4340a can mount a large number of light-emitting devices 4342, which enables bright display. Further, there is an advantage that the light guide plate is unnecessary and the light efficiency of the light emitting device 4342 is not easily impaired. Note that the light-emitting device 4342 may be provided with a lens 4344 for light diffusion as needed.
  • a backlight unit 4340b illustrated in FIG. 17B has a structure in which a light guide plate 4341 is provided directly below a pixel with a diffusion plate 4352 provided therebetween.
  • a plurality of light emitting devices 4342 are provided at the end of the light guide plate 4341.
  • the light guide plate 4341 has a concavo-convex shape on the side opposite to the diffusion plate 4352, and the guided light can be scattered by the concavo-convex shape and emitted toward the diffusion plate 4352.
  • the light emitting device 4342 can be fixed to the printed circuit board 4347. Note that, in FIG. 17B, the light emitting devices 4342 of each color of RGB are illustrated as overlapping, but the light emitting devices 4342 of each color of RGB can be arranged in the depth direction. Further, in the light guide plate 4341, a reflective layer 4348 that reflects visible light may be provided on the side surface on the opposite side of the light emitting device 4342.
  • the backlight unit 4340b can reduce the number of light emitting devices 4342, the backlight unit 4340b can be low cost and thin.
  • a light scattering type liquid crystal device may be used as the liquid crystal device.
  • the light scattering type liquid crystal device it is preferable to use an element having a composite material of liquid crystal and polymer.
  • a polymer dispersed liquid crystal device can be used.
  • a polymer network type liquid crystal (PNLC (Polymer Network Liquid Crystal)) element may be used.
  • the light-scattering liquid crystal device has a structure in which a liquid crystal part is provided in a three-dimensional network structure of a resin part sandwiched by a pair of electrodes.
  • a material used for the liquid crystal portion for example, nematic liquid crystal can be used.
  • a photo-curable resin can be used as the resin portion.
  • the photocurable resin for example, a monofunctional monomer such as acrylate or methacrylate, a polyfunctional monomer such as diacrylate, triacrylate, dimethacrylate, or trimethacrylate, or a polymerizable compound in which these are mixed can be used.
  • the light-scattering liquid crystal device utilizes the anisotropy of the refractive index of the liquid crystal material, and transmits or scatters light to perform display. Further, the resin portion may also have anisotropy in refractive index.
  • the liquid crystal molecules are aligned in a certain direction according to the voltage applied to the light-scattering liquid crystal device, there occurs a direction in which the difference in the refractive index between the liquid crystal part and the resin part becomes smaller, and the light incident along that direction is the liquid crystal part. Transmits without being scattered by. Therefore, the light-scattering liquid crystal device is visually recognized in a transparent state from the direction.
  • the difference in the refractive index between the liquid crystal portion and the resin portion does not significantly change, so the incident light is scattered by the liquid crystal portion. Therefore, the light-scattering liquid crystal device is in an opaque state regardless of the viewing direction.
  • FIG. 18A shows a configuration in which the liquid crystal device 4013 of the display device of FIG. 17A is replaced with a light scattering type liquid crystal device 4016.
  • the light-scattering liquid crystal device 4016 includes a composite layer 4009 including a liquid crystal portion and a resin portion, a first electrode layer 4030, and a second electrode layer 4031. Elements relating to field sequential driving are the same as those in FIG. 17A, but when the light scattering type liquid crystal device 4016 is used, the alignment film and the polarizing plate are not necessary.
  • the spacer 4035 is illustrated as having a spherical shape, it may have a columnar shape.
  • FIG. 18B shows a configuration in which the liquid crystal device 4013 of the display device of FIG. 17B is replaced with a light scattering type liquid crystal device 4016.
  • the light scattering liquid crystal device 4016 operates in a mode in which light is transmitted when a voltage is not applied and the light is scattered when a voltage is applied.
  • a transparent display device can be obtained in a normal state (a state where no display is performed). In this case, color display can be performed when the operation of scattering light is performed.
  • FIGS. 19A to 19E Modifications of the display device shown in FIG. 18B are shown in FIGS. 19A to 19E. Note that in FIGS. 19A to 19E, for clarity, some elements of FIG. 18B are used and other elements are omitted.
  • the first substrate 4001 has a function as a light guide plate.
  • An uneven surface may be provided on the outer surface of the first substrate 4001. With this configuration, since it is not necessary to separately provide the light guide plate, the manufacturing cost can be reduced. Further, the light emitted by the light emitting device 4342 can be efficiently used because the light attenuation by the light guide plate is also eliminated.
  • FIG. 19B shows a structure in which light is incident from the vicinity of the end of the composite layer 4009.
  • Light can be emitted from the light-scattering liquid crystal device to the outside by utilizing the total reflection at the interface between the composite layer 4009 and the second substrate 4006 and the interface between the composite layer 4009 and the first substrate 4001.
  • a material whose refractive index is higher than that of the first substrate 4001 and the second substrate 4006 is used.
  • the light-emitting device 4342 may be provided not only on one side of the display device but also on two opposite sides as shown in FIG. 19C. Further, it may be provided on three sides or four sides. By providing the light-emitting device 4342 on a plurality of sides, light attenuation can be compensated and a large-area display device can be used.
  • FIG. 19D shows a structure in which light emitted from the light emitting device 4342 is guided to the display device through the mirror 4345.
  • FIG. 19E is a configuration having a stack of layers 4003 and 4004 on a composite layer 4009.
  • One of the layers 4003 and 4004 is a support such as a glass substrate, and the other can be formed with an inorganic film, an organic resin coating film, a film, or the like.
  • a material having a higher refractive index than that of the layer 4004 is used for the resin portion of the composite layer 4009.
  • a material having a higher refractive index than the layer 4003 is used for the layer 4004.
  • a first interface is formed between the composite layer 4009 and the layer 4004, and a second interface is formed between the layer 4004 and the layer 4003.
  • FIGS. 18B and 19A to 19E can be combined with each other.
  • the display device of one embodiment of the present invention can be manufactured using various types of transistors such as a bottom-gate transistor and a top-gate transistor. Therefore, the material of the semiconductor layer and the transistor structure to be used can be easily replaced according to the existing manufacturing line.
  • FIG. 20A1 is a cross-sectional view in the channel length direction of a channel protection type transistor 810 which is a kind of bottom gate type transistor.
  • the transistor 810 is formed over the substrate 771.
  • the transistor 810 includes the electrode 746 over the substrate 771 with the insulating layer 772 provided therebetween.
  • the semiconductor layer 742 is provided over the electrode 746 with the insulating layer 726 provided therebetween.
  • the electrode 746 can function as a gate electrode.
  • the insulating layer 726 can function as a gate insulating layer.
  • the insulating layer 741 is provided over the channel formation region of the semiconductor layer 742.
  • the electrode 744a and the electrode 744b are provided over the insulating layer 726 in contact with part of the semiconductor layer 742.
  • the electrode 744a can function as one of a source electrode and a drain electrode.
  • the electrode 744b can function as the other of the source electrode and the drain electrode. Part of the electrode 744a and part of the electrode 744b are formed over the insulating layer 741.
  • the insulating layer 741 can function as a channel protective layer. Providing the insulating layer 741 over the channel formation region can prevent the semiconductor layer 742 from being exposed when the electrodes 744a and 744b are formed. Therefore, the channel formation region of the semiconductor layer 742 can be prevented from being etched when the electrodes 744a and 744b are formed. According to one embodiment of the present invention, a transistor having favorable electric characteristics can be realized.
  • the transistor 810 includes the insulating layer 728 over the electrode 744a, the electrode 744b, and the insulating layer 741 and the insulating layer 729 over the insulating layer 728.
  • an oxide semiconductor is used for the semiconductor layer 742
  • a material capable of depriving oxygen from part of the semiconductor layer 742 and causing oxygen vacancies is used for at least portions of the electrodes 744a and 744b which are in contact with the semiconductor layer 742.
  • the carrier concentration in the region where oxygen deficiency occurs in the semiconductor layer 742 is increased, and the region becomes n-type and becomes an n-type region (n + region). Therefore, the region can function as a source region or a drain region.
  • tungsten, titanium, or the like can be given as an example of a material that can absorb oxygen from the semiconductor layer 742 and cause oxygen vacancies.
  • a layer functioning as an n-type semiconductor or a p-type semiconductor is preferably provided between the semiconductor layer 742 and the electrode 744a and between the semiconductor layer 742 and the electrode 744b.
  • the layer functioning as an n-type semiconductor or a p-type semiconductor can function as a source region or a drain region of a transistor.
  • the insulating layer 729 is preferably formed using a material having a function of preventing or reducing diffusion of impurities from the outside into the transistor. Note that the insulating layer 729 can be omitted if necessary.
  • the transistor 811 illustrated in FIG. 20A2 includes an electrode 723 which can function as a back gate electrode over the insulating layer 729.
  • the electrode 723 can be formed using a material and a method similar to those of the electrode 746.
  • the back gate electrode is formed of a conductive layer, and is arranged so that the channel formation region of the semiconductor layer is sandwiched between the gate electrode and the back gate electrode. Therefore, the back gate electrode can function similarly to the gate electrode.
  • the potential of the back gate electrode may be the same as that of the gate electrode, ground potential (GND potential), or any potential. Further, the threshold voltage of the transistor can be changed by changing the potential of the back gate electrode independently without interlocking with the gate electrode.
  • Both the electrode 746 and the electrode 723 can function as gate electrodes. Therefore, each of the insulating layer 726, the insulating layer 728, and the insulating layer 729 can function as a gate insulating layer. Note that the electrode 723 may be provided between the insulating layers 728 and 729.
  • the other is referred to as a “back gate electrode”.
  • the electrode 746 when the electrode 723 is referred to as a “gate electrode”, the electrode 746 is referred to as a “back gate electrode”.
  • the transistor 811 can be considered as a kind of top-gate transistor.
  • one of the electrode 746 and the electrode 723 may be referred to as a "first gate electrode”, and the other may be referred to as a "second gate electrode”.
  • the electrode 746 and the electrode 723 With the electrode 746 and the electrode 723 with the semiconductor layer 742 provided therebetween, and further by making the electrode 746 and the electrode 723 have the same potential, a region where carriers flow in the semiconductor layer 742 becomes larger in the film thickness direction. The amount of carrier movement increases. As a result, the on-state current of the transistor 811 is increased and the field effect mobility is increased.
  • the transistor 811 is a transistor having a large on-state current with respect to the occupied area. That is, the area occupied by the transistor 811 can be reduced with respect to the required on-state current. According to one embodiment of the present invention, the area occupied by the transistor can be reduced. Therefore, according to one embodiment of the present invention, a highly integrated semiconductor device can be realized.
  • the gate electrode and the back gate electrode are formed of conductive layers, they have a function of preventing an electric field generated outside the transistor from acting on the semiconductor layer in which a channel is formed (especially an electric field shielding function against static electricity). .
  • the back gate electrode By forming the back gate electrode larger than the semiconductor layer and covering the semiconductor layer with the back gate electrode, the electric field shielding function can be improved.
  • the back gate electrode by forming the back gate electrode with a conductive film having a light-blocking property, light can be prevented from entering the semiconductor layer from the back gate electrode side. Therefore, light deterioration of the semiconductor layer can be prevented, and deterioration of electric characteristics such as a shift of the threshold voltage of the transistor can be prevented.
  • a highly reliable transistor can be realized.
  • a semiconductor device with good reliability can be realized.
  • 20B1 is a cross-sectional view in the channel length direction of a channel protection transistor 820 having a structure different from that of FIG. 20A1.
  • the transistor 820 has substantially the same structure as the transistor 810, except that the insulating layer 741 covers an end portion of the semiconductor layer 742.
  • the semiconductor layer 742 and the electrode 744a are electrically connected to each other in the opening formed by selectively removing part of the insulating layer 741 which overlaps with the semiconductor layer 742.
  • the semiconductor layer 742 and the electrode 744b are electrically connected to each other in another opening formed by selectively removing part of the insulating layer 741 which overlaps with the semiconductor layer 742.
  • a region of the insulating layer 741 which overlaps with the channel formation region can function as a channel protective layer.
  • the transistor 821 illustrated in FIG. 20B2 is different from the transistor 820 in that an electrode 723 which can function as a back gate electrode is provided over the insulating layer 729.
  • Providing the insulating layer 741 can prevent the semiconductor layer 742 from being exposed when the electrodes 744a and 744b are formed. Therefore, thinning of the semiconductor layer 742 can be prevented when the electrodes 744a and 744b are formed.
  • the distances between the electrodes 744a and 746 and the distances between the electrodes 744b and 746 are longer than those of the transistors 810 and 811. Therefore, the parasitic capacitance generated between the electrode 744a and the electrode 746 can be reduced. Further, the parasitic capacitance generated between the electrode 744b and the electrode 746 can be reduced. According to one embodiment of the present invention, a transistor having favorable electric characteristics can be realized.
  • FIG. 20C1 is a cross-sectional view in the channel length direction of a channel etching type transistor 825 which is one of bottom gate type transistors.
  • the electrode 744a and the electrode 744b are formed without using the insulating layer 741. Therefore, part of the semiconductor layer 742 that is exposed when the electrodes 744a and 744b are formed may be etched. On the other hand, since the insulating layer 741 is not provided, the productivity of the transistor can be improved.
  • the transistor 826 illustrated in FIG. 20C2 is different from the transistor 825 in that the electrode 823 which can function as a back gate electrode is provided over the insulating layer 729.
  • 21A1 to 21C2 are cross-sectional views in the channel width direction of the transistors 810, 811, 820, 821, 825, and 826, respectively.
  • the gate electrode and the back gate electrode are connected, and the gate electrode and the back gate electrode have the same potential.
  • the semiconductor layer 742 is sandwiched between the gate electrode and the back gate electrode.
  • each of the gate electrode and the back gate electrode in the channel width direction is longer than the length of the semiconductor layer 742 in the channel width direction, and the entire semiconductor layer 742 in the channel width direction includes the insulating layers 726, 741, 728, and 729. It is a structure covered with a gate electrode and a back gate electrode sandwiched therebetween.
  • the semiconductor layer 742 included in the transistor can be electrically surrounded by the electric fields of the gate electrode and the back gate electrode.
  • a device structure of a transistor, such as the transistor 821 and the transistor 826, which electrically surrounds the semiconductor layer 742 in which a channel formation region is formed by an electric field of a gate electrode and a back gate electrode is referred to as a Surrounded channel (S-channel) structure.
  • the S-channel structure With the S-channel structure, an electric field for inducing a channel by one or both of the gate electrode and the back gate electrode can be effectively applied to the semiconductor layer 742, so that the current driving capability of the transistor is improved. It becomes possible to obtain high on-current characteristics. Further, since the on-state current can be increased, the transistor can be miniaturized. In addition, the S-channel structure can increase the mechanical strength of the transistor.
  • the transistor 842 illustrated in FIG. 22A1 is one of top-gate transistors.
  • the electrodes 744a and 744b are electrically connected to the semiconductor layer 742 in the openings formed in the insulating layers 728 and 729.
  • the impurity region can be formed in alignment.
  • the transistor 842 has a region in which the insulating layer 726 extends beyond the end portion of the electrode 746.
  • the impurity concentration of a region of the semiconductor layer 742 in which impurities are introduced through the insulating layer 726 is lower than the impurity concentration of a region in which impurities are introduced without passing through the insulating layer 726. Therefore, in the semiconductor layer 742, an LDD (Lightly Doped Drain) region is formed in a region overlapping with the insulating layer 726 and not overlapping with the electrode 746.
  • LDD Lightly Doped Drain
  • the transistor 843 illustrated in FIG. 22A2 is different from the transistor 842 in including the electrode 723.
  • the transistor 843 has an electrode 723 formed over the substrate 771.
  • the electrode 723 has a region overlapping with the semiconductor layer 742 with the insulating layer 772 provided therebetween.
  • the electrode 723 can function as a back gate electrode.
  • the insulating layer 726 in a region which does not overlap with the electrode 746 may be entirely removed.
  • the insulating layer 726 may be left as in the case of the transistor 846 illustrated in FIG. 22C1 and the transistor 847 illustrated in FIG. 22C2.
  • the impurity region can be formed in the semiconductor layer 742 in a self-aligning manner by forming the electrode 746 and then introducing impurities into the semiconductor layer 742 by using the electrode 746 as a mask.
  • a transistor having favorable electric characteristics can be realized.
  • a highly integrated semiconductor device can be realized.
  • 23A1 to 23C2 are cross-sectional views in the channel width direction of the transistors 842, 843, 844, 845, 846, and 847, respectively.
  • the transistor 843, the transistor 845, and the transistor 847 have the S-channel structure described above. However, the invention is not limited to this, and the transistor 843, the transistor 845, and the transistor 847 do not have to have an S-channel structure.
  • a display device As an electronic device in which the display device according to one embodiment of the present invention can be used, a display device, a personal computer, an image storage device or an image reproducing device including a recording medium, a mobile phone, a game machine including a mobile phone, a mobile data terminal, or the like.
  • E-book readers video cameras, cameras such as digital still cameras, goggle-type displays (head-mounted displays), navigation systems, sound reproduction devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer multifunction machines , An automatic teller machine (ATM), a vending machine, and the like. Specific examples of these electronic devices are shown in FIGS.
  • 24A shows a digital camera, which has a housing 961, a shutter button 962, a microphone 963, a speaker 967, a display portion 965, operation keys 966, a zoom lever 968, a lens 969, and the like.
  • the display portion 965 By using the display device of one embodiment of the present invention for the display portion 965, various images can be displayed.
  • FIG. 24B shows a portable data terminal, which includes a housing 911, a display portion 912, a speaker 913, operation buttons 914, a camera 919, and the like. Information can be input and output by the touch panel function of the display portion 912. By using the display device of one embodiment of the present invention for the display portion 912, various images can be displayed.
  • FIG. 24C illustrates a mobile phone, which includes a housing 951, a display portion 952, operation buttons 953, an external connection port 954, a speaker 955, a microphone 956, a camera 957, and the like.
  • the mobile phone includes a touch sensor in the display portion 952. All operations such as making a call and entering characters can be performed by touching the display portion 952 with a finger, a stylus, or the like.
  • the housing 951 and the display portion 952 have flexibility and can be folded and used as illustrated. By using the display device of one embodiment of the present invention for the display portion 952, various images can be displayed.
  • FIG. 24D shows a video camera, which includes a first housing 901, a second housing 902, a display portion 903, operation keys 904, a lens 905, a connecting portion 906, a speaker 907, and the like.
  • the operation keys 904 and the lens 905 are provided in the first housing 901, and the display portion 903 is provided in the second housing 902.
  • the display portion 903 is provided in the second housing 902.
  • FIG. 24E illustrates a television, which includes a housing 971, a display portion 973, operation buttons 974, a speaker 975, a communication connection terminal 976, an optical sensor 977, and the like.
  • a touch sensor is provided on the display portion 973, and an input operation can be performed.
  • FIG. 24F shows a digital signage, which has a large display portion 922.
  • a large display unit 922 is attached to the side surface of the pillar 921.
  • the transistor characteristics were normally-off, and the off-current was a value below the measurement lower limit of the measuring instrument.
  • the OS transistor has a current capability similar to that of a general low temperature polycrystal silicon (hereinafter referred to as LTPS) transistor.
  • LTPS general low temperature polycrystal silicon
  • FIG. 26A shows a circuit diagram of a pixel using a light emitting device as a display element.
  • the pixel circuit is provided with a memory circuit including one transistor (M4) and one capacitor (CW), and the pixel circuit as a whole has five transistors (M1 to M5) and two transistors.
  • the configuration has capacitors (CW, CS) and a light emitting device (OLED).
  • a back gate which is electrically connected to the front gate is provided in all the transistors.
  • the element included in the pixel circuit has electrical connection with at least one of a gate line (GL1 to GL3), a source line (SL, SLW), a power supply line (ANODE, CATHODE), and a reference potential line (V0).
  • the pixel circuit has a node A and a node B to which some elements are connected. For details, the description of FIG. 2 can be referred to.
  • the OS transistor can function as a memory circuit with one transistor and one capacitor. Therefore, as compared with the case where the LTPS transistor is applied, the memory circuit can be incorporated in the pixel with a smaller number of elements. Further, the memory circuit can hold an analog value.
  • n shown in the timing chart indicates the number of rows of pixels, and n is a natural number of 1 or more.
  • V data ⁇ Write display data (V data )>
  • the gate line GL1 is set to a low potential
  • the gate line GL2 is set to a high potential
  • the potential (V data ) supplied to the source line SL is written to the node A.
  • the voltage V g of the node B (gate of the transistor M2) is (C w (V w ⁇ V 0 ) + C s (V w ⁇ V 0 ) + C w ⁇ V data ) / (C w + C s ).
  • C w is the capacitance value of the capacitor CW
  • C s is the capacitance value of the capacitor CS.
  • V 0 0 V
  • V g V w + (C w / (C w + C s )) ⁇ V data . Therefore, if V w > (C s / (C w + C s )) ⁇ V data , a voltage larger than the output of the source driver can be applied to the pixel.
  • FIG. 27A shows a circuit diagram of a pixel using a liquid crystal device as a display element.
  • the pixel circuit is provided with a memory circuit including one transistor (M4) and one capacitor (CW) similarly to the EL pixel circuit.
  • the pixel circuit as a whole is configured to have two transistors (M1 and M4), two capacitors (CW and CS), and a liquid crystal device (LC).
  • a back gate which is electrically connected to the front gate is provided in all the transistors.
  • the element included in the pixel circuit has electrical connection to at least one of the gate line (GL1 and GL2), the source line (SL and SLW), and the reference potential line (TCOM and CSCOM).
  • the pixel circuit has a node A and a node B to which some elements are connected.
  • FIG. 6A can be referred to.
  • common reference numerals are used for elements common to the EL pixel circuit.
  • V data ⁇ Write display data (V data )>
  • the gate line GL1 is set to a low potential
  • the gate line GL2 is set to a high potential
  • only M4 is made non-conductive to write the potential (V data ) supplied to the source line SL to the node A.
  • the potential of the node B is (C w (V w ⁇ V r ) + (C s + C lc ) ⁇ (V w ⁇ V r ) + C w ⁇ V data ) / (C w due to the capacitive coupling of the capacitor CW. + C s + C lc ).
  • C lc is the capacitance value of the liquid crystal device LC.
  • the potential of the node B depends on the ratio of C w and (C s + C lc ), but can be set to a potential larger than V data by the formula. That is, a potential larger than V data supplied from the source driver can be applied to the liquid crystal device LC.
  • the output voltage of the source driver can be set to a value smaller than 5 V.
  • the voltage V g depends on the capacitance ratio between the capacitor CW and the capacitor CS, but the output voltage of the source driver may be 3.3 V, for example.
  • the output voltage of the source driver can be set to a value smaller than 5V.
  • the voltage of the node B depends on the capacitance ratio between the capacitor CW and the capacitor CS + the liquid crystal device LC, but the output voltage of the source driver may be 3.3V, for example.
  • the amplifier circuit of the source driver does not need to be configured with the technology having the withstand voltage of 5V, and can be configured with the technology having the withstand voltage of 3.3V. Further, by using the above-mentioned liquid crystal pixel circuit, the amplifier circuit of the source driver does not need to be configured with a technology having a withstand voltage of 10 V or more, and can be configured with a technology having a withstand voltage of 10 V or less.
  • the source driver is configured as shown in the block diagram of FIG. 28, and the simulation for estimating the power consumption of each block is performed assuming 5V technology and 3.3V technology.
  • the assumed panel is a smartphone size panel and the number of pixels is 1080 ⁇ 1920.
  • Smartspice manufactured by Silvaco was used.
  • the operating condition of the panel is assumed to be a case where 30% of the display portion is rewritten. Further, it is assumed that the configuration of the logic part of the source driver is common and the transistor size is changed only in the amplifier circuit.
  • FIG. 29A shows the estimation and comparison result of the power consumption of the source driver applied to the EL pixel circuit.
  • the pixel circuit A is assumed to be a conventional pixel circuit (transistor ⁇ 3 + capacitor ⁇ 1, a configuration without the transistors M1 and M3 and the capacitor CW in FIG. 26A), and consumes a source driver having an amplifier circuit of 5V technology. Shows power.
  • the pixel circuit B is assumed to be the pixel circuit (transistor ⁇ 5 + capacitor ⁇ 2, configuration of FIG. 26A) of one embodiment of the present invention, and shows power consumption of a source driver including an amplifier circuit of 3.3V technology. There is.
  • FIG. 29B shows the estimation and comparison result of the power consumption of the source driver applied to the liquid crystal pixel circuit.
  • Pixel circuit C shows power consumption when assuming a conventional pixel circuit (transistor ⁇ 1 + capacitor ⁇ 1, the configuration without transistor M1 and capacitor CW in FIG. 27A) and a source driver.
  • the pixel circuit D is power consumption assuming a pixel circuit of one embodiment of the present invention and a source driver of appropriate technology.
  • the pixel circuit (transistor ⁇ 3 + capacitor ⁇ 2) shown in FIG. 27B which can be expected to consume less power, was used. From the results shown in FIG. 29B, it was found that power consumption of the source driver can be reduced by using the pixel circuit of one embodiment of the present invention, similarly to the result of the source driver applied to the EL pixel circuit.
  • the pixel circuit shown in FIG. 26A corresponds to the above-described pixel circuit B (transistor ⁇ 5 + capacitor ⁇ 2), but can also operate as the pixel circuit A (transistor ⁇ 3 + capacitor ⁇ 1).
  • the source driver uses 5V technology.
  • FIG. 30 shows a comparison result of power consumption when each image is displayed.
  • the power consumption is a value obtained by adding the power consumption of the light emitting device, the power consumption of the source driver, and the power consumption of the gate driver.
  • the power consumption of the light emitting device is the same in both the A mode and the B mode.
  • the power consumption of the gate driver is higher in the B mode in which one gate line is driven, the power consumption of the gate driver is smaller than that of the source driver by an order of magnitude, so that the influence on the power consumption comparison result is small.
  • the difference in power consumption between the displays is substantially the difference in power consumption of the source driver itself, and it was found that the power consumption can be reduced by operating in the B mode. That is, it was confirmed that the pixel circuit of one embodiment of the present invention can operate with lower power consumption than the conventional pixel circuit.
  • Table 1 shows the specifications of the prototype EL display panel.
  • the gate driver was an OS transistor and was provided over the same substrate as the pixel circuit.
  • a white tandem type organic EL device was used as a light emitting device, and a method of colorizing by a color filter was adopted.
  • FIG. 32A is a display result of a prototype EL display panel.
  • ⁇ Liquid crystal display panel> A liquid crystal display panel having the specifications shown in Table 2 was prototyped.
  • the gate driver was an OS transistor and was provided over the same substrate as the pixel circuit.
  • An IC chip capable of outputting -4V to + 4V was used for the source driver.
  • An FFS mode liquid crystal material was used for trial production under the condition that the saturation voltage was 10 V as shown in FIG. 31A. Since this voltage is higher than the output voltage of the source driver, the conventional pixel circuit cannot saturate the liquid crystal device.
  • FIG. 31B shows the result of comparing the relationship between the voltage applied to the liquid crystal device and the brightness of the panel between the conventional pixel circuit X and the pixel circuit Y of one embodiment of the present invention. It was confirmed that a voltage higher than the output of the source driver could be applied to the liquid crystal device by the boosting function of the pixel circuit Y of one embodiment of the present invention.
  • FIG. 32B is a display result of a prototype liquid crystal display panel. Even if a low-output source driver is used, a sufficient voltage can be applied to the liquid crystal device, so that high-luminance display can be achieved.
  • an organic EL display panel and a liquid crystal display panel each having a memory circuit mounted in a pixel were prototyped. It has been confirmed that by holding the weight in the memory, a voltage higher than the output of the source driver can be generated in the pixel, so that the output voltage of the source driver can be lowered. In addition, it was estimated that the effect can reduce the withstand voltage of the transistor forming the source driver and reduce the power consumption of the source driver.
  • the pixel circuit of one embodiment of the present invention can be formed using only OS transistors. Further, there is no special manufacturing process and the number of masks is not increased. Further, in the manufacturing process of the OS transistor, the number of masks can be reduced as compared with the manufacturing process of the LTPS transistor, and it can be said that applying the OS transistor to the display panel is advantageous also in the manufacturing process.

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JP2020556357A JP7441176B2 (ja) 2018-11-09 2019-10-28 表示装置および電子機器
US18/134,054 US12039952B2 (en) 2018-11-09 2023-04-13 Display apparatus and electronic device
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