WO2020088241A1 - 内容寻址存储器、数据处理方法及网络设备 - Google Patents

内容寻址存储器、数据处理方法及网络设备 Download PDF

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Publication number
WO2020088241A1
WO2020088241A1 PCT/CN2019/111238 CN2019111238W WO2020088241A1 WO 2020088241 A1 WO2020088241 A1 WO 2020088241A1 CN 2019111238 W CN2019111238 W CN 2019111238W WO 2020088241 A1 WO2020088241 A1 WO 2020088241A1
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Prior art keywords
voltage
fefet
gate
bit line
bit
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PCT/CN2019/111238
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English (en)
French (fr)
Inventor
喻径舟
王临春
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华为技术有限公司
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Priority to EP19878916.6A priority Critical patent/EP3813067B1/en
Publication of WO2020088241A1 publication Critical patent/WO2020088241A1/zh
Priority to US17/156,938 priority patent/US11468933B2/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/223—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using MOS with ferroelectric gate insulating film
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2273—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2253—Address circuits or decoders
    • G11C11/2255—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2275—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2297—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G11C15/046—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements using non-volatile storage elements

Definitions

  • This application relates to the field of storage technology, in particular to content addressable memory, data processing methods, and network equipment.
  • CAM Content addressable memory
  • a typical CAM is tri-state content addressable memory (ternary content addressable memory (TCAM). It is mainly used to quickly find the access control list (access control list list, ACL), routing table and other entries.
  • each bit unit is composed of 16 transistors (transistor, T), where 12T is used to store the value and mask, 4T For comparison.
  • Search line search line, SL
  • match line match line, ML
  • Each row in the traditional TCAM array represents an entry.
  • searching for data the ML of each row is first charged to a high potential.
  • the SL of each column inputs a bit of the key, compares the value of the bit with the value in the TCAM entry, and all entries are matched at the same time. If all the bits in a row match successfully, ML remains high. If any bit in this row does not match, the ML of this row leaks to a low level. By determining the high and low potential of ML, the matching result is determined.
  • the traditional TMOS-based TCAM requires 16T per bit unit, the area of the TCAM is large, and the power consumption of the TCAM is large, and the power consumption of the larger-sized TCAM is more serious.
  • the content addressable memory, the data processing method, and the network device provided by the embodiments of the present application can reduce the size of the CAM, thereby reducing the power consumption of the CAM.
  • an embodiment of the present application provides a content addressable memory CAM, including: M rows and N columns of bit cells, where M and N are positive integers greater than or equal to 1; each bit cell includes a first ferroelectric field effect transistor (ferro-electric field effect transistor, FeFET) and second FeFET.
  • FeFET ferroelectric field effect transistor
  • the source of the first FeFET is connected to the drain of the second FeFET, and the source of the second FeFET is grounded.
  • CAM is usually composed of multiple rows and columns of bit units. Among them, the data stored in a row of bit units of CAM can form an entry, or the data stored in a row of bit units of CAM can form an entry.
  • the structure of the lower CAM is different.
  • the data stored in a column of bit units of the CAM constitutes an entry. Then, the bit cells in the same column correspond to the same match line; the drain of the first FeFET in each bit cell in the same column is connected to the match line corresponding to the column; the bit cells in the same row correspond to the same first bit line and the same second Bit line, the gates of the first FeFETs in each bit cell in the same row are connected to the first bit line corresponding to the row, and the gates of the second FeFETs in each bit cell in the same row are connected to the row Corresponding second bit line.
  • Structure 2 The data stored in a row of CAM bit units constitutes an entry. Then, the bit cells in the same row correspond to the same match line; the drain of the first FeFET in each bit cell in the same row is connected to the match line corresponding to the row; the bit cells in the same column correspond to the same first bit line and the same second Bit line, the gate of the first FeFET in each bit cell in the same column is connected to the first bit line corresponding to the column, and the gate of the second FeFET in each bit cell in the same column is connected to the column Corresponding second bit line.
  • a row of bit units in structure one is equivalent to a row of bit units in structure two
  • a row of bit units in structure one is equivalent to a row of bit units in structure two
  • structure one and structure two are substantially the same .
  • the embodiments of the present application describe these two structures. It can be understood that, even if only structure 1 is used as an example for description, those skilled in the art may refer to the related description of structure 1 to obtain the CAM of structure 2 and use the CAM to implement data processing Methods.
  • the same column of bit cells corresponds to the same first back gate line and the same second back gate line;
  • the back gate of the first FeFET in each bit cell of the same column is connected to the first back gate line corresponding to the column;
  • the back gate of the second FeFET in each bit cell of the same column is connected to the corresponding column Second back gate line.
  • the same row of bit units correspond to the same first back gate line and the same second back gate line; each bit unit in the same row
  • the back gates of the first FeFETs are connected to the first back gate line corresponding to the row; the back gates of the second FeFETs in each bit cell in the same row are connected to the second back gate line corresponding to the row.
  • each bit unit includes only 2 FeFET transistors. Compared with the prior art that each bit unit includes 16 transistors, the area of the CAM provided by the embodiment of the present application is greatly reduced. Can reduce the power consumption of CAM.
  • a data processing method is provided, which is applied to the CAM described in the first aspect and any implementation manner of the first aspect, and the method includes:
  • the first FeFET and / or the second FeFET in each bit unit are always turned off.
  • the voltage of the drain of the first FeFET connected to the matching line in the CAM is set to a preset voltage respectively, and the preset voltages corresponding to different matching lines are the same or different.
  • the first FeFET and / or the second FeFET in each bit unit are always turned off.
  • the voltage of the drain of the first FeFET connected to the matching line in the CAM is set to a preset voltage respectively, and the preset voltages corresponding to different matching lines are the same or different.
  • each bit cell can be set in the following way The first FeFET and / or the second FeFET are always off: set the gate voltage of the first FeFET connected to the first bit line and / or the second FeFET connected to the second bit line in each bit cell to the first A voltage range, so that the first FeFET and / or the second FeFET are always turned off; wherein, when the voltage of the gate of the FeFET is in the first voltage range, the FeFET is turned off.
  • the matching value is input through the first bit line
  • the opposite value of the matching value is input through the second bit line
  • the matching value is input through the second bit line
  • the matching value is input through the first bit line
  • the opposite value of can be realized in the following manner: setting the voltage of the gate of the first FeFET connected to the first bit line to the first voltage, and setting the voltage of the gate of the second FeFET connected to the second bit line to the second Voltage to input the matching value through the first bit line, input the opposite value of the matching value through the second bit line or input the matching value through the second bit line, and input the matching value through the first bit line The opposite of the matching value.
  • the first in each bit cell can be set in the following way The FeFET and / or the second FeFET are always off: set the voltage difference between the gate and back gate of the first FeFET connected to the first bit line in each bit cell to be in the first voltage range, and / or set each The voltage difference between the gate and the back gate of the second FeFET connected to the second bit line in the bit cell is in the first voltage range, so that the first FeFET and / or the second FeFET are always off; wherein, when the FeFET When the voltage difference between the gate and the back gate is in the first voltage range, the FeFET is turned off.
  • the matching value is input through the first bit line
  • the opposite value of the matching value is input through the second bit line
  • the matching value is input through the second bit line
  • the matching value is input through the first bit line
  • the opposite value of can be realized in the following manner: setting the voltage difference between the gate and back gate of the first FeFET connected to the first bit line to the first voltage, and setting the gate of the second FeFET connected to the second bit line
  • the voltage difference from the back gate is the second voltage to input the matching value through the first bit line, the opposite value of the matching value through the second bit line, or the matching value through the second bit line
  • the opposite value of the matching value is input through the first bit line.
  • a matching value is input through the first bit line, when the matching value is 0, the first voltage is in the second voltage range, and the second voltage is in the third voltage range; when When the matching value is 1, the first voltage is in the third voltage range, and the second voltage is in the second voltage range.
  • a matching value is input through the second bit line, when the matching value is 0, the first voltage is in the third voltage range, and the second voltage is in the second voltage range; when the matching value is At 1, the first voltage is in the second voltage range, and the second voltage is in the third voltage range.
  • the matching entry with the smallest storage address is output as the matching result.
  • Embodiments of the present application provide a method for data matching using the CAM described in the first aspect and any one of its implementation manners.
  • Each bit unit of the CAM includes only two FeFET transistors.
  • the matching value is input through the bit line connected to the gate, and the matching result is output through the matching line connected to the drain.
  • the CAM since the CAM includes only two FeFET transistors, its The small size makes it possible to reduce matching power consumption.
  • an embodiment of the present application also provides a method for writing data in the CAM, specifically: when the matching method of the table entry is exact matching or mask matching and the bit unit mask is 1. At the time, when writing data in the bit unit, different values are written in the first FeFET and the second FeFET, respectively. When the matching method of the table entry is mask matching and the mask of the bit unit is 0, when data is written in the bit unit, 0 is written in both the first FeFET and the second FeFET.
  • the FeFET includes a gate and a back gate, and when writing data in the bit cell, different values may be written in the first FeFET and the second FeFET respectively in the following manner:
  • the voltage difference between the gate and back gate of the first FeFET connected with the first bit line is located in the fourth voltage range
  • the voltage difference between the gate and back gate of the second FeFET connected with the second bit line is located at the fifth voltage Range so that the first FeFET and the second FeFET write different values
  • the fourth voltage range and the fifth voltage range are different.
  • 0 can be written in both the first FeFET and the second FeFET by setting the voltage difference between the gate and back gate of the first FeFET connected by the first bit line, and the The voltage difference between the gate and the back gate of the second FeFET is in the same voltage range so that the values written to the first FeFET and the second FeFET are both zero.
  • the FeFET includes a gate and does not include a back gate
  • different values can be written in the first FeFET and the second FeFET by setting the first FeFET connected by the first bit line
  • the voltage of the gate of is in the fourth voltage range
  • the voltage of the gate of the second FeFET connected to the second bit line is in the fifth voltage range so that the first FeFET and the second FeFET write different values; wherein, the fourth The voltage range is different from the fifth voltage range.
  • 0 can be written in both the first FeFET and the second FeFET by setting the voltage of the gate of the first FeFET connected to the first bit line and the gate of the second FeFET connected to the second bit line to the same
  • the voltage range of is such that the values written to the first FeFET and the second FeFET are both 0.
  • an embodiment of the present application also provides a method for writing data in a specific bit unit in the CAM.
  • the FeFET includes a gate and a back gate
  • the CAM shown in structure 1 when the data stored in a bit unit of the CAM constitutes an entry, it is written in the bit unit located in the X row and Y column
  • the voltage of the gate of the first FeFET connected to the first bit line of the Xth row is the first write voltage
  • the voltage of the gate of the second FeFET connected to the second bit line is the second write voltage
  • the voltage of the gate of the first FeFET connected to the first bit line of the remaining rows is the third write voltage
  • the voltage of the gate of the second FeFET connected to the second bit line is the fourth write voltage.
  • the voltage of the back gate of the first FeFET connected to the first back gate line in the Y column is the fifth write voltage, and the voltage of the back gate of the second FeFET connected to the second back gate line is the sixth write voltage ;
  • the voltage of the back gate of the first FeFET connected to the first back gate line of the remaining columns is the seventh write voltage, and the voltage of the back gate of the second FeFET connected to the second back gate line is the eighth write voltage .
  • the FeFET includes a gate and a back gate
  • the voltage of the gate of the first FeFET connected to the first bit line in the Y column is the first write voltage
  • the voltage of the gate of the second FeFET connected to the second bit line is the second write voltage
  • the voltage of the gate of the first FeFET connected to the first bit line of the remaining columns is the third write voltage
  • the voltage of the gate of the second FeFET connected to the second bit line is the fourth write voltage.
  • the voltage of the back gate of the first FeFET connected to the first back gate line of the Xth row is the fifth write voltage
  • the voltage of the back gate of the second FeFET connected to the second back gate line is the sixth write voltage
  • the voltage of the back gate of the first FeFET connected to the first back gate line of the remaining rows is the seventh write voltage
  • the voltage of the back gate of the second FeFET connected to the second back gate line is the eighth write voltage .
  • the difference between the first write voltage and the fifth write voltage is within a fourth voltage range
  • the difference between the second write voltage and the sixth write voltage is within a fifth voltage range So that data is written only in the bit cells of the Xth row and Yth column
  • the difference between the third write voltage and the fifth write voltage, the fourth write voltage and the sixth write The difference in voltage, the difference between the third write voltage and the seventh write voltage, the difference between the fourth write voltage and the eighth write voltage, the first write voltage and the The difference between the seventh write voltage, the difference between the second write voltage and the eighth write voltage is within the sixth voltage range so that data is not written in the remaining bit cells.
  • the FeFET includes a gate and does not include a back gate
  • the gate of the first FeFET in each bit cell A switch is provided between the pole and the connected first bit line, and a switch is provided between the gate of the second FeFET in each bit cell and the connected second bit line.
  • a switch between the gate of the first FeFET in the bit unit in the X row and Y column and the connected first bit line is provided When turned on, the switch between the gate of the second FeFET and the connected second bit line is opened.
  • the switch between the gate of the first FeFET in the remaining bit cells of the Xth row and the connected first bit line is closed, and the switch between the gate of the second FeFET and the connected second bit line is closed.
  • the voltage of the gate of the first FeFET connected by the first bit line is the third write voltage
  • the voltage of the gate of the second FeFET connected by the second bit line is the fourth write voltage.
  • the first write voltage is in the fourth voltage range
  • the second write voltage is in the fifth voltage range to write data only in the bit cells of the Xth row and Y column
  • the third write The input voltage and the fourth write voltage are within the sixth voltage range so as not to write data in the remaining bit cells other than the bit cells in the Xth row and Y column.
  • the FeFET includes a gate and does not include a back gate, for the CAM shown in Structure 2, when the data stored in a row of bit cells of the CAM forms an entry, the gate of the first FeFET in each bit cell A switch is provided between the pole and the connected first bit line, and a switch is provided between the gate of the second FeFET in each bit cell and the connected second bit line. Then, when writing data in the bit cell located in the X row and Y column in the CAM, a switch between the gate of the first FeFET in the bit unit in the X row and Y column and the connected first bit line is provided When turned on, the switch between the gate of the second FeFET and the connected second bit line is opened.
  • the switch between the gate of the first FeFET and the connected first bit line in the remaining bit cells of the Y column is closed, and the switch between the gate of the second FeFET and the connected second bit line is closed.
  • the voltage of the gate of the first FeFET connected to the first bit line in the Y column is the first write voltage
  • the voltage of the gate of the second FeFET connected to the second bit line is the second write voltage
  • the voltage of the gate of the first FeFET connected to the first bit line of the remaining columns is the third write voltage
  • the voltage of the gate of the second FeFET connected to the second bit line is the fourth write voltage.
  • the first write voltage is in the fourth voltage range
  • the second write voltage is in the fifth voltage range to write data only in the bit cells of the Xth row and Y column
  • the third write The input voltage and the fourth write voltage are within the sixth voltage range so as not to write data in the remaining bit cells other than the bit cells in the Xth row and Y column.
  • the embodiments of the present application provide a method for writing data into a CAM using the CAM described in the first aspect and any one of its implementation manners.
  • Each bit cell of the CAM includes only two FeFET transistors. In this method, the value is written through the bit line connected to the gate.
  • the CAM since the CAM includes only two FeFET transistors, its size is small, so it is possible to reduce the amount of data written. Power consumption.
  • a data processing method is provided, which is applied to the CAM described in the first aspect and any implementation manner of the first aspect.
  • the method includes: when the matching mode of the entry is exact matching or mask matching and bit When the cell mask is 1, when writing data in the bit cell, different values are written in the first FeFET and the second FeFET, respectively.
  • the matching method of the table entry is mask matching and the mask of the bit unit is 0, when data is written in the bit unit, 0 is written in both the first FeFET and the second FeFET.
  • the FeFET includes a gate and a back gate, and when writing data in the bit cell, different values may be written in the first FeFET and the second FeFET respectively in the following manner:
  • the voltage difference between the gate and back gate of the first FeFET connected with the first bit line is located in the fourth voltage range
  • the voltage difference between the gate and back gate of the second FeFET connected with the second bit line is located at the fifth voltage Range so that the first FeFET and the second FeFET write different values
  • the fourth voltage range and the fifth voltage range are different.
  • 0 can be written in both the first FeFET and the second FeFET by setting the voltage difference between the gate and back gate of the first FeFET connected by the first bit line, and the The voltage difference between the gate and the back gate of the second FeFET is in the same voltage range so that the values written to the first FeFET and the second FeFET are both zero.
  • the FeFET includes a gate and does not include a back gate. Then different values can be written in the first FeFET and the second FeFET by setting the voltage of the gate of the first FeFET connected to the first bit line to be in the fourth voltage range, and setting the voltage of the second FeFET connected to the second bit line The voltage of the gate is in the fifth voltage range so that the first FeFET and the second FeFET write different values; wherein the fourth voltage range and the fifth voltage range are different.
  • 0 can be written in both the first FeFET and the second FeFET by setting the voltage of the gate of the first FeFET connected to the first bit line and the gate of the second FeFET connected to the second bit line to the same
  • the voltage range of is such that the values written to the first FeFET and the second FeFET are both 0.
  • an embodiment of the present application also provides a method for writing data in a specific bit unit in the CAM.
  • the FeFET includes a gate and a back gate
  • the CAM shown in structure 1 when the data stored in a bit unit of the CAM constitutes an entry, it is written in the bit unit located in the X row and Y column
  • the voltage of the gate of the first FeFET connected to the first bit line of the Xth row is the first write voltage
  • the voltage of the gate of the second FeFET connected to the second bit line is the second write voltage
  • the voltage of the gate of the first FeFET connected to the first bit line of the remaining rows is the third write voltage
  • the voltage of the gate of the second FeFET connected to the second bit line is the fourth write voltage.
  • the voltage of the back gate of the first FeFET connected to the first back gate line in the Y column is the fifth write voltage, and the voltage of the back gate of the second FeFET connected to the second back gate line is the sixth write voltage ;
  • the voltage of the back gate of the first FeFET connected to the first back gate line of the remaining columns is the seventh write voltage, and the voltage of the back gate of the second FeFET connected to the second back gate line is the eighth write voltage .
  • the FeFET includes a gate and a back gate
  • the voltage of the gate of the first FeFET connected to the first bit line in the Y column is the first write voltage
  • the voltage of the gate of the second FeFET connected to the second bit line is the second write voltage
  • the voltage of the gate of the first FeFET connected to the first bit line of the remaining columns is the third write voltage
  • the voltage of the gate of the second FeFET connected to the second bit line is the fourth write voltage.
  • the voltage of the back gate of the first FeFET connected to the first back gate line of the Xth row is the fifth write voltage
  • the voltage of the back gate of the second FeFET connected to the second back gate line is the sixth write voltage
  • the voltage of the back gate of the first FeFET connected to the first back gate line of the remaining rows is the seventh write voltage
  • the voltage of the back gate of the second FeFET connected to the second back gate line is the eighth write voltage .
  • the difference between the first write voltage and the fifth write voltage is within a fourth voltage range
  • the difference between the second write voltage and the sixth write voltage is within a fifth voltage range So that data is written only in the bit cells of the Xth row and Yth column
  • the difference between the third write voltage and the fifth write voltage, the fourth write voltage and the sixth write The difference in voltage, the difference between the third write voltage and the seventh write voltage, the difference between the fourth write voltage and the eighth write voltage, the first write voltage and the The difference between the seventh write voltage, the difference between the second write voltage and the eighth write voltage is within the sixth voltage range so that data is not written in the remaining bit cells.
  • the FeFET includes a gate and does not include a back gate
  • the gate of the first FeFET in each bit cell A switch is provided between the pole and the connected first bit line, and a switch is provided between the gate of the second FeFET in each bit cell and the connected second bit line.
  • a switch between the gate of the first FeFET in the bit unit in the X row and Y column and the connected first bit line is provided When turned on, the switch between the gate of the second FeFET and the connected second bit line is opened.
  • the switch between the gate of the first FeFET in the remaining bit cells of the Xth row and the connected first bit line is closed, and the switch between the gate of the second FeFET and the connected second bit line is closed.
  • the voltage of the gate of the first FeFET connected by the first bit line is the third write voltage
  • the voltage of the gate of the second FeFET connected by the second bit line is the fourth write voltage.
  • the first write voltage is in the fourth voltage range
  • the second write voltage is in the fifth voltage range to write data only in the bit cells of the Xth row and Y column
  • the third write The input voltage and the fourth write voltage are within the sixth voltage range so as not to write data in the remaining bit cells other than the bit cells in the Xth row and Y column.
  • the FeFET includes a gate and does not include a back gate, for the CAM shown in Structure 2, when the data stored in a row of bit cells of the CAM forms an entry, the gate of the first FeFET in each bit cell A switch is provided between the pole and the connected first bit line, and a switch is provided between the gate of the second FeFET in each bit cell and the connected second bit line. Then, when writing data in the bit cell located in the X row and Y column in the CAM, a switch between the gate of the first FeFET in the bit unit in the X row and Y column and the connected first bit line is provided When turned on, the switch between the gate of the second FeFET and the connected second bit line is opened.
  • the switch between the gate of the first FeFET and the connected first bit line in the remaining bit cells of the Y column is closed, and the switch between the gate of the second FeFET and the connected second bit line is closed.
  • the voltage of the gate of the first FeFET connected to the first bit line in the Y column is the first write voltage
  • the voltage of the gate of the second FeFET connected to the second bit line is the second write voltage
  • the voltage of the gate of the first FeFET connected to the first bit line of the remaining columns is the third write voltage
  • the voltage of the gate of the second FeFET connected to the second bit line is the fourth write voltage.
  • the first write voltage is in the fourth voltage range
  • the second write voltage is in the fifth voltage range to write data only in the bit cells of the Xth row and Y column
  • the third write The input voltage and the fourth write voltage are within the sixth voltage range so as not to write data in the remaining bit cells other than the bit cells in the Xth row and Y column.
  • Embodiments of the present application provide a method for writing data in a CAM using the CAM described in the first aspect and any one of its implementation manners.
  • Each bit unit of the CAM includes only two FeFET transistors. In this method, the value is written through the bit line connected to the gate.
  • the CAM since the CAM includes only two FeFET transistors, its size is small, so it is possible to reduce Power consumption.
  • an embodiment of the present application further provides a method for data matching using the CAM shown in structure one or structure two.
  • the first FeFET and / or the second FeFET in each bit cell are set to be always off.
  • the voltage of the drain of the first FeFET connected to the matching line in the CAM is set to a preset voltage respectively, and the preset voltages corresponding to different matching lines are the same or different.
  • the first FeFET and / or the second FeFET in each bit unit are always turned off.
  • the voltage of the drain of the first FeFET connected to the matching line in the CAM is set to a preset voltage respectively, and the preset voltages corresponding to different matching lines are the same or different.
  • each bit cell can be set in the following way The first FeFET and / or the second FeFET are always off: set the gate voltage of the first FeFET connected to the first bit line and / or the second FeFET connected to the second bit line in each bit cell to the first A voltage range, so that the first FeFET and / or the second FeFET are always turned off; wherein, when the voltage of the gate of the FeFET is in the first voltage range, the FeFET is turned off.
  • the matching value is input through the first bit line
  • the opposite value of the matching value is input through the second bit line
  • the matching value is input through the second bit line
  • the matching value is input through the first bit line
  • the opposite value of can be realized in the following manner: setting the voltage of the gate of the first FeFET connected to the first bit line to the first voltage, and setting the voltage of the gate of the second FeFET connected to the second bit line to the second Voltage to input the matching value through the first bit line, input the opposite value of the matching value through the second bit line or input the matching value through the second bit line, and input the matching value through the first bit line The opposite of the matching value.
  • the first in each bit cell can be set in the following way The FeFET and / or the second FeFET are always off: set the voltage difference between the gate and back gate of the first FeFET connected to the first bit line in each bit cell to be in the first voltage range, and / or set each The voltage difference between the gate and the back gate of the second FeFET connected to the second bit line in the bit cell is in the first voltage range, so that the first FeFET and / or the second FeFET are always off; wherein, when the FeFET When the voltage difference between the gate and the back gate is in the first voltage range, the FeFET is turned off.
  • the matching value is input through the first bit line
  • the opposite value of the matching value is input through the second bit line
  • the matching value is input through the second bit line
  • the matching value is input through the first bit line
  • the opposite value of can be realized in the following manner: setting the voltage difference between the gate and back gate of the first FeFET connected to the first bit line to the first voltage, and setting the gate of the second FeFET connected to the second bit line
  • the voltage difference from the back gate is the second voltage to input the matching value through the first bit line, the opposite value of the matching value through the second bit line, or the matching value through the second bit line
  • the opposite value of the matching value is input through the first bit line.
  • a matching value is input through the first bit line, when the matching value is 0, the first voltage is in the second voltage range, and the second voltage is in the third voltage range; when When the matching value is 1, the first voltage is in the third voltage range, and the second voltage is in the second voltage range.
  • a matching value is input through the second bit line, when the matching value is 0, the first voltage is in the third voltage range, and the second voltage is in the second voltage range; when the matching value is At 1, the first voltage is in the second voltage range, and the second voltage is in the third voltage range.
  • the FeFET includes a gate and does not include a back gate
  • a matching value is input into the FeFET for matching, and when the voltage of the gate is in the third voltage range, FeFET is always on.
  • the FeFET includes a gate and a back gate
  • when the voltage difference between the gate and the back gate is in the second voltage range a matching value is input into the FeFET for matching, and when the voltage difference between the gate and the back gate is In the third voltage range, the FeFET is always on.
  • the matching entry with the smallest storage address is output as the matching result.
  • Embodiments of the present application provide a method for data matching using the CAM described in the first aspect and any one of its implementation manners.
  • Each bit unit of the CAM includes only two FeFET transistors.
  • the matching value is input through the bit line connected to the gate, and the matching result is output through the matching line connected to the drain.
  • the CAM since the CAM includes only two FeFET transistors, its The small size makes it possible to reduce matching power consumption.
  • an embodiment of the present application provides a network device, including a processor, a communication interface, a first memory, a second memory, and a communication bus; wherein, the processor, the communication interface, the first memory, and the second memory pass through The communication buses communicate with each other; the first memory stores computer executable program code, the second memory is the CAM according to the first aspect and any implementation manner of the first aspect, and the processor is used to execute The computer executable program code stored in the first memory controls the second memory to execute the data processing method described in the second aspect and any one of its implementation manners.
  • the processor is configured to execute the computer-executable program code stored in the first memory to control the second memory to execute the data processing method described in the third aspect and any one of its implementation manners.
  • FIG. 1 is a schematic structural diagram of a FeFET provided by an embodiment of this application.
  • FIG. 2 is a schematic structural diagram of a CAM provided by an embodiment of the present application.
  • FIG. 3 is a schematic flowchart of a method for searching data in a CAM provided by an embodiment of the present application
  • FIG. 4 is a schematic flowchart of another method for searching data in a CAM provided by an embodiment of the present application.
  • FIG. 5 is a schematic flowchart of a method for writing data in a CAM provided by an embodiment of the present application
  • FIG. 6 is a schematic flowchart of a method for writing data in a bit unit in a CAM provided by an embodiment of the present application
  • FIG. 7 is a schematic flowchart of another method for writing data in a bit unit in a CAM provided by an embodiment of the present application.
  • FIG. 8 is a schematic flowchart of another method for writing data in a bit unit in a CAM provided by an embodiment of the present application.
  • FIG. 9 is a schematic flowchart of another method for writing data in a bit unit in a CAM provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a network device according to an embodiment of the present application.
  • the structure of the unit cell makes the electric dipole moment appear when the positive and negative charge centers do not coincide, resulting in a polarization intensity not equal to zero, so that the crystal has spontaneous polarization, and the direction of the electric dipole moment can be due to external electric field Changes, showing characteristics similar to ferromagnets, this property of the crystal is called ferroelectricity.
  • Ferro-electric field effect transistor is a kind of field effect transistor with ferroelectric characteristics. Its main principle is to add ferroelectric characteristics to the gate insulator of the field effect transistor, so that FeFET has a hysteresis.
  • the back curve characteristic divides the threshold voltage of the FeFET into two stable states. Therefore, the binary state can be stored in the FeFET. If the gate voltage of the FeFET is higher than the threshold voltage, the FeFET is turned on; if the gate voltage of the FeFET is lower than the threshold voltage, the FeFET is turned off. In addition, even if the gate voltage of the FeFET is 0, the data is still saved.
  • CAM is a memory addressable by content. It is a special storage array. Its working mechanism is to automatically compare an input data item with all the data items stored in the CAM at the same time. Whether the data items match, and output the matching information corresponding to the data items.
  • CAM is an important component of network equipment such as switches and routers.
  • a typical CAM is TCAM. TCAM is developed from the basis of CAM. Generally, there are only two states of each bit in CAM memory, "0" or "1", and each bit in TCAM has three states, in addition to "0" and "1", there is a "don” The 'tcare' state, so called 'tri-state', is implemented through a mask. It is this third state feature of TCAM that allows it to perform both exact match search and fuzzy match search.
  • An embodiment of the present application provides a content addressable memory.
  • Each bit unit of the content addressable memory is composed of two FeFETs connected in series.
  • the drain of the first FeFET (shown as M1 in FIG. 1) is connected to ML, and the source of the first FeFET is connected to the drain of the second FeFET (shown as M2 in FIG. 1).
  • the source of the second FeFET is grounded.
  • the gate of the first FeFET is connected to the first bit line, and the gate of the second FeFET is connected to the second bit line.
  • the FeFET further includes a back gate, and correspondingly, the back gate of the first FeFET is connected to the first back gate line, and the back gate of the second FeFET is connected to the second back gate line.
  • Each bit unit is an exclusive NOR gate based on the two FeFETs connected in series. When performing a search operation, the bit line is used to enter a matching value. Each bit unit can implement the exclusive or non-logic operation (or described as a comparison operation) of the data stored in the bit unit and the matching value.
  • the value to be matched is stored in M1 of the bit unit, and the opposite value of the value to be matched is stored in M2.
  • Table 1 in the following table is a possible implementation of the truth table of the bit unit.
  • the first four lines are exact matches. Only when the value of M1 and the key value are different, M1 and M2 will be opened at the same time, and the matching result of key value and M1 is mismatch. In other cases, when the value stored in M1 and the key value are the same, at least one of M1 and M2 is disconnected, and the matching result of the key value and M1 is a match.
  • the fifth line is mask matching.
  • the mask of the bit unit is 0 as an example. If the mask is 0, the bit does not participate in the matching, and both M1 and M2 store 0, regardless of the value of the entered key value. At least one of M1 and M2 is disconnected, then the value stored in M1 is the same as the key value, and the matching result of key value and M1 is a match.
  • the bit line is used to input data to be written.
  • the matching method of the table entry is exact matching or mask matching and the mask of the bit unit is 1
  • the second FeFET writes the opposite value of the data to be written
  • the second FeFET writes the data to be written
  • the matching mode of the table entry is mask matching and the mask of the bit unit is 0, when writing data in the bit unit, the first bit line and the second bit line are respectively in the first FeFET and the second FeFET Write 0.
  • an embodiment of the present application provides a CAM, which includes: M rows and N columns of bit units, where M and N are both positive integers greater than or equal to 1.
  • each bit cell includes a first FeFET and a second FeFET, the source of the first FeFET is connected to the drain of the second FeFET, and the The source is grounded.
  • the data stored in a column of bit units of the CAM constitutes an entry.
  • the bit cells in the same column correspond to the same matching line, and the drain of the first FeFET in each bit cell in the same column is connected to the matching line corresponding to the column.
  • the bit cells in the same row correspond to the same first bit line and the same second bit line.
  • the gates of the first FeFETs in each bit cell in the same row are connected to the corresponding first bit line in the row, each in the same row.
  • the gates of the second FeFETs in the bit cell are all connected to the second bit line corresponding to the row.
  • bit cells in the same column respectively correspond to the same first back gate line and the same second back gate line; the back gates of the first FeFETs in each bit cell in the same column are connected to the first back corresponding to the column Gate line; the back gates of the second FeFETs in each bit cell in the same column are connected to the second back gate line corresponding to the column.
  • FIG. 2 is a possible implementation manner of CAM.
  • the CAM includes: 4 rows and 4 columns of bit units.
  • the data stored in one column of bit units constitutes an entry.
  • Each bit unit includes two FeFETs, M1 and M2.
  • the drain of M1 in each bit cell of the same column is connected to the matching line corresponding to the column.
  • the gates of all M1s in the same row of bit cells are connected to the first bit line corresponding to the row, and the gates of all M2 in the same row of bit units are connected to the second bit line corresponding to the row.
  • the back gate of M1 in each bit cell of the same column is connected to the first back gate line corresponding to the column
  • the back gate of M2 in each bit cell of the same column is connected to the second back gate corresponding to the column Back grid line.
  • the data stored in a column of bit units of the CAM constitutes an entry.
  • data stored in a row of bit units of the CAM constitute an entry.
  • the bit cells in the same row correspond to the same match line; the drain of the first FeFET in each bit cell in the same row is connected to the match line corresponding to the row; the bit cells in the same column correspond to the same first The bit line and the same second bit line, the gate of the first FeFET in each bit cell in the same column is connected to the first bit line corresponding to the column, the second FeFET in each bit cell in the same column The gates are connected to the second bit line corresponding to the column.
  • bit cells in the same row correspond to the same first back gate line and the same second back gate line; the back gates of the first FeFETs in each bit cell in the same row are connected to the corresponding The first back gate line; the back gates of the second FeFETs in each bit cell in the same row are connected to the second back gate line corresponding to the row.
  • each bit unit includes only 2 FeFET transistors. Compared with the prior art that each bit unit includes 16 transistors, the area of the CAM provided by the embodiment of the present application is greatly reduced. Can reduce the power consumption of CAM.
  • An embodiment of the present application also provides a data processing method based on the above-mentioned CAM provided by an embodiment of the present application.
  • the data processing method specifically includes: writing data in the CAM and searching data in the CAM (or described as matching data from the CAM).
  • the CAM is used to store entry data of tables such as routing tables or ACL tables.
  • a routing table or ACL table consists of multiple entries. Therefore, the data written in the CAM described in the embodiments of the present application is specifically the data written into each entry in the routing table or the ACL table in the CAM.
  • the matching data from the CAM is specifically to search for a certain entry in a routing table or ACL table in the CAM.
  • first voltage range second voltage range
  • third voltage range If the voltage input to the gate of the FeFET is in the first voltage range, the FeFET is always turned off. If the gate input voltage of the FeFET is in the second voltage range, the FeFET is turned on when 1 is written in the FeFET, and the FeFET is turned off when 0 is written in the FeFET. If the voltage input to the gate of the FeFET is in the third voltage range, the FeFET is always on.
  • the first voltage range is -2V to -0.6V
  • the second voltage range is a voltage around 0V, for example: -0.5V to 0.5V
  • the third voltage range is 0.6V to 1.6V.
  • the voltage involved in writing the voltage range of writing 0 and the voltage range of writing 1.
  • the voltage range of writing 0 and the voltage range of writing 1 are different voltage ranges.
  • the gate voltage of the FeFET is set in the voltage range where 0 is written.
  • writing 1 to a FeFET set the gate voltage of this FeFET to the voltage range where 1 is written.
  • the specific values of the voltage range of writing 0 and the voltage range of writing 1 are determined by the properties of the FeFET device. Generally, the voltage of writing 0 is opposite to the voltage of writing 1, but the absolute value is not limited Size relationship.
  • the voltage range for writing 0 is usually less than a negative voltage, and the lower limit is not limited; the voltage range for writing 1 is usually greater than a positive voltage, and the upper limit is not limited; for example, writing 0
  • the voltage range of is -3V to -2V, and the voltage range of writing 1 is 2V to 3V.
  • searching the data in the CAM may be specifically implemented as the following steps S301 to S304:
  • each FeFET includes a gate and does not include a back gate.
  • the first FeFET connected to the first bit line and / or the second The gate voltage of the second FeFET connected to the bit line is in the first voltage range.
  • the FeFET is turned off.
  • each FeFET includes a gate and a back gate, in one implementation of this step, the gate and back gate of the first FeFET connected to the first bit line in each bit cell are separately provided , And / or the voltage difference between the gate and the back gate of the second FeFET connected to the second bit line is in the first voltage range. Wherein, when the voltage difference between the gate and back gate of the FeFET is in the first voltage range, the FeFET is turned off.
  • the preset voltages corresponding to different matching lines may be the same or different.
  • the preset voltage is any voltage.
  • the matching line is precharged to the preset voltage.
  • each FeFET includes a gate and does not include a back gate.
  • the voltage of the gate of the first FeFET connected to the first bit line is set to the first voltage
  • the The voltage of the gate of the second FeFET connected to the two bit lines is the second voltage to input the matching value through the first bit line, input the opposite value of the matching value through the second bit line, or pass the second The bit line inputs the matching value, and the opposite value of the matching value is input through the first bit line.
  • the gate voltages connected to different first bit lines may be the same or different, that is, the first voltages corresponding to different first bit lines may be the same or different, and the gate voltages connected to different second bit lines may be The same or different, that is, the second voltages corresponding to different second bit lines may be the same or different.
  • each FeFET includes a gate and a back gate, in one implementation of this step, the voltage difference between the gate and the back gate of the first FeFET connected to the first bit line is set to the first Voltage, the voltage difference between the gate and back gate of the second FeFET connected to the second bit line is set to a second voltage to input a matching value through the first bit line, and input the matching value through the second bit line Or the matching value through the second bit line, and the opposite value of the matching value through the first bit line.
  • the voltage difference between the gate and back gate of the first FeFET connected by different first bit lines may be the same or different, that is, the first voltages corresponding to different first bit lines may be the same or different, different
  • the voltage difference between the gate and the back gate of the second FeFET connected to the second bit line may be the same or different, that is, the second voltages corresponding to different second bit lines may be the same or different.
  • a matching value is input through the first bit line, when the matching value is 0, the first voltage is in the second voltage range, and the second voltage is in the third voltage range; when When the matching value is 1, the first voltage is in the third voltage range, and the second voltage is in the second voltage range.
  • a matching value is input through the second bit line, when the matching value is 0, the first voltage is in the third voltage range, and the second voltage is in the second voltage range; when the matching value is At 1, the first voltage is in the second voltage range, and the second voltage is in the third voltage range.
  • the FeFET includes a gate and does not include a back gate
  • a matching value is input into the FeFET for matching, and when the voltage of the gate is in the third voltage range
  • the FeFET is always on; or, if the FeFET includes a gate and a back gate, when the voltage difference between the gate and the back gate is in the second voltage range, a matching value is input into the FeFET for matching, when the gate When the voltage difference between the pole and the back gate is in the third voltage range, the FeFET is always on.
  • the matching entry with the smallest storage address is output as the matching result.
  • the entry consisting of the data stored in the bit unit of the target column with the smallest column number is output as the matching result.
  • searching the data in the CAM may be specifically implemented as the following steps S401 to S404:
  • S402 Set the drain voltage of the first FeFET connected to the matching line in the CAM to a preset voltage, respectively.
  • the preset voltages corresponding to different matching lines are the same or different.
  • the matching entry with the smallest storage address is output as the matching result.
  • the entry consisting of the data stored in the bit unit of the target row with the smallest row number is output as the matching result.
  • each bit unit of the CAM only includes two FeFET transistors.
  • the matching value is input through the bit line connected to the gate, and the matching result is output through the matching line connected to the drain.
  • the CAM since the CAM includes only two FeFET transistors, its The small size makes it possible to reduce matching power consumption.
  • a data table is composed of multiple entries.
  • the configuration file of the data table stores the matching methods of the entries.
  • the matching methods of all entries in the same data table are the same. Therefore, when looking up the table in the CAM, the matching method of the entry can be determined according to the configuration file of the table.
  • Table entry matching methods include: exact matching and mask matching. Among them, the exact match means that when the input matching value is the same as the value stored in the bit unit, it means that the value stored in the bit unit matches the value to be matched, otherwise it is considered not to match.
  • Mask matching refers to determining whether the value stored in the bit unit participates in matching according to the mask value of the bit unit.
  • the matching method of the table entry is mask matching and the bit unit mask is 1, it means that the value stored in the bit unit participates in the matching and when the value stored in the bit unit is the same as the value to be matched, it indicates a match. If the matching method of the entry is mask matching and the bit unit mask is 0, it means that the value stored in the bit unit does not participate in the matching.
  • the process of writing data in the CAM includes the following steps S501 and S502.
  • the FeFET includes a gate and a back gate.
  • the voltage difference between the gate and the back gate of the first FeFET connected to the first bit line is In four voltage ranges, the voltage difference between the gate and the back gate of the second FeFET connected to the second bit line is set in the fifth voltage range so that the first FeFET and the second FeFET write different values.
  • the fourth voltage range and the fifth voltage range are different.
  • the FeFET includes a gate and does not include a back gate.
  • the voltage of the gate of the first FeFET connected to the first bit line is located in the fourth voltage range
  • the voltage of the gate of the second FeFET connected to the second bit line is in the fifth voltage range so that the first FeFET and the second FeFET write different values.
  • the fourth voltage range and the fifth voltage range are different.
  • the back gate is generally grounded, so the voltage difference between the gate and the back gate is the gate voltage.
  • the fourth voltage range is the voltage range where 1 is written , That is, this voltage range is used to write 1 in the first FeFET.
  • the fifth voltage range is a voltage range where 0 is written, that is, this voltage range is used to write 0 in the second FeFET.
  • the fourth voltage range is a voltage range where 0 is written, that is, the voltage range is used to write 0 in the first FeFET
  • the fifth voltage range is a voltage range where 0 is written, that is, the voltage range is used To write 1 in the second FeFET.
  • one of the FeFETs in the bit unit is written with 1 and the other FeFET is written with 0.
  • the two FeFETs in the bit unit have one FeFET as the dominant FeFET.
  • the value stored in the FeFET is determined.
  • the FeFET includes a gate and a back gate.
  • the voltage difference between the gate and the back gate of the first FeFET connected to the first bit line is set.
  • the voltage difference between the gate and the back gate of the second FeFET connected by the two bit lines is in the same voltage range so that the values written to the first FeFET and the second FeFET are both zero.
  • the FeFET only includes a gate and does not include a back gate.
  • the gate of the first FeFET connected to the first bit line and the second bit line are connected
  • the voltage of the gate of the second FeFET is in the same voltage range so that the values written to the first FeFET and the second FeFET are both 0.
  • the same voltage range as described above is a voltage range in which 0 is written.
  • the FeFET when the data stored in a bit unit of the CAM constitutes an entry, it is located in the X row and Y column.
  • the following process is performed:
  • the voltage of the gate of the first FeFET connected to the first bit line in the Xth row is the first write voltage
  • the voltage of the gate of the second FeFET connected to the second bit line is the second write voltage
  • the voltages of the gates of the first FeFETs connected to the first bit lines in different rows may be the same or different, that is, the third write voltages corresponding to the different rows may be the same or different.
  • the voltages of the gates of the second FeFETs connected to the second bit lines in different rows may be the same or different, that is, the fourth write voltages corresponding to the different rows may be the same or different.
  • the voltage of the back gate of the first FeFET connected with the first back gate line of the Yth column is the fifth write voltage
  • the voltage of the back gate of the second FeFET connected with the second back gate line is the sixth write ⁇ voltage
  • the fifth write voltage is in a voltage range of about 0V
  • the sixth write voltage is in a voltage range of about 0V.
  • the two voltage ranges may be the same or different.
  • the fifth write voltage is in the voltage range of -0.5V to 0.5V
  • the fifth write voltage is in the voltage range of -0.4V to 0.4V.
  • S604 Set the voltage of the back gate of the first FeFET connected to the first back gate line of the remaining columns to the seventh write voltage, and the voltage of the back gate of the second FeFET connected to the second back gate line to the eighth write Voltage.
  • the voltages of the back gates of the first FeFETs connected to the first back gate lines in different columns may be the same or different, that is, the seventh write voltages corresponding to the different columns may be the same or different.
  • the voltages of the back gates of the second FeFETs connected to the second back gate lines of different columns may be the same or different, that is, the eighth write voltages corresponding to the different columns may be the same or different.
  • the difference between the first write voltage and the fifth write voltage is within a fourth voltage range
  • the difference between the second write voltage and the sixth write voltage is within a fifth voltage range So that data is written only in the bit cells of the Xth row and Yth column
  • the difference between the third write voltage and the fifth write voltage, the fourth write voltage and the sixth write The difference in voltage, the difference between the third write voltage and the seventh write voltage, the difference between the fourth write voltage and the eighth write voltage, the first write voltage and the The difference between the seventh write voltage, the difference between the second write voltage and the eighth write voltage is within the sixth voltage range so that data is not written in the remaining bit cells.
  • the fourth voltage range is different from the fifth voltage range.
  • the specific fourth voltage range is a voltage range where 0 is written, and the fifth voltage range is a voltage range where 1 is written.
  • the fourth voltage range is a voltage range where 1 is written
  • the fifth voltage range is a voltage range where 0 is written.
  • the sixth voltage range is a voltage range in which data is not written, that is, a voltage range other than the voltage range in which 0 is written and the voltage range in which 1 is written.
  • the difference between the first write voltage and the fifth write voltage is within the voltage range of writing 0 to the first FeFET of the bit cell 0 is written in
  • the difference between the second write voltage and the sixth write voltage is within the voltage range of write 1 to write 1 in the second FeFET of the bit cell, so that when the first FeFET is the dominant FeFET,
  • the data stored in this bit unit is 0.
  • the difference between the first write voltage and the fifth write voltage is within the voltage range of write 1 to write 1 in the first FeFET of the bit cell, and between the second write voltage and the sixth write voltage The difference is within the voltage range where 0 is written to write 0 in the second FeFET of the bit cell, so that when the first FeFET is the dominant FeFET, the data stored in the bit cell is 1.
  • the ratio of the third write voltage to the first write voltage is in a preset ratio range, for example, half, and the ratio of the sixth write voltage to the first write voltage is also half
  • the ratio of the fourth write voltage to the second write voltage is in a preset ratio range, for example, half; the ratio of the seventh write voltage to the second write voltage is in the preset ratio range, For example half.
  • the FeFET includes a gate and a back gate
  • the data stored in a row of bit cells of the CAM constitutes an entry
  • the FeFET performs the following procedure:
  • the voltage of the gate of the first FeFET connected to the first bit line in the Y column is the first write voltage
  • the voltage of the gate of the second FeFET connected to the second bit line is the second write voltage
  • the voltage of the back gate of the first FeFET connected to the first back gate line of the Xth row is the fifth write voltage
  • the voltage of the back gate of the second FeFET connected to the second back gate line is the sixth write ⁇ voltage
  • S704 Set the voltage of the back gate of the first FeFET connected to the first back gate line of the remaining rows to the seventh write voltage, and the voltage of the back gate of the second FeFET connected to the second back gate line to the eighth write Voltage.
  • the implementation process of S701 to S704 is different from the implementation process of S601 to S604 in that the implementation process described in S701 to S704 is applied to a scenario where data stored in a row of bit units of a CAM forms an entry, and S601 to S604 The described implementation process is applied in the scenario where the data stored in a column of bit units of the CAM constitutes an entry.
  • the gate and back gate in the FeFET is described by taking the gate and back gate in the FeFET as an example. If the FeFET only includes the gate and does not include the back gate, the data stored in one bit unit of the CAM constitutes a data table entry scenario In each bit cell, a switch is provided between the gate of the first FeFET in each bit cell and the connected first bit line, and a gate is provided between the gate of the second FeFET in each bit cell and the connected second bit line Switch, so as shown in Figure 8, data can be written in the bit cell located in the X row and Y column in the following manner:
  • the switch between the gate of the first FeFET and the connected first bit line in the remaining bit cells of the Xth row is set to close, and the switch between the gate of the second FeFET and the connected second bit line is closed.
  • the voltage of the gate of the first FeFET connected to the first bit line in the Xth row is the first write voltage
  • the voltage of the gate of the second FeFET connected to the second bit line is the second write voltage
  • the first write voltage is in the fourth voltage range
  • the second write voltage is in the fifth voltage range to write data only in the bit cells of the Xth row and Y column
  • the third write The input voltage and the fourth write voltage are within the sixth voltage range so as not to write data in the remaining bit cells other than the bit cells in the Xth row and Y column.
  • the fourth voltage range is within the voltage range of 0 to write 0 in the first FeFET of the bit cell
  • the fifth voltage range is Write 1 within the voltage range to write 1 in the second FeFET of the bit cell, so that when the first FeFET is the dominant FeFET, the data stored in the bit cell is 0.
  • the fourth voltage range is within the voltage range of writing 1 to write 1 in the first FeFET of the bit cell
  • the fifth voltage range is Write a voltage in the range of 0 to write 0 in the second FeFET of the bit cell, so that when the first FeFET is the dominant FeFET, the data stored in the bit cell is 1.
  • the FeFET contains only the gate and not the back gate
  • the data stored in a row of bit cells of the CAM constitutes a data table entry
  • the first FeFET in each bit cell can be A switch is provided between the gate and the connected first bit line, and a switch is provided between the gate of the second FeFET in each bit cell and the connected second bit line.
  • data can be written in the bit cell located in the Xth row and the Yth column in the following manner:
  • the voltage of the gate of the first FeFET connected to the first bit line in the Y column is the first write voltage
  • the voltage of the gate of the second FeFET connected to the second bit line is the second write voltage
  • the third write voltages corresponding to the first bit lines in different columns may be the same or different, and the fourth write voltages corresponding to the second bit lines in different columns may be the same or different.
  • the first write voltage is in the fourth voltage range
  • the second write voltage is in the fifth voltage range to write data only in the bit cells of the Xth row and Y column
  • the third write The input voltage and the fourth write voltage are within the sixth voltage range so as not to write data in the remaining bit cells other than the bit cells in the Xth row and Y column.
  • the fourth voltage range is a voltage range where 0 is written to write 0 in the first FeFET of the bit cell
  • the fifth voltage range is written Enter a voltage range of 1 to write 1 in the second FeFET of the bit cell, so that when the first FeFET is the dominant FeFET, the data stored in the bit cell is 0.
  • the fourth voltage range is within the voltage range of writing 1 to write 1 in the first FeFET of the bit cell
  • the fifth voltage range is Write a voltage in the range of 0 to write 0 in the second FeFET of the bit cell, so that when the first FeFET is the dominant FeFET, the data stored in the bit cell is 1.
  • each bit cell of the CAM only includes two FeFET transistors.
  • the value is written through the bit line connected to the gate.
  • the CAM since the CAM includes only two FeFET transistors, its size is small, so it is possible to reduce the amount of data written. Power consumption.
  • the look-up tables in network equipment are all implemented with search algorithms.
  • the search algorithms are usually divided into multiple levels or multiple nodes. Within a certain level or a certain node, there is usually work that requires accurate search.
  • the traditional method is to read all the data of the level or the node from the memory through memory reading, and then complete the matching work by the logic circuit. This method is very time-consuming and will occupy memory bandwidth.
  • Using the content addressable memory provided in the embodiment of the present application to look up tables in a network device for the lookup work of a certain level or a certain node, the lookup hit inside the algorithm node can be completed directly in the memory, and only the hit part is returned. This saves memory bandwidth and greatly reduces search latency.
  • Common table lookup algorithms include longest prefix matching (LPM), mask matching, and exact matching (EM).
  • LPM includes five levels of processing.
  • the processing flow of each level is as follows: read data from memory and use logic circuits in many entries Find an entry that matches a given matching value (key).
  • key By using the method provided in the embodiment of the present application, it is possible to directly use the CAM to complete the search and match of the entry in the memory, and then directly return the result from the memory, eliminating the process of using the logic circuit to perform the search.
  • the search for mask matching is divided into multi-level processing, and the last level of processing is to find matching rules in a specific container.
  • the traditional algorithm is to read all the data from the memory, and then use the logic circuit to find the matching rules.
  • the exact matching search is divided into multiple levels.
  • the traditional search algorithm is to read the data from the memory, and then use the logic circuit to find the matching data.
  • the content addressable memory provided in the embodiments of the present application is applied to a network device, and the network device may be any device used to transmit data packets through a network.
  • the network device may specifically be a device such as a switch or a router.
  • the network device 1000 includes a communication interface 1010, a processor 1020, a memory 1030, and a bus 1040. Among them, the communication interface 1010, the processor 1020, and the memory 1030 communicate with each other through the bus 1040.
  • the memory 1030 includes a first memory 1031 and a second memory 1032.
  • the second memory 1032 may specifically be a CAM provided by an embodiment of the present application.
  • the network device 1000 communicates with other devices through the communication interface 1010. For example, the network device 1000 receives messages sent by other devices through the communication interface 1010 or sends messages to other devices.
  • the communication interface 1010 includes an ingress media access control (MAC) chip and an egress MAC chip.
  • the network device 1000 can receive the message through the ingress MAC chip and send the message through the egress MAC chip.
  • MAC media access control
  • the processor 1020 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.
  • the processor 1020 is a complementary metal oxide semiconductor (CMOS) logic circuit, and the processor 1020 is used to execute executable program code stored in the first memory 1031, such as a computer program to run and execute The program corresponding to the code.
  • CMOS complementary metal oxide semiconductor
  • the first memory 1031 is used to store executable program code, and the program code includes computer operation instructions.
  • the first memory 1031 may include a high-speed random access memory (random access memory, RAM) memory, or may further include a non-volatile memory (non-volatile memory), such as at least one disk memory.
  • the second memory 1032 may be a CAM provided by an embodiment of this application, for example, it may be a TCAM.
  • the bus 1040 may be an industry standard architecture (ISA) bus, an external device interconnection (peripheral component, PCI) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, or the like.
  • ISA industry standard architecture
  • PCI peripheral component
  • EISA extended industry standard architecture
  • the bus 1040 can be divided into an address bus, a data bus, and a control bus. For ease of representation, only a thick line is used in FIG. 10, but it does not mean that there is only one bus or one type of bus.
  • the method provided in this embodiment of the present application may be specifically implemented as follows: the network device 1000 receives the data message through the communication interface 1010 and hands the data message to the processor 1020, and the processor 1020 performs pre-processing After processing, the second memory 1032 executes S301 to S304 shown in FIG. 3, S401 to S404 shown in FIG. 4, S501 to S502 shown in FIG. 5, S601 to S604 shown in FIG. 6, and S701 shown in FIG. 7.

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Abstract

本申请公开内容寻址存储器、数据处理方法及网络设备，涉及存储技术领域，可解决现有的CAM面积较大，进而功耗较大的问题。该CAM包括：M行N列bit单元，每个bit单元包括第一FeFET和第二FeFET，第一FeFET的源极连接第二FeFET的漏极，第二FeFET的源极接地，同一列bit单元对应同一匹配线；位于同一列的每个bit单元中的第一FeFET的漏极均连接该列对应的匹配线。同一行bit单元对应同一第一位线和同一第二位线，位于同一行的每个bit单元中的第一FeFET的栅极均连接该行对应的第一位线，位于同一行的每个bit单元中的第二FeFET的栅极均连接该行对应的第二位线。该CAM可应用在路由器等网络设备中。

Description

内容寻址存储器、数据处理方法及网络设备
本申请要求于2018年10月30日提交国家知识产权局、申请号为201811281043.6、发明名称为“内容寻址存储器、数据处理方法及网络设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储技术领域，尤其涉及内容寻址存储器、数据处理方法及网络设备。
背景技术
内容寻址存储器(content addressable memory，CAM)是网络设备的重要物理器件，一种典型的CAM为三态内容寻址存储器(ternary content addressable memory，TCAM)主要用于快速查找访问控制列表(access control list，ACL)、路由表等表项。
如图1所示，传统的基于(metal oxide semiconductor，MOS)管的TCAM，每一个位(bit)单元由16个晶体管(transistor，T)构成，其中12T用于存储数值和掩码，4T用于做比较。搜索线(search line，SL)用来输入匹配值(key)，匹配线(match line，ML)用来返回匹配结果。该传统TCAM阵列中每一行代表一个表项，查找数据时，先把每一行的ML都充到高电位。每一列的SL输入key的一个bit，将该bit的值与TCAM表项中的值比较，所有表项同时进行匹配。如果某一行中的所有bit都匹配成功，ML保持高电位。如果该行中有任意bit不匹配，则该行的ML泄漏到低电平。通过判定ML的高低电位，来判定匹配结果。
由于传统的基于MOS管的TCAM每个bit单元需要16T，因此TCAM的面积较大，随之带来的是TCAM的功耗较大，越大尺寸的TCAM的功耗越为严重。
发明内容
本申请实施例提供的内容寻址存储器、数据处理方法及网络设备，能够减小CAM的尺寸，进而减少CAM的功耗。
第一方面，本申请实施例提供一种内容寻址存储器CAM，包括：M行N列bit单元，该M和N均为大于等于1的正整数；每个bit单元包括第一铁电场效应晶体管(ferro-electric field effect transistor，FeFET)和第二FeFET。该第一FeFET的源极连接该第二FeFET的漏极，该第二FeFET的源极接地。
CAM通常由多行多列bit单元组成，其中，可以是CAM的一行bit单元中存储的数据组成一个表项，也可以是CAM的一列bit单元中存储的数据组成一个表项，这两种方式下CAM的结构不同。
结构一：CAM的一列bit单元中存储的数据组成一个表项。那么，同一列bit单元对应同一匹配线；位于同一列的每个bit单元中的第一FeFET的漏极均连接该列对应的匹配线；同一行bit单元对应同一第一位线和同一第二位线，位于同一行的每个bit单元中的第一FeFET的栅极均连接该行对应的第一位线，位于同一行的每个bit单元中的第二FeFET的栅极均连接该行对应的第二位线。
结构二：CAM的一行bit单元中存储的数据组成一个表项。那么，同一行bit单元对应同一匹配线；位于同一行的每个bit单元中的第一FeFET的漏极均连接该行对应的匹配线；同一列bit单元对应同一第一位线和同一第二位线，位于同一列的每个bit单元中的第一FeFET的栅极均连接该列对应的第一位线，位于同一列的每个bit单元中的第二FeFET的栅极均连接该列对应的第二位线。
需要说明的是，结构一中的一列bit单元相当于结构二中的一行bit单元，结构一中的一行bit单元相当于结构二中的一列bit单元，因此结构一和结构二实质上是相同的。本申请实施例针对这两种结构展开描述，可以理解的是，即使仅以结构一为例进行描述，本领域技术人员可参照结构一的相关描述得到结构二的CAM以及利用该CAM实现数据处理的方法。
在一种可能的设计中，针对结构一，也即CAM的一列bit单元中存储的数据组成一个表项，则同一列bit单元分别对应同一第一背栅线和同一第二背栅线；位于同一列的每个bit单元中的第一FeFET的背栅极均连接该列对应的第一背栅线；位于同一列的每个bit单元中的第二FeFET的背栅极均连接该列对应的第二背栅线。针对结构二，也即CAM的一行bit单元中存储的数据组成一个表项，则同一行bit单元分别对应同一第一背栅线和同一第二背栅线；位于同一行的每个bit单元中的第一FeFET的背栅极均连接该行对应的第一背栅线；位于同一行的每个bit单元中的第二FeFET的背栅极均连接该行对应的第二背栅线。
本申请实施例提供的CAM中，每个bit单元中仅包括2个FeFET晶体管，与现有技术中的每个bit单元包括16个晶体管相比，本申请实施例提供的CAM的面积大大减少进而能够减少CAM的功耗。
第二方面，提供一种数据处理方法，应用于第一方面及第一方面任意一种实现方式所述的CAM，该方法包括：
针对结构一所示的CAM，也即若CAM的一列bit单元中存储的数据组成一个表项，则设置每个bit单元中的第一FeFET和/或第二FeFET始终断开。分别设置所述CAM中的匹配线连接的第一FeFET的漏极的电压为预设电压，不同匹配线对应的预设电压相同或不同。分别通过第一位线输入匹配值，通过第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值。若存在目标列的匹配线的输出电压保持为所述目标列对应的预设电压，则确定所述目标列的bit单元中存储的数据组成的表项为匹配表项。
针对结构二所示的CAM，也即若所述CAM的一行bit单元中存储的数据组成一个表项，则设置每个bit单元中的第一FeFET和/或第二FeFET始终断开。分别设置所述CAM中的匹配线连接的第一FeFET的漏极的电压为预设电压，不同匹配线对应的预设电压相同或不同。分别通过第一位线输入匹配值，通过第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值。若存在目标行的匹配线的输出电压保持为所述目标行对应的所述预设电压，则确定该目标行的bit单元中存储的数据组成的表项为匹配表项。
在一种可能的设计中，无论是结构一所示的CAM还是结构二所示的CAM，若CAM中的FeFET包括栅极，不包括背栅极，则可通过以下方式设置每个bit单元中的第一FeFET和/ 或第二FeFET始终断开：设置每个bit单元中与第一位线连接的第一FeFET和/或与第二位线连接的第二FeFET的栅极电压位于第一电压范围，以使得所述第一FeFET和/或第二FeFET始终断开；其中，当FeFET的栅极的电压位于第一电压范围时，FeFET断开。
相应的，分别通过第一位线输入匹配值，通过第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值，可具体实现为以下方式：分别设置第一位线连接的第一FeFET的栅极的电压为第一电压，设置第二位线连接的第二FeFET的栅极的电压为第二电压以通过所述第一位线输入匹配值，通过所述第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值。
在一种可能的设计中，无论是结构一所示的CAM还是结构二所示的CAM，若所述FeFET包括栅极和背栅极，则可通过以下方式设置每个bit单元中的第一FeFET和/或第二FeFET始终断开：设置每个bit单元中与第一位线连接的第一FeFET的栅极和背栅极的电压差位于第一电压范围，和/或，设置每个bit单元中与第二位线连接的第二FeFET的栅极和背栅极的电压差位于第一电压范围，以使得所述第一FeFET和/或第二FeFET始终断开；其中，当FeFET的栅极和背栅极的电压差位于第一电压范围时，所述FeFET断开。
相应的，分别通过第一位线输入匹配值，通过第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值，可具体实现为以下方式：分别设置第一位线连接的第一FeFET的栅极和背栅极的电压差为第一电压，设置第二位线连接的第二FeFET的栅极和背栅极的电压差为第二电压以通过所述第一位线输入匹配值，通过所述第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值。
示例性的，若通过所述第一位线输入匹配值，则当所述匹配值为0时，所述第一电压位于第二电压范围，所述第二电压位于第三电压范围；当所述匹配值为1时，所述第一电压位于第三电压范围，所述第二电压位于第二电压范围。若通过所述第二位线输入匹配值，则当所述匹配值为0时，所述第一电压位于第三电压范围，所述第二电压位于第二电压范围；当所述匹配值为1时，所述第一电压位于第二电压范围，所述第二电压位于第三电压范围。
其中，若FeFET包含栅极，不包含背栅极，则当栅极的电压位于第二电压范围时，所述FeFET中输入匹配值以进行匹配，当栅极的电压位于第三电压范围时，FeFET始终导通。或者，若FeFET包含栅极和背栅极，则当栅极和背栅极的电压差位于第二电压范围时，FeFET中输入匹配值以进行匹配，当栅极和背栅极的电压差位于第三电压范围时，FeFET始终导通。
在一种可能的设计中，若存在至少两个匹配表项，则将存储地址最小的匹配表项作为匹配结果输出。
或者，针对结构一所示的CAM，也即当CAM的一列bit单元中存储的数据组成一个表项时，若存在至少两个匹配表项，则将列号最小的目标列的bit单元中存储的数据组成的表项作为匹配结果输出。
或者，针对结构二所示的CAM，也即当CAM的一行bit单元中存储的数据组成一个表项时，若存在至少两个匹配表项，则将行号最小的目标行的bit单元中存储的数据组成的 表项作为匹配结果输出。
本申请实施例提供了一种利用第一方面及其任意一种实现方式中所述CAM实现数据匹配的方法，该CAM的每个bit单元仅包含两个FeFET晶体管。在该方法中，通过与栅极连接的位线输入匹配值，通过与漏极连接的匹配线输出匹配结果，相比于现有技术中的匹配方法，由于CAM仅包含两个FeFET晶体管，其尺寸较小，因此能够减少匹配功耗。
在一种可能的设计中，本申请实施例还提供了一种在CAM中写入数据的方法，具体为：当表项的匹配方式为精确匹配或掩码匹配且bit单元的掩码为1时，在所述bit单元中写入数据时，分别在第一FeFET和第二FeFET中写入不同值。当表项的匹配方式为掩码匹配且bit单元的掩码为0时，在所述bit单元中写入数据时，在所述第一FeFET和第二FeFET中均写入0。
在一种可能的设计中，所述FeFET包括栅极和背栅极，则在所述bit单元中写入数据时，可通过以下方式分别在第一FeFET和第二FeFET中写入不同值：设置第一位线连接的第一FeFET的栅极和背栅极的电压差位于第四电压范围，设置第二位线连接的第二FeFET的栅极和背栅极的电压差位于第五电压范围以使得第一FeFET和第二FeFET写入不同值；其中，所述第四电压范围和第五电压范围不同。同理，可通过以下方式在所述第一FeFET和第二FeFET中均写入0：设置第一位线连接的第一FeFET的栅极和背栅极的电压差、第二位线连接的第二FeFET的栅极和背栅极的电压差位于相同的电压范围以使得写入所述第一FeFET和第二FeFET的值都为0。
在一种可能的设计中，所述FeFET包括栅极，不包括背栅极，则可通过以下方式在第一FeFET和第二FeFET中写入不同值：设置第一位线连接的第一FeFET的栅极的电压位于第四电压范围，第二位线连接的第二FeFET的栅极的电压位于第五电压范围以使得第一FeFET和第二FeFET写入不同值；其中，所述第四电压范围和第五电压范围不同。可通过以下方式在所述第一FeFET和第二FeFET中均写入0：设置第一位线连接的第一FeFET的栅极和第二位线连接的第二FeFET的栅极的电压位于相同的电压范围以使得写入所述第一FeFET和第二FeFET的值都为0。
在一种可能的设计中，本申请实施例还提供了一种在CAM中具体某个bit单元中写入数据的方法。
其中，若FeFET包括栅极和背栅极，则针对结构一所示的CAM，当CAM的一列bit单元中存储的数据组成一个表项时，则当在位于第X行Y列的bit单元写入数据时，设置第X行的第一位线连接的第一FeFET的栅极的电压为第一写入电压，第二位线连接的第二FeFET的栅极的电压为第二写入电压；设置其余行的第一位线连接的第一FeFET的栅极的电压为第三写入电压，第二位线连接的第二FeFET的栅极的电压为第四写入电压。设置第Y列的第一背栅线连接的第一FeFET的背栅极的电压为第五写入电压，第二背栅线连接的第二FeFET的背栅极的电压为第六写入电压；设置其余列的第一背栅线连接的第一FeFET的背栅极的电压为第七写入电压，第二背栅线连接的第二FeFET的背栅极的电压为第八写入电压。
若FeFET包括栅极和背栅极，则针对结构二所示的CAM，也即当CAM的一行bit单元中存储的数据组成一个表项时，则当在位于第X行Y列的bit单元写入数据时，设置第Y列的第一位线连接的第一FeFET的栅极的电压为第一写入电压，第二位线连接的第二FeFET 的栅极的电压为第二写入电压；设置其余列的第一位线连接的第一FeFET的栅极的电压为第三写入电压，第二位线连接的第二FeFET的栅极的电压为第四写入电压。设置第X行的第一背栅线连接的第一FeFET的背栅极的电压为第五写入电压，第二背栅线连接的第二FeFET的背栅极的电压为第六写入电压；设置其余行的第一背栅线连接的第一FeFET的背栅极的电压为第七写入电压，第二背栅线连接的第二FeFET的背栅极的电压为第八写入电压。
示例性的，所述第一写入电压和所述第五写入电压之差在第四电压范围内、所述第二写入电压和所述第六写入电压之差在第五电压范围内以使得仅在第X行Y列的bit单元中写入数据；所述第三写入电压和所述第五写入电压之差、所述第四写入电压和所述第六写入电压之差、所述第三写入电压和所述第七写入电压之差、所述第四写入电压和所述第八写入电压之差、所述第一写入电压和所述第七写入电压之差、所述第二写入电压和所述第八写入电压之差在第六电压范围内以使得不在其余bit单元中写入数据。
若所述FeFET包括栅极，不包括背栅极，则针对结构一所示的CAM，当CAM的一列bit单元中存储的数据组成一个表项时，每个bit单元中的第一FeFET的栅极与连接的第一位线之间设置有开关，每个bit单元中的第二FeFET的栅极与连接的第二位线之间设置有开关。则当在CAM中位于第X行Y列的bit单元中写入数据时，设置所述第X行Y列的bit单元中的第一FeFET的栅极与连接的第一位线之间的开关打开，第二FeFET的栅极与连接的第二位线之间的开关打开。设置第X行的其余bit单元中的第一FeFET的栅极与连接的第一位线之间的开关关闭，第二FeFET的栅极与连接的第二位线之间的开关关闭。设置第X行的第一位线连接的第一FeFET的栅极的电压为第一写入电压，第二位线连接的第二FeFET的栅极的电压为第二写入电压；设置其余行的第一位线连接的第一FeFET的栅极的电压为第三写入电压，第二位线连接的第二FeFET的栅极的电压为第四写入电压。其中，所述第一写入电压在第四电压范围内，第二写入电压在第五电压范围内以仅在所述第X行Y列的bit单元中写入数据；所述第三写入电压和第四写入电压在第六电压范围内以不在除所述第X行Y列的bit单元以外的其余bit单元中写入数据。
若所述FeFET包括栅极，不包括背栅极，则针对结构二所示的CAM，当CAM的一行bit单元中存储的数据组成一个表项时，每个bit单元中的第一FeFET的栅极与连接的第一位线之间设置有开关，每个bit单元中的第二FeFET的栅极与连接的第二位线之间设置有开关。则当在CAM中位于第X行Y列的bit单元中写入数据时，设置所述第X行Y列的bit单元中的第一FeFET的栅极与连接的第一位线之间的开关打开，第二FeFET的栅极与连接的第二位线之间的开关打开。设置第Y列的其余bit单元中的第一FeFET的栅极与连接的第一位线之间的开关关闭，第二FeFET的栅极与连接的第二位线之间的开关关闭。设置第Y列的第一位线连接的第一FeFET的栅极的电压为第一写入电压，第二位线连接的第二FeFET的栅极的电压为第二写入电压。设置其余列的第一位线连接的第一FeFET的栅极的电压为第三写入电压，第二位线连接的第二FeFET的栅极的电压为第四写入电压。其中，所述第一写入电压在第四电压范围内，第二写入电压在第五电压范围内以仅在所述第X行Y列的bit单元中写入数据；所述第三写入电压和第四写入电压在第六电压范围内以不在除所述第X行Y列的bit单元以外的其余bit单元中写入数据。
本申请实施例提供了一种利用第一方面及其任意一种实现方式中所述CAM在CAM中写 入数据的方法，该CAM的每个bit单元仅包含两个FeFET晶体管。在该方法中，通过与栅极连接的位线写入数值，相比于现有技术中的数据写入方法，由于CAM仅包含两个FeFET晶体管，其尺寸较小，因此能够减少写数据的功耗。
第三方面，提供一种数据处理方法，应用于第一方面以及第一方面任意一种实现方式所述的CAM，所述方法包括：当表项的匹配方式为精确匹配或掩码匹配且bit单元的掩码为1时，在所述bit单元中写入数据时，分别在第一FeFET和第二FeFET中写入不同值。当表项的匹配方式为掩码匹配且bit单元的掩码为0时，在所述bit单元中写入数据时，在所述第一FeFET和第二FeFET中均写入0。
在一种可能的设计中，所述FeFET包括栅极和背栅极，则在所述bit单元中写入数据时，可通过以下方式分别在第一FeFET和第二FeFET中写入不同值：设置第一位线连接的第一FeFET的栅极和背栅极的电压差位于第四电压范围，设置第二位线连接的第二FeFET的栅极和背栅极的电压差位于第五电压范围以使得第一FeFET和第二FeFET写入不同值；其中，所述第四电压范围和第五电压范围不同。同理，可通过以下方式在所述第一FeFET和第二FeFET中均写入0：设置第一位线连接的第一FeFET的栅极和背栅极的电压差、第二位线连接的第二FeFET的栅极和背栅极的电压差位于相同的电压范围以使得写入所述第一FeFET和第二FeFET的值都为0。
在一种可能的设计中，所述FeFET包括栅极，不包括背栅极。则可通过以下方式在第一FeFET和第二FeFET中写入不同值：设置第一位线连接的第一FeFET的栅极的电压位于第四电压范围，第二位线连接的第二FeFET的栅极的电压位于第五电压范围以使得第一FeFET和第二FeFET写入不同值；其中，所述第四电压范围和第五电压范围不同。可通过以下方式在所述第一FeFET和第二FeFET中均写入0：设置第一位线连接的第一FeFET的栅极和第二位线连接的第二FeFET的栅极的电压位于相同的电压范围以使得写入所述第一FeFET和第二FeFET的值都为0。
在一种可能的设计中，本申请实施例还提供了一种在CAM中具体某个bit单元中写入数据的方法。
其中，若FeFET包括栅极和背栅极，则针对结构一所示的CAM，当CAM的一列bit单元中存储的数据组成一个表项时，则当在位于第X行Y列的bit单元写入数据时，设置第X行的第一位线连接的第一FeFET的栅极的电压为第一写入电压，第二位线连接的第二FeFET的栅极的电压为第二写入电压；设置其余行的第一位线连接的第一FeFET的栅极的电压为第三写入电压，第二位线连接的第二FeFET的栅极的电压为第四写入电压。设置第Y列的第一背栅线连接的第一FeFET的背栅极的电压为第五写入电压，第二背栅线连接的第二FeFET的背栅极的电压为第六写入电压；设置其余列的第一背栅线连接的第一FeFET的背栅极的电压为第七写入电压，第二背栅线连接的第二FeFET的背栅极的电压为第八写入电压。
若FeFET包括栅极和背栅极，则针对结构二所示的CAM，也即当CAM的一行bit单元中存储的数据组成一个表项时，则当在位于第X行Y列的bit单元写入数据时，设置第Y列的第一位线连接的第一FeFET的栅极的电压为第一写入电压，第二位线连接的第二FeFET的栅极的电压为第二写入电压；设置其余列的第一位线连接的第一FeFET的栅极的电压为第三写入电压，第二位线连接的第二FeFET的栅极的电压为第四写入电压。设置第X行的 第一背栅线连接的第一FeFET的背栅极的电压为第五写入电压，第二背栅线连接的第二FeFET的背栅极的电压为第六写入电压；设置其余行的第一背栅线连接的第一FeFET的背栅极的电压为第七写入电压，第二背栅线连接的第二FeFET的背栅极的电压为第八写入电压。
示例性的，所述第一写入电压和所述第五写入电压之差在第四电压范围内、所述第二写入电压和所述第六写入电压之差在第五电压范围内以使得仅在第X行Y列的bit单元中写入数据；所述第三写入电压和所述第五写入电压之差、所述第四写入电压和所述第六写入电压之差、所述第三写入电压和所述第七写入电压之差、所述第四写入电压和所述第八写入电压之差、所述第一写入电压和所述第七写入电压之差、所述第二写入电压和所述第八写入电压之差在第六电压范围内以使得不在其余bit单元中写入数据。
若所述FeFET包括栅极，不包括背栅极，则针对结构一所示的CAM，当CAM的一列bit单元中存储的数据组成一个表项时，每个bit单元中的第一FeFET的栅极与连接的第一位线之间设置有开关，每个bit单元中的第二FeFET的栅极与连接的第二位线之间设置有开关。则当在CAM中位于第X行Y列的bit单元中写入数据时，设置所述第X行Y列的bit单元中的第一FeFET的栅极与连接的第一位线之间的开关打开，第二FeFET的栅极与连接的第二位线之间的开关打开。设置第X行的其余bit单元中的第一FeFET的栅极与连接的第一位线之间的开关关闭，第二FeFET的栅极与连接的第二位线之间的开关关闭。设置第X行的第一位线连接的第一FeFET的栅极的电压为第一写入电压，第二位线连接的第二FeFET的栅极的电压为第二写入电压；设置其余行的第一位线连接的第一FeFET的栅极的电压为第三写入电压，第二位线连接的第二FeFET的栅极的电压为第四写入电压。其中，所述第一写入电压在第四电压范围内，第二写入电压在第五电压范围内以仅在所述第X行Y列的bit单元中写入数据；所述第三写入电压和第四写入电压在第六电压范围内以不在除所述第X行Y列的bit单元以外的其余bit单元中写入数据。
若所述FeFET包括栅极，不包括背栅极，则针对结构二所示的CAM，当CAM的一行bit单元中存储的数据组成一个表项时，每个bit单元中的第一FeFET的栅极与连接的第一位线之间设置有开关，每个bit单元中的第二FeFET的栅极与连接的第二位线之间设置有开关。则当在CAM中位于第X行Y列的bit单元中写入数据时，设置所述第X行Y列的bit单元中的第一FeFET的栅极与连接的第一位线之间的开关打开，第二FeFET的栅极与连接的第二位线之间的开关打开。设置第Y列的其余bit单元中的第一FeFET的栅极与连接的第一位线之间的开关关闭，第二FeFET的栅极与连接的第二位线之间的开关关闭。设置第Y列的第一位线连接的第一FeFET的栅极的电压为第一写入电压，第二位线连接的第二FeFET的栅极的电压为第二写入电压。设置其余列的第一位线连接的第一FeFET的栅极的电压为第三写入电压，第二位线连接的第二FeFET的栅极的电压为第四写入电压。其中，所述第一写入电压在第四电压范围内，第二写入电压在第五电压范围内以仅在所述第X行Y列的bit单元中写入数据；所述第三写入电压和第四写入电压在第六电压范围内以不在除所述第X行Y列的bit单元以外的其余bit单元中写入数据。
本申请实施例提供了一种利用第一方面及其任意一种实现方式中所述CAM在CAM中写入数据的方法，该CAM的每个bit单元仅包含两个FeFET晶体管。在该方法中，通过与栅极连接的位线写入数值，相比于现有技术中的数据写入方法，由于CAM仅包含两个FeFET 晶体管，其尺寸较小，因此能够减少写数据的功耗。
在一种可能的设计中，本申请实施例还提供了一种利用结构一或结构二所示的CAM进行数据匹配的方法。其中，针对结构一所示的CAM，也即若CAM的一列位bit单元中存储的数据组成一个表项，则设置每个bit单元中的第一FeFET和/或第二FeFET始终断开。分别设置所述CAM中的匹配线连接的第一FeFET的漏极的电压为预设电压，不同匹配线对应的预设电压相同或不同。分别通过第一位线输入匹配值，通过第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值。若存在目标列的匹配线的输出电压保持为所述目标列对应的预设电压，则确定所述目标列的bit单元中存储的数据组成的表项为匹配表项。
针对结构二所示的CAM，也即若所述CAM的一行bit单元中存储的数据组成一个表项，则设置每个bit单元中的第一FeFET和/或第二FeFET始终断开。分别设置所述CAM中的匹配线连接的第一FeFET的漏极的电压为预设电压，不同匹配线对应的预设电压相同或不同。分别通过第一位线输入匹配值，通过第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值。若存在目标行的匹配线的输出电压保持为所述目标行对应的所述预设电压，则确定该目标行的bit单元中存储的数据组成的表项为匹配表项。
在一种可能的设计中，无论是结构一所示的CAM还是结构二所示的CAM，若CAM中的FeFET包括栅极，不包括背栅极，则可通过以下方式设置每个bit单元中的第一FeFET和/或第二FeFET始终断开：设置每个bit单元中与第一位线连接的第一FeFET和/或与第二位线连接的第二FeFET的栅极电压位于第一电压范围，以使得所述第一FeFET和/或第二FeFET始终断开；其中，当FeFET的栅极的电压位于第一电压范围时，FeFET断开。
相应的，分别通过第一位线输入匹配值，通过第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值，可具体实现为以下方式：分别设置第一位线连接的第一FeFET的栅极的电压为第一电压，设置第二位线连接的第二FeFET的栅极的电压为第二电压以通过所述第一位线输入匹配值，通过所述第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值。
在一种可能的设计中，无论是结构一所示的CAM还是结构二所示的CAM，若所述FeFET包括栅极和背栅极，则可通过以下方式设置每个bit单元中的第一FeFET和/或第二FeFET始终断开：设置每个bit单元中与第一位线连接的第一FeFET的栅极和背栅极的电压差位于第一电压范围，和/或，设置每个bit单元中与第二位线连接的第二FeFET的栅极和背栅极的电压差位于第一电压范围，以使得所述第一FeFET和/或第二FeFET始终断开；其中，当FeFET的栅极和背栅极的电压差位于第一电压范围时，所述FeFET断开。
相应的，分别通过第一位线输入匹配值，通过第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值，可具体实现为以下方式：分别设置第一位线连接的第一FeFET的栅极和背栅极的电压差为第一电压，设置第二位线连接的第二FeFET的栅极和背栅极的电压差为第二电压以通过所述第一位线输入匹配值，通过所述第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值。
示例性的，若通过所述第一位线输入匹配值，则当所述匹配值为0时，所述第一电压位于第二电压范围，所述第二电压位于第三电压范围；当所述匹配值为1时，所述第一电压位于第三电压范围，所述第二电压位于第二电压范围。若通过所述第二位线输入匹配值，则当所述匹配值为0时，所述第一电压位于第三电压范围，所述第二电压位于第二电压范围；当所述匹配值为1时，所述第一电压位于第二电压范围，所述第二电压位于第三电压范围。
其中，若FeFET包含栅极，不包含背栅极，则当栅极的电压位于第二电压范围时，所述FeFET中输入匹配值以进行匹配，当栅极的电压位于第三电压范围时，FeFET始终导通。或者，若FeFET包含栅极和背栅极，则当栅极和背栅极的电压差位于第二电压范围时，FeFET中输入匹配值以进行匹配，当栅极和背栅极的电压差位于第三电压范围时，FeFET始终导通。
在一种可能的设计中，若存在至少两个匹配表项，则将存储地址最小的匹配表项作为匹配结果输出。
或者，针对结构一所示的CAM，也即当CAM的一列bit单元中存储的数据组成一个表项时，若存在至少两个匹配表项，则将列号最小的目标列的bit单元中存储的数据组成的表项作为匹配结果输出。
或者，针对结构二所示的CAM，也即当CAM的一行bit单元中存储的数据组成一个表项时，若存在至少两个匹配表项，则将行号最小的目标行的bit单元中存储的数据组成的表项作为匹配结果输出。
本申请实施例提供了一种利用第一方面及其任意一种实现方式中所述CAM实现数据匹配的方法，该CAM的每个bit单元仅包含两个FeFET晶体管。在该方法中，通过与栅极连接的位线输入匹配值，通过与漏极连接的匹配线输出匹配结果，相比于现有技术中的匹配方法，由于CAM仅包含两个FeFET晶体管，其尺寸较小，因此能够减少匹配功耗。
第四方面，本申请实施例提供一种网络设备，包括处理器、通信接口、第一存储器、第二存储器和通信总线；其中，所述处理器、通信接口、第一存储器和第二存储器通过所述通信总线互相通信；所述第一存储器中存储有计算机可执行程序代码，所述第二存储器为第一方面以及第一方面任意一种实现方式所述的CAM，所述处理器用于执行所述第一存储器中存储的所述计算机可执行程序代码以控制所述第二存储器执行第二方面及其任意一种实现方式所述的数据处理方法。或者，所述处理器用于执行所述第一存储器中存储的所述计算机可执行程序代码以控制所述第二存储器执行第三方面及其任意一种实现方式所述的数据处理方法。
附图说明
图1为本申请实施例提供的一种FeFET的结构示意图；
图2为本申请实施例提供的一种CAM的结构示意图；
图3为本申请实施例提供的一种在CAM中查找数据的方法流程示意图；
图4为本申请实施例提供的另一种在CAM中查找数据的方法流程示意图；
图5为本申请实施例提供的一种在CAM中写入数据的方法流程示意图；
图6为本申请实施例提供的一种在CAM中某个bit单元写入数据的方法流程示意图；
图7为本申请实施例提供的另一种在CAM中某个bit单元写入数据的方法流程示意图；
图8为本申请实施例提供的又一种在CAM中某个bit单元写入数据的方法流程示意图；
图9为本申请实施例提供的再一种在CAM中某个bit单元写入数据的方法流程示意图；
图10为本申请实施例提供的一种网络设备的结构示意图。
具体实施方式
在一些电介质晶体中，晶胞的结构使正负电荷中心不重合而出现电偶极矩，产生不等于零的电极化强度，使晶体具有自发极化，且电偶极矩方向可以因外电场而改变，呈现出类似于铁磁体的特点，晶体的这种性质叫铁电性。
铁电场效应晶体管(ferro-electric field effect transistor，FeFET)是一种具有铁电特性的场效应晶体管，其主要原理是在场效应晶体管的栅极绝缘体中加入有铁电特性的物质，使FeFET拥有滞回曲线特性，将FeFET的阈值电压分成两个稳定的状态，因此，二进制状态可以存储在FeFET中。如果FeFET的栅极电压高于阈值电压，则FeFET导通；如果FeFET的栅极电压低于阈值电压，则FeFET关闭。此外，即使FeFET的栅极电压为0，仍保存数据。
CAM是以内容进行寻址的存储器，是一种特殊的存储阵列，其工作机制为将一个输入数据项与存储在CAM中的所有数据项自动同时进行比较，判别该输入数据项与CAM中存储的数据项是否相匹配，并输出该数据项对应的匹配信息。CAM为交换机、路由器等网络设备的重要组成部件。一种典型的CAM为TCAM，TCAM是从CAM的基础上发展而来的。一般的CAM存储器中每个bit位的状态只有两个，“0”或“1”，而TCAM中每个bit位有三种状态，除掉“0”和“1”外，还有一个“don’t care”状态，所以称为“三态”，它是通过掩码来实现的，正是TCAM的这个第三种状态特征使其既能进行精确匹配查找，又能进行模糊匹配查找。
本申请实施例提供一种内容寻址存储器，该内容寻址存储器的每个bit单元由两个FeFET串联组成。示例性的，如图1所示，第一FeFET(图1中以M1示出)的漏极连接ML，第一FeFET的源极连接第二FeFET(图1中以M2示出)的漏极，第二FeFET的源极接地。第一FeFET的栅极连接第一位线，第二FeFET的栅极连接第二位线。
可选的，所述FeFET还包括背栅极，则相应的，第一FeFET的背栅极连接第一背栅线，第二FeFET的背栅极连接第二背栅线。
每个bit单元为基于串联的这2个FeFET的异或非门。当执行查找操作时，位线用于输入匹配值。每个bit单元能够实现该bit单元存储的数据和匹配值的异或非逻辑运算(或者描述为比较运算)。
示例性的，bit单元的M1中存储有待匹配的值，M2中存储有待匹配值的相反值。下表表一为bit单元的真值表的一种可能实现方式。
表一
Figure PCTCN2019111238-appb-000001
Figure PCTCN2019111238-appb-000002
结合该表一，前四行为精确匹配，只有当M1的值和key值不同时，M1和M2才会同时打开，key值和M1的匹配结果为不匹配。其他情况下，当M1中存储的值和key值相同时，M1和M2中至少一个断开，key值和M1的匹配结果为匹配。第五行为掩码匹配，上述表一中以该bit单元的掩码为0为例说明，掩码为0表示该bit不参与匹配，则M1和M2都存储0，无论输入的key值为何值，M1和M2中至少一个是断开的，则M1中存储的值和key值相同，key值和M1的匹配结果为匹配。
当在内容寻址存储器的一行bit单元或一列bit单元中写入数据时，位线用于输入待写入数据。示例性的，当表项的匹配方式为精确匹配或掩码匹配且bit单元的掩码为1时，在该bit单元中写入数据时，分别通过第一位线和第二位线在第一FeFET和第二FeFET中写入不同值，其中，第一FeFET写入待写入数据，第二FeFET写入待写入数据的相反值或者第二FeFET写入待写入数据，第一FeFET写入待写入数据的相反值。当表项的匹配方式为掩码匹配且bit单元的掩码为0时，在该bit单元中写入数据时，分别通过第一位线和第二位线在第一FeFET和第二FeFET中均写入0。
基于图1所示的bit单元，本申请实施例提供一种CAM，该CAM包括：M行N列bit单元，所述M和N均为大于等于1的正整数。
每个bit单元的结构参见图1所示的bit单元，也即每个bit单元包括第一FeFET和第二FeFET，该第一FeFET的源极连接第二FeFET的漏极，该第二FeFET的源极接地。
在一种实现方式中，所述CAM的一列bit单元中存储的数据组成一个表项。在该实现方式中，同一列bit单元对应同一匹配线，位于同一列的每个bit单元中的第一FeFET的漏极均连接该列对应的匹配线。同一行bit单元对应同一第一位线和同一第二位线，位于同一行的每个bit单元中的第一FeFET的栅极均连接该行对应的第一位线，位于同一行的每个bit单元中的第二FeFET的栅极均连接该行对应的第二位线。可选的，同一列bit单元分别对应同一第一背栅线和同一第二背栅线；位于同一列的每个bit单元中的第一FeFET的背栅极均连接该列对应的第一背栅线；位于同一列的每个bit单元中的第二FeFET的背栅极均连接该列对应的第二背栅线。
示例性的，图2为CAM的一种可能实现方式。该CAM包括：4行4列bit单元，一列bit单元中存储的数据组成一个表项，每个bit单元包括M1和M2两个FeFET。那么，同一列的每个bit单元中的M1的漏极均连接该列对应的匹配线。同一行bit单元中的所有M1的栅极均连接该行对应的第一位线，同一行bit单元中的所有M2的栅极均连接该行对应的第二位线。此外，同一列的每个bit单元中的M1的背栅极均连接该列对应的第一背栅线，同一列的每个bit单元中的M2的背栅极均连接该列对应的第二背栅线。
在上述实现方式中，所述CAM的一列bit单元中存储的数据组成一个表项。在另一种实现方式中，所述CAM的一行bit单元中存储的数据组成一个表项。那么，在该实现方式中，同一行bit单元对应同一匹配线；位于同一行的每个bit单元中的第一FeFET的漏极均连接该行对应的匹配线；同一列bit单元对应同一第一位线和同一第二位线，位于同一列的每个bit单元中的第一FeFET的栅极均连接该列对应的第一位线，位于同一列的每个bit单元中的第二FeFET的栅极均连接该列对应的第二位线。
同理，可选的，同一行bit单元分别对应同一第一背栅线和同一第二背栅线；位于同一行的每个bit单元中的第一FeFET的背栅极均连接该行对应的第一背栅线；位于同一行的每个bit单元中的第二FeFET的背栅极均连接该行对应的第二背栅线。
本申请实施例提供的CAM中，每个bit单元中仅包括2个FeFET晶体管，与现有技术中的每个bit单元包括16个晶体管相比，本申请实施例提供的CAM的面积大大减少进而能够减少CAM的功耗。
本申请实施例还提供基于本申请实施例提供的上述CAM的数据处理方法，该数据处理方法具体包括：在CAM中写入数据和在CAM中查找数据(或者描述为从CAM中匹配数据)。通常，CAM中用于存入路由表或ACL表等表的表项数据。一个路由表或ACL表由多个表项组成。因此，本申请实施例所描述的在CAM中写入数据具体为在CAM中写入路由表或ACL表中各个表项的数据。相应的，从CAM中匹配数据具体为在CAM中查找某个路由表或ACL表的某个表项的数据。
在详细描述本申请实施例提供的数据处理方法之前，先介绍几个与本申请实施例提供的数据处理方法相关的术语。
匹配涉及到的电压：第一电压范围、第二电压范围、第三电压范围。如果FeFET的栅极输入的电压位于第一电压范围，则该FeFET始终断开。如果FeFET的栅极输入电压位于第二电压范围，则在FeFET中写入1时该FeFET导通，在FeFET中写入0时该FeFET断开。如果FeFET的栅极输入的电压位于第三电压范围，则该FeFET始终导通。示例性的，第一电压范围为-2V至-0.6V，第二电压范围为0V左右的电压，例如：-0.5V至0.5V，第三电压范围为0.6V至1.6V。
写入涉及到的电压：写入0的电压范围和写入1的电压范围。该写入0的电压范围和写入1的电压范围为不同的电压范围。其中，当在FeFET中写入0时，设置该FeFET的栅极电压位于写入0的电压范围。当在FeFET中写入1时，设置该FeFET的栅极电压位于写入1的电压范围。此外，写入0的电压范围和写入1的电压范围的具体取值由FeFET器件的属性决定，通常，写入0的电压和写入1的电压正负相反，但不限定其绝对值之间的大小关系。具体的，写入0的电压范围通常为小于某个负值电压，不限定其下限；写入1的电压范围通常为大于某个正值电压，不限定其上限；示例性的，写入0的电压范围为-3V至-2V，写入1的电压范围为2V至3V。
下文分别描述这两种数据处理方法。
一、在CAM中查找数据：
参考图3，若CAM的一列bit单元中存储的数据组成一个表项，则在CAM中查找数据可具体实现为以下步骤S301至S304：
S301、设置每个bit单元中的第一FeFET和/或第二FeFET始终断开。
可选的，每个FeFET包括栅极不包括背栅极，则在本步骤的一种实现方式中，分别设置每个bit单元中与第一位线连接的第一FeFET和/或与第二位线连接的第二FeFET的栅极电压位于第一电压范围。其中，当FeFET栅极电压为位于第一电压范围时，FeFET断开。
可选的，每个FeFET包括栅极和背栅极，则在本步骤的一种实现方式中，分别设置每个bit单元中与第一位线连接的第一FeFET的栅极和背栅极的电压差，和/或，与第二位线连接的第二FeFET的栅极和背栅极的电压差位于第一电压范围。其中，当FeFET的栅极 和背栅极的电压差位于第一电压范围时，FeFET断开。
S302、分别设置CAM中的匹配线连接的第一FeFET的漏极的电压为预设电压。
其中，不同匹配线对应的预设电压可能相同也可能不同。
可选的，所述预设电压为任意电压。在一种可能的实现中，给匹配线预充电至所述预设电压。
S303、分别通过第一位线输入匹配值，通过第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值。
可选的，每个FeFET包括栅极不包括背栅极，则在本步骤的一种实现方式中，分别设置第一位线连接的第一FeFET的栅极的电压为第一电压，设置第二位线连接的第二FeFET的栅极的电压为第二电压以通过所述第一位线输入匹配值，通过所述第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值。
需要说明的是，不同第一位线连接的栅极电压可能相同也可能不同，也即不同第一位线对应的第一电压可能相同也可能不同，不同第二位线连接的栅极电压可能相同也可能不同，也即不同第二位线对应的第二电压可能相同也可能不同。
可选的，每个FeFET包括栅极和背栅极，则在本步骤的一种实现方式中，分别设置第一位线连接的第一FeFET的栅极和背栅极的电压差为第一电压，设置第二位线连接的第二FeFET的栅极和背栅极的电压差为第二电压以通过所述第一位线输入匹配值，通过所述第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值。
需要说明的是，不同第一位线连接的第一FeFET的栅极和背栅极的电压差可能相同也可能不同，也即不同第一位线对应的第一电压可能相同也可能不同，不同第二位线连接的第二FeFET的栅极和背栅极的电压差可能相同也可能不同，也即不同第二位线对应的第二电压可能相同也可能不同。
示例性的，若通过所述第一位线输入匹配值，则当所述匹配值为0时，所述第一电压位于第二电压范围，所述第二电压位于第三电压范围；当所述匹配值为1时，所述第一电压位于第三电压范围，所述第二电压位于第二电压范围。若通过所述第二位线输入匹配值，则当所述匹配值为0时，所述第一电压位于第三电压范围，所述第二电压位于第二电压范围；当所述匹配值为1时，所述第一电压位于第二电压范围，所述第二电压位于第三电压范围。
其中，若FeFET包含栅极，不包含背栅极，则当栅极的电压位于第二电压范围时，所述FeFET中输入匹配值以进行匹配，当栅极的电压位于第三电压范围时，所述FeFET始终导通；或者，若FeFET包含栅极和背栅极，则当栅极和背栅极的电压差位于第二电压范围时，所述FeFET中输入匹配值以进行匹配，当栅极和背栅极的电压差位于第三电压范围时，所述FeFET始终导通。
需要说明的是，本申请实施例不限定上述S301至S303的执行顺序。
S304、若存在目标列的匹配线的输出电压保持为所述目标列对应的预设电压，则确定所述目标列的bit单元中存储的数据组成的表项为匹配表项。
在该步骤中，若某列的匹配线的输出电压仍保持为S302中的预设电压，则确定该列 的bit单元中存储的数据组成的表项为匹配表项。如果某列的匹配线的输出电压泄露为0，则表明该列的所有bit单元中存在至少一个bit单元不匹配。
实际应用中，可能存在多个列的匹配线的输出电压均保持为预设电压，也即存在至少两个匹配表项。这种场景下，若存在至少两个匹配表项，则将存储地址最小的匹配表项作为匹配结果输出。或者，若存在至少两个匹配表项，则将列号最小的目标列的bit单元中存储的数据组成的表项作为匹配结果输出。
示例性的，结合图2所示的4行4列的CAM，一种可能的匹配结果如下表表二所示。
表二
Figure PCTCN2019111238-appb-000003
如表二，存在第2列表项和第3列表项这两列表项均为匹配表项，则取第2列表项为匹配表项。
同理，参考图4，若CAM的一行bit单元中存储的数据组成一个表项，则在CAM中查找数据可具体实现为以下步骤S401至S404：
S401、设置每个bit单元中第一FeFET和/或第二FeFET断开。
S402、分别设置所述CAM中的匹配线连接的第一FeFET的漏极电压为预设电压。
其中，不同匹配线对应的预设电压相同或不同。
S403、分别通过第一位线输入匹配值，通过所述第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值。
需要说明的是，本申请实施例不限定上述S401至S403的执行顺序。
S404、若存在目标行的匹配线的输出电压保持为所述目标行对应的预设电压，则确定所述目标行的bit单元中存储的数据组成的表项为匹配表项。
可选的，若存在至少两个匹配表项，则将存储地址最小的匹配表项作为匹配结果输出。
或者，若存在至少两个匹配表项，则将行号最小的目标行的bit单元中存储的数据组成的表项作为匹配结果输出。
需要说明的是，上述步骤S401至S404所描述的数据处理方法的具体实现可参考上述步骤S301至S304所描述的数据处理方法。其不同之处在于，S301至S304所描述的数据处理方法的应用场景为CAM中一列bit单元中存储的数据组成一个表项。S401至S404所描述的数据处理方法的应用场景为CAM中一行bit单元中存储的数据组成一个表项。
本申请实施例提供的在所述CAM中实现数据匹配的方法，该CAM的每个bit单元仅包 含两个FeFET晶体管。在该方法中，通过与栅极连接的位线输入匹配值，通过与漏极连接的匹配线输出匹配结果，相比于现有技术中的匹配方法，由于CAM仅包含两个FeFET晶体管，其尺寸较小，因此能够减少匹配功耗。
二、在CAM中写入数据：
实际应用中，一个数据表由多个表项组成，数据表的配置文件中存储有表项的匹配方式，同一个数据表中的所有表项的匹配方式相同。因此，在CAM中查表时根据该表的配置文件可确定该表项的匹配方式。表项的匹配方式包括：精确匹配和掩码匹配。其中，精确匹配是指当输入的匹配值和bit单元中存储的值相同时，则表示bit单元中存储的值和待匹配的值匹配，否则认为不匹配。掩码匹配是指根据bit单元的掩码值来确定bit单元中存储的值是否参与匹配。例如：若表项的匹配方式为掩码匹配且bit单元的掩码为1时，表示该bit单元存储的值参与匹配且当该bit单元存储的值和待匹配值相同时，表示匹配。若表项的匹配方式为掩码匹配且bit单元的掩码为0时，表示该bit单元存储的值不参与匹配。
参考图5，在CAM中写入数据的过程包括以下步骤S501和S502。
S501、当表项的匹配方式为精确匹配或掩码匹配且bit单元的掩码为1时，在bit单元中写入数据时，分别在第一FeFET和第二FeFET中写入不同值。
可选的，所述FeFET包括栅极和背栅极，相应的，在本步骤的一种实现方式中，设置第一位线连接的第一FeFET的栅极和背栅极的电压差位于第四电压范围，设置第二位线连接的第二FeFET的栅极和背栅极的电压差位于第五电压范围以使得第一FeFET和第二FeFET写入不同值。其中，所述第四电压范围和第五电压范围不同。
可选的，所述FeFET包括栅极，不包括背栅极，相应的，在本步骤的一种实现方式中，设置第一位线连接的第一FeFET的栅极的电压位于第四电压范围，第二位线连接的第二FeFET的栅极的电压位于第五电压范围以使得第一FeFET和第二FeFET写入不同值。其中，所述第四电压范围和第五电压范围不同。
需要说明的是，实际应用中对于包含背栅极的FeFET，一般背栅极接地，因此栅极和背栅极的电压差即为栅极的电压。
示例性的，当表项的匹配方式为精确匹配或掩码匹配且bit单元的掩码为1时，当在bit单元中写入1时，所述第四电压范围为写入1的电压范围，也即该电压范围用于在第一FeFET中写入1。第五电压范围为写入0的电压范围，也即该电压范围用于在第二FeFET中写入0。或者，所述第四电压范围为写入0的电压范围，也即该电压范围用于在第一FeFET中写入0，第五电压范围为写入0的电压范围，也即该电压范围用于在第二FeFET中写入1。
无论上述哪种实现方式，bit单元中的其中一个FeFET中写入1，另一个FeFET中写入0，bit单元的两个FeFET存在一个FeFET为主导FeFET，该bit单元中存储的数值具体由主导FeFET中存储的值决定。
S502、当表项的匹配方式为掩码匹配且bit单元的掩码为0时，在bit单元中写入数据时，在所述第一FeFET和第二FeFET中均写入0。
可选的，所述FeFET包括栅极和背栅极，相应的，在本步骤的一种实现方式中，设置第一位线连接的第一FeFET的栅极和背栅极的电压差、第二位线连接的第二FeFET的栅极 和背栅极的电压差位于相同的电压范围以使得写入所述第一FeFET和第二FeFET的值都为0。
可选的，所述FeFET仅包括栅极，不包括背栅极，相应的，在本步骤的一种实现方式中，设置第一位线连接的第一FeFET的栅极和第二位线连接的第二FeFET的栅极的电压位于相同的电压范围以使得写入所述第一FeFET和第二FeFET的值都为0。
其中，上述相同的电压范围为写入0的电压范围。
作为图5所示方法的一种具体实现，若FeFET包括栅极和背栅极，当所述CAM的一列bit单元中存储的数据组成一个表项时，则当在位于第X行Y列的bit单元写入数据时，需要设置第X行Y列的bit单元中包含的FeFET的栅极和背栅极的写入电压之差在一定范围内如前文所述的第四电压范围或第五电压范围内，其余行其余列的FeFET的栅极和背栅极的写入电压之差在另一范围(本申请实施例描述为第六电压范围)内以保证仅在第X行Y列的bit单元中写入数据。如图6所示，执行以下过程：
S601、设置第X行的第一位线连接的第一FeFET的栅极的电压为第一写入电压，第二位线连接的第二FeFET的栅极的电压为第二写入电压。
S602、设置其余行的第一位线连接的第一FeFET的栅极的电压为第三写入电压，第二位线连接的第二FeFET的栅极的电压为第四写入电压。
需要说明的是，不同行的第一位线连接的第一FeFET的栅极的电压可能相同可能不同，也即不同行对应的第三写入电压可能相同也可能不同。同理，不同行的第二位线连接的第二FeFET的栅极的电压可能相同也可能不同，也即不同行对应的第四写入电压可能相同也可能不同。
S603、设置第Y列的第一背栅线连接的第一FeFET的背栅极的电压为第五写入电压，第二背栅线连接的第二FeFET的背栅极的电压为第六写入电压。
示例性的，所述第五写入电压位于0V左右的电压范围，第六写入电压位于0V左右的电压范围，这两个电压范围可能相同也可能不同。例如：第五写入电压位于-0.5V至0.5V这一电压范围，第五写入电压位于-0.4V至0.4V这一电压范围。
S604、设置其余列的第一背栅线连接的第一FeFET的背栅极的电压为第七写入电压，第二背栅线连接的第二FeFET的背栅极的电压为第八写入电压。
需要说明的是，不同列的第一背栅线连接的第一FeFET的背栅极的电压可能相同也可能不同，也即不同列对应的第七写入电压可能相同也可能不同。同理，不同列的第二背栅线连接的第二FeFET的背栅极的电压可能相同也可能不同，也即不同列对应的第八写入电压可能相同也可能不同。
可选的，所述第一写入电压和所述第五写入电压之差在第四电压范围内、所述第二写入电压和所述第六写入电压之差在第五电压范围内以使得仅在第X行Y列的bit单元中写入数据；所述第三写入电压和所述第五写入电压之差、所述第四写入电压和所述第六写入电压之差、所述第三写入电压和所述第七写入电压之差、所述第四写入电压和所述第八写入电压之差、所述第一写入电压和所述第七写入电压之差、所述第二写入电压和所述第八写入电压之差在第六电压范围内以使得不在其余bit单元中写入数据。其中，第四电压范围和第五电压范围不同，具体的第四电压范围为写入0的电压范围，第五电压范围为写入1的电压范围。或者，第四电压范围为写入1的电压范围，第五电压范围为写入0的电压 范围。第六电压范围为不写入数据的电压范围，也即所述写入0的电压范围和写入1的电压范围以外的电压范围。
示例性的，当在第X行Y列的bit单元中写入0时，第一写入电压和第五写入电压之差在写入0的电压范围内以在该bit单元的第一FeFET中写入0，第二写入电压和第六写入电压之差在写入1的电压范围内以在该bit单元的第二FeFET中写入1，这样当第一FeFET为主导FeFET时，该bit单元中存储的数据为0。同理，第一写入电压和第五写入电压之差在写入1的电压范围内以在该bit单元的第一FeFET中写入1，第二写入电压和第六写入电压之差在写入0的电压范围内以在该bit单元的第二FeFET中写入0，这样当第一FeFET为主导FeFET时，该bit单元中存储的数据为1。
示例性的，所述第三写入电压占所述第一写入电压的比例位于预设比例范围，例如一半，所述第六写入电压占所述第一写入电压的比例也为一半；所述第四写入电压占所述第二写入电压的比例位于预设比例范围，例如一半；所述第七写入电压占所述第二写入电压的比例位于预设比例范围，比如一半。
需要说明的是，本申请实施例不限定上述S601至S604的执行顺序。
示例性的，结合图2所示的CAM，在第3列第2行写入1时，各行各列的FeFET的电压设置如下表表三所示。
表三
Figure PCTCN2019111238-appb-000004
结合该表三，可见仅第3列第2行的bit单元的栅极和背栅极的电压差达到写入电压，因此仅在该第3列第2行的bit单元中写入了数据。
需要说明的是，上述表三中仅写明了栅极和背栅极的电压之间的关系。bit单元的某个FeFET的栅极和背栅极之间的电压均满足上述关系。但同一个bit单元的两个FeFET的栅极的电压可能相同也可能不同。
同理，若FeFET包括栅极和背栅极，则当CAM的一行bit单元中存储的数据组成一个表项时，则当在位于第X行Y列的bit单元写入数据时，如图7所示，执行以下过程：
S701、设置第Y列的第一位线连接的第一FeFET的栅极的电压为第一写入电压，第二位线连接的第二FeFET的栅极的电压为第二写入电压。
S702、设置其余列的第一位线连接的第一FeFET的栅极的电压为第三写入电压，第二位线连接的第二FeFET的栅极的电压为第四写入电压。
S703、设置第X行的第一背栅线连接的第一FeFET的背栅极的电压为第五写入电压，第二背栅线连接的第二FeFET的背栅极的电压为第六写入电压。
S704、设置其余行的第一背栅线连接的第一FeFET的背栅极的电压为第七写入电压，第二背栅线连接的第二FeFET的背栅极的电压为第八写入电压。
该S701至S704的具体实现过程可参考前述S601至S604，也即第一写入电压、第二写入电压、第三写入电压、第四写入电压、第五写入电压、第六写入电压、第七写入电压、第八写入电压的设置参考S601至S604中各个写入电压的设置。该S701至S704的实现过程与S601至S604的实现过程的不同在于：该S701至S704所描述的实现过程应用在CAM的一行bit单元中存储的数据组成一个表项的场景中，该S601至S604所描述的实现过程应用在CAM的一列bit单元中存储的数据组成一个表项的场景中。
需要说明的是，本申请实施例不限定上述S701至S704的执行顺序。
上文是以FeFET中包含栅极和背栅极为例进行描述，如果FeFET中仅包含栅极，而不包含背栅极，则在CAM的一列bit单元中存储的数据组成一个数据表项的场景中，每个bit单元中的第一FeFET的栅极与连接的第一位线之间设置有开关，每个bit单元中的第二FeFET的栅极与连接的第二位线之间设置有开关，因此如图8所示，可通过以下方式在位于第X行Y列的bit单元中写入数据：
S801、设置所述第X行Y列的bit单元中的第一FeFET的栅极与连接的第一位线之间的开关打开，第二FeFET的栅极与连接的第二位线之间的开关打开。
S802、设置第X行的其余bit单元中的第一FeFET的栅极与连接的第一位线之间的开关关闭，第二FeFET的栅极与连接的第二位线之间的开关关闭。
S803、设置第X行的第一位线连接的第一FeFET的栅极的电压为第一写入电压，第二位线连接的第二FeFET的栅极的电压为第二写入电压。
S804、设置其余行的第一位线连接的第一FeFET的栅极的电压为第三写入电压，第二位线连接的第二FeFET的栅极的电压为第四写入电压。
其中，所述第一写入电压在第四电压范围内，第二写入电压在第五电压范围内以仅在所述第X行Y列的bit单元中写入数据；所述第三写入电压和第四写入电压在第六电压范围内以不在除所述第X行Y列的bit单元以外的其余bit单元中写入数据。
具体的，当在第X行Y列的bit单元中写入0时，第四电压范围为写入0的电压范围内以在该bit单元的第一FeFET中写入0，第五电压范围为写入1的电压范围内以在该bit单元的第二FeFET中写入1，这样当第一FeFET为主导FeFET时，该bit单元中存储的数据为0。同理，当在第X行Y列的bit单元中写入1时，第四电压范围为写入1的电压范围内以在该bit单元的第一FeFET中写入1，第五电压范围为写入0的电压范围内以在该bit单元的第二FeFET中写入0，这样当第一FeFET为主导FeFET时，该bit单元中存储的数据为1。
同理，如果FeFET中仅包含栅极，而不包含背栅极，则在CAM的一行bit单元中存储 的数据组成一个数据表项的场景中，可在每个bit单元中的第一FeFET的栅极与连接的第一位线之间设置有开关，每个bit单元中的第二FeFET的栅极与连接的第二位线之间设置有开关。进而，如图9所示，可通过以下方式在位于第X行Y列的bit单元中写入数据：
S901、设置所述第X行Y列的bit单元中的第一FeFET的栅极与连接的第一位线之间的开关打开，第二FeFET的栅极与连接的第二位线之间的开关打开。
S902、设置第Y列的其余bit单元中的第一FeFET的栅极与连接的第一位线之间的开关关闭，第二FeFET的栅极与连接的第二位线之间的开关关闭。
S903、设置第Y列的第一位线连接的第一FeFET的栅极的电压为第一写入电压，第二位线连接的第二FeFET的栅极的电压为第二写入电压。
S904、设置其余列的第一位线连接的第一FeFET的栅极的电压为第三写入电压，第二位线连接的第二FeFET的栅极的电压为第四写入电压。
需要说明的是，不同列的第一位线对应的第三写入电压可能相同也可能不同，不同列的第二位线对应的第四写入电压可能相同也可能不同。
其中，所述第一写入电压在第四电压范围内，第二写入电压在第五电压范围内以仅在所述第X行Y列的bit单元中写入数据；所述第三写入电压和第四写入电压在第六电压范围内以不在除所述第X行Y列的bit单元以外的其余bit单元中写入数据。
具体的，当在第X行Y列的bit单元中写入0时，第四电压范围为写入0的电压范围以在该bit单元的第一FeFET中写入0，第五电压范围为写入1的电压范围内以在该bit单元的第二FeFET中写入1，这样当第一FeFET为主导FeFET时，该bit单元中存储的数据为0。同理，当在第X行Y列的bit单元中写入1时，第四电压范围为写入1的电压范围内以在该bit单元的第一FeFET中写入1，第五电压范围为写入0的电压范围内以在该bit单元的第二FeFET中写入0，这样当第一FeFET为主导FeFET时，该bit单元中存储的数据为1。
本申请实施例提供的在CAM中写入数据的方法，该CAM的每个bit单元仅包含两个FeFET晶体管。在该方法中，通过与栅极连接的位线写入数值，相比于现有技术中的数据写入方法，由于CAM仅包含两个FeFET晶体管，其尺寸较小，因此能够减少写数据的功耗。
网络设备中的查表都是用查找算法来实现的，查找算法通常分为多级或多节点，在某一级或某个节点内，通常有需要精确查找的工作。传统的做法是：通过内存读取，将该级或该节点的所有数据从内存中读出来，再由逻辑电路完成匹配工作，这种做法非常耗时而且会占用内存带宽。应用本申请实施例提供的内容寻址存储器在网络设备中查表，对于某一级或某一节点的查表工作，能够直接在内存中完成算法节点内部的查找命中，仅返回命中的部分，从而节省内存带宽，同时大幅度减少查找时延。常见的查表算法包括最长前缀匹配(longest prefix match，LPM)、掩码匹配和精确匹配(exact match，EM)。
例如：在LPM的一种查找算法中，LPM包括五级处理过程，传统的查表算法中，每一级的处理流程如下：将数据从内存中读取出来，使用逻辑电路在众多表项中查找与给定匹配值(key)匹配的表项。采用本申请实施例提供的方法，能够直接使用CAM在内存中完成表项的查找匹配，进而直接从内存中返回结果，省去了使用逻辑电路进行查找的过程。
又如：掩码匹配的查找分为多级处理，最后一级的处理为在特定容器中寻找匹配的规则。传统的算法是从内存中将所有数据都读出来，然后再用逻辑电路从中查找匹配的规则。 采用本申请实施例提供的方法，能够直接在进行最后一级处理时从该特定容器中查找到匹配的规则并从内存中直接返回结果。
再如：精确匹配的查找分为多级，传统的查找算法为将数据从内存中读出来，然后再使用逻辑电路从中查找匹配的数据。采用本申请实施例提供的方法，能够直接在内存中完成查找并从内存中返回结果。
本申请实施例提供的内容寻址存储器，应用于网络设备，该网络设备可以为任意用于通过网络传送数据包的设备，示例性的，所述网络设备具体可以为交换机、路由器等设备。
如图10所示为本申请实施例提供的一种网络设备的结构示意图。网络设备1000包括通信接口1010、处理器1020、存储器1030和总线1040。其中，通信接口1010、处理器1020、存储器1030通过总线1040互相通信。存储器1030包括第一存储器1031和第二存储器1032，该第二存储器1032具体可以为本申请实施例提供的CAM。
其中，网络设备1000通过通信接口1010与其他设备之间互相通信。例如：网络设备1000通过通信接口1010接收其他设备发送的报文或向其他设备发送报文。示例性的，通信接口1010包括入口媒体访问控制(media access control，MAC)芯片和出口MAC芯片。网络设备1000可通过入口MAC芯片接收报文，并通过出口MAC芯片发送报文。
处理器1020可能是一个中央处理器(central processing unit，CPU)，或者是特定集成电路(application specific integrated circuit，ASIC)，或者是被配置成实施本申请实施例的一个或多个集成电路。示例性的，处理器1020为互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)逻辑电路，处理器1020用于执行第一存储器1031中存储的可执行程序代码，例如计算机程序来运行与可执行代码对应的程序。
第一存储器1031用于存储可执行程序代码，该程序代码包括计算机操作指令。第一存储器1031可能包含高速随机存取存储器(random access memory，RAM)存储器，也可能还包括非易失性存储器(non-volatile memory)，例如至少一个磁盘存储器。
第二存储器1032可以为本申请实施例提供的CAM，例如可以为TCAM。
总线1040可以是工业标准体系结构(industry standard architecture，ISA)总线、外部设备互连(peripheral component，PCI)总线或扩展工业标准体系结构(extended industry standard architecture，EISA)总线等。该总线1040可以分为地址总线、数据总线、控制总线等。为便于表示，图10中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
结合该图10所示的网络设备，本申请实施例提供的方法具体可以实现为：网络设备1000通过通信接口1010接收数据报文并将数据报文交由处理器1020，由处理器1020进行预处理后由第二存储器1032执行图3所示的S301至S304、图4所示的S401至S404、图5所示的S501至S502、图6所示的S601至S604、图7所示的S701至S704的各个步骤的具体实现过程，或者直接由第二存储器8032直接执行图3所示的S301至S304、图4所示的S401至S404、图5所示的S501至S502、图6所示的S601至S604、图7所示的S701至S704、图8所示的S801至S804、图9所示的S901至S904的各个步骤的具体实现过程。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在 本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (23)

  1. 内容寻址存储器CAM，其特征在于，包括：M行N列位bit单元，所述M和N均为大于等于1的正整数；每个所述bit单元包括第一铁电场效应晶体管FeFET和第二FeFET；所述第一FeFET的源极连接所述第二FeFET的漏极；所述第二FeFET的源极接地；
    所述CAM的一列bit单元中存储的数据组成一个表项；同一列bit单元对应同一匹配线；位于同一列的每个bit单元中的第一FeFET的漏极均连接该列对应的匹配线；同一行bit单元对应同一第一位线和同一第二位线，位于同一行的每个bit单元中的第一FeFET的栅极均连接该行对应的第一位线，位于同一行的每个bit单元中的第二FeFET的栅极均连接该行对应的第二位线。
  2. 根据权利要求1所述的CAM，其特征在于，还包括：
    同一列bit单元分别对应同一第一背栅线和同一第二背栅线；位于同一列的每个bit单元中的第一FeFET的背栅极均连接该列对应的第一背栅线；位于同一列的每个bit单元中的第二FeFET的背栅极均连接该列对应的第二背栅线。
  3. 一种数据处理方法，应用于权利要求1或2所述的内容寻址存储器CAM，其特征在于，所述方法包括：
    设置每个bit单元中的第一FeFET和/或第二FeFET始终断开；
    分别设置所述CAM中的匹配线连接的第一FeFET的漏极的电压为预设电压，不同匹配线对应的预设电压相同或不同；
    分别通过第一位线输入匹配值，通过第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值；
    若存在目标列的匹配线的输出电压保持为所述目标列对应的预设电压，则确定所述目标列的bit单元中存储的数据组成的表项为匹配表项。
  4. 根据权利要求3所述的数据处理方法，其特征在于，所述FeFET包括栅极，不包括背栅极；所述设置每个bit单元中的第一FeFET和/或第二FeFET始终断开包括：
    设置每个bit单元中与第一位线连接的第一FeFET和/或与第二位线连接的第二FeFET的栅极电压位于第一电压范围，以使得所述第一FeFET和/或第二FeFET始终断开；其中，当FeFET的栅极的电压位于第一电压范围时，所述FeFET断开；
    所述分别通过第一位线输入匹配值，通过第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值，包括：
    分别设置第一位线连接的第一FeFET的栅极的电压为第一电压，设置第二位线连接的第二FeFET的栅极的电压为第二电压以通过所述第一位线输入匹配值，通过所述第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值；
    或者，所述FeFET包括栅极和背栅极；
    所述设置每个bit单元中的第一FeFET和/或第二FeFET始终断开包括：
    设置每个bit单元中与第一位线连接的第一FeFET的栅极和背栅极的电压差位于第一电压范围，和/或，设置每个bit单元中与第二位线连接的第二FeFET的栅极和背栅极的电压差位于第一电压范围，以使得所述第一FeFET和/或第二FeFET始终断开；其中，当FeFET的栅极和背栅极的电压差位于第一电压范围时，所述FeFET断开；
    所述分别通过第一位线输入匹配值，通过第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值，包括：
    分别设置第一位线连接的第一FeFET的栅极和背栅极的电压差为第一电压，设置第二位线连接的第二FeFET的栅极和背栅极的电压差为第二电压以通过所述第一位线输入匹配值，通过所述第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值。
  5. 根据权利要求4所述的数据处理方法，其特征在于，
    若通过所述第一位线输入匹配值，则当所述匹配值为0时，所述第一电压位于第二电压范围，所述第二电压位于第三电压范围；当所述匹配值为1时，所述第一电压位于第三电压范围，所述第二电压位于第二电压范围；
    若通过所述第二位线输入匹配值，则当所述匹配值为0时，所述第一电压位于第三电压范围，所述第二电压位于第二电压范围；当所述匹配值为1时，所述第一电压位于第二电压范围，所述第二电压位于第三电压范围；
    其中，若FeFET包含栅极，不包含背栅极，则当栅极的电压位于第二电压范围时，所述FeFET中输入匹配值以进行匹配，当栅极的电压位于第三电压范围时，所述FeFET始终导通；或者，若FeFET包含栅极和背栅极，则当栅极和背栅极的电压差位于第二电压范围时，所述FeFET中输入匹配值以进行匹配，当栅极和背栅极的电压差位于第三电压范围时，所述FeFET始终导通。
  6. 根据权利要求3至5任一项所述的数据处理方法，其特征在于，所述方法还包括：
    若存在至少两个匹配表项，则将存储地址最小的匹配表项作为匹配结果输出；
    或者，将列号最小的目标列的bit单元中存储的数据组成的表项作为匹配结果输出。
  7. 根据权利要求3至6任一项所述的数据处理方法，其特征在于，所述方法还包括：
    当表项的匹配方式为精确匹配或掩码匹配且bit单元的掩码为1时，在所述bit单元中写入数据时，分别在第一FeFET和第二FeFET中写入不同值；
    当表项的匹配方式为掩码匹配且bit单元的掩码为0时，在所述bit单元中写入数据时，在所述第一FeFET和第二FeFET中均写入0。
  8. 根据权利要求7所述的数据处理方法，其特征在于，所述FeFET包括栅极和背栅极；
    所述在所述bit单元中写入数据时，分别在第一FeFET和第二FeFET中写入不同值，包括：
    设置第一位线连接的第一FeFET的栅极和背栅极的电压差位于第四电压范围，设置第二位线连接的第二FeFET的栅极和背栅极的电压差位于第五电压范围以使得第一FeFET和第二FeFET写入不同值；其中，所述第四电压范围和第五电压范围不同；
    所述在所述第一FeFET和第二FeFET中均写入0，包括：
    设置第一位线连接的第一FeFET的栅极和背栅极的电压差、第二位线连接的第二FeFET的栅极和背栅极的电压差位于相同的电压范围以使得写入所述第一FeFET和第二FeFET的值都为0。
  9. 根据权利要求8所述的数据处理方法，其特征在于，所述FeFET包括栅极和背栅极；所述方法还包括：
    当在CAM中位于第X行Y列的bit单元写入数据时，设置第X行的第一位线连接的第一FeFET的栅极的电压为第一写入电压，第二位线连接的第二FeFET的栅极的电压为第二写入电压；设置其余行的第一位线连接的第一FeFET的栅极的电压为第三写入电压，第二位线连接的第二FeFET的栅极的电压为第四写入电压；
    设置第Y列的第一背栅线连接的第一FeFET的背栅极的电压为第五写入电压，第二背栅线连接的第二FeFET的背栅极的电压为第六写入电压；设置其余列的第一背栅线连接的第一FeFET的背栅极的电压为第七写入电压，第二背栅线连接的第二FeFET的背栅极的电压为第八写入电压。
  10. 根据权利要求9所述的数据处理方法，其特征在于，所述第一写入电压和所述第五写入电压之差在第四电压范围内、所述第二写入电压和所述第六写入电压之差在第五电压范围内以使得仅在第X行Y列的bit单元中写入数据；所述第三写入电压和所述第五写入电压之差、所述第四写入电压和所述第六写入电压之差、所述第三写入电压和所述第七写入电压之差、所述第四写入电压和所述第八写入电压之差、所述第一写入电压和所述第七写入电压之差、所述第二写入电压和所述第八写入电压之差在第六电压范围内以使得不在其余bit单元中写入数据。
  11. 根据权利要求7所述的数据处理方法，其特征在于，所述FeFET包括栅极，不包括背栅极；
    所述在所述bit单元中写入数据时，分别在第一FeFET和第二FeFET中写入不同值，包括：
    设置第一位线连接的第一FeFET的栅极的电压位于第四电压范围，第二位线连接的第二FeFET的栅极的电压位于第五电压范围以使得第一FeFET和第二FeFET写入不同值；其中，所述第四电压范围和第五电压范围不同；
    所述在所述第一FeFET和第二FeFET中均写入0，包括：
    设置第一位线连接的第一FeFET的栅极和第二位线连接的第二FeFET的栅极的电压位于相同的电压范围以使得写入所述第一FeFET和第二FeFET的值都为0。
  12. 根据权利要求11所述的数据处理方法，其特征在于，所述FeFET包括栅极，不包括背栅极，每个bit单元中的第一FeFET的栅极与连接的第一位线之间设置有开关，每个bit单元中的第二FeFET的栅极与连接的第二位线之间设置有开关；所述方法还包括：
    当在CAM中位于第X行Y列的bit单元中写入数据时，设置所述第X行Y列的bit单元中的第一FeFET的栅极与连接的第一位线之间的开关打开，第二FeFET的栅极与连接的第二位线之间的开关打开；设置第X行的其余bit单元中的第一FeFET的栅极与连接的第一位线之间的开关关闭，第二FeFET的栅极与连接的第二位线之间的开关关闭；
    设置第X行的第一位线连接的第一FeFET的栅极的电压为第一写入电压，第二位线连接的第二FeFET的栅极的电压为第二写入电压；设置其余行的第一位线连接的第一FeFET的栅极的电压为第三写入电压，第二位线连接的第二FeFET的栅极的电压为第四写入电压；
    其中，所述第一写入电压在第四电压范围内，第二写入电压在第五电压范围内以仅在所述第X行Y列的bit单元中写入数据；所述第三写入电压和第四写入电压在第六电压范围内以不在除所述第X行Y列的bit单元以外的其余bit单元中写入数据。
  13. 一种数据处理方法，其特征在于，应用于权利要求1或2所述的内容寻址存储器 CAM，所述方法包括：
    当表项的匹配方式为精确匹配或掩码匹配且bit单元的掩码为1时，在所述bit单元中写入数据时，分别在第一FeFET和第二FeFET中写入不同值；
    当表项的匹配方式为掩码匹配且bit单元的掩码为0时，在所述bit单元中写入数据时，在所述第一FeFET和第二FeFET中均写入0。
  14. 根据权利要求13所述的数据处理方法，其特征在于，所述FeFET包括栅极和背栅极；
    所述在所述bit单元中写入数据时，分别在第一FeFET和第二FeFET中写入不同值，包括：
    设置第一位线连接的第一FeFET的栅极和背栅极的电压差位于第四电压范围，设置第二位线连接的第二FeFET的栅极和背栅极的电压差位于第五电压范围以使得第一FeFET和第二FeFET写入不同值；其中，所述第四电压范围和第五电压范围不同；
    所述在所述第一FeFET和第二FeFET中均写入0，包括：
    设置第一位线连接的第一FeFET的栅极和背栅极的电压差、第二位线连接的第二FeFET的栅极和背栅极的电压差位于相同的电压范围以使得写入所述第一FeFET和第二FeFET的值都为0。
  15. 根据权利要求14所述的数据处理方法，其特征在于，所述FeFET包括栅极和背栅极；所述方法还包括：
    当在CAM中位于第X行Y列的bit单元写入数据时，设置第X行的第一位线连接的第一FeFET的栅极的电压为第一写入电压，第二位线连接的第二FeFET的栅极的电压为第二写入电压；设置其余行的第一位线连接的第一FeFET的栅极的电压为第三写入电压，第二位线连接的第二FeFET的栅极的电压为第四写入电压；
    设置第Y列的第一背栅线连接的第一FeFET的背栅极的电压为第五写入电压，第二背栅线连接的第二FeFET的背栅极的电压为第六写入电压；设置其余列的第一背栅线连接的第一FeFET的背栅极的电压为第七写入电压，第二背栅线连接的第二FeFET的背栅极的电压为第八写入电压。
  16. 根据权利要求15所述的数据处理方法，其特征在于，所述第一写入电压和所述第五写入电压之差在第四电压范围内、所述第二写入电压和所述第六写入电压之差在第五电压范围内以使得仅在第X行Y列的bit单元中写入数据；所述第三写入电压和所述第五写入电压之差、所述第四写入电压和所述第六写入电压之差、所述第三写入电压和所述第七写入电压之差、所述第四写入电压和所述第八写入电压之差、所述第一写入电压和所述第七写入电压之差、所述第二写入电压和所述第八写入电压之差在第六电压范围内以使得不在其余bit单元中写入数据。
  17. 根据权利要求13所述的数据处理方法，其特征在于，所述FeFET包括栅极，不包括背栅极；
    所述在所述bit单元中写入数据时，分别在第一FeFET和第二FeFET中写入不同值，包括：
    设置第一位线连接的第一FeFET的栅极的电压位于第四电压范围，第二位线连接的第二FeFET的栅极的电压位于第五电压范围以使得第一FeFET和第二FeFET写入不同值；其 中，所述第四电压范围和第五电压范围不同；
    所述在所述第一FeFET和第二FeFET中均写入0，包括：
    设置第一位线连接的第一FeFET的栅极和第二位线连接的第二FeFET的栅极的电压位于相同的电压范围以使得写入所述第一FeFET和第二FeFET的值都为0。
  18. 根据权利要求17所述的数据处理方法，其特征在于，所述FeFET包括栅极，不包括背栅极，每个bit单元中的第一FeFET的栅极与连接的第一位线之间设置有开关，每个bit单元中的第二FeFET的栅极与连接的第二位线之间设置有开关；所述方法还包括：
    当在CAM中位于第X行Y列的bit单元中写入数据时，设置所述第X行Y列的bit单元中的第一FeFET的栅极与连接的第一位线之间的开关打开，第二FeFET的栅极与连接的第二位线之间的开关打开；设置第X行的其余bit单元中的第一FeFET的栅极与连接的第一位线之间的开关关闭，第二FeFET的栅极与连接的第二位线之间的开关关闭；
    设置第X行的第一位线连接的第一FeFET的栅极的电压为第一写入电压，第二位线连接的第二FeFET的栅极的电压为第二写入电压；设置其余行的第一位线连接的第一FeFET的栅极的电压为第三写入电压，第二位线连接的第二FeFET的栅极的电压为第四写入电压；
    其中，所述第一写入电压在第四电压范围内，第二写入电压在第五电压范围内以仅在所述第X行Y列的bit单元中写入数据；所述第三写入电压和第四写入电压在第六电压范围内以不在除所述第X行Y列的bit单元以外的其余bit单元中写入数据。
  19. 根据权利要求13至18任一项所述的数据处理方法，其特征在于，所述方法包括：
    设置每个bit单元中的第一FeFET和/或第二FeFET始终断开；
    分别设置所述CAM中的匹配线连接的第一FeFET的漏极的电压为预设电压，不同匹配线对应的预设电压相同或不同；
    分别通过第一位线输入匹配值，通过第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值；
    若存在目标列的匹配线的输出电压保持为所述目标列对应的预设电压，则确定所述目标列的bit单元中存储的数据组成的表项为匹配表项。
  20. 根据权利要求19所述的数据处理方法，其特征在于，所述FeFET包括栅极，不包括背栅极；所述设置每个bit单元中的第一FeFET和/或第二FeFET始终断开包括：
    设置每个bit单元中与第一位线连接的第一FeFET和/或与第二位线连接的第二FeFET的栅极电压位于第一电压范围，以使得所述第一FeFET和/或第二FeFET始终断开；其中，当FeFET的栅极的电压位于第一电压范围时，所述FeFET断开；
    所述分别通过第一位线输入匹配值，通过第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值，包括：
    分别设置第一位线连接的第一FeFET的栅极的电压为第一电压，设置第二位线连接的第二FeFET的栅极的电压为第二电压以通过所述第一位线输入匹配值，通过所述第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值；
    或者，所述FeFET包括栅极和背栅极；
    所述设置每个bit单元中的第一FeFET和/或第二FeFET始终断开包括：
    设置每个bit单元中与第一位线连接的第一FeFET的栅极和背栅极的电压差位于第一 电压范围，和/或，设置每个bit单元中与第二位线连接的第二FeFET的栅极和背栅极的电压差位于第一电压范围，以使得所述第一FeFET和/或第二FeFET始终断开；其中，当FeFET的栅极和背栅极的电压差位于第一电压范围时，所述FeFET断开；
    所述分别通过第一位线输入匹配值，通过第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值，包括：
    分别设置第一位线连接的第一FeFET的栅极和背栅极的电压差为第一电压，设置第二位线连接的第二FeFET的栅极和背栅极的电压差为第二电压以通过所述第一位线输入匹配值，通过所述第二位线输入所述匹配值的相反值或者通过所述第二位线输入匹配值，通过所述第一位线输入所述匹配值的相反值。
  21. 根据权利要求20所述的数据处理方法，其特征在于，
    若通过所述第一位线输入匹配值，则当所述匹配值为0时，所述第一电压位于第二电压范围，所述第二电压位于第三电压范围；当所述匹配值为1时，所述第一电压位于第三电压范围，所述第二电压位于第二电压范围；
    若通过所述第二位线输入匹配值，则当所述匹配值为0时，所述第一电压位于第三电压范围，所述第二电压位于第二电压范围；当所述匹配值为1时，所述第一电压位于第二电压范围，所述第二电压位于第三电压范围；
    其中，若FeFET包含栅极，不包含背栅极，则当栅极的电压位于第二电压范围时，所述FeFET中输入匹配值以进行匹配，当栅极的电压位于第三电压范围时，所述FeFET始终导通；或者，若FeFET包含栅极和背栅极，则当栅极和背栅极的电压差位于第二电压范围时，所述FeFET中输入匹配值以进行匹配，当栅极和背栅极的电压差位于第三电压范围时，所述FeFET始终导通。
  22. 根据权利要求19至21任一项所述的数据处理方法，其特征在于，所述方法还包括：
    若存在至少两个匹配表项，则将存储地址最小的匹配表项作为匹配结果输出；
    或者，将列号最小的目标列的bit单元中存储的数据组成的表项作为匹配结果输出。
  23. 一种网络设备，其特征在于，包括处理器、通信接口、第一存储器、第二存储器和通信总线；其中，所述处理器、通信接口、第一存储器、第二存储器通过所述通信总线互相通信；所述第一存储器中存储有计算机可执行程序代码，所述第二存储器为权利要求1或2所述的内容寻址存储器CAM；
    所述处理器用于执行所述第一存储器中存储的所述计算机可执行程序代码以控制所述第二存储器执行权利要求3至12任一项所述的数据处理方法；
    或者，所述处理器用于执行所述第一存储器中存储的所述计算机可执行程序代码以控制所述第二存储器执行权利要求13至22任一项所述的数据处理方法。
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113096710B (zh) * 2021-04-28 2023-03-31 清华大学 一种单元电路及其动态三态内容寻址存储器
KR20220149304A (ko) 2021-04-30 2022-11-08 삼성전자주식회사 단순한 셀 구성을 갖는 불휘발성 연상기억장치 및 그 동작방법
US11527277B1 (en) 2021-06-04 2022-12-13 Kepler Computing Inc. High-density low voltage ferroelectric memory bit-cell
TWI766773B (zh) * 2021-07-23 2022-06-01 旺宏電子股份有限公司 多階內容可定址記憶體、多階編碼方法與多階搜尋方法
US11482270B1 (en) 2021-11-17 2022-10-25 Kepler Computing Inc. Pulsing scheme for a ferroelectric memory bit-cell to minimize read or write disturb effect and refresh logic
US11854619B2 (en) * 2022-01-19 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device with content addressable memory units
US20230395134A1 (en) 2022-06-03 2023-12-07 Kepler Computing Inc. Write disturb mitigation for non-linear polar material based multi-capacitor bit-cell
US12062584B1 (en) 2022-10-28 2024-08-13 Kepler Computing Inc. Iterative method of multilayer stack development for device applications
US11741428B1 (en) 2022-12-23 2023-08-29 Kepler Computing Inc. Iterative monetization of process development of non-linear polar material and devices
US11765908B1 (en) 2023-02-10 2023-09-19 Kepler Computing Inc. Memory device fabrication through wafer bonding

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1490880A (zh) * 2002-09-27 2004-04-21 �Ҵ���˾ 使用铁电栅极场效应晶体管的非易失性存储器和制造方法
US20080055961A1 (en) * 2006-09-01 2008-03-06 Seiko Epson Corporation Ferroelectric memory device and electronic apparatus
CN101271728A (zh) * 2008-04-22 2008-09-24 清华大学 一种抑制小信号干扰的铁电存储器存储阵列结构
CN108447909A (zh) * 2013-05-17 2018-08-24 美光科技公司 具有铁电场效应晶体管存储器阵列的设备及相关方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003100086A (ja) * 2001-09-25 2003-04-04 Fujitsu Ltd 連想メモリ回路
JP4367281B2 (ja) * 2004-08-03 2009-11-18 ソニー株式会社 演算回路
US7319608B2 (en) * 2005-06-30 2008-01-15 International Business Machines Corporation Non-volatile content addressable memory using phase-change-material memory elements
US7616468B2 (en) * 2006-08-04 2009-11-10 Qualcomm Incorporated Method and apparatus for reducing power consumption in a content addressable memory
JP5140849B2 (ja) * 2008-02-13 2013-02-13 ルネサスエレクトロニクス株式会社 内容参照メモリ
US8120937B2 (en) * 2009-03-06 2012-02-21 International Business Machines Corporation Ternary content addressable memory using phase change devices
US7944724B2 (en) * 2009-04-28 2011-05-17 Netlogic Microsystems, Inc. Ternary content addressable memory having reduced leakage effects
US8054662B2 (en) * 2009-08-28 2011-11-08 International Business Machines Corporation Content addressable memory array
US9001545B2 (en) * 2012-08-31 2015-04-07 Aplus Flash Technology, Inc. NOR-based BCAM/TCAM cell and array with NAND scalability
CN105099918B (zh) * 2014-05-13 2019-01-29 华为技术有限公司 一种数据查找匹配的方法和装置
US9312006B2 (en) * 2014-06-03 2016-04-12 National Tsing Hua University Non-volatile ternary content-addressable memory with resistive memory device
US10650892B2 (en) * 2018-04-23 2020-05-12 Ferroelectric Memory Gmbh Ternary memory cell and ternary memory cell arrangement
US10453531B1 (en) * 2018-06-29 2019-10-22 Sandisk Technologies Llc Content addressable memory using threshold-adjustable vertical transistors and methods of forming the same
US11289162B2 (en) * 2020-04-30 2022-03-29 Hewlett Packard Enterprise Development Lp Analog content addressable memory utilizing three terminal memory devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1490880A (zh) * 2002-09-27 2004-04-21 �Ҵ���˾ 使用铁电栅极场效应晶体管的非易失性存储器和制造方法
US20080055961A1 (en) * 2006-09-01 2008-03-06 Seiko Epson Corporation Ferroelectric memory device and electronic apparatus
CN101271728A (zh) * 2008-04-22 2008-09-24 清华大学 一种抑制小信号干扰的铁电存储器存储阵列结构
CN108447909A (zh) * 2013-05-17 2018-08-24 美光科技公司 具有铁电场效应晶体管存储器阵列的设备及相关方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3813067A4

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