WO2020087581A1 - 薄膜晶体管结构及沟道电阻和接触电阻的测量方法 - Google Patents

薄膜晶体管结构及沟道电阻和接触电阻的测量方法 Download PDF

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WO2020087581A1
WO2020087581A1 PCT/CN2018/116007 CN2018116007W WO2020087581A1 WO 2020087581 A1 WO2020087581 A1 WO 2020087581A1 CN 2018116007 W CN2018116007 W CN 2018116007W WO 2020087581 A1 WO2020087581 A1 WO 2020087581A1
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thin film
electrode
film transistor
drain
layer
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PCT/CN2018/116007
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English (en)
French (fr)
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朱茂霞
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深圳市华星光电半导体显示技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/08—Measuring resistance by measuring both voltage and current
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/20—Measuring earth resistance; Measuring contact resistance, e.g. of earth connections, e.g. plates
    • G01R27/205—Measuring contact resistance of connections, e.g. of earth connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line

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  • the invention relates to the technical field of display, in particular to a thin film transistor structure and a method for measuring channel resistance and contact resistance.
  • flat panel display devices are widely used in mobile phones, TVs, personal digital assistants, digital cameras, notebook computers, desktops due to their advantages of high image quality, power saving, thin body, and wide range of applications.
  • Various consumer electronic products such as computers have become the mainstream in display devices.
  • An active matrix (AM) flat panel display device is currently the most commonly used display device.
  • the active matrix flat panel display device controls the input of data signals through a thin film transistor switch (Thin Film Transistor, TFT), and then controls the screen display.
  • TFT Thin Film Transistor
  • the current display technology continues to develop in the direction of high resolution, for example, the resolution of mobile phones has reached the level of 1080P (1080 ⁇ 1920), and the resolution of TVs has reached the level of 4K (4096 ⁇ 2160), accompanied by resolution
  • the rate continues to increase, it is necessary to continuously improve the driving ability of thin film transistors, and the key to improving the driving ability of thin film transistors is how to obtain a larger current on current at a lower driving voltage.
  • the resistance is how to obtain a larger current on current at a lower driving voltage.
  • the thin film transistor includes a channel resistance and a contact resistance.
  • the contact resistance mainly comes from the contact between the active layer and the source / drain.
  • the contact resistance affects the calculation of mobility and even threshold voltage, so the channel resistance is accurately calculated
  • the contact resistance is very important, it can accurately help us to calculate the intrinsic mobility and threshold voltage of the amorphous silicon thin film, so as to provide a basis for improving the driving ability of the thin film transistor.
  • the traditional method of calculating contact resistance is Transfer Length Measurement (TLM).
  • TLM Transfer Length Measurement
  • the method is to measure multiple thin film transistors with different channel lengths, calculate the total resistance, and then define the resistance and the y-intercept.
  • the contact resistance can be obtained by twice the contact resistance.
  • the limitation is that multiple sets of thin film transistors with different channel lengths need to be designed on the photomask, and multiple sets of data are measured for calculation and fitting. The above is cumbersome, and because of the uncertainty of the fitting, it is impossible to accurately calculate the contact resistance.
  • the object of the present invention is to provide a thin film transistor structure that can quickly and accurately complete the measurement of the channel resistance and contact resistance of a thin film transistor through a single thin film transistor.
  • the object of the present invention is also to provide a method for measuring the channel resistance and contact resistance, which can quickly and accurately complete the measurement of the channel resistance and contact resistance of the thin film transistor through a single thin film transistor.
  • the present invention provides a thin film transistor structure, including: a base substrate, a gate provided on the base substrate, a gate insulating layer provided on the gate, and a An active layer on the gate insulating layer and the source electrode, the measuring electrode and the drain electrode arranged on the active layer in sequence at intervals;
  • the separation distance between the measurement electrode and the source electrode is different from the separation distance between the measurement electrode and the drain electrode.
  • the material of the active layer is amorphous silicon, which includes an undoped layer provided on the gate insulating layer, and between the source electrode and the undoped layer, the measurement electrode and the non-doped layer Doped layers between doped layers and between the drain and the undoped layer.
  • the doped layer is an N-type doped layer.
  • the material of the active layer is a metal oxide semiconductor material.
  • the separation distance between the measurement electrode and the source electrode is greater than the separation distance between the measurement electrode and the drain electrode.
  • the invention also provides a method for measuring the channel resistance and the contact resistance, including the following steps:
  • Step S1 A thin film transistor is provided.
  • the thin film transistor includes: a base substrate, a gate provided on the base substrate, a gate insulating layer provided on the gate, and an insulation provided on the gate An active layer on the layer and the source electrode, the measuring electrode and the drain electrode arranged on the active layer in sequence at intervals; the separation distance between the measuring electrode and the source electrode is different from that of the measuring electrode and The separation distance between the drains;
  • Step S2 ground the source of the thin film transistor, connect the drain to the first voltage, and measure the current flowing through the drain of the thin film transistor and the voltage on the measuring electrode;
  • Step S3 Determine the channel resistance and contact resistance of the thin film transistor according to the current flowing through the drain of the thin film transistor and the voltage on the measurement electrode;
  • R 1 is the channel resistance
  • R 2 is the contact resistance
  • V A is the voltage on the measurement electrode
  • V 1 is the first voltage
  • X A is the separation distance between the measurement electrode and the source
  • L is the channel length
  • I D is a drain current flowing through the thin film transistor.
  • the material of the active layer is amorphous silicon, which includes an undoped layer provided on the gate insulating layer, and between the source electrode and the undoped layer, the measurement electrode and the non-doped layer Doped layers between doped layers and between the drain and the undoped layer.
  • the doped layer is an N-type doped layer.
  • the material of the active layer is a metal oxide semiconductor material.
  • the separation distance between the measurement electrode and the source electrode is greater than the separation distance between the measurement electrode and the drain electrode.
  • the present invention provides a thin film transistor structure, including: a base substrate, a gate provided on the base substrate, a gate insulating layer provided on the gate, and a An active layer on the gate insulating layer and a source electrode, a measurement electrode, and a drain electrode arranged on the active layer in this order; the separation distance between the measurement electrode and the source electrode is different from that The distance between the measuring electrode and the drain, a measuring electrode is provided on the active layer, and then the channel resistance of the thin film transistor is determined by measuring the voltage on the measuring electrode and the current flowing through the drain And the contact resistance can quickly and accurately complete the measurement of the channel resistance and contact resistance of the thin film transistor through a single thin film transistor.
  • the invention also provides a method for measuring the channel resistance and contact resistance, which can quickly and accurately complete the measurement of the channel resistance and contact resistance of the thin film transistor through a single thin film transistor.
  • FIG. 1 is a top view of a first embodiment of the thin film transistor structure of the present invention
  • Figure 2 is a cross-sectional view at A-A in Figure 1;
  • FIG. 3 is a schematic diagram of a second embodiment of the thin film transistor structure of the present invention.
  • FIG. 4 is a cross-sectional view at B-B in FIG. 3;
  • FIG. 6 is a flowchart of a method for measuring channel resistance and contact resistance of the present invention.
  • the present invention provides a thin film transistor structure, including: a base substrate 1, a gate 2 provided on the base substrate 1, a gate provided on the gate The gate insulating layer 3 on the 2, the active layer 4 provided on the gate insulating layer 3, and the source electrode 5, the measuring electrode 6 and the drain electrode 7 arranged on the active layer 4 in sequence at intervals ;
  • the separation distance between the measurement electrode 6 and the source electrode 5 is different from the separation distance between the measurement electrode 6 and the drain electrode 7.
  • the structure of the thin film transistor of the present invention is advantageous for measuring the channel resistance and contact resistance.
  • the source 5 of the thin film transistor can be grounded first, and the drain 7 can be connected to the first voltage, and the flow through the The current of the drain 7 of the thin film transistor and the voltage on the measuring electrode 6, and then the channel resistance and the contact resistance of the thin film transistor are determined according to the current on the drain 7 of the thin film transistor and the voltage on the measuring electrode 6, wherein ,
  • the formula for determining the channel resistance and contact resistance of the thin film transistor is:
  • R 1 is the channel resistance
  • R 2 is the contact resistance
  • V A is the voltage on the measuring electrode 6
  • V 1 is the first voltage
  • X A is the separation distance between the measuring electrode 6 and the source electrode 5
  • L is the channel length
  • I D is a drain current of the thin film transistor 7 is flowing.
  • the measurement principle of the above measurement process is: As shown in FIG. 5, the voltage at the measurement electrode 6 can be measured at the measurement electrode 6, but no current passes, so there is no contact resistance. According to the current and voltage resistance Relationship, since the current from the source 5 to the measuring electrode 6 is equal to the current from the source 5 to the drain 7, the following formula can be obtained:
  • the channel resistance and contact resistance of the thin film transistor can be determined In order to achieve the measurement of the channel resistance and contact resistance of the thin film transistor quickly and accurately through a single thin film transistor.
  • the material of the active layer 4 is amorphous silicon, which includes an undoped layer provided on the gate insulating layer 3
  • the doped layer 32 is an N-type doped layer.
  • the doped layer 32 may be a P-type doped layer.
  • the material of the active layer 4 is a metal oxide semiconductor material, and at this time, the active layer 4 includes a layer of metal oxide Semiconductor thin film.
  • the material of the active layer 4 is indium gallium zinc oxide (IGZO).
  • the separation distance between the measurement electrode 6 and the source electrode 5 is greater than the separation distance between the measurement electrode 6 and the drain electrode 7, of course, this is not a limitation of the present invention, the measurement electrode 6
  • the separation distance from the source electrode 5 may also be smaller than the separation distance between the measurement electrode 6 and the drain electrode 7.
  • the materials of the gate 2, the source 5, the measuring electrode 6, and the drain 7 are one or a combination of molybdenum, aluminum, and copper.
  • the base substrate 1 is a glass substrate.
  • the material of the gate insulating layer 3 is one or a combination of silicon oxide and silicon nitride.
  • the present invention also provides a method for measuring channel resistance and contact resistance, including the following steps:
  • Step S1 a thin film transistor is provided.
  • the thin film transistor includes: a base substrate 1, a gate 2 provided on the base substrate 1, a gate insulating layer 3 provided on the gate 2, and a An active layer 4 on the gate insulating layer 3 and a source electrode 5, a measuring electrode 6 and a drain electrode 7 arranged on the active layer 4 in sequence at intervals; the measuring electrode 6 and the source electrode The separation distance between 5 is different from the separation distance between the measuring electrode 6 and the drain 7.
  • the material of the active layer 4 is crystalline silicon, which includes a non-doped layer provided on the gate insulating layer 3
  • the doped layer 32 is an N-type doped layer.
  • the doped layer 32 may be a P-type doped layer.
  • the material of the active layer 4 is a metal oxide semiconductor material, and at this time, the active layer 4 includes a layer of metal oxide Semiconductor thin film.
  • the material of the active layer 4 is indium gallium zinc oxide (IGZO).
  • the separation distance between the measurement electrode 6 and the source electrode 5 is greater than the separation distance between the measurement electrode 6 and the drain electrode 7, of course, this is not a limitation of the present invention, the measurement electrode 6
  • the separation distance from the source electrode 5 may also be smaller than the separation distance between the measurement electrode 6 and the drain electrode 7.
  • the materials of the gate 2, the source 5, the measuring electrode 6, and the drain 7 are one or a combination of molybdenum, aluminum, and copper.
  • the base substrate 1 is a glass substrate.
  • the material of the gate insulating layer 3 is one or a combination of silicon oxide and silicon nitride.
  • Step S2 The source 5 of the thin film transistor is grounded, the drain 7 is connected to the first voltage, and the current flowing through the drain 7 of the thin film transistor and the voltage on the measurement electrode 6 are measured.
  • Step S3 Determine the channel resistance and contact resistance of the thin film transistor according to the current flowing through the drain 7 of the thin film transistor and the voltage on the measurement electrode 6;
  • R 1 is the channel resistance
  • R 2 is the contact resistance
  • V A is the voltage on the measuring electrode 6
  • V 1 is the first voltage
  • X A is the separation distance between the measuring electrode 6 and the source electrode 5
  • L is the channel length
  • I D is a drain current of the thin film transistor 7 is flowing.
  • the measurement principle of the above measurement method is: as shown in FIG. 5, the voltage at the measurement electrode 6 can be measured at the measurement electrode 6, but no current passes, so there is no contact resistance. According to the current and voltage resistance Relationship, since the current from the source 5 to the measuring electrode 6 is equal to the current from the source 5 to the drain 7, the following formula can be obtained:
  • the channel resistance and contact resistance of the thin film transistor can be determined In order to achieve the measurement of the channel resistance and contact resistance of the thin film transistor quickly and accurately through a single thin film transistor.
  • the present invention provides a thin film transistor structure, including: a base substrate, a gate provided on the base substrate, a gate insulating layer provided on the gate, and a An active layer on the gate insulating layer and a source electrode, a measuring electrode and a drain electrode arranged on the active layer in sequence at intervals; the separation distance between the measuring electrode and the source electrode is different from the Measuring the separation distance between the electrode and the drain, setting a measuring electrode on the active layer, and then determining the channel resistance and the channel resistance of the thin film transistor by measuring the voltage on the measuring electrode and the current flowing through the drain
  • the contact resistance can quickly and accurately measure the channel resistance and contact resistance of the thin film transistor through a single thin film transistor.
  • the invention also provides a method for measuring the channel resistance and contact resistance, which can quickly and accurately complete the measurement of the channel resistance and contact resistance of the thin film transistor through a single thin film transistor.

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Abstract

一种薄膜晶体管结构及沟道电阻和接触电阻的测量方法。所述薄膜晶体管结构包括：衬底基板（1）、设于所述衬底基板（1）上的栅极（2）、设于所述栅极（2）上的栅极绝缘层（3）、设于所述栅极绝缘层（3）上的有源层（4）以及设于所述有源层（4）上的依次间隔排列的源极（5）、测量电极（6）和漏极（7）；所述测量电极（6）与所述源极（5）之间的间隔距离不同于所述测量电极（6）与所述漏极（7）之间的间隔距离，在有源层（4）上设置测量电极（6），进而通过测量所述测量电极（6）上的电压和流过漏极（7）的电流，确定所述薄膜晶体管的沟道电阻（R1）和接触电阻（R2），能够通过单颗薄膜晶体管，快速准确完成薄膜晶体管的沟道电阻（R1）和接触电阻（R2）的测量。

Description

薄膜晶体管结构及沟道电阻和接触电阻的测量方法 技术领域
本发明涉及显示技术领域，尤其涉及一种薄膜晶体管结构及沟道电阻和接触电阻的测量方法。
背景技术
随着显示技术的发展，平板显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
主动矩阵式(Active Matrix，AM)平板显示装置是目前最常用的显示装置，所述主动矩阵式平板显示装置通过一薄膜晶体管开关(Thin Film Transistor，TFT)来控制数据信号的输入，进而控制画面显示。
目前的显示技术朝着高分辨率的方向不断发展，例如手机的分辨率已经达到1080P的水准(1080×1920)，而电视的分辨率更是达到4K(4096×2160)的级别，伴随着分辨率的不断提升，需要不断提高薄膜晶体管的驱动能力，而提升薄膜晶体管的驱动能力的关键在于，如何在较低的驱动电压下获得较大的电流的导通电流，为此需要尽量降低薄膜晶体管的电阻。
其中，所述薄膜晶体管包括沟道电阻和接触电阻，接触电阻主要来自于有源层与源极/漏极的接触，接触电阻会影响迁移率甚至阈值电压的计算，所以准确计算出沟道电阻和接触电阻是非常重要的，可以准确帮助我们计算非晶硅薄膜本征迁移率和阈值电压，从而为改善薄膜晶体管的驱动能力提供依据。
传统计算接触电阻的方法为转换长度测量法(Transfer Length Measurement，TLM)，其方法是量测多个不同沟道长度的薄膜晶体管，计算其总电阻，然后将其电阻与y轴的截距定义为2倍接触电阻，即可得到接触电阻，其局限性是需要在光罩上设计多组不同沟道长度的薄膜晶体管，并量测多组数据进行计算和拟合，在设计上和量测上较为繁琐，且由于拟合存在不确定性，所以无法准确计算接触电阻。
发明内容
本发明的目的在于提供一种薄膜晶体管结构，能够通过单颗薄膜晶体 管，快速准确完成薄膜晶体管的沟道电阻和接触电阻的测量。
本发明的目的还在于提供一种沟道电阻和接触电阻的测量方法，能够通过单颗薄膜晶体管，快速准确完成薄膜晶体管的沟道电阻和接触电阻的测量。
为实现上述目的，本发明提供了一种薄膜晶体管结构，包括：衬底基板、设于所述衬底基板上的栅极、设于所述栅极上的栅极绝缘层、设于所述栅极绝缘层上的有源层以及设于所述有源层上的依次间隔排列的源极、测量电极和漏极；
所述测量电极与所述源极之间的间隔距离不同于所述测量电极与所述漏极之间的间隔距离。
所述有源层的材料为非晶硅，其包括设于所述栅极绝缘层上的非掺杂层以及位于所述源极与所述非掺杂层之间、测量电极与所述非掺杂层之间及漏极与所述非掺杂层之间的掺杂层。
所述掺杂层为N型掺杂层。
所述有源层的材料为金属氧化物半导体材料。
所述测量电极与所述源极之间的间隔距离大于所述测量电极与所述漏极之间的间隔距离。
本发明还提供一种沟道电阻和接触电阻的测量方法，包括如下步骤：
步骤S1、提供一薄膜晶体管，所述薄膜晶体管包括：衬底基板、设于所述衬底基板上的栅极、设于所述栅极上的栅极绝缘层、设于所述栅极绝缘层上的有源层以及设于所述有源层上的依次间隔排列的源极、测量电极和漏极；所述测量电极与所述源极之间的间隔距离不同于所述测量电极与所述漏极之间的间隔距离；
步骤S2、将所述薄膜晶体管的源极接地，漏极接入第一电压，并测量流过所述薄膜晶体管的漏极的电流和测量电极上的电压；
步骤S3、根据流过所述薄膜晶体管的漏极的电流和测量电极上的电压，确定所述薄膜晶体管的沟道电阻和接触电阻；
其中，确定所述薄膜晶体管的沟道电阻和接触电阻的公式为：
Figure PCTCN2018116007-appb-000001
Figure PCTCN2018116007-appb-000002
其中，R 1为沟道电阻，R 2为接触电阻，V A为测量电极上的电压，V 1为第一电压，X A为测量电极与源极之间的间隔距离，L为沟道长度，I D为 流过所述薄膜晶体管的漏极的电流。
所述有源层的材料为非晶硅，其包括设于所述栅极绝缘层上的非掺杂层以及位于所述源极与所述非掺杂层之间、测量电极与所述非掺杂层之间及漏极与所述非掺杂层之间的掺杂层。
所述掺杂层为N型掺杂层。
所述有源层的材料为金属氧化物半导体材料。
所述测量电极与所述源极之间的间隔距离大于所述测量电极与所述漏极之间的间隔距离。
本发明的有益效果：本发明提供了一种薄膜晶体管结构，包括：衬底基板、设于所述衬底基板上的栅极、设于所述栅极上的栅极绝缘层、设于所述栅极绝缘层上的有源层以及设于所述有源层上的依次间隔排列的源极、测量电极和漏极；所述测量电极与所述源极之间的间隔距离不同于所述测量电极与所述漏极之间的间隔距离，在有源层上设置测量电极，进而通过测量所述测量电极上的电压和流过漏极的电流，确定所述薄膜晶体管的沟道电阻和接触电阻，能够通过单颗薄膜晶体管，快速准确完成薄膜晶体管的沟道电阻和接触电阻的测量。本发明还提供一种沟道电阻和接触电阻的测量方法，能够通过单颗薄膜晶体管，快速准确完成薄膜晶体管的沟道电阻和接触电阻的测量。
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为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的薄膜晶体管结构的第一实施例的俯视图；
图2为图1中A-A处的剖面图；
图3为本发明的薄膜晶体管结构的第二实施例的示意图；
图4为图3中B-B处的剖面图；
图5为本发明的沟道电阻和接触电阻的测量方法的等效电路图；
图6为本发明的沟道电阻和接触电阻的测量方法的流程图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1和图2或图3和图4，本发明提供一种薄膜晶体管结构，包括：衬底基板1、设于所述衬底基板1上的栅极2、设于所述栅极2上的栅极绝缘层3、设于所述栅极绝缘层3上的有源层4以及设于所述有源层4上的依次间隔排列的源极5、测量电极6和漏极7；
所述测量电极6与所述源极5之间的间隔距离不同于所述测量电极6与所述漏极7之间的间隔距离。
具体地，本发明的薄膜晶体管结构利于测量沟道电阻和接触电阻，测量时，可在先将所述薄膜晶体管的源极5接地，漏极7接入第一电压，并测量流过所述薄膜晶体管的漏极7的电流和测量电极6上的电压，接着根据所述薄膜晶体管的漏极7端的电流和测量电极6上的电压，确定所述薄膜晶体管的沟道电阻和接触电阻，其中，确定所述薄膜晶体管的沟道电阻和接触电阻的公式为：
Figure PCTCN2018116007-appb-000003
Figure PCTCN2018116007-appb-000004
其中，R 1为沟道电阻，R 2为接触电阻，V A为测量电极6上的电压，V 1为第一电压，X A为测量电极6与源极5之间的间隔距离，L为沟道长度，I D为流过所述薄膜晶体管的漏极7的电流。
具体地，如图5所示，所述接触电阻R 2为源极5与有源层4之间的接触电阻R 21和漏极7与有源层4之间的接触电阻R 22的和。
需要说明的是，上述测量过程的测量原理为：如图5所示，在测量电极6处可以测量到测量电极6处电压，但无电流通过，所以不存在接触电阻，根据电流与电压电阻的关系，由于源极5到测量电极6处电流与源极5到漏极7处电流相等，可以得到如下公式：
I D＝V A/(X AR 1/L+R 2)＝V D/(R 1+2R 2)；
据此可知，
Figure PCTCN2018116007-appb-000005
Figure PCTCN2018116007-appb-000006
从而，本发明通过在有源层4上设置测量电极6，进而通过测量所述测量电极6上的电压和流过漏极7的电流，即可确定所述薄膜晶体管的沟道电阻和接触电阻，从而实现通过单颗薄膜晶体管，快速准确完成薄膜晶体 管的沟道电阻和接触电阻的测量。
具体地，如图1和图2所示，在本发明的第一实施例中，所述有源层4的材料为非晶硅，其包括设于所述栅极绝缘层3上的非掺杂层31以及位于所述源极5与所述非掺杂层31之间、测量电极6与所述非掺杂层31之间及漏极7与所述非掺杂层31之间的掺杂层32。
优选地，所述掺杂层32为N型掺杂层，当然，所述掺杂层32可以为P型掺杂层。
具体地，如图1和图2所示，在本发明的第一实施例中，所述有源层4的材料为金属氧化物半导体材料，此时所述有源层4包括一层金属氧化物半导体薄膜。
优选地，所述有源层4的材料为铟镓锌氧化物(IGZO)。
优选地，所述测量电极6与所述源极5之间的间隔距离大于所述测量电极6与所述漏极7之间的间隔距离，当然这并非对本发明的限制，所述测量电极6与所述源极5之间的间隔距离也可以小于所述测量电极6与所述漏极7之间的间隔距离。
具体地，所述栅极2、源极5、测量电极6及漏极7的材料为为钼、铝及铜中的一种或多种的组合，所述衬底基板1为玻璃基板，所述栅极绝缘层3的材料为氧化硅和氮化硅中的一种或二者的组合。
请参阅图6，本发明还提供一种沟道电阻和接触电阻的测量方法，包括如下步骤：
步骤S1、提供一薄膜晶体管，所述薄膜晶体管包括：衬底基板1、设于所述衬底基板1上的栅极2、设于所述栅极2上的栅极绝缘层3、设于所述栅极绝缘层3上的有源层4以及设于所述有源层4上的依次间隔排列的源极5、测量电极6和漏极7；所述测量电极6与所述源极5之间的间隔距离不同于所述测量电极6与所述漏极7之间的间隔距离。
具体地，如图1和图2所示，在本发明的第一实施例中，所述有源层4的材料为为晶硅，其包括设于所述栅极绝缘层3上的非掺杂层31以及位于所述源极5与所述非掺杂层31之间、测量电极6与所述非掺杂层31之间及漏极7与所述非掺杂层31之间的掺杂层32。
优选地，所述掺杂层32为N型掺杂层，当然，所述掺杂层32可以为P型掺杂层。
具体地，如图1和图2所示，在本发明的第一实施例中，所述有源层4的材料为金属氧化物半导体材料，此时所述有源层4包括一层金属氧化物半导体薄膜。
优选地，所述有源层4的材料为铟镓锌氧化物(IGZO)。
优选地，所述测量电极6与所述源极5之间的间隔距离大于所述测量电极6与所述漏极7之间的间隔距离，当然这并非对本发明的限制，所述测量电极6与所述源极5之间的间隔距离也可以小于所述测量电极6与所述漏极7之间的间隔距离。
具体地，所述栅极2、源极5、测量电极6及漏极7的材料为钼、铝及铜中的一种或多种的组合，所述衬底基板1为玻璃基板，所述栅极绝缘层3的材料为氧化硅和氮化硅中的一种或二者的组合。
步骤S2、将所述薄膜晶体管的源极5接地，漏极7接入第一电压，并测量流过所述薄膜晶体管的漏极7的电流和测量电极6上的电压。
步骤S3、根据流过所述薄膜晶体管的漏极7的电流和测量电极6上的电压，确定所述薄膜晶体管的沟道电阻和接触电阻；
其中，确定所述薄膜晶体管的沟道电阻和接触电阻的公式为：
Figure PCTCN2018116007-appb-000007
Figure PCTCN2018116007-appb-000008
其中，R 1为沟道电阻，R 2为接触电阻，V A为测量电极6上的电压，V 1为第一电压，X A为测量电极6与源极5之间的间隔距离，L为沟道长度，I D为流过所述薄膜晶体管的漏极7的电流。
具体地，如图5所示，所述接触电阻R 2为源极5与有源层4之间的接触电阻R 21和漏极7与有源层4之间的接触电阻R 22的和。
需要说明的是，上述测量方法的测量原理为：如图5所示，在测量电极6处可以测量到测量电极6处电压，但无电流通过，所以不存在接触电阻，根据电流与电压电阻的关系，由于源极5到测量电极6处电流与源极5到漏极7处电流相等，可以得到如下公式：
I D＝V A/(X AR 1/L+R 2)＝VD/(R 1+2R 2)；
据此可知，
Figure PCTCN2018116007-appb-000009
Figure PCTCN2018116007-appb-000010
从而，本发明通过在有源层4上设置测量电极6，进而通过测量所述测量电极6上的电压和流过漏极7的电流，即可确定所述薄膜晶体管的沟道 电阻和接触电阻，从而实现通过单颗薄膜晶体管，快速准确完成薄膜晶体管的沟道电阻和接触电阻的测量。
综上所述，本发明提供了一种薄膜晶体管结构，包括：衬底基板、设于所述衬底基板上的栅极、设于所述栅极上的栅极绝缘层、设于所述栅极绝缘层上的有源层以及设于所述有源层上的依次间隔排列的源极、测量电极和漏极；所述测量电极与所述源极之间的间隔距离不同于所述测量电极与所述漏极之间的间隔距离，在有源层上设置测量电极，进而通过测量所述测量电极上的电压和流过漏极的电流，确定所述薄膜晶体管的沟道电阻和接触电阻，能够通过单颗薄膜晶体管，快速准确完成薄膜晶体管的沟道电阻和接触电阻的测量。本发明还提供一种沟道电阻和接触电阻的测量方法，能够通过单颗薄膜晶体管，快速准确完成薄膜晶体管的沟道电阻和接触电阻的测量。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种薄膜晶体管结构，包括：衬底基板、设于所述衬底基板上的栅极、设于所述栅极上的栅极绝缘层、设于所述栅极绝缘层上的有源层以及设于所述有源层上的依次间隔排列的源极、测量电极和漏极；
    所述测量电极与所述源极之间的间隔距离不同于所述测量电极与所述漏极之间的间隔距离。
  2. 如权利要求1所述的薄膜晶体管结构，其中，所述有源层的材料为非晶硅，其包括设于所述栅极绝缘层上的非掺杂层以及位于所述源极与所述非掺杂层之间、测量电极与所述非掺杂层之间及漏极与所述非掺杂层之间的掺杂层。
  3. 如权利要求2所述的薄膜晶体管结构，其中，所述掺杂层为N型掺杂层。
  4. 如权利要求1所述的薄膜晶体管结构，其中，所述有源层的材料为金属氧化物半导体材料。
  5. 如权利要求1所述的薄膜晶体管结构，其中，所述测量电极与所述源极之间的间隔距离大于所述测量电极与所述漏极之间的间隔距离。
  6. 一种沟道电阻和接触电阻的测量方法，包括如下步骤：
    步骤S1、提供一薄膜晶体管，所述薄膜晶体管包括：衬底基板、设于所述衬底基板上的栅极、设于所述栅极上的栅极绝缘层、设于所述栅极绝缘层上的有源层以及设于所述有源层上的依次间隔排列的源极、测量电极和漏极；所述测量电极与所述源极之间的间隔距离不同于所述测量电极与所述漏极之间的间隔距离；
    步骤S2、将所述薄膜晶体管的源极接地，漏极接入第一电压，并测量流过所述薄膜晶体管的漏极的电流和测量电极上的电压；
    步骤S3、根据流过所述薄膜晶体管的漏极的电流和测量电极上的电压，确定所述薄膜晶体管的沟道电阻和接触电阻；
    其中，确定所述薄膜晶体管的沟道电阻和接触电阻的公式为：
    Figure PCTCN2018116007-appb-100001
    Figure PCTCN2018116007-appb-100002
    其中，R 1为沟道电阻，R 2为接触电阻，V A为测量电极上的电压，V 1 为第一电压，X A为测量电极与源极之间的间隔距离，L为沟道长度，I D为流过所述薄膜晶体管的漏极的电流。
  7. 如权利要求6所述的沟道电阻和接触电阻的测量方法，其中，所述有源层的材料为非晶硅，其包括设于所述栅极绝缘层上的非掺杂层以及位于所述源极与所述非掺杂层之间、测量电极与所述非掺杂层之间及漏极与所述非掺杂层之间的掺杂层。
  8. 如权利要求7所述的沟道电阻和接触电阻的测量方法，其中，所述掺杂层为N型掺杂层。
  9. 如权利要求6所述的沟道电阻和接触电阻的测量方法，其中，所述有源层的材料为金属氧化物半导体材料。
  10. 如权利要求6所述的沟道电阻和接触电阻的测量方法，其中，所述测量电极与所述源极之间的间隔距离大于所述测量电极与所述漏极之间的间隔距离。
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