WO2020082624A1 - 一种薄膜晶体管阵列基板的制备方法 - Google Patents

一种薄膜晶体管阵列基板的制备方法 Download PDF

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WO2020082624A1
WO2020082624A1 PCT/CN2019/071847 CN2019071847W WO2020082624A1 WO 2020082624 A1 WO2020082624 A1 WO 2020082624A1 CN 2019071847 W CN2019071847 W CN 2019071847W WO 2020082624 A1 WO2020082624 A1 WO 2020082624A1
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film
layer
copper
carbon composite
composite film
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French (fr)
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胡小波
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6736—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes characterised by the shape of gate insulators

Definitions

  • the invention relates to the technical field of semiconductor materials, in particular to a method for preparing a thin film transistor array substrate.
  • the yellow light process and the etching process are all exposed to the air, and the surface Cu will be partially oxidized, exposing the Cu film to the air for more than 30min.
  • the surface resistivity will increase by more than 30%, which will lead to an increase in the resistivity of Cu line; and CuO x and Cu (OH) x generated on the Cu film will cause Electro-Static discharge (ESD) phenomenon, Affect the display effect of TFT devices.
  • ESD Electro-Static discharge
  • the thicker the Cu film layer the larger the crystal grains, the larger the surface roughness, and the larger the grain boundary voids. So in the subsequent TFT process, there will be Part of O 2 and H 2 O penetrate into the film layer along the grain boundary gap, accelerate the oxidation of the surface Cu film, generate electrostatic breakdown or generate local parasitic capacitance, and further affect the display effect of the TFT device.
  • Embodiments of the present invention provide a method for preparing a thin film transistor array substrate, which prevents Cu film from being oxidized during subsequent yellowing process and etching process, thereby reducing the surface resistivity of Cu film, avoiding ESD phenomenon of Cu film, and improving the film The display effect of the transistor array substrate.
  • the first aspect of the present application provides a method for preparing a thin film transistor array substrate.
  • the method includes forming a Cu metal thin film layer on the gate insulating layer, and before the yellowing process and the etching process, in the Cu metal The step of depositing a layer of C film above the thin film layer.
  • the method includes:
  • a C film is deposited on the Cu film as a Cu film protective layer.
  • the method further includes:
  • the semiconductor layer, the source-drain electrode layer, the passivation layer, and the pixel electrode layer are sequentially manufactured.
  • processing of the C film to make a copper-carbon composite film layer includes:
  • the photoresist pattern is completed
  • a Cu film wet etching and photoresist removal process is performed to form a copper-carbon composite film layer.
  • the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer includes:
  • H 2 plasma treatment is performed on the copper-carbon composite film layer, so that the C film on the Cu film in the copper-carbon composite film layer and H + generate vaporized CH compounds to remove the C film on the Cu film in the copper-carbon composite film layer.
  • the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer includes:
  • N 2 plasma treatment is performed on the copper-carbon composite film layer, so that the C film on the Cu film in the copper-carbon composite film layer and H + generate a vaporized NH compound to remove the C film on the Cu film in the copper-carbon composite film layer.
  • the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer includes:
  • O 2 plasma treatment is performed on the copper-carbon composite film layer, so that the C film above the Cu film in the copper-carbon composite film layer and H + generate a vaporized OH compound to remove the C film above the Cu film in the copper-carbon composite film layer.
  • the step of depositing and forming a gate insulating layer includes:
  • the gate insulating layer is deposited.
  • the manufacturing method of the source-drain electrode layer is the same as the manufacturing method of the gate electrode layer.
  • the step of depositing and forming a gate electrode layer on the glass substrate, and depositing and forming a Cu film above the gate electrode layer includes:
  • a MoCu composite film layer is deposited on the glass substrate to form a gate electrode layer, wherein the Mo film is under the Cu film, the Mo film is used as the gate electrode layer, and the Cu film is a conductive functional layer.
  • the material of the gate electrode layer is MoTi, MoNb, Ti, Ta or W.
  • the step of depositing a MoCu composite film layer on the glass substrate to form a gate electrode layer includes:
  • a physical vapor deposition PVD sputtering process is used to deposit a MoCu composite film layer on the glass substrate to form a gate electrode layer.
  • the step of depositing a C film on the Cu film as a Cu film protective layer includes:
  • a layer of C film is deposited on the Cu film by a sputtering process as a Cu film protective layer, and the thickness of the C film is 50 ⁇ -200 ⁇ .
  • the thickness of the Mo film is 100-500 angstroms.
  • the present application provides a method for manufacturing a thin film transistor array substrate, the method includes:
  • the semiconductor layer, the source-drain electrode layer, the passivation layer, and the pixel electrode layer are sequentially manufactured.
  • processing of the C film to make a copper-carbon composite film layer includes:
  • the photoresist pattern is completed
  • a Cu film wet etching and photoresist removal process is performed to form a copper-carbon composite film layer.
  • the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer includes:
  • H 2 plasma treatment is performed on the copper-carbon composite film layer, so that the C film on the Cu film in the copper-carbon composite film layer and H + generate vaporized CH compounds to remove the C film on the Cu film in the copper-carbon composite film layer.
  • the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer includes:
  • N 2 plasma treatment is performed on the copper-carbon composite film layer, so that the C film on the Cu film in the copper-carbon composite film layer and H + generate a vaporized NH compound to remove the C film on the Cu film in the copper-carbon composite film layer.
  • the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer includes:
  • O 2 plasma treatment is performed on the copper-carbon composite film layer, so that the C film above the Cu film in the copper-carbon composite film layer and H + generate a vaporized OH compound to remove the C film above the Cu film in the copper-carbon composite film layer.
  • the step of depositing and forming a gate electrode layer on the glass substrate, and depositing and forming a Cu film above the gate electrode layer includes:
  • a MoCu composite film layer is deposited on the glass substrate to form a gate electrode layer, wherein the Mo film is under the Cu film, the Mo film is used as the gate electrode layer, and the Cu film is a conductive functional layer.
  • the method of the embodiment of the present invention includes the steps of depositing a C film on the Cu metal thin film layer after forming the Cu metal thin film layer on the gate insulating layer, and before the yellow light process and the etching process.
  • the Cu film is isolated from the outside world, which can prevent the Cu film from being oxidized during the subsequent yellowing process and etching process, thereby reducing the surface resistivity of the Cu film, avoiding the ESD phenomenon of the Cu film, and improving the thin film transistor array The display effect of the substrate.
  • FIG. 1 is a schematic flowchart of an embodiment of a method for preparing a thin film transistor array substrate provided by an embodiment of the present invention
  • FIG. 2 is a schematic structural view of a method for manufacturing a thin film transistor array substrate provided by an embodiment of the present invention after a MoCu composite film layer is deposited on a glass substrate to form a gate electrode layer;
  • FIG. 3 is a schematic structural view of a method for preparing a thin film transistor array substrate provided by an embodiment of the present invention after depositing a layer of C film on the Cu film as a Cu film protective layer;
  • H 2 plasma treatment is performed on a copper-carbon composite film layer, so that the C film and H + on the Cu film in the copper-carbon composite film layer generate vaporized CH compounds to Schematic diagram of the structure after removing the C film above the Cu film in the copper-carbon composite film layer;
  • FIG. 5 is a schematic structural view of a copper-carbon composite film layer formed by performing a Cu film wet etching and photoresist removal process in a method for preparing a thin film transistor array substrate provided by an embodiment of the present invention
  • FIG. 6 is a schematic structural view of a method for preparing a thin film transistor array substrate provided by an embodiment of the present invention after performing H 2 plasma treatment on a copper-carbon composite film layer to remove the C film above the Cu film in the copper-carbon composite film layer;
  • FIG. 7 is a schematic structural view of a method for manufacturing a thin film transistor array substrate provided by an embodiment of the present invention after a gate insulating layer is deposited;
  • FIG. 8 is a schematic structural view of a thin film transistor array substrate formed by sequentially manufacturing a semiconductor layer, a source-drain electrode layer, a passivation layer, and a pixel electrode layer in the method for manufacturing a thin film transistor array substrate provided by an embodiment of the present invention.
  • Thin-film transistors are one of the types of field-effect transistors, which are roughly fabricated by depositing various thin films on the substrate, such as semiconductor active layers, dielectric layers, and metal electrode layers. Thin film transistors play a very important role in the performance of display devices.
  • An embodiment of the present invention provides a method for manufacturing a thin film transistor array substrate.
  • the method includes forming a Cu metal thin film layer on a gate insulating layer, and depositing the Cu metal thin film layer before the yellow light process and the etching process The step of applying a layer of C film.
  • the method of the embodiment of the present invention includes the steps of depositing a C film on the Cu metal thin film layer after forming the Cu metal thin film layer on the gate insulating layer, and before the yellow light process and the etching process.
  • the Cu film is isolated from the outside world, which can prevent the Cu film from being oxidized during the subsequent yellowing process and etching process, thereby reducing the surface resistivity of the Cu film, avoiding the ESD phenomenon of the Cu film, and improving the thin film transistor array The display effect of the substrate.
  • the method in the embodiment of the present invention includes: depositing a gate electrode layer on a glass substrate, depositing a Cu film on the gate electrode layer; depositing a C film on the Cu film as a Cu film The protective layer.
  • the method in the embodiment of the present invention further includes: processing the C film to form a copper-carbon composite film layer; performing plasma treatment on the copper-carbon composite film layer to remove the Cu film on the copper-carbon composite film layer C film; deposition to form a gate insulating layer; the semiconductor layer, the source-drain electrode layer, the passivation layer, and the pixel electrode layer are sequentially manufactured.
  • the processing of the C film to make a copper-carbon composite film layer includes: preparing a photoresist pattern; performing plasma treatment on the C film on the glass substrate so that the C film without the photoresist protection generates gas Compound; Wet etching of Cu film and photoresist removal process to form a copper-carbon composite film layer.
  • the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer includes: performing H 2 plasma treatment on the copper-carbon composite film layer , So that the C film above the Cu film in the copper-carbon composite film layer and H + generate vaporized CH compounds to remove the C film above the Cu film in the copper-carbon composite film layer.
  • the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer includes: performing N 2 plasma treatment on the copper-carbon composite film layer , So that the C film above the Cu film in the copper-carbon composite film layer and H + generate a vaporized NH compound to remove the C film above the Cu film in the copper-carbon composite film layer.
  • the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer includes: performing O 2 plasma treatment on the copper-carbon composite film layer , So that the C film above the Cu film in the copper-carbon composite film layer and H + generate vaporized OH compounds to remove the C film above the Cu film in the copper-carbon composite film layer.
  • the step of depositing and forming the gate insulating layer includes: removing the C film above the Cu film in the copper-carbon composite film layer, exposing the Cu film, and then performing the gate insulating layer deposition.
  • the manufacturing method of the source-drain electrode layer is the same as the manufacturing method of the gate electrode layer.
  • the step of depositing and forming a gate electrode layer on the glass substrate, and the step of depositing and forming a Cu film above the gate electrode layer includes: depositing a MoCu composite film layer on the glass substrate to form a gate electrode layer, wherein, Mo The film is under the Cu film, the Mo film serves as the gate electrode layer, and the Cu film serves as the conductive functional layer.
  • the material of the gate electrode layer is MoTi, MoNb, Ti, Ta or W. Further, the thickness of the Mo film is 100-500 angstroms.
  • the step of depositing the MoCu composite film layer on the glass substrate to form the gate electrode layer includes: depositing the MoCu composite film layer on the glass substrate by a physical vapor deposition PVD sputtering process to form the gate electrode layer.
  • the step of depositing a C film on the Cu film as a Cu film protective layer includes: depositing a C film on the Cu film as a Cu film protective layer by a sputtering process
  • the thickness of the C film is 50 ⁇ ⁇ 200 ⁇ .
  • FIG. 1 it is a schematic diagram of an embodiment of a method for preparing a thin film transistor array substrate in an embodiment of the present invention.
  • the method includes:
  • the step of depositing and forming a gate electrode layer on the glass substrate, and the step of depositing and forming a Cu film above the gate electrode layer may further include: depositing a MoCu composite film layer on the glass substrate to form a gate electrode layer.
  • the step of forming a gate electrode layer by depositing a MoCu composite film layer on a glass substrate may specifically include: using physical vapor deposition (Physical Vapor) Deposition (PVD) sputtering process deposits a MoCu composite film layer on the glass substrate to form a gate electrode layer.
  • the Mo film is under the Cu film
  • the Mo film is used as the gate electrode layer
  • the thickness of the Mo film may be 100-500 angstroms.
  • the Cu film is a conductive functional layer, and the thickness is not limited.
  • the thickness of the Cu film can be used according to the conventional method in the prior art.
  • the material of the gate electrode layer may also be MoTi, MoNb, Ti, Ta, or W, which is not limited herein.
  • a C film can be deposited on the Cu film by a sputtering process as a Cu film protective layer, and the thickness of the C film is 50 ⁇ -200 ⁇ .
  • the sputtering process is a process in which particles (ions or neutral atoms, molecules) of a certain energy bombard a solid surface so that atoms or molecules near the surface of the solid obtain sufficient energy to finally escape from the solid surface. Sputtering can only be carried out under a certain vacuum.
  • the sputtering process is a common technical method in the technical field, and it is not described in detail here how to use the sputtering process to deposit a layer of C film on the Cu film.
  • the thickness of the C film is preferably 60 ⁇ to 120 ⁇ .
  • the step of processing the C film to form the copper-carbon composite film layer includes: preparing a photoresist pattern; performing plasma treatment on the C film on the glass substrate, so that the C film without the photoresist protection generates gas compounds; A Cu film wet etching and photoresist removal process is performed to form a copper-carbon composite film layer.
  • H 2 plasma treatment, N 2 plasma treatment, O 2 plasma treatment, or the like may be used.
  • the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film above the Cu film in the copper-carbon composite film layer may include: performing H 2 plasma treatment on the copper-carbon composite film layer to make the copper carbon The C film and H + on the Cu film in the composite film layer generate vaporized CH compounds to remove the C film on the Cu film in the copper-carbon composite film layer, as shown in FIG. 4.
  • the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film above the Cu film in the copper-carbon composite film layer includes: performing N 2 plasma treatment on the copper-carbon composite film layer to make the copper-carbon composite film The C film above the Cu film in the layer and H + generate vaporized NH compounds to remove the C film above the Cu film in the copper-carbon composite film layer.
  • the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film above the Cu film in the copper-carbon composite film layer includes: performing O 2 plasma treatment on the copper-carbon composite film layer to make the copper-carbon composite film The C film and H + on the Cu film in the layer generate vaporized OH compounds to remove the C film on the Cu film in the copper-carbon composite film layer.
  • a Cu film wet etching and photoresist removal process is performed to form a copper-carbon composite film layer.
  • the Cu and C films are etched away, leaving the Cu and C films at both ends of the channel.
  • S104 Perform plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer.
  • the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer may also adopt H 2 plasma treatment, N 2 plasma treatment, or O 2 plasma treatment.
  • plasma processing may be performed on the C film on the glass substrate, so that the step of generating a gas compound in the C film that is not protected by the photoresist is implemented, and details are not described herein.
  • FIG. 6 it is a schematic view of the structure after the copper-carbon composite film layer is subjected to H 2 plasma treatment again to remove the C film on the Cu film in the copper-carbon composite film layer.
  • the gate insulating layer refers to the GI layer.
  • the GI layer is formed by a process in an LTPS called GI Deposition, which is called GI layer deposition.
  • GI is the insulating layer between the gate metal and semiconductor Si in TFT, usually SiNx / SiOx is called Gate Insulator gate insulating layer.
  • the gate insulating layer is deposited.
  • the semiconductor layer, the source-drain electrode layer, the passivation layer, and the pixel electrode layer are sequentially manufactured.
  • FIG. 8 it is a thin-film transistor array substrate formed after sequentially manufacturing a semiconductor layer, a source-drain electrode layer, a passivation layer, and a pixel electrode layer.
  • the method of the embodiment of the present invention includes after forming a Cu metal thin film layer on the gate insulating layer, and before the yellow light process and the etching process, depositing a C film on the Cu metal thin film layer, and using the C film to be vaporized
  • the characteristic of the reaction is to vaporize the C film, and the C film will not remain on the product, reducing the surface resistivity of the Cu film, avoiding the ESD phenomenon of the Cu film, and improving the display effect of the thin film transistor array substrate.

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Abstract

一种薄膜晶体管阵列基板的制备方法。该方法包括在栅极绝缘层上形成Cu金属薄膜层之后，在黄光制程和刻蚀制程之前，在Cu金属薄膜层上方沉积上一层C膜的步骤。本发明实施例中降低了Cu膜表面电阻率，避免了Cu膜产生ESD现象，提高了薄膜晶体管阵列基板的显示效果。

Description

一种薄膜晶体管阵列基板的制备方法 技术领域
本发明涉及半导体材料技术领域，具体涉及一种薄膜晶体管阵列基板的制备方法。
 背景技术
随着平板显示技术的发展，人们对显示器尺寸、分辨率和画面刷新速率的追求越来越高，因此采用铜取代铝作为导电金属材料。
现有的阵列基板工艺方法中，Cu膜沉积结束后，经过黄光制程，刻蚀制程，都是暴露在空气中，表层的Cu会有部分被氧化，将Cu膜暴露在空气当中超过30min，其表面电阻率会升高30%以上，从而会导致Cu line的电阻率升高；且Cu膜上产生的CuO x及Cu(OH) x会导致静电释放（Electro-Static discharge，ESD）现象，影响TFT器件的显示效果。
技术问题
在TFT制程中，Cu膜沉积结束后，Cu膜层越厚，其晶粒就会越大，表面粗糙度增大，晶界的空隙也随之变大，如此在后续TFT制程中，会有部分O 2和H 2O沿着晶界空隙渗透到膜层内部，加速表层Cu膜的氧化，产生静电击穿或产生局部寄生电容，进一步影响TFT器件的显示效果。
技术解决方案
本发明实施例提供一种薄膜晶体管阵列基板的制备方法，避免后续黄光制程和刻蚀制程时Cu膜被氧化，从而降低了Cu膜表面电阻率，避免了Cu膜产生ESD现象，提高了薄膜晶体管阵列基板的显示效果。
为解决上述问题，本申请第一方面提供一种薄膜晶体管阵列基板的制备方法，该方法包括在栅极绝缘层上形成Cu金属薄膜层之后，在黄光制程和刻蚀制程之前，在Cu金属薄膜层上方沉积上一层C膜的步骤。
进一步的，所述方法包括：
在玻璃基板上沉积形成栅极电极层，所述栅极电极层上方沉积形成Cu膜；
在所述Cu膜之上沉积一层C膜，作为Cu膜保护层。
进一步的，所述方法还包括：
对C膜进行处理，形成铜碳复合膜层；
对所述铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜；
沉积形成栅极绝缘层；
依次进行半导体层、源漏电极层、钝化层、像素电极层的制作。
进一步的，所述对C膜进行处理，以制作铜碳复合膜层，包括：
制作完成光刻胶图案；
对玻璃基板上的C膜进行等离子处理，使得没有光刻胶保护的C膜生成气体化合物；
进行Cu膜湿法刻蚀及光刻胶去除工艺，形成铜碳复合膜层。
进一步的，所述对所述铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜的步骤，包括：
对所述铜碳复合膜层进行H 2等离子处理，使得铜碳复合膜层中Cu膜上方C膜与H+生成气化C-H化合物，以去除铜碳复合膜层中Cu膜之上的C膜。
进一步的，所述对所述铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜的步骤，包括：
对所述铜碳复合膜层进行N 2等离子处理，使得铜碳复合膜层中Cu膜上方C膜与H+生成气化N-H化合物，以去除铜碳复合膜层中Cu膜之上的C膜。
进一步的，所述对所述铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜的步骤，包括：
对所述铜碳复合膜层进行O 2等离子处理，使得铜碳复合膜层中Cu膜上方C膜与H+生成气化O-H化合物，以去除铜碳复合膜层中Cu膜之上的C膜。
进一步的，所述沉积形成栅极绝缘层的步骤，包括：
在去除铜碳复合膜层中Cu膜之上的C膜，将Cu膜暴露出来之后，再进行栅极绝缘层沉积。
进一步的，所述源漏电极层的制作方法和所述栅极电极层的制作方法一致。
进一步的，所述在玻璃基板上沉积形成栅极电极层，所述栅极电极层上方沉积形成Cu膜的步骤，包括：
在玻璃基板上沉积MoCu复合膜层形成栅极电极层，其中，Mo膜在Cu膜之下，Mo膜作为栅极电极层，Cu膜为导电功能层。
进一步的，所述栅极电极层材料为MoTi、MoNb、Ti、Ta或W。
进一步的，所述在玻璃基板上沉积MoCu复合膜层形成栅极电极层的步骤，包括：
用物理气相沉积PVD溅射工艺在玻璃基板上沉积MoCu复合膜层形成栅极电极层。
进一步的，所述在所述Cu膜之上沉积一层C膜，作为Cu膜保护层的步骤，包括：
用溅射工艺在所述Cu膜之上沉积一层C膜，作为Cu膜保护层，所述C膜厚度50Å~200Å。
进一步的，所述Mo膜厚度为100-500埃。
第二方面，本申请提供一种薄膜晶体管阵列基板的制备方法，所述方法包括：
在玻璃基板上沉积形成栅极电极层，所述栅极电极层上方沉积形成Cu膜；
在所述Cu膜之上沉积一层C膜，作为Cu膜保护层；
对C膜进行处理，形成铜碳复合膜层；
对所述铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜；
沉积形成栅极绝缘层；
依次进行半导体层、源漏电极层、钝化层、像素电极层的制作。
进一步的，所述对C膜进行处理，以制作铜碳复合膜层，包括：
制作完成光刻胶图案；
对玻璃基板上的C膜进行等离子处理，使得没有光刻胶保护的C膜生成气体化合物；
进行Cu膜湿法刻蚀及光刻胶去除工艺，形成铜碳复合膜层。
进一步的，所述对所述铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜的步骤，包括：
对所述铜碳复合膜层进行H 2等离子处理，使得铜碳复合膜层中Cu膜上方C膜与H+生成气化C-H化合物，以去除铜碳复合膜层中Cu膜之上的C膜。
进一步的，所述对所述铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜的步骤，包括：
对所述铜碳复合膜层进行N 2等离子处理，使得铜碳复合膜层中Cu膜上方C膜与H+生成气化N-H化合物，以去除铜碳复合膜层中Cu膜之上的C膜。
进一步的，所述对所述铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜的步骤，包括：
对所述铜碳复合膜层进行O 2等离子处理，使得铜碳复合膜层中Cu膜上方C膜与H+生成气化O-H化合物，以去除铜碳复合膜层中Cu膜之上的C膜。
进一步的，所述在玻璃基板上沉积形成栅极电极层，所述栅极电极层上方沉积形成Cu膜的步骤，包括：
在玻璃基板上沉积MoCu复合膜层形成栅极电极层，其中，Mo膜在Cu膜之下，Mo膜作为栅极电极层，Cu膜为导电功能层。
 有益效果
本发明实施例方法包括在栅极绝缘层上形成Cu金属薄膜层之后，在黄光制程和刻蚀制程之前，在Cu金属薄膜层上方沉积上一层C膜的步骤。本发明实施例中将Cu膜与外界隔绝，可以避免后续黄光制程和刻蚀制程时Cu膜被氧化，从而降低了Cu膜表面电阻率，避免了Cu膜产生ESD现象，提高了薄膜晶体管阵列基板的显示效果。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的薄膜晶体管阵列基板的制备方法的一个实施例流程示意图；
图2是本发明实施例提供的薄膜晶体管阵列基板的制备方法中在玻璃基板上沉积MoCu复合膜层形成栅极电极层后的结构示意图；
图3是本发明实施例提供的薄膜晶体管阵列基板的制备方法中在Cu膜之上沉积一层C膜，作为Cu膜保护层后的结构示意图；
图4是本发明实施例提供的薄膜晶体管阵列基板的制备方法中对铜碳复合膜层进行H 2等离子处理，使得铜碳复合膜层中Cu膜上方C膜与H+生成气化C-H化合物，以去除铜碳复合膜层中Cu膜之上的C膜后的结构示意图；
图5是本发明实施例提供的薄膜晶体管阵列基板的制备方法中行Cu膜湿法刻蚀及光刻胶去除工艺，形成铜碳复合膜层后的结构示意图；
图6是本发明实施例提供的薄膜晶体管阵列基板的制备方法中对铜碳复合膜层进行H 2等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜后的结构示意图；
图7是本发明实施例提供的薄膜晶体管阵列基板的制备方法中进行栅极绝缘层沉积后的结构示意图；
图8是本发明实施例提供的薄膜晶体管阵列基板的制备方法中依次进行半导体层、源漏电极层、钝化层、像素电极层的制作，形成的薄膜晶体管阵列基板的结构示意图。
 本发明的实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
薄膜晶体管（Thin-film transistor，TFT）是场效应晶体管的种类之一，大略的制作方式是在基板上沉积各种不同的薄膜，如半导体主动层、介电层和金属电极层等。薄膜晶体管对显示器件的工作性能具有十分重要的作用.
本发明实施例中提供一种薄膜晶体管阵列基板的制备方法，所述方法包括在栅极绝缘层上形成Cu金属薄膜层之后，在黄光制程和刻蚀制程之前，在Cu金属薄膜层上方沉积上一层C膜的步骤。
本发明实施例方法包括在栅极绝缘层上形成Cu金属薄膜层之后，在黄光制程和刻蚀制程之前，在Cu金属薄膜层上方沉积上一层C膜的步骤。本发明实施例中将Cu膜与外界隔绝，可以避免后续黄光制程和刻蚀制程时Cu膜被氧化，从而降低了Cu膜表面电阻率，避免了Cu膜产生ESD现象，提高了薄膜晶体管阵列基板的显示效果。
进一步的，本发明实施例中方法包括：在玻璃基板上沉积形成栅极电极层，所述栅极电极层上方沉积形成Cu膜；在所述Cu膜之上沉积一层C膜，作为Cu膜保护层。
进一步的，本发明实施例中方法还包括：对C膜进行处理，形成铜碳复合膜层；对所述铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜；沉积形成栅极绝缘层；依次进行半导体层、源漏电极层、钝化层、像素电极层的制作。
进一步的，所述对C膜进行处理，以制作铜碳复合膜层，包括：制作完成光刻胶图案；对玻璃基板上的C膜进行等离子处理，使得没有光刻胶保护的C膜生成气体化合物；进行Cu膜湿法刻蚀及光刻胶去除工艺，形成铜碳复合膜层。
进一步的，所述对所述铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜的步骤，包括：对所述铜碳复合膜层进行H 2等离子处理，使得铜碳复合膜层中Cu膜上方C膜与H+生成气化C-H化合物，以去除铜碳复合膜层中Cu膜之上的C膜。
进一步的，所述对所述铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜的步骤，包括：对所述铜碳复合膜层进行N 2等离子处理，使得铜碳复合膜层中Cu膜上方C膜与H+生成气化N-H化合物，以去除铜碳复合膜层中Cu膜之上的C膜。
进一步的，所述对所述铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜的步骤，包括：对所述铜碳复合膜层进行O 2等离子处理，使得铜碳复合膜层中Cu膜上方C膜与H+生成气化O-H化合物，以去除铜碳复合膜层中Cu膜之上的C膜。
进一步的，所述沉积形成栅极绝缘层的步骤，包括：在去除铜碳复合膜层中Cu膜之上的C膜，将Cu膜暴露出来之后，再进行栅极绝缘层沉积。
进一步的，所述源漏电极层的制作方法和所述栅极电极层的制作方法一致。
进一步的，所述在玻璃基板上沉积形成栅极电极层，所述栅极电极层上方沉积形成Cu膜的步骤，包括：在玻璃基板上沉积MoCu复合膜层形成栅极电极层，其中，Mo膜在Cu膜之下，Mo膜作为栅极电极层，Cu膜为导电功能层。
进一步的，所述栅极电极层材料为MoTi、MoNb、Ti、Ta或W。进一步的，所述Mo膜厚度为100-500埃。
进一步的，所述在玻璃基板上沉积MoCu复合膜层形成栅极电极层的步骤，包括：用物理气相沉积PVD溅射工艺在玻璃基板上沉积MoCu复合膜层形成栅极电极层。
进一步的，所述在所述Cu膜之上沉积一层C膜，作为Cu膜保护层的步骤，包括：用溅射工艺在所述Cu膜之上沉积一层C膜，作为Cu膜保护层，所述C膜厚度50Å~200Å。
如图1所示，为本发明实施例中薄膜晶体管阵列基板的制备方法的一个实施例示意图，该方法包括：
S101、在玻璃基板上沉积形成栅极电极层，所述栅极电极层上方沉积形成Cu膜。
其中，该在玻璃基板上沉积形成栅极电极层，所述栅极电极层上方沉积形成Cu膜的步骤可以进一步包括：在玻璃基板上沉积MoCu复合膜层形成栅极电极层。
进一步的，如图2所示，该在玻璃基板上沉积MoCu复合膜层形成栅极电极层的步骤，具体可以包括：用物理气相沉积物理气相沉积(Physical Vapor Deposition，PVD)溅射工艺在玻璃基板上沉积MoCu复合膜层形成栅极电极层。其中，Mo膜在Cu膜之下，Mo膜作为栅极电极层，Mo膜厚度可以为100-500埃。Cu膜为导电功能层，厚度不作限制，可以按现有技术中惯用手段采用的Cu膜厚度。另外，该栅极电极层材料还可以为MoTi、MoNb、Ti、Ta或W，此处不作限定。
S102、在Cu膜之上沉积一层C膜，作为Cu膜保护层。
具体的，如图3所示，可以用溅射工艺在Cu膜之上沉积一层C膜，作为Cu膜保护层，该C膜厚度50Å~200Å。溅射工艺是以一定能量的粒子（离子或中性原子、分子）轰击固体表面，使固体近表面的原子或分子获得足够大的能量而最终逸出固体表面的工艺。溅射只能在一定的真空状态下进行。溅射工艺为本技术领域惯用技术手段，此处不再详细描述如何利用溅射工艺在Cu膜之上沉积一层C膜。
另外，本发明实施例中，为了在达到良好的保护Cu膜的作用，同时避免后期C膜气化成气体化合物难度增加，C膜厚度优选为60Å~120Å。
S103、对C膜进行处理，形成铜碳复合膜层。
其中，该对C膜进行处理，形成铜碳复合膜层的步骤包括：制作完成光刻胶图案；对玻璃基板上的C膜进行等离子处理，使得没有光刻胶保护的C膜生成气体化合物；进行Cu膜湿法刻蚀及光刻胶去除工艺，形成铜碳复合膜层。
进一步的，对玻璃基板上的C膜进行等离子处理，使得没有光刻胶保护的C膜生成气体化合物的步骤中，可以采用H 2等离子处理、N 2等离子处理或O 2等离子处理等。
具体的，该对铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜的步骤，可以包括：对铜碳复合膜层进行H 2等离子处理，使得铜碳复合膜层中Cu膜上方C膜与H+生成气化C-H化合物，以去除铜碳复合膜层中Cu膜之上的C膜，具体如图4所示。或者，该对铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜的步骤，包括：对铜碳复合膜层进行N 2等离子处理，使得铜碳复合膜层中Cu膜上方C膜与H+生成气化N-H化合物，以去除铜碳复合膜层中Cu膜之上的C膜。或者，该对铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜的步骤，包括：对铜碳复合膜层进行O 2等离子处理，使得铜碳复合膜层中Cu膜上方C膜与H+生成气化O-H化合物，以去除铜碳复合膜层中Cu膜之上的C膜。
在使得没有光刻胶保护的C膜生成气体化合物之后，如图5所示，进行Cu膜湿法刻蚀及光刻胶去除工艺，形成铜碳复合膜层，此时玻璃基板上方沟道内的Cu膜和C膜刻蚀掉了，保留沟道两端Cu膜和C膜。
S104、对铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜。
同样的，该对铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜的步骤也可以采用H 2等离子处理、N 2等离子处理或O 2等离子处理。具体可以步骤S103中对玻璃基板上的C膜进行等离子处理，使得没有光刻胶保护的C膜生成气体化合物的步骤的实现过程，此处不再赘述。如图6所示，为再次对铜碳复合膜层进行H 2等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜后的结构示意图。
S105、沉积形成栅极绝缘层。
其中，栅极绝缘层指的是GI层，GI层通过一个LTPS中的工艺，叫GI Deposition也就是GI层沉积形成。GI是TFT中，栅极金属和半导体Si之间的绝缘层，通常为SiNx/SiOx称之为Gate Insulator 栅极绝缘层。
具体的，如图7所示，在去除铜碳复合膜层中Cu膜之上的C膜，将Cu膜暴露出来之后，再进行栅极绝缘层沉积。
S106、依次进行半导体层、源漏电极层、钝化层、像素电极层的制作。
本发明实施例中，进行半导体层、源漏电极层、钝化层、像素电极层的制作的步骤具体可以参照现有技术，具体此处不作限定。如图8所示，为依次进行半导体层、源漏电极层、钝化层、像素电极层的制作之后，形成的薄膜晶体管阵列基板。
本发明实施例方法包括在栅极绝缘层上形成Cu金属薄膜层之后，在黄光制程和刻蚀制程之前，在Cu金属薄膜层上方沉积上一层C膜，并利用C薄膜可以被气化反应的特性，将C膜气化反应掉，C膜不会保留在产品上，降低了Cu膜表面电阻率，避免了Cu膜产生ESD现象，提高了薄膜晶体管阵列基板的显示效果。
以上对本发明实施例所提供的一种薄膜晶体管阵列基板的制备方法进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (20)

  1. 一种薄膜晶体管阵列基板的制备方法，其中，所述方法包括在栅极绝缘层上形成Cu金属薄膜层之后，在黄光制程和刻蚀制程之前，在Cu金属薄膜层上方沉积上一层C膜的步骤。
  2. 根据权利要求1所述的薄膜晶体管阵列基板的制备方法，其中，所述方法包括：
    在玻璃基板上沉积形成栅极电极层，所述栅极电极层上方沉积形成Cu膜；
    在所述Cu膜之上沉积一层C膜，作为Cu膜保护层。
  3. 根据权利要求2所述的薄膜晶体管阵列基板的制备方法，其中，所述方法还包括：
    对C膜进行处理，形成铜碳复合膜层；
    对所述铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜；
    沉积形成栅极绝缘层；
    依次进行半导体层、源漏电极层、钝化层、像素电极层的制作。
  4. 根据权利要求3所述的薄膜晶体管阵列基板的制备方法，其中，所述对C膜进行处理，以制作铜碳复合膜层，包括：
    制作完成光刻胶图案；
    对玻璃基板上的C膜进行等离子处理，使得没有光刻胶保护的C膜生成气体化合物；
    进行Cu膜湿法刻蚀及光刻胶去除工艺，形成铜碳复合膜层。
  5. 根据权利要求3所述的薄膜晶体管阵列基板的制备方法，其中，所述对所述铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜的步骤，包括：
    对所述铜碳复合膜层进行H 2等离子处理，使得铜碳复合膜层中Cu膜上方C膜与H+生成气化C-H化合物，以去除铜碳复合膜层中Cu膜之上的C膜。
  6. 根据权利要求3所述的薄膜晶体管阵列基板的制备方法，其中，所述对所述铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜的步骤，包括：
    对所述铜碳复合膜层进行N 2等离子处理，使得铜碳复合膜层中Cu膜上方C膜与H+生成气化N-H化合物，以去除铜碳复合膜层中Cu膜之上的C膜。
  7. 根据权利要求3所述的薄膜晶体管阵列基板的制备方法，其中，所述对所述铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜的步骤，包括：
    对所述铜碳复合膜层进行O 2等离子处理，使得铜碳复合膜层中Cu膜上方C膜与H+生成气化O-H化合物，以去除铜碳复合膜层中Cu膜之上的C膜。
  8. 根据权利要求7所述的薄膜晶体管的制备方法，其中，所述沉积形成栅极绝缘层的步骤，包括：
    在去除铜碳复合膜层中Cu膜之上的C膜，将Cu膜暴露出来之后，再进行栅极绝缘层沉积。
  9. 根据权利要求3所述的薄膜晶体管阵列基板的制备方法，其中，所述源漏电极层的制作方法和所述栅极电极层的制作方法一致。
  10. 根据权利要求3所述的薄膜晶体管阵列基板的制备方法，其中，所述在玻璃基板上沉积形成栅极电极层，所述栅极电极层上方沉积形成Cu膜的步骤，包括：
    在玻璃基板上沉积MoCu复合膜层形成栅极电极层，其中，Mo膜在Cu膜之下，Mo膜作为栅极电极层，Cu膜为导电功能层。
  11. 根据权利要求2所述的薄膜晶体管阵列基板的制备方法，其中，所述栅极电极层材料为MoTi、MoNb、Ti、Ta或W。
  12. 根据权利要求2所述的薄膜晶体管阵列基板的制备方法，其中，所述在玻璃基板上沉积MoCu复合膜层形成栅极电极层的步骤，包括：
    用物理气相沉积PVD溅射工艺在玻璃基板上沉积MoCu复合膜层形成栅极电极层。
  13. 根据权利要求2所述的薄膜晶体管阵列基板的制备方法，其中，所述在所述Cu膜之上沉积一层C膜，作为Cu膜保护层的步骤，包括：
    用溅射工艺在所述Cu膜之上沉积一层C膜，作为Cu膜保护层，所述C膜厚度50Å~200Å。
  14. 根据权利要求2所述的薄膜晶体管阵列基板的制备方法，其中，所述Mo膜厚度为100-500埃。
  15. 一种薄膜晶体管阵列基板的制备方法，其中，所述方法包括：
    在玻璃基板上沉积形成栅极电极层，所述栅极电极层上方沉积形成Cu膜；
    在所述Cu膜之上沉积一层C膜，作为Cu膜保护层；
    对C膜进行处理，形成铜碳复合膜层；
    对所述铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜；
    沉积形成栅极绝缘层；
    依次进行半导体层、源漏电极层、钝化层、像素电极层的制作。
  16. 根据权利15所述的薄膜晶体管阵列基板的制备方法，其中，所述对C膜进行处理，以制作铜碳复合膜层，包括：
    制作完成光刻胶图案；
    对玻璃基板上的C膜进行等离子处理，使得没有光刻胶保护的C膜生成气体化合物；
    进行Cu膜湿法刻蚀及光刻胶去除工艺，形成铜碳复合膜层。
  17. 根据权利要求15所述的薄膜晶体管阵列基板的制备方法，其中，所述对所述铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜的步骤，包括：
    对所述铜碳复合膜层进行H 2等离子处理，使得铜碳复合膜层中Cu膜上方C膜与H+生成气化C-H化合物，以去除铜碳复合膜层中Cu膜之上的C膜。
  18. 根据权利要求15所述的薄膜晶体管阵列基板的制备方法，其中，所述对所述铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜的步骤，包括：
    对所述铜碳复合膜层进行N 2等离子处理，使得铜碳复合膜层中Cu膜上方C膜与H+生成气化N-H化合物，以去除铜碳复合膜层中Cu膜之上的C膜。
  19. 根据权利要求15所述的薄膜晶体管阵列基板的制备方法，其中，所述对所述铜碳复合膜层进行等离子处理，以去除铜碳复合膜层中Cu膜之上的C膜的步骤，包括：
    对所述铜碳复合膜层进行O 2等离子处理，使得铜碳复合膜层中Cu膜上方C膜与H+生成气化O-H化合物，以去除铜碳复合膜层中Cu膜之上的C膜。
  20. 根据权利要求15所述的薄膜晶体管阵列基板的制备方法，其中，所述在玻璃基板上沉积形成栅极电极层，所述栅极电极层上方沉积形成Cu膜的步骤，包括：
    在玻璃基板上沉积MoCu复合膜层形成栅极电极层，其中，Mo膜在Cu膜之下，Mo膜作为栅极电极层，Cu膜为导电功能层。
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