WO2020077853A1 - 阵列基板及采用该阵列基板的显示装置 - Google Patents

阵列基板及采用该阵列基板的显示装置 Download PDF

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WO2020077853A1
WO2020077853A1 PCT/CN2018/124063 CN2018124063W WO2020077853A1 WO 2020077853 A1 WO2020077853 A1 WO 2020077853A1 CN 2018124063 W CN2018124063 W CN 2018124063W WO 2020077853 A1 WO2020077853 A1 WO 2020077853A1
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line
circular
array substrate
gate
substrate according
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刘杰
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the invention relates to the field of liquid crystal display, in particular to an array substrate and a display device using the array substrate.
  • OLED Organic Light-Emitting Diode (organic light-emitting diode) display device
  • OLED Organic Light-Emitting Diode (organic light-emitting diode) display device
  • OLED display devices are current-driven.
  • the amount of light emitted by the organic light-emitting material is controlled by the magnitude of the current, which requires that the OLED display device must accurately and stably control the driving current.
  • the stable output current can be obtained by using the current characteristics of the array substrate in the saturation region, because at this time The output current is independent of the output voltage V DS of the array substrate, and a stable current can be obtained at the drain end. That is, the output resistance of the array substrate is high.
  • the size of the output current I DS is related to the width-to-length ratio of the array substrate W / L.
  • a key issue in achieving flexibility in displays is how to maintain the stability of the array substrate.
  • the channel is extremely easy to disconnect when the screen is bent.
  • the film layer of the array substrate will be broken due to the tensile force.
  • the characteristics of the array substrate may have two possible changes. If the length direction of the array substrate is perpendicular to the bending direction, the channel region of the array substrate will change, but it will not be completely disconnected. As another example, when the length direction of the array substrate is the same as the bending direction, the channel region of the array substrate will be affected more than the first case, and it may even be completely broken. This break may cause the signal voltage to be unable to transmit To the pixel electrode line, resulting in poor display.
  • the square array substrate has a large change in the array substrate characteristics when it is bent, and the voltage will change to varying degrees when bending occurs, resulting in changes in display performance. How to maintain the characteristics of the array substrate in the curved state does not change is the most critical issue in the flexible display industry.
  • the ring array substrate is an array substrate with a ring structure, which has the advantages of large wireless output resistance and little change in characteristics in a bent state.
  • the source and drain traces of the ring array substrate completely overlap the gate traces, and the parasitic capacitance is very high. Large, which limits the application of Hall ring array substrates in high-resolution display devices.
  • the parasitic capacitance in the panel is one of the factors affecting the refresh rate of the panel.
  • the presence of parasitic capacitance affects the stability of the circuit signal, which reduces the picture quality.
  • the distance between the source-drain electrode and the gate is a key parameter that determines its parasitic capacitance. Increasing the distance between the source-drain electrode and the gate can reduce the parasitic capacitance, which can be achieved by thickening the gate insulating layer or the source-drain insulating layer.
  • the parasitic capacitance in the panel is one of the factors affecting the refresh rate of the panel.
  • the presence of parasitic capacitance affects the stability of the circuit signal, which reduces the picture quality.
  • the distance between the source-drain electrode and the gate is a key parameter that determines its parasitic capacitance. Increasing the distance between the source-drain electrode and the gate can reduce the parasitic capacitance, which can be achieved by thickening the gate insulating layer or the source-drain insulating layer.
  • the object of the present invention is to provide an array substrate and a display device using the array substrate, which use a closed ring gate layer and an active layer.
  • the thin film transistor in the array substrate works in a saturated region and the channel is pinched off At the same time, its width and length change at the same ratio. The result is that its width-to-length ratio is constant and has an infinite output resistance to ensure the stability of the output current.
  • the present invention provides an array substrate including a gate line and a gate insulating layer covering the gate line; an active layer provided on the gate insulating layer; a ring source The polar line is provided on the active layer; the circular drain line is provided on the active layer, the center of the circular drain line coincides with the center of the circular source line; There are a circular pad height block and a circular pad height block; the circular pad height block is supported between the circular source line and the active layer, and the circular pad height block is supported by the circular drain line And the active layer.
  • the array substrate further includes an insulating layer covering the active layer, the circular drain line and the ring-shaped source line; the pixel electrode line is provided on the insulating layer, and the One end is connected to the circular drain line.
  • the insulating layer is provided with a through hole, which vertically penetrates from the surface of the insulating layer to the surface of the circular drain line, and one end of the pixel electrode line is connected to the circle through the through hole Shaped drain line.
  • a first circular protrusion is formed at the circular drain line corresponding to the circular pad height block; an annular protrusion is formed at the circular source line corresponding to the circular pad height block.
  • the through hole is a circular through hole, and the diameter of the circular through hole is smaller than or equal to the diameter of the first circular protrusion.
  • the gate insulating layer has a circular shape, and the line between the center of the gate insulating layer and the center of the circular drain line is perpendicular to the substrate.
  • the gate line is circular, and the straight line where the center of the gate line and the center of the gate insulating layer are located is perpendicular to the substrate.
  • a second circular protrusion is formed at the gate insulating layer corresponding to the gate line.
  • the array substrate further includes a source connection line extending from the ring-shaped source line to an edge of the gate insulation layer, the source connection line is located on the gate insulation The part of the edge of the layer is the external portion of the source; the gate connection line, one end is connected to the gate line; the gate connection line extends from the gate line to the edge of the substrate, the gate The part of the connection line located at the edge of the substrate is the gate external portion.
  • the invention also provides a display device using the array substrate.
  • the array substrate and the display device adopting the array substrate of the present invention are designed with uneven source and drain electrodes, so that the distance between the gate electrode and the source-drain electrode is expanded while keeping the distance between the gate electrode and the active layer constant.
  • the pitch greatly reduces the parasitic capacitance, making the array substrate more controllable.
  • FIG. 1 is a partial cross-sectional view of an array substrate in an embodiment.
  • FIG. 2 is a top cross-sectional view of the array substrate in the embodiment.
  • FIG. 3 is a schematic diagram of the source and drain electrodes of the array substrate in the embodiment.
  • Insulation layer 70 Insulation layer; 80 pixel electrode lines;
  • the array substrate 1 of the present invention includes a substrate 10, a gate line 20, a gate insulating layer 30, an active layer 40, a circular drain line 50, and a ring-shaped source line 60. Insulation layer 70, pixel electrode line 80, and pad layer 90.
  • the gate line 20 is provided on the substrate 10. Since the square array substrate in the prior art is in a bent state, its array substrate characteristic changes greatly, which may easily cause a change in display performance. Therefore, in this embodiment, the gate line 20 adopts a circular structure.
  • the gate insulating layer 30 completely covers the gate line 20. Since the gate line 20 in this embodiment adopts a circular structure, the gate insulating layer 30 is formed corresponding to the gate line 20 A second circular protrusion 310 corresponding to the gate line 20.
  • the active layer 40 is formed on the gate insulating layer 30, and the active layer 40 has a circular structure.
  • the circular drain line 50 is formed on the active layer 40, and a straight line where the center of the circle of the circular drain line 50 and the center of the gate line 20 are perpendicular to the active layer 40.
  • the ring-shaped source line 60 is formed on the active layer 40, the ring-shaped source line 60 surrounds the circular drain line 50, the circular drain line 50 and the ring-shaped source line 60 There is a gap between them.
  • the area of the active layer 40 corresponding to the gap between the circular drain line 50 and the ring-shaped source line 60 is the area of the electron channel 410.
  • the circular drain line 50 and the circular source line 60 are disposed on the same plane, that is, on the active layer 40.
  • the circular drain line 50 and the circular source line 60 exhibit a concentric circle structure, and the center of the concentric circle structure is located at the center of the circular drain line 50.
  • the present invention is not limited to concentric circle structures, such as elliptical and rectangular structures are within the scope of the present invention.
  • FIG. 4 is the output characteristic curve of the drain of the array substrate in this embodiment. Since the value of the length (L) and width (W) of the array substrate is not isolated, specific , The width and length of the illustrated array substrate 1 are as shown in Formula 2:
  • L R2-R1, and R 2 / R 1 ratio of the diameter of the ring 50 to the source line 60 and the inner diameter of the circular drain lines. Therefore, when the electron channel 410 on the array substrate 1 is pinched off, its length and width change in the same proportion. As a result, its length to width ratio remains unchanged. While increasing the drain potential, the output current remains unchanged. change. Since the gate line 20, the gate insulating layer 30, and the active layer 40 adopt a circular structure, this structure has the advantages of infinite output resistance, little change in characteristics in a bent state, and a circular array substrate When the structure is applied to a flexible screen, it has more stable performance than the square array substrate structure in the prior art.
  • an array substrate 1 composed of a circular drain line 50 and a ring-shaped source line 60 has a shape source line 60 electrode that consumes more electrons than a circular drain line 50 electrode.
  • the ring-shaped array substrate 1 in the saturated state has less electric charge than the channel of the rectangular array substrate. Therefore, few electrons are trapped due to the SHS (self-heating stress) effect, and the voltage change is small.
  • mechanical bending strain leads to an increase in the distance of atoms in the semiconductor layer, which effectively reduces the splitting level ( ⁇ E) of the bonding and anti-bonding orbits between atoms.
  • the array substrate 1 is not limited by the bending direction, and it shows good stability in mechanical bending strain.
  • a high-level pad 90 is added to increase the height of the circular drain line 50 relative to the gate line 20, and the circular source line 60 relative to the gate The height of the line 20 is to reduce the parasitic capacitance.
  • the pad height 90 is divided into a round pad height block 910 and a ring pad height block 920, wherein the round pad height block 910 is placed on the round drain line 50 and the Between the source layers 40, and the diameter of the circular pad height block 910 is smaller than that of the circular drain line 50, and a first circle is formed at the circular drain line 50 corresponding to the circular pad height block 910 Protrusion 510, the portion of the circular drain line 50 where the first circular protrusion 510 is not formed is still provided on the active layer 40, so that the circular drain line 50 can still be The source layer 40 is connected.
  • the ring-shaped pad height block 920 is disposed between the ring-shaped source line 60 and the active layer 40, and the block width of the ring-shaped pad height block 920 is smaller than that of the ring-shaped source line 60 Line width, a ring-shaped protrusion 620 is formed at the ring-shaped source line 60 corresponding to the ring-shaped pad height block 920, and a portion of the ring-shaped source line 60 where the ring-shaped protrusion 620 is not formed is still provided in the active layer 40, so that the ring-shaped source line 60 can still be connected to the active layer 40.
  • the insulating layer 70 has a ring shape, is attached to the gate insulating layer 30, and has a diameter smaller than that of the gate insulating layer 30.
  • a through hole 710 is formed in the center of the insulating layer 70.
  • the through hole 710 vertically penetrates from the surface of the insulating layer 70 to the surface of the circular drain line 50.
  • the through hole 710 is a circular through hole, and the diameter of the circular through hole 710 is less than or equal to the diameter of the first circular protrusion 510.
  • the pixel electrode line 80 is electrically connected to the circular drain line 50 through the through hole 710, that is, one end of the pixel electrode line 80 is connected to the circular drain through the through hole 710 Line 50.
  • the size of the through hole 710 is approximately equal to the size of the circular drain line 50, that is to say, the through hole 710 is circular in a plan view, however, in other embodiments
  • the shapes of the through hole 710 and the circular drain line 50 may also be different, as long as the pixel electrode line 80 can contact the circular drain line 50.
  • An opening can also be formed in the circular drain line 50 to connect the opening to the through hole 710, which can increase the contact area of the pixel electrode line 80 and the circular drain line 50, further enhancing the The charging ability of the pixel electrode line 80 will be described.
  • the present invention does not limit the size and shape of the opening, as long as the pixel electrode line 80 can be in contact with the circular drain line 50.
  • the substrate 1 is further provided with a source connection line 610, and one end of the source connection line 610 is connected to the outer edge of the ring-shaped source line 60, and From the outer edge of the ring-shaped source line 60 to the edge of the gate insulating layer 30, the source connection line 610 at the edge of the gate insulating layer 30 is exposed outside the insulating layer 70.
  • the substrate 1 is also provided with a gate connection line 210 that extends from the gate line 20 to the edge of the substrate 1 at the edge of the substrate 1 The gate connection line 210 is exposed outside the gate insulating layer 30.
  • the present invention also provides a display device, the main improvement points and features of which are concentrated on the array substrate 1.
  • Other components of the display device, such as the display layer, will not be described in detail.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

本发明公开了一种阵列基板及采用该阵列基板的显示装置，所述阵列基板包括栅极线；栅极绝缘层，覆盖于所述栅极线上；有源层，设于所述栅极绝缘层上；环形源极线，设于所述有源层上；圆形漏极线，设于所述有源层上，所述圆形漏极线的圆心与所述环形源极线的中心重合；垫高层，其中具有环形垫高块和圆形垫高块；所述环形垫高块支撑于所述环形源极线和有源层之间，所述圆形垫高块支撑于所述圆形漏极线和有源层之间。本发明的有益效果在于采用封闭环形的栅极和有源层，保证输出电流稳定，同时采用凹凸的源漏电极设计，减小源漏电极与栅电极的寄生电容，具有更高的可控性。

Description

阵列基板及采用该阵列基板的显示装置 技术领域
本发明涉及液晶显示领域，特别涉及一种阵列基板及采用该阵列基板的显示装置。
 背景技术
OLED(Organic Light-Emitting Diode  有机发光二极管)显示器件的原理是电流经过有机发光材料，载流子在有机材料之间传递、复合发出各类波长段的光，所以，OLED显示器件是电流驱动。而有机发光材料的发光量受到电流大小的控制，这就要求OLED显示器件必须要精确并稳定的控制驱动电流。
如公式1I DS=(1/2)u nC OX(W/L)(V GS-V th)^ 2所示，利用阵列基板在饱和区的电流特性可以获得稳定的输出电流，因为此时的输出电流与阵列基板的输出电压V DS的大小无关，漏极端可以获得大小稳定的电流。即阵列基板的输出电阻是较高的。但是，如公式1所示，输出电流I DS的大小是与阵列基板的宽长比W/L有关，当V DS达到一定程度，导致夹断点左移时，L的大小实际是发生了变化，逐渐变小。这就会导致阵列基板的输出电流I DS逐渐变大，既阵列基板的输出电阻不是较高的。这就会导致输入电流的不稳定，更难以被精确控制。如何使得驱动阵列基板有着更大的输出电阻，进而获得稳定的输出电流，一直是OLED显示行业亟待解决的难题和关键。
在显示器实现柔性化的一个关键问题是如何保持阵列基板的稳定性。在传统的方形阵列基板中，沟道极容易在屏幕弯曲的状态下断开。柔性屏弯曲时，阵列基板的膜层会由于受到拉伸力的作用而出现断裂。按照阵列基板的长宽方向和弯曲的方向的相同或者不同，其阵列基板的特性会出现两种可能的变化。如阵列基板的长度方向与弯曲方向垂直，此时阵列基板的沟道区会出现变化，但是不会完全断开。再如，阵列基板的长度方向与弯曲方向相同时，此时阵列基板的沟道区受到的影响会远远大于第一种情况，甚至可能会完全断裂，这种断裂可能导致信号的电压无法传输至像素电极线，从而导致显示不良。
另一方面，即使不考虑完全断裂的情况，方形阵列基板在弯曲状态时，其阵列基板特性变化也较大，在发生弯曲时，其电压会发生不同程度的变化，从而导致显示性能出现变化，如何维持阵列基板在弯曲状态的特性不发生变化，是柔性显示行业最关注的关键性问题。
环形阵列基板是一种环形结构的阵列基板,具有输出电阻无线大、弯曲状态下特性变化小的优点,但是，环形阵列基板的源漏极走线与栅极走线完全垂直重合，寄生电容非常大，这就限制了霍尔环形 阵列基板在高分辨显示器件中的应用。
面板中的寄生电容，是影响面板刷新率的影响因素之一。此外，对于OLED而言，由于OLED是电流驱动，寄生电容的存在影响了电路信号的稳定性，会降低画面质量。源漏电极与栅极之间的距离是决定其寄生电容大小的关键参数。加大源漏电极与栅极之间的距离可以降低寄生电容，可以通过增厚栅极绝缘层，或者源漏绝缘层来实现。但是，增厚栅极绝缘层之后，为了在有源层中形成相同的沟道，就需要增加栅极的电压，这会提高功耗，并且寄生电容的影响会变大。而增加源漏绝缘层的厚度，又会增加制造成本，并且增加过孔难度。
 技术问题
面板中的寄生电容，是影响面板刷新率的影响因素之一。此外，对于OLED而言，由于OLED是电流驱动，寄生电容的存在影响了电路信号的稳定性，会降低画面质量。源漏电极与栅极之间的距离是决定其寄生电容大小的关键参数。加大源漏电极与栅极之间的距离可以降低寄生电容，可以通过增厚栅极绝缘层，或者源漏绝缘层来实现。但是，增厚栅极绝缘层之后，为了在有源层中形成相同的沟道，就需要增加栅极的电压，这会提高功耗，并且寄生电容的影响会变大。而增加源漏绝缘层的厚度，又会增加制造成本，并且增加过孔难度
 技术解决方案
本发明的目的在于提供一种阵列基板及采用该阵列基板的显示装置，其采用封闭环形的栅极层和有源层，当阵列基板中的薄膜晶体管工作在饱和区，沟道被夹断之后，其宽、长同时同比例发生变化，结果是其宽长比恒定不变，有无限大的输出电阻，以保证输出电流的稳定性。
为了解决上述技术问题，本发明提供了一种阵列基板，包括栅极线，栅极绝缘层，覆盖于所述栅极线上；有源层，设于所述栅极绝缘层上；环形源极线，设于所述有源层上；圆形漏极线，设于所述有源层上，所述圆形漏极线的圆心与所述环形源极线的中心重合；垫高层，其中具有环形垫高块和圆形垫高块；所述环形垫高块支撑于所述环形源极线和有源层之间，所述圆形垫高块支撑于所述圆形漏极线和有源层之间。
进一步地，所述阵列基板还包括绝缘层，覆于所述有源层、所述圆形漏极线和所述环形源极线上；像素电极线，设于所述绝缘层上，且其一端连接至所述圆形漏极线。
进一步地，所述绝缘层设有一通孔，从所述绝缘层的表面垂直贯穿至所述圆形漏极线的表面，所述像素电极线的一端穿过所述通孔连接至所述圆形漏极线。
进一步地，所述圆形漏极线对应所述圆形垫高块处形成有第一圆形凸起；所述环形源极线对应所述环形垫高块处形成有环形凸起。
进一步地，所述通孔为圆形通孔，所述圆形通孔的直径小于或等于所述第一圆形凸起的直径。
进一步地，所述栅极绝缘层为圆形，所述栅极绝缘层的圆心与所述圆形漏极线的圆心所在直线垂直于所述基板。
进一步地，所述栅极线为圆形，所述栅极线的圆心与所述栅极绝缘层的圆心所在直线垂直于所述基板。
进一步地，所述栅极绝缘层对应于所述栅极线处形成第二圆形凸起。
进一步地，所述阵列基板还包括源极连接线，所述源极连接线从所述环形源极线延伸至所述栅极绝缘层的边缘，所述源极连接线位于所述栅极绝缘层的边缘的部分为源极外接部；栅极连接线，一端连接至所述栅极线；所述栅极连接线从所述栅极线处延伸至所述基板的边缘，所述栅极连接线位于所述基板的边缘的部分为栅极外接部。
本发明还提供了一种显示装置，采用所述阵列基板。
 有益效果
本发明的阵列基板及采用该阵列基板的显示装置，通过凸凹不平的源漏电极设计，使得在保持栅电极与有源层距离不变的条件下，扩大了栅电极与源漏电极之间的间距，大幅度降低了寄生电容，使得阵列基板有更高的可控制性。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是实施例中中阵列基板部分剖视图。
图2是实施例中的阵列基板俯视剖面图。
图3是实施例中的阵列基板源漏电极示意图。
图4是实施例中阵列基板的输出特性曲线。
附图中部件标记为：
1阵列基板；
10基板；                20栅极线；
30 栅极绝缘层            40 有源层；
50 圆形漏极线；          60 环形源极线；
70 绝缘层；              80 像素电极线；
90 垫高层；
210 栅极连接线；         310 第二圆形凸起；
410 电子沟道；
510 第一圆形凸起；
610 源极连接线；        620 环形凸起；
710 通孔；
910 圆形垫高块；        920 环形垫高块；
 本发明的最佳实施方式
以下实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「顶」、「底」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
如图1所示，在本实施例中，本发明的阵列基板1，包括基板10、栅极线20、栅极绝缘层30、有源层40、圆形漏极线50、环形源极线60、绝缘层70、像素电极线80、垫高层90。
所述栅极线20设于所述基板10上，由于现有技术中的方形阵列基板在弯曲状态时，其阵列基板特性变化较大，容易导致显示性能发生变化。因此，在本实施例中，所述栅极线20采用圆形结构。
所述栅极绝缘层30完全覆盖栅极线20上，由于本实施例中的所述栅极线20采用圆形结构，因此，所述栅极绝缘层30对应所述栅极线20上形成一个对应所述栅极线20的第二圆形凸起310。
所述有源层40形成于所述栅极绝缘层30上，所述有源层40采用圆形结构。
所述圆形漏极线50形成于所述有源层40上，所述圆形漏极线50的圆心与所述栅极线20的圆心所在直线与所述有源层40垂直。
所述环形源极线60形成于所述有源层40上，所述环形源极线60环绕于所述圆形漏极线50所述圆形漏极线50与所述环形源极线60之间存在间隙。所述圆形漏极线50与所述环形源极线60之间所述空隙对应的有源层40的区域为电子沟道410的区域。
在本实施例中，所述圆形漏极线50和环形源极线60设置在同一平面上，即所述有源层40上。所述圆形漏极线50和所述环形源极线60呈现一种同心圆结构，该同心圆结构的圆心位于圆形漏极线50的中心。然而，本发明并不局限于同心圆结构，如椭圆、矩形结构皆在本发明的范围内。
参照背景技术中的公式1部分以及图4所示，图4为本实施例中的阵列基板漏极的输出特性曲线，由于阵列基板的长（L）宽(W)数值不是孤立的，具体的，所示阵列基板1的宽长比如公式2所示：
W/L=(2∏)/I n(R 2/R 1)
其中L=R2-R1,且R 2/R 1为所述环形源极线60内径与所述圆形漏极线50直径比。因此，当所述阵列基板1上的所述电子沟道410被夹断时，其长宽发生同比例变化，结果是其长宽比不变，在提高漏极电位的同时，输出电流保持不变。由于所述栅极线20、所述栅极绝缘层30和所述有源层40采用圆形结构，这种结构具有输出电阻无限大、弯曲状态下特性变化小的优点，且环形的阵列基板结构运用到柔性屏之中时，比现有技术中的方形阵列基板结构更具有稳定的性能。
如图3所示，由圆形漏极线50与环形源极线60组成的阵列基板1，其形源极线60电极比圆形漏极线50电极需要消耗更多的电子，所以在漏极相同偏压的情况下，饱和状态下的环形阵列基板1相较于矩形阵列基板沟道的电荷更少。因此很少的电子会因为SHS(自热应力)效应被诱捕，电压变化小。另一方面，机械弯曲应变导致半导体层中的原子距离增大，会使原子间的成键和反键轨道的分裂能级(△E)有效的减少。
这是因为当更多电子被激发到有源层40的反键轨道时，费米函数值的将会发生变化，而沟道导电性的增强在阵列基板转移特性上表现为所述阵列基板1的输出电压V th发生负漂，所述阵列基板1不受弯曲方向局限，在机械弯曲应变中都表现出很好的稳定性。
所述阵列基板1弯曲而导致所述电子沟道410开裂时，无论其弯曲方向是左右还是上下，该电子沟道410都只会受到小幅度的影响，即所述阵列基板1的抗弯曲能力好。 由于显示面板中的寄生电容是影响该显示面板刷新率的影响因素之一，对于OLED显示面板而言，由于OLED显示面板是电流驱动，寄生电容的存在影响了电路信号的稳定，会降低画面质量，所以，本实施例中设计采用加设垫高层90用来增高所述圆形漏极线50相对于所述栅极线20的高度、以及所述环形源极线60相对于所述栅极线20的高度，以达到降低寄生电容的目的。
在本实施例中，所述垫高层90分为圆形垫高块910和环形垫高块920，其中，所述圆形垫高块910置于所述圆形漏极线50和所述有源层40之间，且所述圆形垫高块910直径小于所述圆形漏极线50，所述圆形漏极线50对应所述圆形垫高块910处形成有第一圆形凸起510，所述圆形漏极线50中未形成第一圆形凸起510的部分仍然设置在所述有源层40上，以便所述圆形漏极线50仍可与所述有源层40相连。 同样的，所述环形垫高块920置于所述环形源极线60和所述有源层40之间，且所述环形垫高块920的块体宽度小于所述环形源极线60的线宽，所述环形源极线60对应所述环形垫高块920处形成有环形凸起620，所述环形源极线60中未形成环形凸起620的部分仍然设置在所述有源层40上，以便所述环形源极线60仍可与所述有源层40相连。
所述绝缘层70为环形，贴附于所述栅极绝缘层30上，且其直径小于所述栅极绝缘层30的直径。所述绝缘层70中心处有一通孔710，所述通孔710从所述绝缘层70的表面垂直贯穿至所述圆形漏极线50的表面。所述通孔710为圆形通孔，所述圆形通孔710的直径小于或等于所述第一圆形凸起510的直径。且所述像素电极线80经由所述通孔710与所述圆形漏极线50电性连接，即所述像素电极线80的一端穿过所述通孔710连接至所述圆形漏极线50。在本实施例中，所述通孔710的大小约等于所述圆形漏极线50的大小，也就是说，所述通孔710由俯视方向来看为圆形，然而，在其他实施例中，所述通孔710和所述圆形漏极线50的形状也可以不同，只要使得所述像素电极线80可以接触所述圆形漏极线50即可。也可在所述圆形漏极线50上开设开孔，使开孔与所述通孔710连接，这样可以增加所述像素电极线80与圆形漏极线50的接触面积，进一步增强所述像素电极线80的充电能力。同样的，本发明并不限定开孔的大小与形状，只要能够使所述像素电极线80与所述圆形漏极线50接触即可。
如图1及图2所示，在本实施例中，所述基板1中还设有源极连接线610，所述源极连接线610一端连接至所述环形源极线60外侧边缘，且从所述环形源极线60外侧边缘延伸至所述栅极绝缘层30边缘处，位于所述栅极绝缘层30边缘处的源极连接线610裸露于所述绝缘层70之外。同样的，所述基板1中还设有栅极连接线210，所述栅极连接线210从所述栅极线20上延伸至所述基板1的边缘处，位于所述基板1的边缘处的所述栅极连接线210裸露于所述栅极绝缘层30之外。
本发明还提供了一种显示装置，其主要的改进点和特征均集中体现在所述阵列基板1上，对于显示装置其他部件，如显示层等，就不再一一赘述。
以上仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (18)

  1. 一种阵列基板，其包括
    栅极线；
    栅极绝缘层，覆盖于所述栅极线上；
    有源层，设于所述栅极绝缘层上；
    环形源极线，设于所述有源层上；
    圆形漏极线，设于所述有源层上，所述圆形漏极线的圆心与所述环形源极线的中心重合；
    垫高层，其中具有环形垫高块和圆形垫高块；
    所述环形垫高块支撑于所述环形源极线和有源层之间，所述圆形垫高块支撑于所述圆形漏极线和有源层之间。
  2. 如权利要求1所述的阵列基板，其中还包括
    绝缘层，覆于所述有源层、所述圆形漏极线和所述环形源极线上；
    像素电极线，设于所述绝缘层上，且其一端连接至所述圆形漏极线。
  3. 如权利要求2所述的阵列基板，其中，所述绝缘层设有一通孔，从所述绝缘层的表面垂直贯穿至所述圆形漏极线的表面，所述像素电极线的一端穿过所述通孔连接至所述圆形漏极线。
  4. 如权利要求3所述的阵列基板，其中，所述圆形漏极线对应所述圆形垫高块处形成有第一圆形凸起；所述环形源极线对应所述环形垫高块处形成有环形凸起。
  5. 如权利要求4所述的阵列基板，其中，所述通孔为圆形通孔，所述圆形通孔的直径小于或等于所述第一圆形凸起的直径。
  6. 如权利要求1所述的阵列基板，其中，所述栅极绝缘层为圆形，所述栅极绝缘层的圆心与所述圆形漏极线的圆心所在直线垂直于所述基板。
  7. 如权利要求6所述的阵列基板，其中，所述栅极线为圆形，所述栅极线的圆心与所述栅极绝缘层的圆心所在直线垂直于所述基板。
  8. 如权利要求7所述的阵列基板，其中，所述栅极绝缘层对应于所述栅极线处形成第二圆形凸起。
  9. 如权利要求1所述的阵列基板，其中还包括
    源极连接线，所述源极连接线从所述环形源极线延伸至所述栅极绝缘层的边缘，所述源极连接线位于所述栅极绝缘层的边缘的部分为源极外接部；
    栅极连接线，一端连接至所述栅极线；所述栅极连接线从所述栅极线处延伸至所述基板的边缘，所述栅极连接线位于所述基板的边缘的部分为栅极外接部。
  10. 一种显示装置，其中，采用如权利要求1中所述的阵列基板。
  11. 一种显示装置，其中，采用如权利要求2中所述的阵列基板。
  12. 一种显示装置，其中，采用如权利要求3中所述的阵列基板。
  13. 一种显示装置，其中，采用如权利要求4中所述的阵列基板。
  14. 一种显示装置，其中，采用如权利要求5中所述的阵列基板。
  15. 一种显示装置，其中，采用如权利要求6中所述的阵列基板。
  16. 一种显示装置，其中，采用如权利要求7中所述的阵列基板。
  17. 一种显示装置，其中，采用如权利要求8中所述的阵列基板。
  18. 一种显示装置，其中，采用如权利要求9中所述的阵列基板。
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