WO2020073471A1 - 一种goa电路、显示装置和显示器控制方法 - Google Patents

一种goa电路、显示装置和显示器控制方法 Download PDF

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Publication number
WO2020073471A1
WO2020073471A1 PCT/CN2018/120046 CN2018120046W WO2020073471A1 WO 2020073471 A1 WO2020073471 A1 WO 2020073471A1 CN 2018120046 W CN2018120046 W CN 2018120046W WO 2020073471 A1 WO2020073471 A1 WO 2020073471A1
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Prior art keywords
latch
gate
input terminal
terminal
enable
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Ceased
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PCT/CN2018/120046
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English (en)
French (fr)
Inventor
管曦萌
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Shenzhen Royole Technologies Co Ltd
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Shenzhen Royole Technologies Co Ltd
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Priority to CN201880095926.XA priority Critical patent/CN112639954A/zh
Publication of WO2020073471A1 publication Critical patent/WO2020073471A1/zh
Priority to US17/226,714 priority patent/US11355046B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0857—Static memory circuit, e.g. flip-flop
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the technical field of display panels, and more specifically, to a GOA circuit, a display device, and a display control method.
  • Gate driver on The array (GOA) circuit is widely used in electronic displays such as LCD and AMOLED. It is a key part of the display panel and is used to provide scan pulse signals to the pixel matrix.
  • the traditional GOA circuit is designed based on the basic idea that the pre-stage triggers the post-stage, and generally consists of a bootstrap capacitor and a unipolar transistor. Based on this design, the scanning of the pixel array can only be performed sequentially, not randomly.
  • C gon is the load contribution of the GOA in the active state to the clock line
  • C ov is the load contribution of the remaining N-1 level GOA in the inactive state to the clock line
  • C pixel is the contribution of all pixels on the clock line to the clock line Load contribution.
  • each row of pixels is reduced, and the available area of the GOA circuit used with it is continuously reduced.
  • the size of the transistor that makes the GOA circuit is further restricted, and the driving ability is reduced.
  • the technical problem to be solved by the present invention is to provide a GOA circuit, a display device and a display control method in view of the above-mentioned defects of the prior art.
  • the technical solution adopted by the present invention to solve its technical problem is to provide a GOA circuit, which includes a plurality of mutually independent GOA units, and each of the GOA units includes an enable module and a drive corresponding to the enable module.
  • the enable module includes an input terminal for receiving a row address signal of a row address signal, and an enable signal output terminal for outputting an enable signal according to the row address signal;
  • the driving module includes an enable signal input terminal for receiving an enable signal output from the enable signal output terminal, and a drive signal output terminal for outputting a drive signal according to the enable signal, the drive signal output
  • the terminal is connected to the gate line of the row corresponding to the driving module to send the driving signal to the gate line of the corresponding row to gate the corresponding row.
  • the invention also provides a display device including the GOA circuit described above.
  • the invention also provides a display control method.
  • the method includes:
  • the driving module receiving the enable signal drives the pixels of the corresponding row to work.
  • a GOA circuit, display device and display control method embodying the present invention have the following beneficial effects:
  • the present invention provides a GOA circuit that supports random addressing.
  • the GOA circuit allows data to be written to the screen out of line order. Most areas of the screen are static images. When only a few areas are constantly changing, it is only necessary to program this area, and because the rows of the unchanged image are not gated, the dynamic power consumption is effectively reduced, and at the same time, it can be increased for image changes.
  • the time of each line makes it possible to realize real-time and dynamic adjustment between display size and display power, and display refresh rate.
  • the GOA circuit of the present invention does not depend on the trigger of the previous stage, so when the isolated one-stage GOA unit has a defect, the functions of the remaining GOA units will not be affected, so that the yield and rating of the screen are improved. Provides the possibility to dynamically repair the screen.
  • the GOA circuit of the present invention does not use the traditional bootstrap structure.
  • the clock line does not need to directly drive the output transistor in the GOA unit. Therefore, the dynamic response of the (N-1) level inactive GOA unit can be greatly reduced Impact of power consumption.
  • the reset operation of the GOA circuit of the present invention does not depend on an external clock signal, and the output waveform quality is high, which is suitable for a high-resolution, large-size screen.
  • FIG. 1 is a schematic structural diagram of a first embodiment of a single GOA unit in a GOA circuit of the present invention
  • FIG. 2 is a schematic structural diagram of a second embodiment of a single GOA unit in a GOA circuit of the present invention
  • Fig. 3 is a circuit schematic diagram of a decoder for a sequential codec
  • FIG. 4 is a circuit schematic diagram of a row decoder implemented with N-type transistors of the present invention.
  • FIG. 5 is a circuit schematic diagram of a row decoder implemented with P-type transistors of the present invention.
  • FIG. 6a is a layout design diagram of a row decoder implemented with N-type transistors (transistors are not merged),
  • FIG. 6b is a layout design diagram of the row decoder after merging transistors according to the preset conditions of the present invention, and
  • FIG. 6c is a diagram 6b circuit schematic;
  • FIG. 7a is a schematic diagram of the current flow direction of a row decoder (transistors not combined) implemented with N-type transistors
  • FIG. 7b is a schematic diagram of the current flow direction of a row decoder after merging transistors according to the preset conditions of the present invention
  • FIG. 8 is a circuit schematic diagram of the first embodiment of the reset module of the present invention.
  • FIG. 9 is a circuit schematic diagram of the second embodiment of the reset module of the present invention.
  • FIG. 10 is a schematic structural diagram of a positive edge flip-flop provided by an embodiment of the present invention.
  • FIG. 11 is a circuit schematic diagram of a latch provided by an embodiment of the present invention.
  • FIG. 12 is a circuit schematic diagram of a buffer inverter provided by an embodiment of the present invention.
  • Fig. 13a is a circuit schematic diagram of a single GOA unit using a P-type transistor as a decoder
  • Fig. 13b is a circuit schematic diagram of a single GOA unit using an N-type transistor as a decoder
  • FIG. 14a is a circuit schematic diagram of a single GOA unit of the first embodiment used by the reset module, and FIG. 14b is a single-stage operation timing of the circuit of FIG. 14a;
  • Figure 15 is a single-stage operation timing simulation verification diagram using the circuit of Figure 14a;
  • FIG. 16 is a schematic diagram of a full-screen GOA circuit using the circuit of FIG. 14a;
  • FIG. 17 is a simulation verification diagram of the multi-stage cascade working timing of FIG. 16;
  • FIG. 19 is a working timing simulation verification diagram of FIG. 18;
  • FIG. 20 is a schematic diagram of a full-screen GOA circuit using the circuit of FIG. 18;
  • Figure 21 is the working timing diagram and working timing simulation verification diagram of Figure 20;
  • FIG. 22 is a schematic diagram of the layout of a GOA circuit in a rollable collection display screen according to an embodiment of the invention.
  • FIG. 23 is a schematic diagram of a layout of a GOA circuit in a splicing screen according to an embodiment of the invention.
  • 24 is a schematic flowchart of a display control method according to an embodiment of the present invention.
  • FIG. 1 it is a schematic structural diagram of a first embodiment of a GOA circuit of the present invention.
  • the GOA circuit of this embodiment includes a plurality of mutually independent GOA units 10, and each GOA unit 10 includes an enabling module 11 and a driving module 12 corresponding to the enabling module 11.
  • the GOA circuit of the present invention is based on transistors of complementary polarity, that is, there are both N-type and P-type transistors on the panel.
  • the enable module 11 includes an input terminal for receiving a row address signal, and an enable signal output terminal for outputting an enable signal according to the row address signal.
  • the present invention does not limit the source of the row address signal.
  • the row address signal may be generated by an external driver IC, but in other embodiments, the row address signal may also be generated by the display screen itself.
  • the display screen can provide two transistors with complementary polarities, a dedicated circuit is designed on the display screen. The dedicated circuit can directly generate the aforementioned row address signal without the need of an external driver IC.
  • the enabling module 11 of the embodiment of the present invention is a row decoder based on binary encoding, or a row decoder based on Gray code encoding.
  • each row of decoders may include multiple transistors connected in series, and two transistors in adjacent rows and in the same column are combined into one transistor when the preset conditions are satisfied.
  • the row decoder of the embodiment of the present invention By using the row decoder of the embodiment of the present invention, random addressing can be achieved, data is not written to the screen in the order of rows, and the subsequent stage trigger does not depend on the previous stage trigger, which effectively improves the screen yield and rating.
  • the dynamic repair screen provides the possibility, and by using the Gray code row decoder can reduce the horizontal cross-over in the layout, allowing more transistors to merge, reducing the dynamic power of the decoder during the most commonly used sequential scanning process Consume.
  • FIG. 3 it is the circuit schematic diagram of the sequential encoding decoder.
  • This row of decoders uses 4-bit 16-level GOA as an example. If the decoder is designed with sequential encoding, the level 0 encoding is 0000, The level 1 code is 0001, ..., and the level 15 code is 1111, as shown in Table 1.
  • the decoder implemented in sequential encoding has many horizontal cross-lines, and the number of horizontal cross-lines required for each row is different.
  • N the required horizontal crossover reaches (N-1).
  • PPI pixel density
  • the row decoder based on the Gray code encoding of the present invention can be known from the nature of the Gray code. There is only 1 bit difference between adjacent codes, so each row decoder of the present invention only needs one horizontal cross line. This property has nothing to do with the size of the screen resolution, that is, whether it is FHD or 4K UHD, when using the GOA row decoder of the present invention, only one horizontal cross-line for each row is required.
  • the circuit schematic diagram of a specific embodiment of the row decoder based on Gray code encoding of the present invention is shown in FIG. 4.
  • the row decoder of this embodiment takes 4-bit 16-level GOA as an example, then the level 0 encoding is 0000, the level 1 encoding is 0001, the level 2 encoding is 0011, the level 3 encoding is 0010, ..., the The 15-level code is 1000, as shown in Table 2.
  • the transistors in the schematic diagrams of FIG. 3 and FIG. 4 are N-type transistors and only have 16 levels and 4 address bits. However, the scope of application of the present invention should include N-type and P-type transistors and any multi-level case.
  • the transistor symbols in FIG. 3 and FIG. 4 only represent the transistors needed here, not the number of transistors here.
  • the schematic diagram of FIG. 4 if two transistors in adjacent rows and in the same column satisfy the preset condition, they can be merged into one transistor. That is, two transistors in adjacent rows and the same column can be merged into a transistor with a larger size and a higher driving capacity when the preset conditions are satisfied.
  • the two transistors in the adjacent row and the same column satisfy the preset conditions including: the gates of the two transistors are shorted together, and each is the most significant transistor of the decoder of the row, or the gates of the two transistors The transistors shorted together and the transistors immediately before the previous one are merged together.
  • the row decoder of the present invention can also be implemented using P-type transistors, where the implementation of P-type transistors is similar to that of N-type transistors, with the difference that code 0 corresponds to a positive signal, code 1 corresponds to a negative signal, and the voltage Polarity is symmetrical with N-type.
  • the circuit schematic diagram realized by the P-type transistor is shown in FIG. 5, and the specific coding is shown in Table 3.
  • the merging conditions of the transistors in the row decoder implemented by the P-type transistors are the same as the merging conditions of the N-type transistors, and will not be repeated here.
  • FIG. 6b it is a layout design diagram of a row decoder implemented by an N-type transistor of the present invention.
  • the layout of the row decoder can be achieved to be very compact, saving area and optimizing delay effects.
  • the transistors in the same row are connected in series with each other, so the source and drain of adjacent transistors in the same row can be shared, and there is no need to use metal and contact holes to achieve the connection.
  • This design method can save The lateral area can effectively avoid the influence of the contact resistance and load capacitance brought by the metal wiring on the delay of the row decoder.
  • FIG. 6a is a schematic diagram of the transistors not merged
  • FIG. 6b is a schematic diagram of the transistors merged.
  • the transistors (n11 ⁇ n14) in the leftmost first column (a1) according to the preset conditions, because their gates are shorted together, and each is the highest transistor in the row, Therefore, the transistors (n11 ⁇ n14) in the first column (a1) on the left can be merged.
  • the merged layout is shown in the first column (a1 ') on the left in Figure 6b.
  • the gates of transistor n31 and transistor n32 are shorted, and the gates of transistor n33 and transistor n34 are short Connected, but the gates of transistor n32 and transistor n33 are not short-circuited), so the four transistors (n31 ⁇ n34) in this column (a3) cannot be combined; however, the two transistors in the upper half (transistor n31 and transistor n32) The gates of the two transistors (transistor n33 and transistor n34) in the lower half are shorted together, and they are adjacent to the previous high-order transistor (ie, the transistors (n21 ⁇ n24) in the second column from the left (a2)) Merged together, so according to the preset conditions, the two transistors in the upper half (transistor n31 and transistor n32) and the two transistors in the lower half (transistor n33 and transistor n34) can be merged in pairs, and the merged layout is shown in Figure 6b Is shown in the third column
  • merging refers to the active areas of transistors that originally belong to different rows of transistors on the layout (the gray area (AA) in Figure 6 can be fused.
  • the width of the active area can be increased, that is, the transistor's
  • a higher drive current can be obtained (or equivalently, the on-resistance can be lower)
  • the edges of the active regions that are separated from each other must meet the design rules for the minimum separation requirements of the process, and after fusion No need to consider this rule, the requirements for mask making and lithography can be reduced, and the yield of the process is greatly improved.
  • the merging technology enables the row decoding design of the present invention to support a high-resolution screen, so that the decoding speed is basically independent of the increased address line.
  • the driving module 12 includes an enable signal input terminal connected to the enable signal output terminal of the enable module 11, an enable signal input terminal for receiving the enable signal output by the enable signal output terminal, and A driving signal output terminal capable of outputting a driving signal, and the driving signal output terminal is connected to a gate line of a row corresponding to the driving module 12 to send the driving signal to the gate line of the corresponding row, gated The corresponding line.
  • the driving signal output by the driving module 12 is a pulse signal.
  • the driving module 12 may be a pulse generator.
  • the solution of the embodiment of the present invention provides a GOA circuit that supports random addressing.
  • the GOA circuit allows data to be written to the screen out of line order. When most areas of the screen are static images and only a few areas are constantly changing, Only this part of the area needs to be programmed, and since the row with the unchanged image is not gated, the dynamic power consumption is effectively reduced, and at the same time, the time left for each row of the image change can be increased, so that the display size and display power, display refresh The real-time and dynamic adjustment is possible between rates.
  • the rear stage trigger in the GOA circuit of the present invention does not depend on the previous stage trigger, so when the isolated first-level GOA unit 10 has a defect, the functions of the remaining GOA unit 10 will not be affected, so that the screen yield and rating are The upgrade provides the possibility to dynamically repair the screen.
  • the GOA circuit of the present invention does not use the traditional bootstrap structure, and the clock line does not need to directly drive the output transistor in the GOA unit 10, therefore, the impact of the (N-1) -level inactive GOA unit 10 on dynamic power consumption can be greatly reduced .
  • the GOA circuit of the present invention is suitable for high-resolution, large-size screens.
  • FIG. 2 is a schematic structural diagram of a second embodiment of a GOA circuit of the present invention.
  • each GOA unit 10 further includes an enable signal output terminal connected to the enable module 11, and is used to output a drive signal after the drive module 12 outputs After the corresponding row is selected, the reset module 13 resets the enable module 11.
  • the reset module 13 may include one or more.
  • each reset module 13 is set corresponding to each row of decoders.
  • the reset module 13 of the row is reset to make the next row address signal When it comes, reselect the row that outputs the drive signal. Specifically, if the enable signal output by the enable module 11 is a high level (1), the reset module 13 will be reset to a low level (0); if the enable module 11 outputs a low level (0 ), The reset module 13 will reset to high level (1).
  • FIG. 8 it is a circuit schematic diagram of the first embodiment of the reset module 13 of the present invention.
  • it is an embodiment of a reset module 13 provided in any row of a decoder composed of P-type transistors and corresponding to the row.
  • the reset module 13 may include a reset transistor.
  • the first electrode of the reset transistor is connected to the enable signal output terminal of the enable module 11, the second electrode of the reset transistor is grounded (GND), and the gate of the reset transistor is connected to the first clock signal (CLKR).
  • CLKR first clock signal
  • this embodiment is a row decoder composed of P-type transistors. When a row decoder composed of N-type transistors is used, its polarity is completely symmetrical with that of a row decoder composed of P-type transistors. Repeat again.
  • Fig. 8 takes P-type transistors as decoders and the decode output is high level as an example.
  • FIG. 9 it is a circuit schematic diagram of the second embodiment of the reset module 13 of the present invention.
  • it is an embodiment of a reset module 13 provided in any row of a decoder composed of P-type transistors and corresponding to the row.
  • the reset module 13 includes a pull-down transistor 135, a first-stage positive edge flip-flop 132, a first-stage inverter 131, a second-stage positive edge flip-flop 134, and a second-stage inverter 133.
  • the positive input terminal (D) of the first-stage positive edge flip-flop 132 and the input terminal of the first-stage inverter 131 are connected to the enable signal output terminal of the enable module 11 together.
  • the input terminal is connected to the output terminal of the first-stage inverter 131, and the clock signal input terminal (CK) of the first-stage positive edge flip-flop 132 is connected to the second clock signal (CLK) together with the input terminal of the second-stage inverter 133 );
  • the positive input terminal (D) of the second-stage positive edge flip-flop 134 is connected to the positive output terminal (Q) of the first-stage positive edge flip-flop 132, and the negative input terminal of the second-stage positive edge flip-flop 134 is connected to the first stage
  • the inverse output of the positive edge flip-flop 132, the clock signal input of the second-stage positive edge flip-flop 134 is connected to the output of the second-stage inverter 133, and the positive output (Q) of the second-stage positive edge flip-flop 134
  • the reset module 13 does not need an additional reset clock, and it shares a clock (CLK) and its reverse signal with the latch of this stage, that is, (CLK) in this embodiment is the same as the lock of this stage Common to the memory (CLK).
  • the reset module 13 of this embodiment is composed of a two-stage cascaded positive edge flip-flop and an inverter.
  • the positive edge flip-flop is one of the basic circuits in the digital logic circuit. Its basic function is to store and send the signal of the input terminal (D) to the output terminal (Q) only at the rising edge of the input clock. How does the input (D) change, the signal at the output (Q) remains unchanged.
  • the reset principle of the reset module 13 in this embodiment is: when EN is selected and a high level is output, the high potential is latched on the rising edge of CLK and passed to the pull-down transistor 135 on the next falling edge of CLK Gate (NRES terminal), turn on the pull-down transistor 135, reset EN to low level; when EN is not selected, the output is low, the trigger has no output, the gate of the pull-down transistor 135 (NRES terminal) is always At low level, the pull-down transistor 135 is turned off without affecting the EN potential.
  • the positive edge trigger has multiple implementation forms, and the present invention is not limited to the specific implementation of the trigger. A specific embodiment will be described below.
  • the applied positive edge flip-flop may be a master-slave flip-flop, which may be composed of two-stage latches.
  • the first-stage positive edge flip-flop 132 and the second-stage positive edge flip-flop 134 each include a master flip-flop 1301, a slave flip-flop 1302, and a master-slave inverter 1303.
  • the input terminal (S) of the main trigger 1301 is the positive input terminal (D) of the positive edge trigger
  • the positive output terminal of the main trigger 1301 is connected to the input terminal (S) of the slave trigger
  • the reset terminal (R) of the main trigger ) Is the inverting input terminal of the positive edge trigger
  • the inverting output terminal of the master trigger 1301 is connected to the reset terminal (R) of the slave trigger 1302
  • the positive output terminal (Q) of the slave trigger 1302 is the positive output of the positive edge trigger Terminal (Q)
  • the inverting output of the slave flip-flop 1302 is the inverting output of the positive edge flip-flop
  • the clock signal input (CP) of the slave flip-flop 1302 passes through the output of the master-slave inverter 1303, and the master-slave invert
  • the connection terminal of the input terminal of the converter 1303 and the clock signal input terminal (CP) of the main flip-flop 1301 is the clock signal input terminal (CK) of the positive edge flip-flop.
  • the driving module 12 of the embodiment of the present invention may include a latch circuit 121.
  • the buffer amplifier circuit 122 wherein the first end of the latch circuit 121 is connected to the second clock signal (CLK), the second end of the latch circuit 121 is connected to the enable signal output end of the enable module 11, the latch circuit 121
  • CLK clock signal
  • the third terminal is connected to the input terminal of the buffer amplifier circuit 122, and the output terminal of the buffer amplifier circuit 122 is used as the drive signal output terminal of the driver module 12 to connect the gate line of the row corresponding to the driver module 12.
  • the driving module 12 of the embodiment of the present invention may further include a buffer amplifier circuit 122.
  • the output terminal of the latch circuit 121 is not directly connected to the gate line of the row corresponding to the drive module 12, but is first connected to the input terminal of the buffer amplifier circuit 122, and then the output terminal of the buffer amplifier circuit 122 is used as the drive module
  • the driving signal output terminal of 12 is connected to the gate line of the row corresponding to the driving module 12.
  • the latch circuit 121 may include a latch
  • the buffer amplifier circuit 122 may be composed of a one-stage inverter or a multi-stage cascaded inverter.
  • the buffer amplifier circuit 122 is composed of a first-level inverter and the latch circuit 121 is composed of a latch
  • the input terminal (S) of the latch is connected to the second clock signal (CLK)
  • the enable terminal (CP) of the register is connected to the enable signal output terminal of the enable module 11
  • the output terminal (Q) of the latch is connected to the input terminal of the primary inverter
  • the output terminal of the primary inverter is connected to
  • the driving module 12 corresponds to the gate lines of the arranged rows.
  • the input end (S) of the latch is the data input end of the latch circuit 121
  • the enable end (CP) of the latch is the clock input end of the latch circuit 121
  • the output end (Q) of the latch It is the output terminal of the latch circuit 121
  • the input terminal of the primary inverter is the input terminal of the buffer amplifier circuit 122
  • the output terminal of the primary inverter is the output terminal of the buffer amplifier circuit 122.
  • the latch circuit 121 is composed of latches, assuming that there are n stages, where n is an integer greater than or equal to 2 ,
  • the input terminal (S) of the latch is connected to the second clock signal (CLK), the enable terminal (CP) of the latch is connected to the enable signal output terminal of the enable module 11, and the output terminal (Q) of the latch )
  • Connect the input terminal of the first-stage inverter, the output terminal of the n-th inverter is connected to the gate line of the row corresponding to the drive module 12;
  • the input terminal (S) of the latch is the data of the latch circuit 121
  • the input terminal, the enable terminal (CP) of the latch is the clock input terminal of the latch circuit 121, and the output terminal (Q) of the latch is the output terminal of the latch circuit 121; the input terminal of the first-stage inverter
  • the output terminal of the n-th inverter As the input terminal of the buffer amplifier circuit 122, the output terminal of the n-th invert
  • the latches used in the embodiments of the present invention are all latches with a gate control function, and their working principles are:
  • the present invention can produce the following advantages by using a latch in each GOA unit 10: using the latch principle, the internal AC signal or glitch signal of the circuit can be effectively suppressed from coupling to the output terminal, and the latch has a waveform reconstruction function, even if the external The clock waveform is distorted due to the RC delay. After the reconstruction of the latch, it can also output high-quality square wave pulses.
  • the following uses a specific embodiment to describe the latch used in the present invention. Among them, the most commonly used latch is an SR type latch.
  • the latch includes: a latch inverter 1210, a first AND gate 1211, a second AND gate 1212, a first NOR gate 1213, and a second NOR gate 1214.
  • the input terminal of the latched inverter 1210 is connected to the first input terminal of the first AND gate 1211 together with a second clock signal (CLK), and the output terminal of the latched inverter 1210 is connected to the second input of the second AND gate 1212 Terminal, the second input terminal of the first AND gate 1211 and the first input terminal of the second AND gate 1212 are connected to the enable signal output terminal of the enable module; the output terminal of the first AND gate 1211 is connected to the first NOR gate
  • the first input terminal of 1213, the second input terminal of the first NOR gate 1213 is connected to the output terminal of the second NOR gate 1214, and the output terminal of the first NOR gate 1213 is connected to the first input terminal of the second NOR gate 1214
  • the output terminal of the first NOR gate 1213 is also connected to the input terminal of the buffer amplifier circuit 122; the second input terminal of the second NOR gate 1214 is connected to the output terminal of the second AND gate 1212.
  • the first input terminal of the first AND gate 1211 is the first terminal of the latch circuit 121
  • the connection terminal of the second input terminal of the first AND gate 1211 and the first input terminal of the second AND gate 1212 is the latch circuit 121
  • the second terminal of the first output terminal of the first NOR gate 1213 is the third terminal of the latch circuit 121.
  • the inverters used in the buffer amplifier circuit in the embodiments of the present invention may all be composed of transistors.
  • each inverter may include a P-type transistor and an N-type transistor.
  • the first electrode of the P-type transistor is connected to the constant voltage high potential (VGH)
  • the second electrode of the P-type transistor is connected to the first electrode of the N-type transistor
  • the second electrode of the N-type transistor is connected to the constant voltage low potential (VGL)
  • the gate of the P-type transistor is connected to the gate of the N-type transistor
  • the second electrode of the P-type transistor is connected to the first electrode of the N-type transistor.
  • connection between the gate of the P-type transistor and the gate of the N-type transistor is the input of the inverter, and the connection of the second electrode of the P-type transistor and the first electrode of the N-type transistor is the output of the inverter end.
  • the P-type transistor in each GOA unit 10 is low-temperature polysilicon, amorphous silicon, or a channel made of materials in which carbon, silicon, and germanium are mixed in any ratio. Thin film transistor.
  • the N-type transistor in each GOA unit 10 is a thin-film transistor with a channel made based on metal oxide.
  • the embodiment of the present invention is a GOA circuit based on transistors of complementary polarities, that is, the case where N-type and P-type transistors can exist on the panel at the same time.
  • 13a and 13b are circuit schematic diagrams of a single GOA unit 10 that uses P-type transistors and N-type transistors as decoders respectively according to an embodiment of the present invention.
  • VSS is the input DC low level
  • VDD is the input DC high level
  • S [0: N] is the input address signal
  • CLK is the input clock signal
  • EN is GOA
  • NFET represents a row decoder composed of N-type transistors
  • PFET represents a row decoder composed of P-type transistors
  • R represents a reset module
  • 121 represents a latch circuit
  • Buf represents a buffer amplifier circuit 122.
  • FIG. 14a is a circuit schematic diagram in which a decoder is composed of P-type transistors, and the reset module 13 uses a single GOA unit 10 of the first embodiment shown in FIG. In this embodiment, taking a 4-bit address as an example; the latch circuit 121 includes a latch;
  • CLK1 ⁇ CLK4 can all be provided by the driver IC, and will continue to be provided after the screen is turned on;
  • S [0: N] is the row address signal of the input row decoder,
  • Dn-2, Dn-1, Dn , Dn + 1, Dn + 2 are the row address signals at different periods in the row address signal (S [0: N]) of the input row decoder.
  • Time period t1 the address decoding stage, the row decoder in the GOA unit 10 of a certain stage corresponding to the row address signal Dn in S [0: N] is selected, and the enable signal output of the row decoder of the row
  • the enable signal output from the terminal (EN) is high. Since the first clock signal (CLKR) is low, the reset transistor in the reset module 13 is turned off, which does not affect the output of the enable signal; and the second clock
  • the latch stores the high-level signal input from the input terminal (S) and sends it to the output terminal (Q) to output to the buffer amplifier circuit 122, which is processed by the buffer amplifier circuit 122 and output to the The gate line corresponding to this row.
  • Period t2 The output of the enable node (EN) is still at a high level, the reset transistor in the reset module 13 is still in an off state, the voltage of the second clock signal (CLK) falls back, and the voltage at the output terminal (OUT) falls back.
  • Time period t3 the rising edge of the first clock signal (CLKR) comes at a high level, and the reset transistor in the reset module 13 is turned on, thereby pulling down the enable node (EN) to a low level (GND), which translates The encoder is reset.
  • the enable terminal (CP) of the latch becomes a low level, so its output does not change with the change of the input terminal (S), but remains at a low level.
  • Period t4 EN is not selected, the second clock signal (CLK) is still at a low level, the enable input (CP) of the latch is kept at a low level, and its output does not change with the change of the input (S) Remains low, the reset transistor in the reset module 13 is still at a low level, and the reset transistor in the reset module 13 is turned off.
  • FIG. 15 is a working timing simulation verification diagram of FIG. 14a. As can be seen from FIG. 15, the simulation result is equivalent to the working timing result.
  • a schematic diagram of using multiple GOA units 10 shown in FIG. 14 is shown in FIG. 16. It can be seen from FIG. 16 that in each stage of the GOA unit 10, unlike the conventional GOA circuit, the output of each stage of the GOA unit 10 only enters the pixel array, and does not enter any stage of the GOA unit 10 after or before. That is, the operation of the GOA unit 10 of any stage of the present invention does not depend on the enable signal provided by the GOA of the previous stage or the latter stage, but the enable signal is generated by the row decoder within the stage.
  • 17 is a simulation verification diagram of the multi-stage cascade operation timing of FIG. 16.
  • the reset module 13 includes a pull-down transistor 135, a first-stage positive edge flip-flop 132, and a second-stage positive edge flip-flop 134;
  • the latch circuit 121 includes a latch.
  • CLK is provided by the driver IC;
  • S [0: N] is the row address signal of the input row decoder, Dn-3, Dn-2, Dn-1, Dn, Dn + 1, Dn + 2 It is the row address signal at different time periods in the row address signal (S [0: N]) of the input row decoder.
  • Time period t1 the address decoding stage, the row decoder in the GOA unit 10 of a certain stage corresponding to the row address signal Dn is selected, and the enable signal output terminal (EN) of the row decoder of the row is enabled.
  • the signal is at a high level, and since the reset signal (NRES) is at a low level, the pull-down transistor 135 is turned off and does not affect the output of the enable signal.
  • Period t2 A pulse of the second clock signal (CLK) arrives.
  • the latch in the latch circuit 121 stores the pulse signal input from the input terminal (S) and sends it to the output terminal (Q) to output to the buffer amplifier circuit 122.
  • the first-stage positive edge flip-flop 132 latches the EN high level and outputs it to the output terminal of the first-stage positive edge flip-flop 132.
  • the second-stage positive edge flip-flop 134 latches the high level output by the aforementioned first-stage positive edge flip-flop 132 and outputs it to the output terminal of the second-stage positive edge flip-flop 134 And output to the gate (NRES) of the pull-down transistor 135.
  • Period t3 As the reset signal (NRES) rises, the pull-down transistor 135 is turned on, the enable signal output terminal (EN) of the row decoder is reset to a low level, and the latch in the latch circuit 121 is closed. After this, until the decoder is selected again, the enable signal output terminal (EN) of the row decoder is low, the latch in the latch circuit 121 remains closed, and its output remains low. level.
  • FIG. 19 the working timing simulation verification diagram of Figure 18 is shown in Figure 19. It can be seen from Fig. 19 that the simulation results are equivalent to the operation timing results.
  • FIG. 20 the schematic diagram of the full-screen GOA circuit using the circuit of FIG. 18 is shown in FIG. 20, and the working timing simulation verification diagram is shown in FIG. 21.
  • each GOA unit 10 by introducing a latch in each GOA unit 10, it effectively resists the coupling of the internal AC signal or glitch signal of the circuit to the output terminal, and has a waveform reconstruction function, even if the external clock waveform is deformed due to RC delay, it can be output
  • High-quality square-wave pulses in some embodiments, can also generate a reset (reset) signal (self-reset) by itself, without relying on additional clocks; fewer clocks are required, and at least only two opposite phases are required Square wave clock.
  • the number of lines that can be randomly programmed at any time increases, up to 1/2 of the total number of lines. Especially suitable for the circuit design of high-resolution, variable-size screens.
  • the GOA circuit of the embodiment of the present invention can also be applied to a foldable or rollable retractable screen, and for a foldable or rollable retractable screen, the folded and retracted part does not display images and does not generate power consumption; it allows dynamic Adjust the dividing line between the displayed and non-displayed areas.
  • FIGS. 22 and 23 The layout of the GOA circuit of the embodiment of the present invention for the rollable, foldable, and splicing screens in the screen is shown in FIGS. 22 and 23.
  • the address range sent to the GOA is line j + 1 to line N
  • the curly collection part (the part subject to mechanical stress) can be programmed with a black signal when the first frame is conveyed, and it will not be scanned afterwards, so as to save power and extend the service life.
  • the address range of the input GOA can be dynamically adjusted to change the scanning and non-scanning parts, so as to achieve the purpose of dynamically saving power consumption.
  • the GOA circuit of the embodiment of the present invention can be applied to a seamlessly spliced display screen.
  • a seamlessly spliced display screen when each display screen to be spliced is designed and manufactured, the decoder reserves a higher address. And set aside redundant address lines.
  • the GOA part is directly electrically bridged at the junction, the address line, clock line and power supply line are shorted separately, and the higher address can be enabled.
  • the solution of the embodiment of the present invention provides a latch-based GOA circuit that supports random addressing.
  • the GOA circuit allows data to be written to the screen not in line order. Most areas of the screen are static images, but only a few When a part of the area is constantly changing, it is only necessary to program the part of the area, and because the row of the unchanged image is not gated, the dynamic power consumption is effectively reduced, and at the same time, the time left for each row of the image change can be increased, so that the display size It can realize real-time and dynamic adjustment between display power and display refresh rate.
  • the rear stage trigger in the GOA circuit of the present invention does not depend on the previous stage trigger, so when the isolated first-level GOA unit 10 has a defect, the functions of the remaining GOA unit 10 will not be affected, so that the screen yield and rating are The upgrade provides the possibility to dynamically repair the screen.
  • the GOA circuit of the present invention does not use the traditional bootstrap structure, and the clock line does not need to directly drive the output transistor in the GOA unit 10, therefore, the impact of the (N-1) -level inactive GOA unit 10 on dynamic power consumption can be greatly reduced .
  • the GOA circuit of the present invention is suitable for high-resolution, large-size screens.
  • each GOA unit by introducing a latch in each GOA unit, it effectively resists the coupling of the internal AC signal or glitch signal of the circuit to the output terminal, and has a waveform reconstruction function, even if the external clock waveform is deformed due to RC delay.
  • Output high-quality square wave pulses In some embodiments, it can also generate a reset (reset) signal (self-reset) by itself, which does not depend on an additional clock; the number of clocks required is small, and only at least 2 phases are required.
  • Square wave clock The number of lines that can be randomly programmed at any time increases, up to 1/2 of the total number of lines. Especially suitable for the circuit design of high-resolution, variable-size screens.
  • the GOA circuit of the embodiment of the present invention can also be applied to a foldable or rollable retractable screen, and for a foldable or rollable retractable screen, the folded and retracted part does not display images and does not generate power consumption; it allows dynamic Adjust the dividing line between the displayed and non-displayed areas.
  • the present invention also provides a display device including the GOA circuit of the foregoing embodiment.
  • the display device includes but is not limited to an LTPS display device and an AMOLED display device.
  • the present invention also provides a display control method. As shown in FIG. 24, the display control method may include the following steps:
  • Step S1 input the addressing signal to each row decoder in the GOA circuit of the display.
  • Step S2 Turn on the row decoder corresponding to the addressing signal.
  • Step S3 Output the enable signal to the driving module of the GOA circuit of the display through the opened row decoder.
  • Step S4 Drive the pixels of the corresponding row to work through the driving module receiving the enable signal.
  • the GOA circuit of the display may be the GOA circuit of the foregoing embodiment.
  • the display control method of the embodiment of the present invention further includes: when the row decoder corresponding to the address signal is turned on, the row decoder that does not correspond to the address signal remains off.
  • the display control method further includes: selectively turning on a part of the row decoder by using an address signal.
  • the driving module includes a latch, and the latch is used to receive an enable signal.
  • the display control method further includes: inputting a second clock signal to the latch; and the latch reconstructs the waveform of the second clock signal according to the enable signal and then outputs it.
  • the driving module further includes an amplifier, and the signal output by the latch is amplified by the amplifier to drive the pixels of the corresponding row to work.
  • the display control method of the embodiment of the present invention further includes: resetting the enable signal output by the turned-on row decoder.
  • the reset of the enable signal output by the pair of turned-on row decoders can be performed by a reset circuit.
  • the display control method of the embodiment of the present invention further includes: inputting a first clock signal to the reset circuit; the reset circuit resets the enable signal according to the first clock signal.
  • the display control method of the embodiment of the present invention further includes: inputting a second clock signal to the reset circuit; the reset circuit resets the enable signal according to the second clock signal.

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Abstract

一种GOA电路、显示装置和显示器控制方法，包括多个相互独立的GOA单元（10），每一个GOA单元（10）包括一个使能模块（11）以及与使能模块（11）对应设置的驱动模块（12）；使能模块（11）包括用于接收行地址信号的行地址信号的输入端，以及用于根据行地址信号输出使能信号的使能信号输出端；驱动模块（12）包括用于接收使能信号输出端输出的使能信号的使能信号输入端，以及用于根据使能信号输出驱动信号的驱动信号输出端，驱动信号输出端连接与驱动模块（12）对应设置的行的栅线，以将驱动信号发送至对应行的栅线，选通对应行。GOA电路支持随机寻址，产品良率高，功耗低，复位操作不依赖外部时钟信号，输出波形质量高。

Description

一种GOA电路、显示装置和显示器控制方法 技术领域
本发明涉及显示面板的技术领域，更具体地说，涉及一种GOA电路、显示装置和显示器控制方法。
 背景技术
Gate driver on array（GOA）电路广泛应用于LCD和AMOLED等电子显示器中，它是显示面板的关键部分，用于向像素矩阵提供扫描脉冲信号。
传统的GOA电路基于前级触发后级的基本思想设计，一般由自举电容和单一极性的晶体管组成。基于该设计，像素阵列的扫描只能顺序进行，无法随机进行。
当屏幕有N行，采用逐行扫描，刷新率是60Hz，留给每一行的时间是1/60/N。驱动GOA的时钟线的电容负载正比于：C gon+C ov*（N-1）+C pixel。C gon是处于激活状态的GOA对时钟线的负载贡献，C ov是处于非激活状态的其余N-1级GOA对时钟线的负载贡献，C pixel是正在扫描的行上所有像素对时钟线的负载贡献。当GOA输出晶体管尺寸增加时，Cgon和Cov都会按比例增加。
当屏幕尺寸不断增加、分辨率不断增高、像素密度不断增加时，对GOA电路的挑战会不断增加，这表现在：
每一行像素数量增加，GOA电路的负载增加(Cpixel)。
每一行像素的尺寸减小，与之配合的GOA电路可以使用的面积不断减小，制作GOA电路的晶体管尺寸受到进一步限制，驱动能力下降。
绝对行数的增加使得每一行的扫描时间不断减小（1/60/N），为了满足更为苛刻的时序要求，GOA输出晶体管的尺寸需要增加。这个要求不仅和前述面积减小矛盾，而且导致Cgon和Cov不断增加。
绝对行数的增加使得处于关闭状态的GOA的级数(N-1)不断增加，时钟线的负载相应增加，无用功增加。
绝对行数的增加使得GOA出现缺陷的可能增加。一旦某一级GOA出现失误，就会导致后面所有GOA失误，造成屏幕报废。
以上一切因素导致传统GOA的电路结构在用于尺寸不断增大、分辨率不断增加、像素密度不断提高的屏幕中时，面临的根本困难越来越严重，时序难以满足，功耗不断增加，且良率不断下降。
 技术问题
本发明要解决的技术问题在于，针对现有技术的上述缺陷，提供一种GOA电路、显示装置和显示器控制方法。
 技术解决方案
本发明解决其技术问题所采用的技术方案是：提供一种GOA电路，包括多个相互独立的GOA单元，每一个所述GOA单元包括一个使能模块以及与所述使能模块对应设置的驱动模块；
所述使能模块包括用于接收行地址信号的行地址信号的输入端，以及用于根据所述行地址信号输出使能信号的使能信号输出端；
所述驱动模块包括用于接收所述使能信号输出端输出的使能信号的使能信号输入端，以及用于根据所述使能信号输出驱动信号的驱动信号输出端，所述驱动信号输出端连接与所述驱动模块对应设置的行的栅线，以将所述驱动信号发送至所述对应行的栅线，选通所述对应行。
本发明还提供一种显示装置，包括以上所述的GOA电路。
本发明还提供一种显示器控制方法，所述方法包括：
输入寻址信号至显示器的GOA电路中的各个行译码器；
开启与所述寻址信号对应的行译码器；
通过开启的行译码器输出使能信号至显示器的GOA电路的驱动模块；
通过接收使能信号的驱动模块驱动对应行的像素工作。
 有益效果
实施本发明的一种GOA电路、显示装置和显示器控制方法，具有以下有益效果：本发明提供了一种支持随机寻址的GOA电路，该GOA电路允许数据不按照行的顺序写入屏幕，在屏幕大部分区域是静态图像，只有少部分区域不断变化时，只需要对该部分区域进行编程，且由于图像不变的行未选通，所以动态功耗有效降低，同时可以增加留给图像改变的每一行的时间，使得在显示尺寸和显示功率、显示刷新率之间可以实现实时、动态调整的可能。
另外，本发明的GOA电路中后级触发不依赖于前级的触发，所以当孤立一级GOA单元出现缺陷时，其余GOA单元的功能不会受到影响，使屏幕的良率和评级得到提升，提供了动态修理屏幕的可能。而且本发明的GOA电路不使用传统的自举结构，在某些实施例中时钟线不需要直接驱动GOA单元中的输出晶体管，因此，可以大大减少（N-1）级非活跃GOA单元对动态功耗的影响。
进一步地，本发明的GOA电路复位操作不依赖外部时钟信号，输出波形质量高，适用于高分辨率、大尺寸屏幕。
 附图说明
下面将结合附图及实施例对本发明作进一步说明，附图中：
图1是本发明一种GOA电路中单个GOA单元第一实施例的结构示意图；
图2是本发明一种GOA电路中单个GOA单元第二实施例的结构示意图；
图3是为顺序编码译码器的译码器的电路原理图；
图4是本发明以N型晶体管实现的行译码器的电路原理图；
图5是本发明以P型晶体管实现的行译码器的电路原理图；
图6a是以N型晶体管实现的行译码器的版图设计图（晶体管未合并）、图6b是根据本发明的预设条件合并晶体管后的行译码器的版图设计图，图6c是图6b的电路原理图；
图7a是以N型晶体管实现的行译码器（晶体管未合并）的电流流向示意图，图7b是根据本发明的预设条件合并晶体管后的行译码器的电流流向示意图；
图8是本发明重置模块第一实施例的电路原理图；
图9是本发明重置模块第二实施例的电路原理图；
图10为本发明一实施例提供的正边沿触发器的结构示意图；
图11为本发明实施例提供的锁存器的电路原理图；
图12为本发明实施例提供的缓冲反相器的电路原理图；
图13a为采用P型晶体管做译码器的单个GOA单元的电路原理图，图13b为采用N型晶体管做译码器的单个GOA单元的电路原理图；
图14a为重置模块采用第一实施例的单个GOA单元的电路原理图，图14b为采用图14a的电路的单级工作时序；
图15为采用图14a电路的单级工作时序仿真验证图；
图16为采用图14a电路的全屏GOA电路的示意图；
图17为图16的多级级联工作时序仿真验证图；
图18为重置模块采用第二实施例的单个GOA单元的电路原理图和工作时序图；
图19为图18的工作时序仿真验证图；
图20为采用图18电路的全屏GOA电路的示意图；
图21为图20的工作时序图和工作时序仿真验证图；
图22为本发明实施例的GOA电路在可卷曲收藏显示屏中的布局示意图；
图23为本发明实施例的GOA电路在拼接屏幕中的布局示意图；
图24为本发明实施例的一种显示器控制方法的流程示意图。
 本发明的最佳实施方式
为了对本发明的技术特征、目的和效果有更加清楚的理解，现对照附图详细说明本发明的具体实施方式。
参考图1，为本发明一种GOA电路第一实施例的结构示意图。
如图1所示，该实施例的GOA电路包括多个相互独立的GOA单元10，每一个GOA单元10包括一个使能模块11以及与该使能模块11对应设置的驱动模块12。本发明的GOA电路基于互补极性的晶体管，即在面板上同时存在N型和P型晶体管。
使能模块11，包括用于接收行地址信号的输入端，以及用于根据所述行地址信号输出使能信号的使能信号输出端。
这里，需要说明的是，本发明并不限定行地址信号的来源。在一些具体实施例中，该行地址信号可以由外部的驱动IC产生，但在另一些实施例中，行地址信号也可以由显示屏自身产生。例如，当显示屏可以提供两种互补极性晶体管时，在显示屏上设计专用电路，该专用电路可直接产生前述行地址信号，而不需要外部的驱动IC提供。
可选的，本发明实施例的使能模块11为基于二进制编码的行译码器，或者为基于格雷码编码的行译码器。其中，每一行译码器可以包括多个串联的晶体管，且相邻行、同一列的两个晶体管在满足预设条件时合并为一个晶体管。
通过使用本发明实施例的行译码器，可以实现随机寻址，允许数据不按照行的顺序写入屏幕，且后级触发不依赖于前级的触发，有效提升屏幕良率和评级，给动态修理屏幕提供了可能，而且通过采用格雷码编码的行译码器可以减少版图中的横向跨线，允许更多的晶体管合并，在最常使用的顺序扫描过程中减少译码器的动态功耗。
以下以顺序编码译码器与本发明的行译码器设计进行对比说明：
如图3所示，为顺序编码译码器的电路原理图，该行译码器以4位16级的GOA为例，如果以顺序编码来设计译码器，则第0级编码是0000、第1级编码是0001、……、第15级编码是1111，具体如表1所示。
Figure 535848dest_path_image001
表1
由图3可以看出，以顺序编码实施的译码器存在很多横向跨线，并且每一行需要的横向跨线数目不一。对于2 N级译码器，最坏情况下，在第2 N-1 -1和2 N-1级之间，需要的横向跨线达到（N-1）条。而由于横向跨线过多，必然对屏幕带来一定影响。如：占用行高，限制像素密度（PPI）的增加；增加连线之间的互感，造成信号串扰、增加连线负载，引起动态功耗和延时上升；不利于修理、不利于良率提升。
而采用本发明的基于格雷码编码的行译码器，由格雷码的性质可以知道，相邻编码之间只有1位不同，所以本发明的每一行译码器只需要一根横向跨线，这个性质与屏幕分辨率的大小无关，即无论是FHD或者4K UHD，在使用本发明的GOA行译码器时每一行的横向跨线都只需要一条。其中，本发明基于格雷码编码的行译码器的一个具体实施例的电路原理图如图4所示。该实施例的行译码器以4位16级GOA为例，则第0级编码是0000、第1级编码是0001、第2级编码是0011、第3级编码是0010、……、第15级编码是1000，具体如表2所示。
Figure 727795dest_path_image002
表2
这里需要说明的是图3、图4的原理图中晶体管为N型晶体管且只有16级、4个地址位。但本发明适用范围应包括N型和P型晶体管以及任意多级的情况。另外，图3、图4中的晶体管符号仅代表此处需要晶体管，并不代表此处晶体管的数量。特别的，在图4的原理图中，如果相邻行、同一列的两个晶体管满足预设条件时可以合并为一个晶体管。即相邻行、同一列的两个晶体管在满足预设条件时可以合并为一个尺寸更大、驱动能力更高的晶体管。
其中，相邻行、同一列的两个晶体管满足预设条件包括：两个晶体管的栅极短接在一起，且各自是本行译码器的最高位的晶体管，或者两个晶体管的栅极短接在一起，且紧邻前一高位的晶体管合并在一起。
当然，本发明的行译码器也可以采用P型晶体管实现，其中，P型晶体管的实现和N型晶体管的实现类似，区别点在于：编码0对应正信号，编码1对应反信号，且电压极性与N型对称。具体的，以P型晶体管实现的电路原理图如图5所示，具体编码如表3所示。
Figure 932380dest_path_image003
表3
同样地，P型晶体管实现的行译码器中的晶体管的合并条件与N型晶体管的合并条件相同，在此不再赘述。
进一步地，如图6b所示，为本发明以N型晶体管实现的行译码器的版图设计图。本发明通过采用前述的以晶体管串联实现的行译码器，可以使得行译码器的版图实现十分紧凑、节省面积和优化延时的效果。
具体的，如图6b所示，同一行的晶体管相互间是串联的，所以同一行的相邻晶体管的源漏极可以共用，不需要使用金属和接触孔来实现连接，该设计方式既可以节省横向的面积，又可以有效避免金属连线带来的接触电阻和负载电容对行译码器延时的影响。
其中，图6a的版图为晶体管未合并的示意图，图6b为晶体管合并后的示意图。
如图6a-6c所示，其最左边第一列（a1）的晶体管（n11~n14），根据预设条件，由于它们的栅极短接在一起，并且各自是本行最高位的晶体管，所以，左边第一列（a1）的晶体管（n11~n14）可以合并，合并后的版图如图6b的左边第一列（a1'）所示。接着考虑图6a左数第二列（a2），由于它们的栅极短接在一起，并且它们紧邻前一高位的晶体管（即左数第一列（a1）的晶体管（n11~n14））已经合并在一起，所以，根据预设条件，左数第二列（a2）的晶体管（n21~n24）也可以合并在一起，合并后的版图如图6b的左数第二列（a2'）所示。接着考虑图6a左数第三列（a3），由于栅极并不全部短接在一起（如图6c所示，晶体管n31与晶体管n32的栅极短接，晶体管n33与晶体管n34的栅极短接，但是晶体管n32与晶体管n33的栅极不短接），所以这一列（a3）的4个晶体管（n31~n34）不能全部合并；但是，上半部分两个晶体管（晶体管n31与晶体管n32）和下半部分两个晶体管（晶体管n33与晶体管n34）的栅极分别短接在一起，并且它们紧邻前一高位的晶体管（即左数第二列（a2）的晶体管（n21~n24））已经合并在一起，所以根据预设条件，上半部分两个晶体管（晶体管n31与晶体管n32）和下半部分两个晶体管（晶体管n33与晶体管n34）可以分别两两合并，合并后的版图如图6b的左数第三列（a3'）所示。最后考虑最低列（a4），这四个晶体管（n41~n44）只有中间两个晶体管（晶体管n42和晶体管n43）的栅极短接在一起，然而中间这两个晶体管（晶体管n42和晶体管n43）的紧邻前一高位的晶体管（晶体管n32和晶体管n33）并没有合并，所以这四个晶体管（n41~n44）不满足预设条件，不能合并，因此，最低列（a4）的四个晶体管（n41~n44）没有任何两个晶体管可以合并，所以最后行译码器合并后的版图如图6b所示。其中，图6b的电路原理图如图6c所示，在图6c中虚线框内的晶体管合并在一起。
这里需要说明的是，合并是指晶体管在版图上原属于不同行的晶体管的有源区（如图6中的灰色区域（AA）可以融合。经过融合，可以使有源区宽度增加，即晶体管的宽度增加，可以获得更高的驱动电流（或等效来看，可以使导通电阻更低）；且相互分离的有源区的边缘之间必须满足制程最小间隔要求的设计规则，而融合之后不需要考虑此规则，对掩膜版制作和光刻的要求都可以得到降低，对制程良率有很大的改善。
以下以图7a和图7b对合并后的行译码器的优势作进一步说明。
如图7a所示，考虑0001行被选中的情形。在没有合并的情况下，电流只能从本行的4个串联的TFT流过。在合并的情况下，电流向高位流动时可迅速分散到更宽的路径中（如图7b所示）。由于电阻和电流路径宽度成反比，越到高位，电阻越小，所以对使能端放电的总电阻比不合并的小，即译码速度加快。
假设，不合并情况下单个晶体管开启后的有效电阻是R，两个晶体管合并后有效电阻降为R/2。所以不合并情况下，每一行的放电总电阻为4*R；合并情况下的放电总电阻为R*（1+1/2+1/4+1/8）<2*R（等比级数）。考虑一个4096行的屏幕，需要14位地址，14个晶体管串联。不合并情况下总电阻为14*R，合并后总电阻是R*（1+1/2+1/4+1/8+ …… + 1/4096）<2*R。根据等比级数的特性可以看出合并后的总放电电阻不会随着分辨率行数的增加而等比例增加，而是存在一个上限，因此放电时间即译码时间在合并后即不受分辨率增加的影响。所以合并技术使得本发明的行译码设计可以支持高分辨率屏幕，使得译码速度基本和增加的地址线无关。
驱动模块12，其包括与所述使能模块11的使能信号输出端连接、用于接收所述使能信号输出端输出的使能信号的使能信号输入端，以及用于根据所述使能信号输出驱动信号的驱动信号输出端，所述驱动信号输出端连接与所述驱动模块12对应设置的行的栅线，以将所述驱动信号发送至所述对应行的栅线，选通所述对应行。
可选的，该驱动模块12所输出的驱动信号为脉冲信号。其中，该驱动模块12可以为脉冲发生器。
本发明实施例的方案，提供了一种支持随机寻址的GOA电路，该GOA电路允许数据不按照行的顺序写入屏幕，在屏幕大部分区域是静态图像，只有少部分区域不断变化时，只需要对该部分区域进行编程，且由于图像不变的行未选通，所以动态功耗有效降低，同时可以增加留给图像改变的每一行的时间，使得在显示尺寸和显示功率、显示刷新率之间可以实现实时、动态调整的可能。
另外，本发明的GOA电路中后级触发不依赖于前级的触发，所以当孤立一级GOA单元10出现缺陷时，其余GOA单元10的功能不会受到影响，使屏幕的良率和评级得到提升，提供了动态修理屏幕的可能。而且本发明的GOA电路不使用传统的自举结构，时钟线不需要直接驱动GOA单元10中的输出晶体管，因此，可以大大减少（N-1）级非活跃GOA单元10对动态功耗的影响。
本发明的GOA电路适用于高分辨率、大尺寸屏幕。
参考图2，为本发明一种GOA电路第二实施例的结构示意图。
该实施例在实施例一的基础上，进一步地，每一个GOA单元10还包括与所述使能模块11的使能信号输出端连接、用于在所述驱动模块12输出驱动信号后并将所述对应行选通后、将所述使能模块11重置的重置模块13。
可选的，该重置模块13可以包括一个或者多个。当该重置模块13包括多个时，每一个重置模块13与每一行译码器对应设置。
其中，在行译码器中的任意一行译码器完成一次使能信号输出，并使驱动模块12输出驱动信号后，该行的重置模块13都进行重置，以使在下一个行地址信号到来时重新选择输出驱动信号的行。具体的，如果使能模块11输出的使能信号为高电平（1），则重置模块13将重置为低电平（0）；如果使能模块11输出的是低电平（0），则重置模块13将重置为高电平（1）。
如图8所示，为本发明以重置模块13第一实施例的电路原理图。在该实施例中，是以P型晶体管组成的译码器的任意一行与该行对应设置的重置模块13的一个实施例。
如图8所示，该重置模块13可以包括复位晶体管。
该复位晶体管的第一电极连接所述使能模块11的使能信号输出端，复位晶体管的第二电极接地信号（GND），复位晶体管的栅极连接第一时钟信号（CLKR）。这里需要说明的是，该第一时钟信号（CLKR）为由外部提供的额外的时钟信号。进一步地，该实施例是以P型晶体管组成的行译码器，当采用N型晶体管组成的行译码器时，其极性与P型晶体管组成的行译码器完全对称，在此不再赘述。
图8以P型晶体管做译码器、译码输出为高电平作示例。
如图8所示，当第一时钟信号（CLKR）的高脉冲到来时，复位晶体管打开，对该行译码器的输出端被下拉到低电平，该行译码器的输出端被重置为低电平。
如图9所示，为本发明以重置模块13第二实施例的电路原理图。在该实施例中，是以P型晶体管组成的译码器的任意一行与该行对应设置的重置模块13的一个实施例。
如图9所示，该重置模块13包括下拉晶体管135、第一级正边沿触发器132、第一级反相器131、第二级正边沿触发器134和第二级反相器133。
第一级正边沿触发器132的正输入端（D）和第一级反相器131的输入端一并连接使能模块11的使能信号输出端，第一级正边沿触发器132的反输入端连接第一级反相器131的输出端，第一级正边沿触发器132的时钟信号输入端（CK）与第二级反相器133的输入端一并连接第二时钟信号（CLK）；第二级正边沿触发器134的正输入端（D）连接第一级正边沿触发器132的正输出端（Q），第二级正边沿触发器134的反输入端连接第一级正边沿触发器132的反输出端，第二级正边沿触发器134的时钟信号输入端连接第二级反相器133的输出端，第二级正边沿触发器134的正输出端（Q）连接下拉晶体管135的栅极。其中，下拉晶体管135的第一电极连接使能模块11的使能信号输出端，下拉晶体管135的第二电极接地信号（GND）。
该实施例中，重置模块13不需要额外的重置时钟，其与本级锁存器共用一个时钟（CLK）及其反向信号，即本实施例中的（CLK）为与本级锁存器共用的（CLK）。
如图9所示，本实施例的重置模块13是由两级级联的正边沿触发器和反相器组成的。其中，正边沿触发器是数字逻辑电路中的基本电路之一，其基本功能是：只在输入时钟的上升沿将输入端（D）的信号存储并送到输出端（Q），其他时刻不管输入端（D）如何变化，输出端（Q）的信号保持不变。基于该原理，本实施例中重置模块13的重置原理为：EN被选中、输出高电平时，在CLK上升沿锁存该高电位，并在CLK的下一个下降沿传递到下拉晶体管135的栅极（NRES端），打开下拉晶体管135，将EN重置到低电平；EN没被选中、输出为低电平时，触发器无输出，下拉晶体管135的栅极（NRES端）始终为低电平，下拉晶体管135关闭，不影响EN电位。
本发明实施例中，正边沿触发器具有多种实现形式，本发明不局限于该触发器的具体实现。以下以一个具体实施例进行说明。具体的，如图10所示，在该实施例中，所应用的正边沿触发器可以为主从触发器，其可以由两级锁存器组成。
如图10所示，第一级正边沿触发器132和第二级正边沿触发器134均包括主触发器1301、从触发器1302和主从反相器1303。
主触发器1301的输入端（S）为正边沿触发器的正输入端（D），主触发器1301的正输出端连接从触发器的输入端（S），主触发器的复位端（R）为正边沿触发器的反输入端，主触发器1301的反输出端连接从触发器1302的复位端（R）；从触发器1302的正输出端（Q）为正边沿触发器的正输出端（Q），从触发器1302的反输出端为正边沿触发器的反输出端，从触发器1302的时钟信号输入端（CP）通过主从反相器1303的输出端，主从反相器1303的输入端和主触发器1301的时钟信号输入端（CP）的连接端为正边沿触发器的时钟信号输入端（CK）。
进一步地，本发明实施例的驱动模块12可以包括锁存电路121。和缓冲放大电路122，其中，锁存电路121的第一端连接第二时钟信号（CLK），锁存电路121的第二端连接使能模块11的使能信号输出端，锁存电路121的第三端连接缓冲放大电路122输入端，缓冲放大电路122的输出端作为驱动模块12的驱动信号输出端连接与驱动模块12对应设置的行的栅线。
进一步地，本发明实施例的驱动模块12还可以包括缓冲放大电路122。此时，锁存电路121的输出端不直接与驱动模块12对应设置的行的栅线连接，而是先与缓冲放大电路122的输入端连接，然后缓冲放大电路122的输出端再作为驱动模块12的驱动信号输出端连接与驱动模块12对应设置的行的栅线。
进一步地，本发明实施例中，锁存电路121可以包括锁存器，缓冲放大电路122可以由一级反相器组成或者由多级级联的反相器组成。
在一个具体实施例中，若缓冲放大电路122由一级反相器组成，锁存电路121由锁存器组成，则锁存器的输入端（S）连接第二时钟信号（CLK），锁存器的使能端（CP）连接使能模块11的使能信号输出端，锁存器的输出端（Q）连接一级反相器的输入端，一级反相器的输出端连接于驱动模块12对应设置的行的栅线。其中，锁存器的输入端（S）为锁存电路121的数据输入端，锁存器的使能端（CP）为锁存电路121的时钟输入端，锁存器的输出端（Q）为锁存电路121的输出端；一级反相器的输入端为缓冲放大电路122的输入端，一级反相器的输出端为缓冲放大电路122的输出端。
进一步地，在另一个具体实施例中，若缓冲放大电路122由多级级联的反相器组成，锁存电路121由锁存器组成，假设有n级，n为大于或等于2的整数，则锁存器的输入端（S）连接第二时钟信号（CLK），锁存器的使能端（CP）连接使能模块11的使能信号输出端，锁存器的输出端（Q）连接第1级反相器的输入端，第n级反相器的输出端连接于驱动模块12对应设置的行的栅线；锁存器的输入端（S）为锁存电路121的数据输入端，锁存器的使能端（CP）为锁存电路121的时钟输入端，锁存器的输出端（Q）为锁存电路121的输出端；第1级反相器的输入端为缓冲放大电路122的输入端，第n级反相器的输出端为缓冲放大电路122的输出端。
这里，本发明实施例所采用的锁存器均为带有门控功能的锁存器，其工作原理为：
以使能端（CP）高电平有效的锁存器为例：
当CP电位为低电平时，输出端Q保持不变，输入端S的信号不影响输出端Q。
当CP电位为高电平时，输出端Q的二进制信号随着输入端S的输入电位变化。可以理解地，锁存器有多种实施方案，本发明不局限于锁存器的某一种具体实施方案。本发明通过在每个GOA单元10中采用锁存器可以产生以下优势：利用锁存原理，可以有效抑制电路内部交流信号或毛刺信号偶合到输出端，且锁存器具有波形重建功能，即使外部时钟波形因为RC延时产生变形，经过锁存器重建以后，也能输出高质量方波脉冲。
以下以一个具体的实施例对本发明采用的锁存器进行说明，其中，最常用的锁存器为SR型锁存器。
如图11所示，在该实施例中，锁存器包括：锁存反相器1210、第一与门1211、第二与门1212、第一或非门1213和第二或非门1214。
锁存反相器1210的输入端与第一与门1211的第一输入端一并连接第二时钟信号（CLK），锁存反相器1210的输出端连接第二与门1212的第二输入端，第一与门1211的第二输入端和第二与门1212的第一输入端一并连接使能模块的使能信号输出端；第一与门1211的输出端连接第一或非门1213的第一输入端，第一或非门1213的第二输入端连接第二或非门1214的输出端，第一或非门1213的输出端连接第二或非门1214的第一输入端，第一或非门1213的输出端还连接缓冲放大电路122的输入端；第二或非门1214的第二输入端连接第二与门1212的输出端。
其中，第一与门1211的第一输入端为锁存电路121的第一端，第一与门1211的第二输入端和第二与门1212的第一输入端的连接端为锁存电路121的第二端，第一或非门1213的输出端为锁存电路121的第三端。
进一步地，本发明实施例中缓冲放大电路中所采用的反相器均可以由晶体管组成。
具体的，如图12所示，每一个反相器均可以包括：P型晶体管和N型晶体管。
具体的，P型晶体管的第一电极连接恒压高电位（VGH），P型晶体管的第二电极连接N型晶体管的第一电极，N型晶体管的第二电极连接恒压低电位（VGL），P型晶体管的栅极和N型晶体管的栅极连接，P型晶体管的第二电极和N型晶体管的第一电极连接。
其中，P型晶体管的栅极和N型晶体管的栅极的连接端为反相器的输入端，P型晶体管的第二电极和N型晶体管的第一电极的连接端为反相器的输出端。
这里需要说明的是，本发明实施例中，每一个GOA单元10中的P型晶体管是低温多晶硅、无定型硅、或者是由碳、硅、锗三种元素按任意比例混合的材料制作沟道的薄膜晶体管。每一个GOA单元10中的N型晶体管是基于金属氧化物制作沟道的薄膜晶体管。而且，本发明实施例为基于互补极性的晶体管的GOA电路，即在面板上可以同时存在N型和P型晶体管的情况。
参考图13a和图13b为本发明实施例分别采用P型晶体管和N型晶体管做译码器的单个GOA单元10的电路原理图。
如图13a和图13b所示，其中，VSS为输入的直流低电平，VDD为输入的直流高电平，S[0:N]为输入选址信号，CLK为输入时钟信号，EN为GOA单元10的内部使能节点。NFET表示N型晶体管组成的行译码器，PFET 表示P型晶体管组成的行译码器，R表示重置模块13，121表示锁存电路，Buf表示缓冲放大电路122。
参考图14a和图14b，图14a是以P型晶体管组成译码器、且重置模块13采用图8所示第一实施例的单个GOA单元10的电路原理图。在该实施例中，以4位地址为例；锁存电路121包括锁存器；
如图14b所示，CLK1~CLK4均可以由驱动IC提供，在屏幕开启显示后持续提供；S[0:N]为输入行译码器的行地址信号，Dn-2、Dn-1、Dn、Dn+1、Dn+2为输入行译码器的行地址信号（S[0:N]）中不同时段的行地址信号。
时段t1：为地址译码阶段，S[0:N]中的行地址信号Dn对应的某一级GOA单元10中的行译码器被选中，该行的行译码器的使能信号输出端（EN）输出的使能信号为高电平，由于第一时钟信号（CLKR）为低电平，所以重置模块13中的复位晶体管关闭，不影响使能信号的输出；而第二时钟信号（CLK）的上升沿到来，锁存器将输入端（S）输入的高电平信号存储并送到输出端（Q）输出至缓冲放大电路122，由缓冲放大路122处理后输出至与该行对应的栅线。
时段t2：使能节点（EN）输出的仍为高电平，重置模块13中的复位晶体管仍处于关闭状态，第二时钟信号（CLK）电压回落，带动输出端（OUT）电压回落。
时段t3：第一时钟信号（CLKR）的上升沿到来、为高电平，重置模块13中的复位晶体管被打开，从而将使能节点（EN）下拉到低电平（GND），即行译码器被重置。锁存器的使能端（CP）变为低电平，因此其输出不随输入端(S)的变化而变化，而保持为低电平。
时段t4：EN未被选中，第二时钟信号（CLK）仍处于低电平，锁存器的使能输入端（CP）保持为低电平，其输出不随输入端(S)的变化而变化，仍然保持为低电平，重置模块13中的复位晶体管仍处于低电平，重置模块13中的复位晶体管关闭。
其中，图15为图14a的工作时序仿真验证图，由图15可以看出，仿真结果与工作时序结果相当。其中，采用图14所示的多个GOA单元10的示意图如图16所示。由图16中可以看出在每一级GOA单元10中，和传统的GOA电路不同，每一级GOA单元10的输出只进入像素阵列，不进入之后或之前的任何一级GOA单元10。即本发明的任一级GOA单元10的工作都不依赖于前级或后级的GOA提供使能信号，而是由本级内部的行译码器来产生使能信号。
参考图17为图16的多级级联工作时序仿真验证图。
参考图18，为重置模块采用图9所示第二实施例的单个GOA单元10的电路原理图和工作时序图。该实施例中，重置模块13包括下拉晶体管135、第一级正边沿触发器132、第二级正边沿触发器134；锁存电路121包括锁存器。
如图18所示，CLK由驱动IC提供；S[0:N]为输入行译码器的行地址信号，Dn-3、Dn-2、Dn-1、Dn、Dn+1、Dn+2为输入行译码器的行地址信号（S[0:N]）中不同时段的行地址信号。
时段t1：为地址译码阶段，行地址信号Dn对应的某一级GOA单元10中的行译码器被选中，该行的行译码器的使能信号输出端（EN）输出的使能信号为高电平，由于重置信号（NRES）为低电平，所以下拉晶体管135关闭，不影响使能信号的输出。
时段t2：第二时钟信号（CLK）的一个脉冲到来，锁存电路121中的锁存器将输入端（S）输入的脉冲信号存储并送到输出端（Q）输出至缓冲放大电路122。同时，在这个时钟信号的上升沿，第一级正边沿触发器132将EN高电平锁存，并输出到第一级正边沿触发器132的输出端。在随后到来的时钟信号的下降沿，第二级正边沿触发器134将前述第一级正边沿触发器132输出的高电平锁存，并输出到第二级正边沿触发器134的输出端，并输出至下拉晶体管135的栅极(NRES)。
时段t3：由于重置信号（NRES）升高，下拉晶体管135打开，行译码器的使能信号输出端（EN）被重置为低电平，锁存电路121中的锁存器关闭。在此之后，直到译码器再次被选中为止，行译码器的使能信号输出端（EN）都是低电平，锁存电路121中的锁存器保持关闭，其输出保持为低电平。
其中，图18的工作时序仿真验证图详见图19。由图19可以看出仿真结果与工作时序结果相当。其中，采用图18的电路的全屏GOA电路的示意图如图20所示，其工作时序仿真验证图详见图21。
本发明实施例通过在每一个GOA单元10中引入锁存器，有效抵制电路内部交流信号或毛刺信号偶合到输出端，且具有波形重建功能，即使外部时钟波形因为RC延时而变形也能输出高质量方波脉冲，在某些实施例中，还可以通过自身产生复位（重置）信号（自复位），不依赖于额外的时钟；需要的时钟数少，最少只需要2个相位相反的方波时钟。任意时间可以随机编程的行数比例增加，最高可达全部行数的1/2。特别适合高分辨率、可变尺寸屏幕的电路设计。
另外，本发明实施例的GOA电路还可适用于可折叠或可卷曲收回的屏幕，且对于可折叠或可卷曲收回的屏幕，允许折叠和收回的部分不显示图像、不产生功耗；允许动态调整显示和不显示区域的分界线。
其中，本发明实施例的GOA电路对于可卷曲、可折叠、拼接屏幕在屏幕中的布局如图22和图23所示。
如图22所示，采用本发明实施例的GOA电路，在可卷曲收藏的柔性显示屏中，只需要扫描需要显示图像的部分，即输送给GOA的地址范围为第j+1行到第N行，卷曲收藏部分（承受机械应力部分）可以在第一帧画面输送时编入黑色信号，此后不再扫描，以达到节省功耗、延长使用寿命的目的。在屏幕伸缩调整时，可以通过动态调整输入GOA的地址范围为改变扫描和不扫描的部分，达到动态节省功耗的目的。
如图23所示，本发明实施例的GOA电路可以应用于无缝拼接显示屏，在无缝拼接显示屏中，每块待拼接显示屏设计制造时，译码器预留更高位的地址，并留出冗余的地址线。单块屏幕单独工作时，只需将不需要的高位地址线置于全开电平，保证所有行译码器的高位晶体管全部打开，则只需对低位扫描即可。多块屏幕拼接时，GOA部分在结合处直接电学桥接，地址线、时钟线和供电线各自短接，启用更高位的地址即可。
本发明实施例的方案，提供了一种基于锁存器的、支持随机寻址的GOA电路，该GOA电路允许数据不按照行的顺序写入屏幕，在屏幕大部分区域是静态图像，只有少部分区域不断变化时，只需要对该部分区域进行编程，且由于图像不变的行未选通，所以动态功耗有效降低，同时可以增加留给图像改变的每一行的时间，使得在显示尺寸和显示功率、显示刷新率之间可以实现实时、动态调整的可能。
另外，本发明的GOA电路中后级触发不依赖于前级的触发，所以当孤立一级GOA单元10出现缺陷时，其余GOA单元10的功能不会受到影响，使屏幕的良率和评级得到提升，提供了动态修理屏幕的可能。而且本发明的GOA电路不使用传统的自举结构，时钟线不需要直接驱动GOA单元10中的输出晶体管，因此，可以大大减少（N-1）级非活跃GOA单元10对动态功耗的影响。
本发明的GOA电路适用于高分辨率、大尺寸屏幕。
而且，本发明实施例通过在每一个GOA单元中引入锁存器，有效抵制电路内部交流信号或毛刺信号偶合到输出端，且具有波形重建功能，即使外部时钟波形因为RC延时而变形也能输出高质量方波脉冲，在某些实施例中，还可以通过自身产生复位（重置）信号（自复位），不依赖于额外的时钟；需要的时钟数少，最少只需要2个相位相反的方波时钟。任意时间可以随机编程的行数比例增加，最高可达全部行数的1/2。特别适合高分辨率、可变尺寸屏幕的电路设计。
另外，本发明实施例的GOA电路还可适用于可折叠或可卷曲收回的屏幕，且对于可折叠或可卷曲收回的屏幕，允许折叠和收回的部分不显示图像、不产生功耗；允许动态调整显示和不显示区域的分界线。
进一步地，本发明还提供了一种显示装置，该显示装置包括前述实施例的GOA电路。其中，该显示装置包括但不限于LTPS显示装置、AMOLED显示装置。
本发明还提供了一种显示器控制方法，如图24所示，该显示器控制方法可以包括以下步骤：
步骤S1、输入寻址信号至显示器的GOA电路中的各个行译码器。
步骤S2、开启与寻址信号对应的行译码器。
步骤S3、通过开启的行译码器输出使能信号至显示器的GOA电路的驱动模块。
步骤S4、通过接收使能信号的驱动模块驱动对应行的像素工作。
本发明实施例的显示器控制方法中，显示器的GOA电路可以为前述实施例的GOA电路。
进一步地，本发明实施例的显示器控制方法还包括：开启与寻址信号对应的行译码器时，与寻址信号不对应的行译码器保持关闭。
进一步地，本发明实施例的显示器控制方法还包括：通过寻址信号选择性地开启部分行译码器。
可选的，本发明实施例中，驱动模块包括锁存器，该锁存器用于接收使能信号。
进一步地，本发明实施例的显示器控制方法还包括：输入第二时钟信号至锁存器；锁存器根据使能信号对所述第二时钟信号的波形进行重建之后输出。
进一步地，本发明实施例中，驱动模块还包括放大器，锁存器输出的信号经由放大器放大之后驱动对应行的像素工作。
进一步地，本发明实施例的显示器控制方法还包括：对开启的行译码器输出的使能信号复位。其中，该对开启的行译码器输出的使能信号复位可以通过复位电路执行。
进一步地，本发明实施例的显示器控制方法还包括：输入第一时钟信号至复位电路；该复位电路根据第一时钟信号对使能信号进行复位。
进一步地，本发明实施例的显示器控制方法还包括：输入第二时钟信号至复位电路；该复位电路根据第二时钟信号对使能信号进行复位。
以上实施例只为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并据此实施，并不能限制本发明的保护范围。凡跟本发明权利要求范围所做的均等变化与修饰，均应属于本发明权利要求的涵盖范围。
应当理解的是，对本领域普通技术人员来说，可以根据上述说明加以改进或变换，而所有这些改进和变换都应属于本发明所附权利要求的保护范围。

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  1. 一种GOA电路，其特征在于，包括多个相互独立的GOA单元，每一个所述GOA单元包括一个使能模块以及与所述使能模块对应设置的驱动模块；
    所述使能模块包括用于接收行地址信号的行地址信号的输入端，以及用于根据所述行地址信号输出使能信号的使能信号输出端；
    所述驱动模块包括用于接收所述使能信号输出端输出的使能信号的使能信号输入端，以及用于根据所述使能信号输出驱动信号的驱动信号输出端，所述驱动信号输出端连接与所述驱动模块对应设置的行的栅线，以将所述驱动信号发送至所述对应行的栅线，选通所述对应行。
  2. 根据权利要求1所述的GOA电路，其特征在于，所述使能模块为基于二进制编码的行译码器或者基于格雷码编码的行译码器。
  3. 根据权利要求2所述的GOA电路，其特征在于，所述每一行译码器包括多个串联的晶体管，且相邻行、同一列的两个晶体管在满足预设条件时合并为一个晶体管。
  4. 根据权利要求3所述的GOA电路，其特征在于，所述相邻行、同一列的两个晶体管满足预设条件包括：
    两个晶体管的栅极短接在一起，且各自是本行译码器的最高位的晶体管，或者两个晶体管的栅极短接在一起，且紧邻前一高位的晶体管合并在一起。
  5. 根据权利要求1所述的GOA电路，其特征在于，每一个所述GOA单元还包括与所述使能模块的使能信号输出端连接、用于在所述驱动模块输出驱动信号并将所述对应行选通后、将所述使能模块重置的重置模块。
  6. 根据权利要求5所述的GOA电路，其特征在于，所述重置模块包括复位晶体管；
    所述复位晶体管的第一电极连接所述使能模块的使能信号输出端，所述复位晶体管的第二电极接地信号，所述复位晶体管的栅极连接第一时钟信号。
  7. 根据权利要求5所述的GOA电路，其特征在于，所述重置模块包括下拉晶体管、第一级正边沿触发器、第一级反相器、第二级正边沿触发器和第二级反相器；
    所述第一级正边沿触发器的正输入端和所述第一级反相器的输入端一并连接所述使能模块的使能信号输出端，所述第一级正边沿触发器的反输入端连接所述第一级反相器的输出端，所述第一级正边沿触发器的时钟信号输入端连接与所述第二级反相器的输入端一并连接第二时钟信号；
    所述第二级正边沿触发器的正输入端连接所述第一级正边沿触发器的正输出端，所述第二级正边沿触发器的反输入端连接所述第一级正边沿触发器的反输出端，所述第二级正边沿触发器的时钟信号输入端连接所述第二级反相器的输出端，所述第二级正边沿触发器的正输出端连接所述下拉晶体管的栅极；
    所述下拉晶体管的第一电极连接所述使能模块的使能信号输出端，所述下拉晶体管的第二电极接地信号。
  8. 根据权利要求7所述的GOA电路，其特征在于，所述第一级正边沿触发器和所述第二级正边沿触发器均包括主触发器、从触发器和主从反相器；
    所述主触发器的输入端为正边沿触发器的正输入端，所述主触发器的正输出端连接所述从触发器的输入端，所述主触发器的复位端为正边沿触发器的反输入端，所述主触发器的反输出端连接所述从触发器的复位端；
    所述从触发器的正输出端为正边沿触发器的正输出端，所述从触发器的反输出端为正边沿触发器的反输出端，所述从触发器的时钟信号输入端通过所述主从反相器的输出端，所述主从反相器的输入端和所述主触发器的时钟信号输入端的连接端为正边沿触发器的时钟信号输入端。
  9. 根据权利要求1所述的GOA电路，其特征在于，所述驱动模块包括：锁存电路；
    所述锁存电路的数据输入端连接第二时钟信号，所述锁存电路的时钟输入端连接所述使能模块的使能信号输出端，所述锁存电路的输出端作为所述驱动模块的驱动信号输出端连接与所述驱动模块对应设置的行的栅线。
  10. 根据权利要求9所述的GOA电路，其特征在于，所述驱动模块还包括缓冲放大电路；
    所述缓冲放大电路的输入端连接所述锁存电路的输出端，所述缓冲放大电路的输出端作为所述驱动模块的驱动信号输出端连接与所述驱动模块对应设置的行的栅线。
  11. 根据权利要求10所述的GOA电路，其特征在于，所述锁存电路包括锁存器；所述缓冲放大电路包括一级反相器；
    所述锁存器的输入端连接第二时钟信号，所述锁存器的使能端连接所述使能模块的使能信号输出端，所述锁存器的输出端连接所述一级反相器的输入端，所述一级反相器的输出端连接与所述驱动模块对应设置的行的栅线；
    所述锁存器的输入端为所述锁存电路的数据输入端，所述锁存器的使能端为所述锁存电路的时钟输入端，所述锁存器的输出端为所述锁存电路的输出端；
    所述一级反相器的输入端为所述缓冲放大电路的输入端，所述一级反相器的输出端为所述缓冲放大电路的输出端。
  12. 根据权利要求10所述的GOA电路，其特征在于，所述锁存电路包括锁存器；所述缓冲放大电路包括n级级联的反相器；其中，n为大于或等于2的整数；
    锁存器的输入端连接第二时钟信号，所述锁存器的使能端连接所述使能模块的使能信号输出端，所述锁存器的输出端连接第1级反相器的输入端，第n级反相器的输出端连接与所述驱动模块对应设置的行的栅线；
    所述锁存器的输入端为所述锁存电路的数据输入端，所述锁存器的使能端为所述锁存电路的数据输入端，所述锁存器的输出端为所述锁存电路的输出端；
    所述第1级反相器的输入端为所述缓冲放大电路的输入端，所述第n级反相器的输出端为所述缓冲放大电路的输出端。
  13. 根据权利要求11或12所述的GOA电路，其特征在于，所述锁存器包括：锁存反相器、第一与门、第二与门、第一或非门和第二或非门；
    所述锁存反相器的输入端与所述第一与门的第一输入端一并连接第二时钟信号，所述锁存反相器的输出端连接所述第二与门的第二输入端，所述第一与门的第二输入端和所述第二与门的第一输入端一并连接所述使能模块的使能信号输出端；
    所述第一与门的输出端连接所述第一或非门的第一输入端，所述第一或非门的第二输入端连接所述第二或非门的输出端，所述第一或非门的输出端连接所述第二或非门的第一输入端，所述第一或非门的输出端还连接所述缓冲放大电路的输入端；所述第二或非门的第二输入端连接所述第二与门的输出端；
    所述第一与门的第一输入端为所述锁存电路的数据输入端，所述第一与门的第二输入端和所述第二与门的第一输入端的连接端为所述锁存电路的时钟输入端，所述第一或非门的输出端为所述锁存电路的输出端。
  14. 权利要求11或12所述的GOA电路，其特征在于，所述反相器包括：P型晶体管和N型晶体管；
    所述P型晶体管的第一电极连接恒压高电位，所述P型晶体管的第二电极连接所述N型晶体管的第一电极，所述N型晶体管的第二电极连接恒压低电位，所述P型晶体管的栅极和所述N型晶体管的栅极连接，所述P型晶体管的第二电极和所述N型晶体管的第一电极连接；
    其中，所述P型晶体管的栅极和所述N型晶体管的栅极的连接端为所述反相器的输入端，所述P型晶体管的第二电极和所述N型晶体管的第一电极的连接端为所述反相器的输出端。
  15. 根据权利要求1所述的GOA电路，其特征在于，每一个所述GOA单元中的P型晶体管是低温多晶硅、无定型硅、或者是由碳、硅、锗三种元素按任意比例混合的材料制作沟道的薄膜晶体管。
  16. 根据权利要求1所述的GOA电路，其特征在于，每一个所述GOA单元中的N型晶体管是基于金属氧化物制作沟道的薄膜晶体管。
  17. 一种显示装置，其特征在于，包括权利要求1-16任一项所述的GOA电路。
  18. 一种显示器控制方法，其特征在于，所述方法包括：
    输入寻址信号至显示器的GOA电路中的各个行译码器；
    开启与所述寻址信号对应的行译码器；
    通过开启的行译码器输出使能信号至显示器的GOA电路的驱动模块；
    通过接收使能信号的驱动模块驱动对应行的像素工作。
  19. 根据权利要求18所述的显示器控制方法，其特征在于，所述方法还包括：
    开启与所述寻址信号对应的行译码器时，与所述寻址信号不对应的行译码器保持关闭。
  20. 根据权利要求18所述的显示器控制方法，其特征在于，所述方法还包括：
    所述寻址信号选择性地开启部分行译码器。
  21. 根据权利要求18所述的显示器控制方法，其特征在于，所述驱动模块包括锁存器，所述锁存器用于接收所述使能信号。
  22. 根据权利要求21所述的显示器控制方法，其特征在于，所述方法还包括：
    输入第二时钟信号至所述锁存器；
    所述锁存器根据所述使能信号对所述第二时钟信号的波形进行重建之后输出。
  23. 根据权利要求21所述的显示器控制方法，其特征在于，所述驱动模块还包括放大器，所述锁存器输出的信号经由所述放大器放大之后驱动对应行的像素工作。
  24. 根据权利要求21所述的显示器控制方法，其特征在于，所述方法还包括：
    对开启的行译码器输出的使能信号复位。
  25. 根据权利要求24所述的显示器控制方法，其特征在于，所述对开启的行译码器输出的使能信号复位通过复位电路执行。
  26. 根据权利要求25所述的显示器控制方法，其特征在于，所述方法还包括：
    输入第一时钟信号至所述复位电路；
    所述复位电路根据所述第一时钟信号对使能信号进行复位。
  27. 根据权利要求25所述的显示器控制方法，其特征在于，所述方法还包括：
    输入第二时钟信号至所述复位电路；
    所述复位电路根据所述第二时钟信号对使能信号进行复位。
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