WO2020063359A1 - Procédé de production de mémoire programmable - Google Patents

Procédé de production de mémoire programmable Download PDF

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Publication number
WO2020063359A1
WO2020063359A1 PCT/CN2019/105517 CN2019105517W WO2020063359A1 WO 2020063359 A1 WO2020063359 A1 WO 2020063359A1 CN 2019105517 W CN2019105517 W CN 2019105517W WO 2020063359 A1 WO2020063359 A1 WO 2020063359A1
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WO
WIPO (PCT)
Prior art keywords
layer
finger
isolation
holes
hole
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PCT/CN2019/105517
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English (en)
Chinese (zh)
Inventor
彭泽忠
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成都皮兆永存科技有限公司
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Publication date
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Publication of WO2020063359A1 publication Critical patent/WO2020063359A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the invention relates to a technology for preparing a memory.
  • the technical problem to be solved by the present invention is to provide a method for preparing a programmable memory.
  • the prepared memory has the characteristics of high density and low cost.
  • the technical solution adopted by the present invention to solve the technical problem is a method for preparing a programmable memory, which includes the following steps:
  • step of forming the basic structure setting the conductive medium layer and the insulating medium layer in a predetermined number of layers in a manner that the conductive medium layer and the insulating medium layer alternately overlap to form the basic structure;
  • the step of forming a finger structure on the basic structure divide the basic structure into two interdigitated finger structures by setting a split structure that runs through the top to the bottom of the basic structure, and the finger structure includes at least two Finger strip and a common connection strip, each finger strip in the same interdigitation structure is connected with the common connection strip in the interdigitation structure; the divided structure includes a columnar hole array and an isolation groove filled with an insulating material; The area between two adjacent fingers is called the inter-finger area, and the cylindrical holes in the same inter-finger area are the same cylindrical holes;
  • Steps of forming a cylindrical storage unit According to a preset memory structure, the required intermediate layer dielectric materials are arranged layer by layer on the inner wall of the cylindrical hole, and finally the core dielectric material is filled in the cylindrical hole to form the core dielectric material Floor.
  • the preset memory is: a PN junction semiconductor memory, a Schottky diode memory, or a memory medium memory;
  • the memory medium memory is a resistance change memory, a magnetic change memory, a phase change memory, or a ferroelectric memory.
  • step 2) the columnar holes are separated from each other.
  • the step 2) includes:
  • the base structure is divided into two interdigitated interdigitated structures by providing isolation grooves that run through the top layer to the bottom layer of the basic structure.
  • the interdigitated structure includes at least two finger bars and a common connection bar. The same finger structure Each finger in the finger is connected to the common connection bar in the finger structure;
  • the step 2) includes the following steps:
  • An isolation hole is provided between the center points of the two adjacent cylindrical holes that are adjacent to each other, the isolation hole penetrates into the adjacent two cylindrical holes, and the edge of the isolation hole is located between the center points of the adjacent two cylindrical holes; Fill the isolation holes with insulating material.
  • step 2) in the column hole array, adjacent column holes in the same row invade each other, and the nearest edge of the intruder is between the center point of the intruder and the center point of the intruder, and the nearest edge is The edge closest to the center point of the intruded party.
  • each step is: A) the step of forming a basic structure: setting a predetermined number of conductive medium layers and insulating medium layers in a manner that the conductive medium layer and the insulating medium layer are staggered to form a basic structure body;
  • the base structure is divided into two interdigitated interdigitated structures by providing isolation grooves that run through the top layer to the bottom layer of the basic structure.
  • the interdigitated structure includes at least two finger bars and a common connecting bar. The same finger structure Each finger in the finger is connected to the common connection bar in the finger structure;
  • Steps of forming a cylindrical storage unit According to a preset memory structure, the required intermediate layer dielectric materials are arranged layer by layer on the inner wall of the cylindrical hole, and finally the core dielectric material is filled in the cylindrical hole to form the core dielectric material.
  • the required intermediate layer dielectric materials are arranged layer by layer on the inner wall of the cylindrical hole, and finally the core dielectric material is filled in the cylindrical hole to form the core dielectric material.
  • Floor According to a preset memory structure, the required intermediate layer dielectric materials are arranged layer by layer on the inner wall of the cylindrical hole, and finally the core dielectric material is filled in the cylindrical hole to form the core dielectric material.
  • the present invention is the following steps in order:
  • the required intermediate layer dielectric materials are arranged layer by layer on the inner wall of the columnar hole, and finally the core medium material is filled in the columnar hole to form the core medium material layer;
  • Isolation holes are provided between two adjacent cylindrical holes in the same row and left and right ends of each column of cylindrical holes, and the isolation holes penetrate the core dielectric material in the cylindrical holes on both sides thereof.
  • the insulation medium in the isolation trench and the isolation hole is silicon dioxide or air.
  • the invention has the beneficial effects that the prepared semiconductor memory has high storage density, low process cost and easy implementation.
  • FIG. 1 is a schematic diagram of a three-dimensional structure of a semiconductor memory obtained by the manufacturing method of Embodiment 1 of the present invention.
  • FIG. 2 is a schematic diagram (view from above) of a memory cell according to the present invention.
  • FIG. 3 is a schematic perspective view of step 1 in Embodiment 2 of the present invention.
  • FIG. 4 is a schematic plan view of step 1 in Embodiment 2 of the present invention.
  • FIG. 5 is a schematic diagram of step 2 in Embodiment 2 of the present invention.
  • FIG. 6 is a schematic diagram of step 3 in Embodiment 2 of the present invention.
  • FIG. 7 is a schematic diagram of step 4 in Embodiment 2 of the present invention.
  • FIG. 8 is a schematic diagram of step 5 in Embodiment 2 of the present invention.
  • FIG. 9 is a schematic diagram of step 6 in Embodiment 2 of the present invention.
  • FIG. 10 is a schematic diagram of step 7 in Embodiment 3 of the present invention.
  • FIG. 11 is a schematic diagram of step 8 in Embodiment 3 of the present invention.
  • FIG. 12 shows a range of two adjacent cylindrical holes of Embodiment 4.
  • FIG. 13 shows the positions of the isolation holes of the fourth embodiment.
  • FIG. 14 is a schematic diagram of Step 2 of Embodiment 4.
  • FIG. 14 is a schematic diagram of Step 2 of Embodiment 4.
  • FIG. 15 is a schematic diagram showing Step 3 of Embodiment 4.
  • FIG. 15 is a schematic diagram showing Step 3 of Embodiment 4.
  • FIG. 16 is a schematic diagram of step 4 in Embodiment 4.
  • FIG. 16 is a schematic diagram of step 4 in Embodiment 4.
  • FIG. 17 is a schematic diagram of Step 5 in Embodiment 4.
  • FIG. 17 is a schematic diagram of Step 5 in Embodiment 4.
  • FIG. 18 is a schematic diagram showing Step 6 of Embodiment 4.
  • FIG. 18 is a schematic diagram showing Step 6 of Embodiment 4.
  • FIG. 19 is a schematic diagram of Step 7 of Embodiment 4.
  • FIG. 19 is a schematic diagram of Step 7 of Embodiment 4.
  • FIG. 20 is a schematic diagram of the fifth embodiment.
  • FIG. 1 illustrates one of the semiconductor memory structures prepared by the present invention.
  • 11 is a conductive medium
  • 12 is a first dielectric layer
  • 13 is a core dielectric layer.
  • the area shown by the oval dotted line is the memory.
  • Two memories on the same layer are distributed on both sides of a cylindrical structure.
  • Embodiment 1 This embodiment is a two-layer cylindrical structure, see FIG. 1 and FIG. 2.
  • the materials of the conductive dielectric layer, the first dielectric layer, and the core dielectric layer may be any combination in Table 1.
  • Embodiment 2 The cylinder of this embodiment has a three-layer structure.
  • Step 1 A deposition process is used to arrange the conductive dielectric layer and the insulating dielectric layer in a staggered manner to set a predetermined number of conductive dielectric layers and insulating dielectric layers to form a basic structure.
  • FIG. 3 is a schematic perspective view of the basic structure, and FIG. 4 Is a top view.
  • Step 2 Define with a mask and use deep-well etching to etch the isolation trenches 50 that run through the top to bottom of the basic structure to form two interdigitated interdigitated structures, which include at least two fingers and one Common connection bar, each finger bar in the same finger structure is connected with the common connection bar in the finger structure, and an insulation medium is filled in the isolation groove.
  • 51, 52, 53, 54 are finger bars
  • 55 and 56 are public connection bars
  • the finger bars 51, 53 and the public connection bar 55 form the first interdigitated structure
  • the finger bars 52, 54 are connected to the public
  • the strip 56 forms a second finger structure, and the fingers of the two finger structure are staggered, as shown in FIG. 5.
  • Step 3 Define with a mask and use deep-well etching to form holes 60 through the top to bottom of the basic structure at the isolation trenches to form a columnar hole array; the area between two adjacent fingers is called an inter-finger In the region, the columnar holes in the same interdigital area are the columnar holes of the same row, as shown in Figure 6.
  • Step 4 A layer of programmable dielectric with a thickness of 0.5 to 5 nm is grown on the inner wall of the cylindrical hole by using the ALD process as the first dielectric layer, as shown in FIG. 7;
  • Step 5 Use the ALD process to grow a layer of buffered P-polysilicon or silicon on the inner wall of the columnar hole (that is, the surface of the first dielectric layer) as the second dielectric layer. . See Figure 8.
  • Step 6 After the dielectric layer on the inner wall of the cylindrical hole is set, the core dielectric material is deposited and filled in the cavity inside the cylindrical hole by an ALD process to form a core dielectric material layer.
  • the core dielectric material is an N + semiconductor or a Schottky metal, as shown in FIG. 9.
  • the materials of the conductive dielectric layer, the first dielectric layer, the second dielectric layer, and the core dielectric layer may adopt any combination in Table 2:
  • This embodiment has the following steps after step 6 in Embodiment 2:
  • Step 7 Define it with a mask and use a deep-well etching process to set an isolation hole between the center points of two adjacent cylindrical holes adjacent to each other.
  • the isolation hole invades the two adjacent cylindrical holes and the edge of the isolation hole. Located between the center points of two adjacent cylindrical holes, that is, after the isolation hole is opened, the core dielectric material layer of the cylindrical hole remains as a whole, see FIG. 10;
  • Step 8 Use an ALD process to fill the isolation hole with insulating material, as shown in FIG. 11.
  • the cylindrical holes of Examples 2 and 3 are independent of each other.
  • the adjacent columnar holes in the same row invade each other. Since the isolation holes are provided in the subsequent process, the isolation holes completely isolate the relevant medium in the columnar holes on the left and right sides thereof.
  • the closest edge of the intruder is between the center of the intruder and the center of the intruder, and the nearest edge is the edge closest to the center of the intruder to maintain the integrity of the core medium. See FIGS. 12 and 13.
  • Figure 12 shows the range of two adjacent cylindrical holes
  • Figure 13 shows the location of the isolation holes.
  • This embodiment is an improved embodiment. It includes the following steps:
  • Step of forming a basic structure a predetermined number of conductive medium layers and insulating medium layers are provided in a manner that the conductive medium layer and the insulating medium layer are alternately overlapped to form a basic structure; this step is the same as that of the second embodiment.
  • An ALD process is used to form a first dielectric layer with a layer of 0.5 to 5 nm on the surface of the inner wall of the cylindrical hole, as shown in FIG. 15.
  • the ALD process is used to grow a layer of buffer P-polysilicon or silicon on the surface of the first dielectric layer in the columnar hole to form a second dielectric layer, the thickness of which is optimized according to the requirements of the programmed reverse diode leakage current. See Figure 16.
  • the cavity inside the cylindrical hole is filled with a core dielectric material, such as N + semiconductor or silicon, or Schottky metal, to form the core dielectric material layer; as shown in FIG. 17.
  • a core dielectric material such as N + semiconductor or silicon, or Schottky metal
  • Isolation holes are provided between adjacent two cylindrical holes in the same row and the left and right ends of each row of cylindrical holes, the isolation holes penetrate the core dielectric material layer in the cylindrical holes on both sides, and The left and right ends of the finger strip area are alternately arranged with isolation grooves in rows to form two interdigitated finger prong structures, as shown in FIG. 18.
  • the finger structure of this embodiment is finally formed by drilling holes at the ends of the finger strips, which is different from the method of forming the complete finger structure with isolation grooves in Embodiments 2 and 3. See Figure 20.
  • the hole at the end of the finger can be a cylindrical hole as a storage unit, or it can be an isolation hole.
  • the former is equivalent to expanding the number of storage units.

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Abstract

L'invention concerne un procédé de production d'une mémoire programmable, se rapportant à la technologie de la production de mémoires. La présente invention comprend les étapes suivantes : (1) une étape de formation d'un corps de structure de base ; (2) une étape de formation d'une structure interdigitée sur le corps de structure de base ; et (3) une étape de formation d'une unité de mémoire en colonne : la fourniture de matériaux diélectriques de couche intermédiaire requis sur la paroi interne d'une couche de trou cylindrique par couche selon une structure prédéfinie de la mémoire, et enfin le remplissage du trou cylindrique avec un matériau diélectrique central pour former une couche de matériau diélectrique central. Les effets avantageux obtenus sont que la mémoire à semi-conducteur produite présente une densité de mémorisation élevée, de faibles coûts de traitement et est facile à obtenir.
PCT/CN2019/105517 2018-09-25 2019-09-12 Procédé de production de mémoire programmable WO2020063359A1 (fr)

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CN201811117241.9A CN109686703B (zh) 2018-09-25 2018-09-25 可编程存储器的制备方法
CN201811117241.9 2018-09-25

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Publication number Priority date Publication date Assignee Title
CN109686703B (zh) * 2018-09-25 2020-11-20 成都皮兆永存科技有限公司 可编程存储器的制备方法
CN110610943A (zh) * 2019-08-07 2019-12-24 成都皮兆永存科技有限公司 高密度三维结构半导体存储器及制备方法
CN113035874A (zh) * 2020-04-08 2021-06-25 成都皮兆永存科技有限公司 高密度三维可编程存储器的制备方法
CN112992906B (zh) * 2021-02-19 2023-08-01 成都皮兆永存科技有限公司 全自对准高密度3d多层存储器的制备方法
US20220320178A1 (en) * 2021-03-25 2022-10-06 Jack Zezhong Peng Methods of manufacturing programmable memory devices
CN113644074B (zh) * 2021-06-04 2023-12-15 成都皮兆永存科技有限公司 高密度三维多层存储器及制备方法
CN113540097A (zh) * 2021-07-02 2021-10-22 成都皮兆永存科技有限公司 高密度三维多层存储器及制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7177191B2 (en) * 2004-12-30 2007-02-13 Sandisk 3D Llc Integrated circuit including memory array incorporating multiple types of NAND string structures
CN102709269A (zh) * 2011-01-19 2012-10-03 旺宏电子股份有限公司 改良位线电容单一性的3d阵列存储器装置
CN106910743A (zh) * 2017-04-05 2017-06-30 中国科学院上海微系统与信息技术研究所 三维非易失性存储器件及其制造方法
CN109686703A (zh) * 2018-09-25 2019-04-26 成都皮兆永存科技有限公司 可编程存储器的制备方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7202548B2 (en) * 2005-09-13 2007-04-10 Via Technologies, Inc. Embedded capacitor with interdigitated structure
CN204189796U (zh) * 2014-09-16 2015-03-04 华中科技大学 一种三维半导体存储器件
US9397043B1 (en) * 2015-03-27 2016-07-19 Kabushiki Kaisha Toshiba Semiconductor memory device
US9935124B2 (en) * 2015-11-25 2018-04-03 Sandisk Technologies Llc Split memory cells with unsplit select gates in a three-dimensional memory device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7177191B2 (en) * 2004-12-30 2007-02-13 Sandisk 3D Llc Integrated circuit including memory array incorporating multiple types of NAND string structures
CN102709269A (zh) * 2011-01-19 2012-10-03 旺宏电子股份有限公司 改良位线电容单一性的3d阵列存储器装置
CN106910743A (zh) * 2017-04-05 2017-06-30 中国科学院上海微系统与信息技术研究所 三维非易失性存储器件及其制造方法
CN109686703A (zh) * 2018-09-25 2019-04-26 成都皮兆永存科技有限公司 可编程存储器的制备方法

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