WO2020056923A1 - 一种三维堆叠相变存储器及其制备方法 - Google Patents

一种三维堆叠相变存储器及其制备方法 Download PDF

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WO2020056923A1
WO2020056923A1 PCT/CN2018/118146 CN2018118146W WO2020056923A1 WO 2020056923 A1 WO2020056923 A1 WO 2020056923A1 CN 2018118146 W CN2018118146 W CN 2018118146W WO 2020056923 A1 WO2020056923 A1 WO 2020056923A1
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phase change
strip
layer
horizontal electrode
electrode
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PCT/CN2018/118146
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French (fr)
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缪向水
童浩
沈裕山
蔡旺
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华中科技大学
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/066—Shaping switching materials by filling of openings, e.g. damascene method
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H10B63/845—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays the switching components being connected to a common vertical conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe

Definitions

  • the invention belongs to the technical field of microelectronic devices and memories, and more particularly, relates to a three-dimensional stacked phase change memory and a preparation method thereof.
  • phase change memory is gradually developed to three dimensions in order to meet the demand for high-capacity storage in the era of big data, forming a multi-layer stacked three-dimensional phase change memory.
  • three-dimensional stacked phase change memories are simply stacked vertically based on a horizontal electrode cross-point array structure.
  • the structure is simple, as the number of stacked layers increases, the process steps are cumbersome, and the surface unevenness is exacerbated. Reliability issues;
  • the feature size of memory cells is limited by advanced lithography processes and is costly. In summary, it is not conducive to further multi-layer stacking and high-density integration.
  • the object of the present invention is to provide a three-dimensional stacked phase change memory and a method for manufacturing the same, in which the overall flow process design of its key manufacturing method, the shape setting of each detailed structure, etc. are performed. Improved, compared with the prior art, it can effectively solve the problems of complicated multi-layer stacking steps in the process preparation of three-dimensional stacked phase change memory devices, difficult process realization, and shrinking cell size.
  • the present invention uses a vertical electrode structure to establish three-dimensional phases.
  • the characteristic size of the phase change unit is determined by the thickness of the film (for example, the thickness of the phase change layer can be as low as 2nm, which breaks through the lithographic process limit), and the phase change unit in the formed three-dimensional stacked phase change memory is located at the horizontal electrode The area overlapping with the vertical electrode can effectively simplify the preparation process.
  • a method for manufacturing a three-dimensional stacked phase change memory which includes the following steps:
  • N is a preset positive integer greater than or equal to 2;
  • a second horizontal electrode is prepared on the first insulating layer, the second horizontal electrode has exactly the same pitch distribution as the first horizontal electrode, and the second horizontal electrode is on the first
  • the projection on the insulating layer is completely covered by the projection of the first horizontal electrode on the first insulating layer;
  • a second strip-shaped phase change layer having a certain gap in the center is filled in a region corresponding to a space between two adjacent electrodes of the second horizontal electrode, and the second strip-shaped phase change layer has a distance from the first
  • the strip-shaped phase change layer has exactly the same central gap distribution, and the projection of the second strip-shaped phase change layer on the first insulating layer is completely separated by the first strip-shaped phase change layer on the first insulation. Covered by the projection on the layer;
  • (N-1) ⁇ M insulating layers are prepared on the top insulating layer and projected at positions corresponding to the areas corresponding to the distances between the two adjacent electrodes of the uppermost horizontal electrode.
  • Array through-holes the width of any one of the through-holes of the insulating layer array through-hole is larger than the distance between the two adjacent electrodes, and the bottom surface of the through-holes of the insulating layer array directly reaches the substrate;
  • M is preset A positive integer greater than or equal to 2;
  • a vertical electrode array is prepared between two adjacent insulating layer array through-holes of the insulating layer array through-holes corresponding to the area corresponding to the pitch corresponding to the space between two adjacent electrodes of the same uppermost horizontal electrode. Through holes, the bottom surfaces of the through holes of the vertical electrode arrays reach the substrate directly;
  • the method further includes repeating the step (4) to the step (8) several times in order to form a multi-level Steps of electrode, strip-shaped phase change layer, gate and insulation layer.
  • the total number of the through holes of the vertical electrode array is (N-1) ⁇ (M-1).
  • the width of the first strip-shaped phase change layer having a certain gap in the center is larger than the first level.
  • the distance between two adjacent electrodes in the electrode is 0 to 4um.
  • the width of the first gate tube is larger than that of the first strip-shaped phase change layer, corresponding to any adjacent two electrodes of the first horizontal electrode.
  • the central gap width is 0 ⁇ 4um.
  • a line width of the first horizontal electrode is 2 ⁇ m to 30 ⁇ m, and a pitch is 8 ⁇ m to 60 ⁇ m.
  • the width of the first strip-shaped phase change layer having a certain gap in the center is larger than the first level.
  • the distance between two adjacent electrodes in the electrode is 0 to 2um.
  • the outer edge of the first strip-shaped phase change layer is located on the first horizontal electrode.
  • the width of the first gate tube is larger than that of the first strip-shaped phase change layer, corresponding to any adjacent two electrodes of the first horizontal electrode.
  • the width of the central gap is 0 to 2um.
  • an edge of the first gating tube is located on the first strip-shaped phase change layer.
  • the first horizontal electrodes having a distance from each other are first horizontal electrodes having an equal distance;
  • the first strip-shaped phase change layer with a certain gap in the center obtained by filling for the first strip-shaped phase change layer with a certain gap in the center obtained by filling, the first strip-shaped phase change layer with a certain gap filled in the area corresponding to the distance between any two adjacent electrodes, they are The line width is the same, and the width of the center gap is also the same.
  • the present invention provides a three-dimensional stacked phase change memory prepared by using the above manufacturing method.
  • the existing 3D XPoint memory mainly adopts a planar three-dimensional stacking method.
  • the electrode (bit line) is deposited layer by layer, and then the above steps are repeated to achieve multi-layer stacking.
  • This method can follow the original method of preparing a planar phase change memory.
  • the gate and the phase change memory material can be integrated by simple continuous deposition, but The number of times of photolithography is proportional to the number of layers in the three-dimensional stack.
  • the three-dimensional stacked phase-change memory cell structure and the preparation method in the present invention are based on a horizontal electrode.
  • the present invention adopts a vertical electrode structure. Hole deposition is formed at one time, which greatly reduces the number of lithography during multi-layer stacking and effectively reduces costs. In the preparation process, the functional materials are almost equal in height. Excess materials can be removed by etching, which effectively relieves the multi-layer stacking.
  • the feature size of the memory cell proposed by the present invention is determined by the thickness of the film rather than the width of the process line. This aspect is conducive to increasing the storage density and establishing a large-capacity three-dimensional storage array. The small phase change region size (as low as 2nm) is conducive to reducing operating current and reducing power consumption.
  • the present invention adopts a cross structure of horizontal electrodes and vertical electrodes, which can realize multilayer stacking in the vertical direction.
  • the feature size of the phase change unit is small and the surface is flat, which is beneficial to stacking more layers; it is beneficial to reducing the unit.
  • Phase-change operating current reduces power consumption.
  • 1 (a1) to 1 (a17) are schematic cross-sectional views of a process for preparing a three-layer stack in an embodiment of a three-dimensional stacked phase change memory according to the present invention, which is perpendicular to a horizontal electrode direction;
  • FIG. 1 (a2) is a schematic diagram of preparing a first horizontal electrode on a substrate surface
  • FIG. 1 (a3) is a schematic diagram of preparing a first strip-shaped phase change layer with a gap in the center between the first horizontal electrode pitches;
  • FIG. 1 (a4) is a schematic diagram of forming a first gate tube by filling a gate material in the gap between the first strip-shaped phase change layers;
  • FIG. 1 (a5) is a schematic diagram of preparing a first insulating layer on a lower structure
  • FIG. 1 (a6) is a schematic diagram of preparing a second horizontal electrode over a first insulating layer
  • FIG. 1 (a7) is a schematic diagram of preparing a second strip-shaped phase change layer having the same gap in the center between the second horizontal electrode pitches;
  • FIG. 1 (a8) is a schematic diagram of filling a gate material with a second strip-shaped phase change layer to form a second gate;
  • FIG. 1 (a9) is a schematic diagram of preparing a second insulating layer on the underlying structure
  • FIG. 1 (a10) is a schematic diagram of preparing a third horizontal electrode above the second insulating layer
  • FIG. 1 (a11) is a schematic diagram of preparing a third strip-shaped phase change layer with the same gap in the center between the third horizontal electrode pitches;
  • 1 (a12) is a schematic diagram of filling a gate material with a third stripe of phase change layer to form a third gate
  • FIG. 1 (a13) is a schematic diagram of preparing a third insulating layer on the underlying structure
  • FIG. 1 (a14) is a schematic diagram of preparing a through-hole of an insulating layer array in a horizontal direction on the above structure
  • 1 (a15) is a schematic diagram of forming a vertical isolation layer by filling an insulating material in a through hole of an insulating layer array;
  • FIG. 1 (a16) is a schematic diagram of preparing a through hole of a vertical electrode array on the above structure
  • FIG. 1 (a17) is a schematic diagram of forming a vertical electrode by filling an electrode material in a vertical electrode array through hole.
  • 2 (b1) to 2 (b17) are schematic plan views of a process for preparing a three-layer stack in an embodiment of a three-dimensional stacked phase change memory according to the present invention
  • FIG. 3 is a schematic cross-sectional view of a multilayer three-dimensional stacked phase change memory according to the present invention.
  • N first horizontal electrodes with the same pitch along a certain direction are prepared on the substrate; first stripe phase change layers with a gap in the center are prepared between the first horizontal electrode pitches; A first gate tube is prepared between the gaps of the phase change layer; on the above structure, a first insulating layer is prepared; second horizontal electrodes with the same direction and pitch are prepared at the same vertical position on the first insulating layer; A second strip-shaped phase change layer with a gap in the center is prepared between the horizontal electrode spacings; a second gate tube is prepared between the gaps of the second strip-shaped phase change layer; on the above structure, a second insulating layer is prepared; and stacked in the same way The third layer, the fourth layer, ...; then, a horizontal insulating hole is prepared between the horizontal electrode pitches; a vertical electrode is formed between adjacent insulating holes to form a multi-layer stacked phase change memory with a vertical structure.
  • the method for preparing a three-dimensional stacked phase change memory in the present invention may specifically include the following steps:
  • N is smaller than the maximum number of first horizontal electrodes that the substrate can accommodate in this direction; in order to increase the storage density of the memory as much as possible, N may be taken as large as possible within the value range.
  • each phase change layer having gaps in the first strip-shaped phase change layer is larger than the first horizontal electrode gap by 0 to 4 um.
  • a second insulating layer is prepared on the above structure, the insulating material completely covers the underlying structure, and the second horizontal electrode pin is exposed;
  • N-1 * M insulating layer array through holes having a width slightly larger than the electrode pitch are prepared at the gap positions of the horizontal electrodes, and the bottom of the through holes is the substrate surface;
  • M is smaller than the maximum number of through-holes of the insulating layer that can be accommodated in the direction of the horizontal electrode; in order to increase the storage density of the memory as much as possible, M can be taken as large as possible within the value range.
  • the phase change unit is located in a space overlapping region of the horizontal electrode and the vertical electrode.
  • the horizontal electrodes of each layer have the same number, direction, and line width except that the length decreases as the number of layers increases.
  • the width of each phase change layer is larger than the first horizontal electrode gap by 0 to 4um, which can ensure that the phase change layer can contact the electrode under the overprint error;
  • the phase change layer can also be set similarly.
  • the through hole of the insulating layer array is used to fill the insulating material, so that the phase change and the gate material are divided into different regions in the direction of the horizontal electrode, and the distance slightly larger than the electrode is to ensure the ability to be cut off.
  • the length of each layer of the horizontal electrode decreases in order, which can form a staircase structure, exposing the lower electrode.
  • first horizontal electrodes may be set in a non-equal pitch manner in addition to the equal-pitch settings (of course, the second horizontal electrode and the third horizontal electrode are also similar); the first strip with a certain gap
  • the line width can be different, and the width of the center gap can also be different
  • the second stripe phase change layer and the third stripe phase change Layers are also similar
  • the central gap is used to fill the gate material, and its width is greater than the vertical electrode side length.
  • This embodiment uses a two-layer stacked memory as an example to propose a specific implementation of a three-dimensional stacked phase change memory and a method for manufacturing the same, including the following steps:
  • Step 1 On a single crystal silicon substrate, obtain a number of first horizontal electrode patterns with a line width of 10 ⁇ m in a certain direction and a pitch of 15 ⁇ m along a certain direction by a photolithographic process, and deposit a 100 nm TiW alloy electrode material on the photolithographic substrate. After the stripping process, a first horizontal electrode corresponding to the lithographic pattern is obtained, as shown in FIGS. 1 (a1) to 1 (a2) and FIGS. 2 (b1) to 2 (b2).
  • Step 2 Based on Step 1, the first strip-shaped phase change layer pattern with a gap in the center of the photolithography, the line width is 17 ⁇ m, the gap is 10 ⁇ m, and the pitch is 8 ⁇ m. This pattern covers the spacing of the first horizontal electrode, and the edge 1 ⁇ m on a horizontal electrode, and then a phase change material 100 nm GST was precipitated. After the stripping process, a first phase change layer with array through holes covering the first strip electrode corresponding to the lithographic pattern is obtained, as shown in FIGS. 1 (a3) and 2 (b3).
  • Step 3 On the basis of Step 2, lithography and fill the gate material in the central gap of two adjacent phase-change materials, with a line width of 12 ⁇ m and an edge of 1 ⁇ m on the first phase-change layer to form the first Gating tube, as shown in Figure 1 (a4) and Figure 2 (b4).
  • Step 4 On the basis of Step 3, lithography and deposit 100nm SiO 2 insulating material, completely cover the underlying structure, and expose the first horizontal electrode pins to obtain the first insulating layer, as shown in Figure 1 (a5) and Figure 2 ( b5).
  • Step 5 On the first insulating layer, prepare a second horizontal electrode that is the same as the first horizontal flat electrode except that the length is slightly shorter, as shown in FIGS. 1 (a6) and 2 (b6).
  • Step 6 Based on Step 5, a second strip-shaped phase change layer pattern with a gap in the center of the lithography, with a line width of 17 ⁇ m, a gap of 10 ⁇ m, and a pitch of 8 ⁇ m. This pattern covers the spacing of the second horizontal electrode. 1 ⁇ m on a horizontal electrode, and then a phase change material 100 nm GST was precipitated. After the stripping process, a second phase change layer with array through holes covering the second strip electrode corresponding to the lithographic pattern is obtained, as shown in FIG. 1 (a3) and FIG. 2 (b3), as shown in FIG. 1 (a7) As shown in Figure 2 (b7).
  • Step 7 On the basis of Step 6, lithography and fill the gate material in the central gap of each two adjacent phase change materials with a line width of 12 ⁇ m and an edge of 1 ⁇ m on the second phase change layer to form a second Gating tube, as shown in Figure 1 (a8) and Figure 2 (b8).
  • Step 8 On the basis of Step 7, photolithography and deposition of 100nm SiO 2 insulating material, completely covering the underlying structure, and exposing the second horizontal electrode pin to obtain a second insulating layer, as shown in Figure 1 (a9) and Figure 2 ( b9).
  • Step 9 Repeat the above steps for more layers, as shown in Figure 1 (a10) - Figure 1 (a13) and Figure 2 (b10) - Figure 2 (b13).
  • Step 10 Prepare N-1 * M insulating layer array vias with a width slightly larger than the electrode pitch at the gap positions of the horizontal electrodes.
  • the bottom of the via is the substrate surface, the width is 17 ⁇ m, and the interval is 6 ⁇ m.
  • Horizontal electrical thermal isolation as shown in Figures 1 (a14)-1 (a15) and Figures 2 (b14)-2 (b15).
  • Step eleven prepare N-1 * M-1 vertical electrode array square through holes at the gap positions of the horizontal electrodes, the bottom of the through holes is the substrate surface, and the side length is 8 ⁇ m; and fill the electrode material to prepare vertical electrodes.
  • Both N and M in the present invention can be preset preset positive integers greater than or equal to 2, and the specific sizes of the line width, interval, and central gap of each structure can be flexibly adjusted as required.
  • the gate material in the present invention materials known in the art such as GeSe can be used.

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Abstract

一种三维堆叠相变存储器及其制备方法，其中制备方法具体是在衬底上制备彼此具有间距的第一水平电极；在第一水平电极间距间制备中央具有间隙的第一条状相变层；在第一条状相变层的间隙间制备第一选通管；制备第一绝缘层；在第一绝缘层上的相同垂直位置制备第二水平电极；然后制备第二条状相变层；接着制备第二选通管；然后，在水平电极间距间制备水平方向的绝缘孔；在相邻绝缘孔间制备垂直电极后形成垂直结构的多层堆叠的相变存储器。本发明通过对其关键制备方法的整体流程工艺设计，各个细节结构的形状设置等进行改进，能够有效解决三维堆叠相变存储器件在工艺制备中存在的多层堆叠步骤复杂，工艺实现难度大及单元尺寸微缩等问题。

Description

一种三维堆叠相变存储器及其制备方法 【技术领域】
本发明属于微电子器件及存储器技术领域，更具体地，涉及一种三维堆叠相变存储器及其制备方法。
【背景技术】
作为最可能发展成为未来主流存储器之一的新型存储器，相变存储器为了适应大数据时代对高容量存储的需求，逐渐向三维发展，形成多层堆叠的三维相变存储器。
目前三维堆叠的相变存储器都是基于水平电极交叉点阵列结构进行简单的垂直向上堆叠，虽然结构简单，但随着堆叠层数的增加，工艺步骤繁琐，且表面不平坦现象加剧，带来了可靠性问题；另外，存储单元的特征尺寸大小受限于先进的光刻工艺，成本高昂。综合来说，不利于进一步的多层堆叠与高密度集成。
【发明内容】
针对现有技术的以上缺陷或改进需求，本发明的目的在于提供一种三维堆叠相变存储器及其制备方法，其中通过对其关键制备方法的整体流程工艺设计，各个细节结构的形状设置等进行改进，与现有技术相比能够有效解决三维堆叠相变存储器件在工艺制备中存在的多层堆叠步骤复杂，工艺实现难度大以及单元尺寸微缩等的问题，本发明采用垂直电极结构建立三维相变存储阵列，相变单元特征尺寸的大小由薄膜厚度决定(例如，相变层的厚度可低至2nm，突破光刻工艺限制)，形成的三维堆叠相变存储器其中的相变单元位于水平电极与垂直电极的空间交叠区域，制备工艺可有效简化。
为实现上述目的，按照本发明的一个方面，提供了一种三维堆叠相变 存储器的制备方法，其特征在于，包括下述步骤：
(1)在衬底上制备N条平行于某一方向的、且彼此具有间距的第一水平电极；其中，N为预先设定的、且大于等于2的正整数；
(2)在所述第一水平电极的各相邻两电极的间距对应区域中填充中央具有一定间隙的第一条状相变层；
(3)在所述第一条状相变层的中央间隙中填充选通管材料，形成第一选通管；
(4)在所述衬底上继续制备由绝缘材料构成的第一绝缘层，使该第一绝缘层覆盖所述第一水平电极、所述第一条状相变层及所述第一选通管；所述第一水平电极有部分区域不被覆盖，这部分裸露出的区域用于形成第一水平电极引脚；
(5)在所述第一绝缘层上制备第二水平电极，所述第二水平电极具有与所述第一水平电极完全相同的间距分布，并且，所述第二水平电极在所述第一绝缘层上的投影完全被所述第一水平电极在所述第一绝缘层上的投影所覆盖；
(6)在所述第二水平电极的各相邻两电极的间距对应区域中填充中央具有一定间隙的第二条状相变层，所述第二条状相变层具有与所述第一条状相变层完全相同的中央间隙分布，并且，所述第二条状相变层在所述第一绝缘层上的投影完全被所述第一条状相变层在所述第一绝缘层上的投影所覆盖；
(7)在所述第二条状相变层的中央间隙中填充选通管材料，形成第二选通管；
(8)在所述衬底上继续制备由绝缘材料构成的第二绝缘层，使该第二绝缘层覆盖所述第二水平电极、所述第二条状相变层及所述第二选通管；所述第二水平电极有部分区域不被覆盖，这部分裸露出的区域用于形成第二水平电极引脚；
(9)对于位于顶层的顶层绝缘层，在该顶层绝缘层上、且投影与最上层水平电极各相邻两电极的间距对应区域相对应的位置制备出(N-1)×M个绝缘层阵列通孔，该绝缘层阵列通孔中的任意一个通孔其宽度大于与之对应的相邻两电极的间距，并且这些绝缘层阵列通孔的底面直达衬底；其中，M为预先设定的、且大于等于2的正整数；
(10)在所述绝缘层阵列通孔中填充绝缘材料，用于水平方向上的电热隔离；
(11)对于投影与同一最上层水平电极相邻两电极的间距对应区域相对应的绝缘层阵列通孔，在这些绝缘层阵列通孔的两相邻绝缘层阵列通孔之间制备垂直电极阵列通孔，这些垂直电极阵列通孔的底面直达衬底；
(12)在所述垂直电极阵列通孔中填充电极材料制备垂直电极，从而形成多层堆叠的相变存储器。
作为本发明的进一步优选，在所述步骤(8)完成后、所述步骤(9)开始前，还包括依次重复所述步骤(4)至所述步骤(8)若干次以形成多层水平电极、条状相变层、选通管及绝缘层的步骤。
作为本发明的进一步优选，所述步骤(11)中，所述垂直电极阵列通孔的总个数为(N-1)×(M-1)个。
作为本发明的进一步优选，所述步骤(2)中，对于所述第一水平电极的任意相邻两电极，所述中央具有一定间隙的第一条状相变层的宽度大于该第一水平电极中相邻两电极的间距0～4um。
作为本发明的进一步优选，所述步骤(3)中，对应于所述第一水平电极的任意相邻两电极，所述第一选通管的宽度大于所述第一条状相变层的中央间隙宽度0～4um。
作为本发明的进一步优选，所述步骤(1)中，所述第一水平电极的线宽为2μm～30μm，间距为8μm～60μm。
作为本发明的进一步优选，所述步骤(2)中，对于所述第一水平电极 的任意相邻两电极，所述中央具有一定间隙的第一条状相变层的宽度大于该第一水平电极中相邻两电极的间距0～2um，优选的，该第一条状相变层的外边缘位于第一水平电极上。
作为本发明的进一步优选，所述步骤(3)中，对应于所述第一水平电极的任意相邻两电极，所述第一选通管的宽度大于所述第一条状相变层的中央间隙宽度0～2um，优选的，该第一选通管的边缘位于所述第一条状相变层上。
作为本发明的进一步优选，所述步骤(1)中，所述彼此具有间距的第一水平电极为具有同等间距的第一水平电极；
所述步骤(2)中，对于填充得到的中央具有一定间隙的第一条状相变层，任意两个相邻两电极间距对应区域中填充的具有一定间隙的第一条状相变层它们的线宽相同、且中央间隙的宽度也相同。
按照本发明的另一方面，本发明提供了利用上述制备方法制备得到的三维堆叠相变存储器。
通过本发明所构思的以上技术方案，与现有技术相比，现有的3D XPoint存储器主要采用平面三维堆叠方式，下电极(字线)、绝缘层、选通层、相变存储层、上电极(位线)等逐层沉积，再重复上述步骤实现多层堆叠，该方法可沿用原有平面相变存储器的制备方法，选通管与相变存储材料可通过简单连续沉积实现集成，但是其光刻的次数与三维堆叠的层数成正比，多层堆叠时因光刻制程的增加带来成本的急剧提升，并且每一层电极的制备均引起一定的表面不平整度，多层堆叠时将带来严重的器件可靠性问题。尽管在部分资料(例如本课题组的硕士学位论文《3D XPoint存储器制备工艺研究》)中虽提及“基于垂直电极的3D XPoint存储器”，但仅提供了一个简单的电极结构示意图，没有3D XPoint存储器具体各层的结构设计以及工艺实现方案，更没有考虑实际3D XPoint器件所必须的选通管,而本发明涉及的各层尺寸的设计、套刻的实现以及选通管和存储单元的有效集 成正是垂直三维堆叠相比于水平堆叠方式的难点所在。本发明中的三维堆叠相变存储器单元结构及其制备方法，相较于现有的3D Xpoint结构都是基于水平电极的结构，本发明采用了垂直电极结构，所有位线通过刻蚀后的通孔沉积一次形成，大大减小了多层堆叠时的光刻次数，有效降低成本；制备工艺上，各功能材料面内几乎等高，多余材料可通过刻蚀去除，有效缓解多层堆叠带来的表面不平整问题；此外，本发明提出的存储单元的特征尺寸由薄膜厚度决定，而非工艺线宽，这一方面利于提高存储密度，建立大容量的三维存储阵列，另一方面，可减小相变区域尺寸(可低至2nm)，有利于减小操作电流，降低功耗。
综上，本发明采用水平电极与垂直电极的交叉结构，能够实现垂直方向上的多层堆叠，相变单元的特征尺寸小，表面较为平坦，有利于更多层的堆叠；有利于减小单元相变的操作电流，降低功耗。
【附图说明】
图1(a1)至图1(a17)为本发明三维堆叠相变存储器实施例中三层堆叠的制备工艺流程在与水平电极方向垂直的剖面示意图；
其中，图1(a1)为所选衬底的示意图；
图1(a2)为在衬底表面上制备第一水平电极的示意图；
图1(a3)为在第一水平电极间距间制备中央具有间隙的第一条状相变层的示意图；
图1(a4)为在第一条状相变层间隙中填充选通材料形成第一选通管的示意图；
图1(a5)为在下层结构上制备第一绝缘层的示意图；
图1(a6)为在第一绝缘层上方制备第二水平电极的示意图；
图1(a7)为在第二水平电极间距间制备中央具有相同间隙的第二条状相变层的示意图；
图1(a8)为在第二条状相变层间隙中填充选通材料形成第二选通管的 示意图；
图1(a9)为在下层结构上制备第二绝缘层的示意图；
图1(a10)为在第二绝缘层上方制备第三水平电极的示意图；
图1(a11)为在第三水平电极间距间制备中央具有相同间隙的第三条状相变层的示意图；
图1(a12)为在第三条状相变层间隙中填充选通材料形成第三选通管的示意图；
图1(a13)为在下层结构上制备第三绝缘层的示意图；
图1(a14)为在上述结构上，制备水平方向绝缘层阵列通孔的示意图；
图1(a15)为在绝缘层阵列通孔中填充绝缘材料形成垂直隔离层的示意图；
图1(a16)为在上述结构上，制备垂直电极阵列通孔的示意图；
图1(a17)为在垂直电极阵列通孔中填充电极材料形成垂直电极的示意图。
图2(b1)至图2(b17)为本发明三维堆叠相变存储器实施例中三层堆叠的制备工艺流程俯视图示意图；
其中，图2(b1)～图2(b17)示意图所示过程与图1(a1)～图1(a17)所示相对应。
图3为本发明多层三维堆叠相变存储器的剖面示意图。
【具体实施方式】
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。此外，下面所描述的本发明各个实施方式中所涉及到的技术特征只要彼此之间未构成冲突就可以相互组合。
概括来讲，在衬底上制备N条沿某一方向的具有相同间距的第一水平 电极；在第一水平电极间距间制备中央具有间隙的第一条状相变层；在第一条状相变层的间隙间制备第一选通管；在上述结构上，制备第一绝缘层；在第一绝缘层上的相同垂直位置制备N条方向与间距相同的第二水平电极；在第二水平电极间距间制备中央具有间隙的第二条状相变层；在第二条状相变层的间隙间制备第二选通管；在上述结构上，制备第二绝缘层；同样的方法堆叠第三层、第四层、……；然后，在水平电极间距间制备水平方向的绝缘孔；在相邻绝缘孔间制备垂直电极后形成垂直结构的多层堆叠的相变存储器。
如图1(a1)至图1(a17)所示，本发明中三维堆叠相变存储器的制备方法，具体可以包括以下步骤：
(1)在衬底上制备N条沿某一向方向的具有同等间距的第一水平电极；
其中，N小于衬底沿该方向所能容纳第一水平电极数目的最大值；为了尽可能的提高存储器的存储密度，N可以在取值范围内尽可能取大的值。
(2)在第一水平电极的各相邻两条电极间隙中填充相同的中央具有一定间隙的第一条状相变层；
其中，第一条状相变层具有间隙的每条相变层宽度大于第一水平电极间隙0～4um。
(3)在各两条邻近相变材料的中央间隙中填充选通管材料；
(4)在上述结构上制备第一绝缘层，绝缘材料完全覆盖下层结构，并裸露出第一水平电极引脚；
(5)在第一绝缘层上的与第一水平电极相同的位置，制备除长度稍短外，其他与第一水平平极相同的第二水平电极；
(6)在第二水平电极的各相邻两条电极间隙中，在与第一条状相变层相同的位置上填充除长度稍短外，其他与第一条状相变层相同的第二条状相变层；
(7)在各两条邻近相变材料的中央间隙中填充选通管材料；
(8)在上述结构上制备第二绝缘层，绝缘材料完全覆盖下层结构，并裸露出第二水平电极引脚；
(9)更多层的堆叠则重复上述步骤；
(10)在水平电极的间隙位置制备出N-1*M个宽度稍大于电极间距的绝缘层阵列通孔，通孔底部为衬底表面；
其中，M小于沿水平电极方向所能容纳绝缘层通孔数目的最大值；为了尽可能的提高存储器的存储密度，M可以在取值范围内尽可能取大的值。
(11)在绝缘层阵列通孔中填充绝缘材料，用于水平方向上的电热隔离；
(12)在绝缘层阵列通孔的相邻通孔间制备出N-1*M-1个垂直电极阵列通孔，通孔底部为衬底表面；
(13)在阵列通孔中填充电极材料得到垂直电极。
相变单元位于水平电极与垂直电极的空间交叠区域。各层水平电极，除长度随层数增加而递减外，其数目、方向与线宽均相同。
以步骤(2)形成第一条状相变层为例，每条相变层宽度大于第一水平电极间隙0～4um，能够保证相变层在套刻误差下能与电极接触；第二条状相变层也可以相似进行设置。步骤(10)中，绝缘层阵列通孔是用于填充绝缘材料，从而将相变和选通材料在水平电极方向上分成不同区域，稍大于电极间距是为了保证能隔断。另外本发明中，每层水平电极的长度依次递减，可形成楼梯型的结构，暴露下层电极。
另外，上述的第一水平电极除了同等间距设置外，还可以采用非同等间距的方式来进行设置(当然第二水平电极、第三水平电极等也相类似)；具有一定间隙的第一条状相变层除了采用线宽相同、中央间隙的宽度也相同的设置方式外，线宽可以不相同，中央间隙的宽度也可以不相同(当然第二条状相变层、第三条状相变层等也相类似)；只要不同垂直高度上的水 平电极它们的长度梯度变化即可(如第二水平电极是在沿电极方向上比第一水平电极要短)，保证各层水平电极的引脚能够裸露出来即可。其次，中央间隙的用以填充选通管材料，其宽度大于垂直电极边长即可。
以下为具体实施例：
实施例1
本实施例以两层堆叠存储器为例提出了一种三维堆叠相变存储器及其制备方法具体实施方案，包括以下步骤：
步骤一：在单晶硅衬底上，通过光刻工艺得到若干沿某一方向的线宽为10μm的间距为15μm第一水平电极图形，在光刻后的衬底上沉淀100nmTiW合金电极材料，经过剥离工艺后，得到对应光刻图形的第一水平电极，如图1(a1)～图1(a2)和图2(b1)～图2(b2)所示。
步骤二：在步骤一的基础上，光刻中央具有间隙的第一条状相变层图形，线宽为17μm，间隙为10μm，间距为8μm，该图形覆盖第一水平电极的间距，边缘的1μm在水平电极上，然后沉淀相变材料100nm GST。经过剥离工艺后，得到对应光刻图形的覆盖第一条状电极的具有阵列通孔的第一相变层，如图1(a3)和图2(b3)所示。
步骤三：在步骤二的基础上，在各两条邻近相变材料的中央间隙中光刻并填充选通管材料，线宽为12μm，边缘的1μm在第一相变层上，形成第一选通管，如图1(a4)和图2(b4)所示。
步骤四：在步骤三的基础上，光刻并沉积100nmSiO 2绝缘材料，完全覆盖下层结构，并裸露出第一水平电极引脚，得到第一绝缘层，如图1(a5)和图2(b5)所示。
步骤五：在第一绝缘层上，制备除长度稍短外，其他与第一水平平极相同的第二水平电极，如图1(a6)和图2(b6)所示。
步骤六：在步骤五的基础上，光刻中央具有间隙的第二条状相变层图形，线宽为17μm，间隙为10μm，间距为8μm，该图形覆盖第二水平电极 的间距，边缘的1μm在水平电极上，然后沉淀相变材料100nm GST。经过剥离工艺后，得到对应光刻图形的覆盖第二条状电极的具有阵列通孔的第二相变层，如图1(a3)和图2(b3)所示，如图1(a7)和图2(b7)所示。
步骤七：在步骤六的基础上，在各两条邻近相变材料的中央间隙中光刻并填充选通管材料，线宽为12μm，边缘的1μm在第二相变层上，形成第二选通管，如图1(a8)和图2(b8)所示。
步骤八：在步骤七的基础上，光刻并沉积100nmSiO 2绝缘材料，完全覆盖下层结构，并裸露出第二水平电极引脚，得到第二绝缘层，如图1(a9)和图2(b9)所示。
步骤九：更多层的堆叠则重复上述步骤，如图1(a10)-图1(a13)和图2(b10)-图2(b13)所示.
步骤十：在水平电极的间隙位置制备出N-1*M个宽度稍大于电极间距的绝缘层阵列通孔，通孔底部为衬底表面，宽度为17μm，间隔6μm；并填充绝缘材料用于水平电热隔离，如图1(a14)-图1(a15)和图2(b14)-图2(b15)所示。
步骤十一：在水平电极的间隙位置制备出N-1*M-1个垂直电极阵列方形通孔，通孔底部为衬底表面，边长为8μm；并填充电极材料，制备得到垂直电极，如图1(a16)-图1(a17)和图2(b16)-图2(b17)所示。
本发明中的N、M均可为预先设置的、大于等于2的正整数，各个结构的线宽、间隔、中央间隙等的具体大小均可根据需要灵活调整。
本发明中的选通管材料，可以采用GeSe等现有技术已知材料。
本领域的技术人员容易理解，以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种三维堆叠相变存储器的制备方法，其特征在于，包括下述步骤：
    (1)在衬底上制备N条平行于某一方向的、且彼此具有间距的第一水平电极；其中，N为预先设定的、且大于等于2的正整数；
    (2)在所述第一水平电极的各相邻两电极的间距对应区域中填充中央具有一定间隙的第一条状相变层；
    (3)在所述第一条状相变层的中央间隙中填充选通管材料，形成第一选通管；
    (4)在所述衬底上继续制备由绝缘材料构成的第一绝缘层，使该第一绝缘层覆盖所述第一水平电极、所述第一条状相变层及所述第一选通管；所述第一水平电极有部分区域不被覆盖，这部分裸露出的区域用于形成第一水平电极引脚；
    (5)在所述第一绝缘层上制备第二水平电极，所述第二水平电极具有与所述第一水平电极完全相同的间距分布，并且，所述第二水平电极在所述第一绝缘层上的投影完全被所述第一水平电极在所述第一绝缘层上的投影所覆盖；
    (6)在所述第二水平电极的各相邻两电极的间距对应区域中填充中央具有一定间隙的第二条状相变层，所述第二条状相变层具有与所述第一条状相变层完全相同的中央间隙分布，并且，所述第二条状相变层在所述第一绝缘层上的投影完全被所述第一条状相变层在所述第一绝缘层上的投影所覆盖；
    (7)在所述第二条状相变层的中央间隙中填充选通管材料，形成第二选通管；
    (8)在所述衬底上继续制备由绝缘材料构成的第二绝缘层，使该第二绝缘层覆盖所述第二水平电极、所述第二条状相变层及所述第二选通管； 所述第二水平电极有部分区域不被覆盖，这部分裸露出的区域用于形成第二水平电极引脚；
    (9)对于位于顶层的顶层绝缘层，在该顶层绝缘层上、且投影与最上层水平电极各相邻两电极的间距对应区域相对应的位置制备出(N-1)×M个绝缘层阵列通孔，该绝缘层阵列通孔中的任意一个通孔其宽度大于与之对应的相邻两电极的间距，并且这些绝缘层阵列通孔的底面直达衬底；其中，M为预先设定的、且大于等于2的正整数；
    (10)在所述绝缘层阵列通孔中填充绝缘材料，用于水平方向上的电热隔离；
    (11)对于投影与同一最上层水平电极相邻两电极的间距对应区域相对应的绝缘层阵列通孔，在这些绝缘层阵列通孔的两相邻绝缘层阵列通孔之间制备垂直电极阵列通孔，这些垂直电极阵列通孔的底面直达衬底；
    (12)在所述垂直电极阵列通孔中填充电极材料制备垂直电极，从而形成多层堆叠的相变存储器。
  2. 如权利要求1所述三维堆叠相变存储器的制备方法，其特征在于，在所述步骤(8)完成后、所述步骤(9)开始前，还包括依次重复所述步骤(4)至所述步骤(8)若干次以形成多层水平电极、条状相变层、选通管及绝缘层的步骤。
  3. 如权利要求1所述三维堆叠相变存储器的制备方法，其特征在于，所述步骤(11)中，所述垂直电极阵列通孔的总个数为(N-1)×(M-1)个。
  4. 如权利要求1所述三维堆叠相变存储器的制备方法，其特征在于，所述步骤(2)中，对于所述第一水平电极的任意相邻两电极，所述中央具有一定间隙的第一条状相变层的宽度大于该第一水平电极中相邻两电极的间距0～4um。
  5. 如权利要求1所述三维堆叠相变存储器的制备方法，其特征在于，所述步骤(3)中，对应于所述第一水平电极的任意相邻两电极，所述第一 选通管的宽度大于所述第一条状相变层的中央间隙宽度0～4um。
  6. 如权利要求1所述三维堆叠相变存储器的制备方法，其特征在于，所述步骤(1)中，所述第一水平电极的线宽为2μm～30μm，间距为8μm～60μm。
  7. 如权利要求4所述三维堆叠相变存储器的制备方法，其特征在于，所述步骤(2)中，对于所述第一水平电极的任意相邻两电极，所述中央具有一定间隙的第一条状相变层的宽度大于该第一水平电极中相邻两电极的间距0～2um，优选的，该第一条状相变层的外边缘位于第一水平电极上。
  8. 如权利要求5所述三维堆叠相变存储器的制备方法，其特征在于，所述步骤(3)中，对应于所述第一水平电极的任意相邻两电极，所述第一选通管的宽度大于所述第一条状相变层的中央间隙宽度0～2um，优选的，该第一选通管的边缘位于所述第一条状相变层上。
  9. 如权利要求1所述三维堆叠相变存储器的制备方法，其特征在于，所述步骤(1)中，所述彼此具有间距的第一水平电极为具有同等间距的第一水平电极；
    所述步骤(2)中，对于填充得到的中央具有一定间隙的第一条状相变层，任意两个相邻两电极间距对应区域中填充的具有一定间隙的第一条状相变层它们的线宽相同、且中央间隙的宽度也相同。
  10. 利用如权利要求1－9任意一项所述制备方法制备得到的三维堆叠相变存储器。
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