WO2020056906A1 - 阵列基板及其制作方法，以及显示面板 - Google Patents

阵列基板及其制作方法，以及显示面板 Download PDF

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Publication number
WO2020056906A1
WO2020056906A1 PCT/CN2018/116669 CN2018116669W WO2020056906A1 WO 2020056906 A1 WO2020056906 A1 WO 2020056906A1 CN 2018116669 W CN2018116669 W CN 2018116669W WO 2020056906 A1 WO2020056906 A1 WO 2020056906A1
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Prior art keywords
layer
conductive
gate
metal layer
substrate
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English (en)
French (fr)
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何怀亮
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HKC Co Ltd
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HKC Co Ltd
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Priority to US16/254,586 priority Critical patent/US20200098792A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present application relates to the technical field of electronic circuits, and in particular, to an array substrate and a manufacturing method thereof, and a display panel.
  • one or more thin film transistors are generally provided.
  • a metal layer is usually used to make a gate.
  • metal ions are easily diffused in a subsequent high temperature process and affect the thin film transistor. Due to the switching characteristics, the display is abnormal or the gate is prone to unevenness, forming a tip discharge, which affects the life of the thin film transistor.
  • the main purpose of this application is to propose an array substrate, a manufacturing method thereof, and a display panel, which are intended to ensure the stability of the thin film transistor of the array substrate.
  • the present application proposes a method for manufacturing an array substrate.
  • the method for manufacturing an array substrate includes:
  • a first metal layer and a first conductive layer are deposited on the substrate, and the first metal layer and the first conductive layer are patterned using a first photomask to form a gate and a conductive layer covering the gate. Isolation layer;
  • a semiconductor layer and a second metal layer are sequentially deposited on the gate insulating layer, and the semiconductor layer is patterned to form an active layer, which is patterned using a second photomask.
  • the second metal layer forms a source electrode, a drain electrode, and a pixel electrode.
  • the first metal layer and the first conductive layer are deposited on the substrate, and the first metal layer and the first conductive layer are patterned with a first photomask to form a gate and cover the substrate.
  • the steps of the conductive isolation layer on the gate specifically include:
  • a first conductive layer is deposited on the gate, and the first metal layer is patterned using the first photomask to form a conductive isolation layer.
  • the step of depositing a first metal layer on the substrate specifically includes:
  • a film is formed by a physical vapor deposition method, or the first metal layer is formed on the substrate by a sputtering deposition process.
  • the step of depositing a first conductive layer on the gate specifically includes:
  • the first conductive layer is covered on the gate by physical vapor deposition.
  • the first metal layer and the first conductive layer are deposited on the substrate, and the first metal layer and the first conductive layer are patterned with a first photomask to form a gate and cover the substrate.
  • the steps of the conductive isolation layer on the gate specifically include:
  • the first metal layer is copper or a copper alloy
  • the first conductive layer is conductive by one or more kinds of multi-metal oxide conductive materials such as indium tin oxide, indium zinc oxide, aluminum-doped zinc oxide, indium gallium zinc oxide, zinc tin oxide and other multi-metal oxide conductive materials Laminated structure of materials.
  • multi-metal oxide conductive materials such as indium tin oxide, indium zinc oxide, aluminum-doped zinc oxide, indium gallium zinc oxide, zinc tin oxide and other multi-metal oxide conductive materials Laminated structure of materials.
  • the first metal layer and the first conductive layer are deposited on the substrate, and the first metal layer and the first conductive layer are patterned with a first photomask to form a gate and cover the substrate.
  • the steps of the conductive isolation layer on the gate specifically include:
  • a first metal layer and a first conductive layer are sequentially deposited on the substrate, and the first metal layer and the first conductive layer are patterned using a first photomask to form a gate and a layer covering the gate.
  • Conductive isolation layer is sequentially deposited on the substrate, and the first metal layer and the first conductive layer are patterned using a first photomask to form a gate and a layer covering the gate.
  • the step of sequentially depositing a first metal layer and a first conductive layer on the substrate specifically includes:
  • a film is formed by a physical vapor deposition method, or a first metal layer is formed on a substrate by a sputtering deposition process, and then a first conductive layer is covered on the first metal layer by a physical vapor deposition.
  • the first metal layer and the first conductive layer are deposited on the substrate, and the first metal layer and the first conductive layer are patterned with a first photomask to form a gate and cover the substrate.
  • the steps of the conductive isolation layer on the gate specifically include:
  • the first metal layer is copper or a copper alloy
  • the first conductive layer is conductive by one or more kinds of multi-metal oxide conductive materials such as indium tin oxide, indium zinc oxide, aluminum-doped zinc oxide, indium gallium zinc oxide, zinc tin oxide and other multi-metal oxide conductive materials Laminated structure of materials.
  • multi-metal oxide conductive materials such as indium tin oxide, indium zinc oxide, aluminum-doped zinc oxide, indium gallium zinc oxide, zinc tin oxide and other multi-metal oxide conductive materials Laminated structure of materials.
  • the process of patterning the semiconductor layer to form the active layer includes:
  • a third photomask is used to pattern the semiconductor layer to form the active layer.
  • the method for manufacturing the array substrate further includes:
  • a passivation layer is deposited on the surfaces of the source electrode, the drain electrode, and the pixel electrode, and the passivation layer is patterned by using a fourth photomask.
  • the present application also proposes an array substrate.
  • the array substrate includes:
  • a gate insulating layer disposed on a side of the substrate facing the gate and the conductive isolation layer and covering the conductive isolation layer;
  • the second metal layer includes a source electrode, a drain electrode, and a pixel electrode.
  • the source electrode and the drain electrode pass through the active layer. Layer electrical connection.
  • the gate is made of copper or a copper alloy material.
  • the conductive isolation layer is indium tin oxide, indium zinc oxide, aluminum doped zinc oxide, indium gallium zinc oxide, zinc tin oxide
  • the second metal layer further includes data lines, and the data lines may be formed by patterning the second metal layer through a second photomask.
  • the pixel electrode further includes a passivation layer, and the passivation layer is stacked on the second metal layer.
  • the present application also provides a display panel including a color filter substrate, a liquid crystal layer, and an array substrate as described above.
  • Pixel electrodes are formed on the array substrate, and common electrodes are formed on the color filter substrate;
  • the liquid crystal layer is disposed between the color filter substrate and the array substrate;
  • the display panel controls the liquid crystal molecules of the liquid crystal layer to rotate through a voltage difference between the pixel electrode and the common electrode, and displays an image through the color filter substrate.
  • the gate is made of copper or a copper alloy material.
  • the conductive isolation layer is indium tin oxide, indium zinc oxide, aluminum doped zinc oxide, indium gallium zinc oxide, zinc tin oxide
  • the second metal layer further includes data lines, and the data lines may be formed by patterning the second metal layer through a second photomask.
  • the pixel electrode further includes a passivation layer, and the passivation layer is stacked on the second metal layer.
  • the manufacturing method of the array substrate of the present application is to deposit a first metal layer and a first conductive layer on a provided substrate, and use a first photomask to pattern the first metal layer and the first conductive layer to form a gate and cover the A conductive isolation layer on the gate, and after forming a gate insulating layer on the gate, a semiconductor layer and a second metal layer are sequentially deposited on the gate insulating layer, and the semiconductor layer is patterned to form In the active layer, a second mask is used to pattern the second metal layer to form a source electrode, a drain electrode, and a pixel electrode to complete the fabrication of the array substrate.
  • the conductive isolation layer formed by patterning the first conductive layer is wrapped and covered on the gate layer, so that the conductive isolation layer can completely cover the gate to the package, thereby preventing metal ions, such as copper ions from diffusing in subsequent high-temperature processes.
  • the active layer of the thin film transistor affects the switching characteristics of the thin film transistor, and affects other electrical properties of the thin film transistor, ensuring the stability of the thin film transistor.
  • This application also covers the gate with a conductive isolation layer, so that when the sides of the gate have metal burrs on the slope angle formed after photolithography, the metal burrs on the gate can be covered, which is beneficial to prevent metal burrs. Exposed outside the gate, causing a tip discharge.
  • FIG. 1 is a flowchart of an embodiment of a manufacturing method of an array substrate of the present application
  • FIG. 2 is a schematic diagram of an embodiment of an array substrate manufactured in step S200 in the method for manufacturing an array substrate of the present application.
  • FIG. 3 and FIG. 4 are schematic diagrams of an embodiment of an array substrate manufactured in step S300 of the method for manufacturing an array substrate of the present application.
  • FIG. 5 is a schematic structural diagram of an embodiment of an array substrate according to the present application.
  • FIG. 6 is a schematic structural diagram of an embodiment of a display panel of the present application.
  • Label name Label name 10 Substrate 70 Drain 20 Grid 80 Pixel electrode 30 Conductive isolation layer 90 Passivation layer 40 Gate insulation 100 Array substrate 50 Active layer 200 Color film substrate 60 Source 300 Liquid crystal layer
  • the directional indication is only used to explain in a specific posture (as shown in the drawings) (Shown) the relative positional relationship, movement, etc. of the various components, if the specific posture changes, the directional indicator will change accordingly.
  • This application proposes a method for manufacturing an array substrate.
  • the display device may be a display device with a display panel such as a television, a mobile phone, or a computer.
  • Array substrates are generally provided with thin film transistors. transistor, TFT), pixel electrode, common electrode, common signal line, data line, scan line, etc., where the scan line is electrically connected to the gate of the thin film transistor, and the data line and the pixel electrode are electrically connected to the source of the thin film transistor, respectively. Or the drain, the scanning line provides a scanning signal to control the connection or disconnection of the source and the drain.
  • the data line transmits a data signal to control the voltage of the pixel electrode
  • the common signal line is electrically connected
  • the common electrode controls the voltage of the common electrode, and the liquid crystal molecules are controlled to rotate by controlling the voltage difference between the pixel electrode and the common electrode, so that the display panel displays the content of the image.
  • a method for manufacturing the array substrate 100 includes:
  • Step S100 Provide a substrate 10.
  • the substrate 10 is a transparent substrate 10, and the transparent substrate 10 may be a rigid substrate 10 made of a transparent material such as glass or plastic.
  • Step S200 depositing a first metal layer and a first conductive layer on the substrate 10, and patterning the first metal layer and the first conductive layer with a first photomask to form a gate electrode 20 and cover the gate electrode 20.
  • the first metal layer can be formed by physical vapor deposition (Physical Vapor Deposition (PVD) method is used to form a film on the substrate 10, or it is formed on the substrate 10 by a sputtering deposition process, and the metal layer is annealed to activate the metal layer.
  • PVD Physical Vapor Deposition
  • the first metal layer may be made of metal materials such as copper Cu, molybdenum Mo, titanium Ti, aluminum Al, chromium Cr, silver Ag, and gold Au.
  • the first metal layer may be implemented by using a single metal layer of the above metals, or any two Or a composite metal layer composed of a combination of two or more metals.
  • This embodiment may be made of a single copper metal layer.
  • the conductive isolation layer 30 may be indium tin oxide (ITO), indium zinc oxide (IZO), aluminum doped zinc oxide (AZO), indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO)
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • AZO aluminum doped zinc oxide
  • IGZO indium gallium zinc oxide
  • ZTO zinc tin oxide
  • the first photomask includes an exposure area corresponding to the pattern of the gate 20 to be formed and the conductive isolation layer 30 covering the gate 20.
  • Ultraviolet, yellow, or other light sources face away from the substrate 10 from the first photomask.
  • One side is irradiated toward the substrate 10, and the first metal layer and the first conductive layer are exposed through the exposure area, and then a gate electrode 20 and a conductive isolation layer 30 with a specific pattern are formed by an etching process.
  • the etching process may be adopted This is achieved by a dry engraving process or a wet engraving process.
  • the metal can be etched by a wet etching process under the protection of a photoresist mask Layer and conductive isolation layer 30 to remove portions of the metal layer and conductive isolation layer 30 that are not covered by the photoresist mask.
  • the gate 20 formed by patterning the first metal layer is used for subsequent formation of a thin film transistor.
  • the conductive isolation layer 30 formed by patterning the first conductive layer is wrapped and covered on the gate 20 layer.
  • the conductive isolation layer 30 can completely form the gate 20 Covering the package to prevent metal ions, such as copper ions, from diffusing into the active layer 50 of the thin film transistor during subsequent high temperature processes, affecting the switching characteristics of the thin film transistor, and affecting other electrical properties of the thin film transistor, ensuring the stability of the thin film transistor .
  • the side of the gate 20 may have a phenomenon of metal burrs from the perspective of the microstructure.
  • Step S300 After depositing a gate insulating layer 40 on the gate 20, a semiconductor layer and a second metal layer are sequentially deposited on the gate insulating layer 40, and the semiconductor layer is patterned to form an active layer 50. Two photomasks pattern the second metal layer to form a source electrode 60, a drain electrode 70, and a pixel electrode 80.
  • the material of the gate insulating layer 40 may be a laminated structure of one or more insulating dielectric materials among insulating dielectric materials such as SiOx, SiNx, HfO2, Al2O3, etc., and is processed by a chemical vapor deposition process or other
  • the process to form the gate insulating layer 40 may be other processes known to those skilled in the art.
  • a photoresist is deposited on the gate insulating layer 40. The exposure is performed through a photomask, wherein the photomask divides the gate insulation layer 40 into a non-exposed area and an exposed area, The exposure region is located on the gate 20 layer.
  • the exposed substrate 10 is developed to retain a photoresist in a non-exposed area.
  • the gate insulating layer 40 not covered by the photoresist is incompletely etched to form a gate insulating layer 40 to isolate the gate 20 from an active layer 50 formed subsequently on the gate insulating layer 40.
  • the semiconductor layer may be an oxide thin film layer, and the oxide thin film layer may be indium gallium zinc oxide (IGZO), aluminum-doped zinc oxide (AZO), indium zinc oxide (IZO), indium gallium zinc oxide (IGTO), zinc tin oxide (ZTO) and one or more of multiple metal oxide conductive materials
  • IGZO indium gallium zinc oxide
  • AZO aluminum-doped zinc oxide
  • IZO indium zinc oxide
  • IGTO indium gallium zinc oxide
  • ZTO zinc tin oxide
  • a multilayer structure of a polymetal oxide conductive material is formed by a chemical vapor deposition process. Of course, other processes known to those skilled in the art can also be used.
  • the photoresist layer can be exposed and developed using a gray photomask process to obtain a photoresist mask. Under the protection of the photoresist mask, a dry etching process is applied to etch the semiconductor. Layer to remove portions of the semiconductor layer that are not covered by the photoresist mask,
  • the second metal layer may be made of metal materials such as copper Cu, molybdenum Mo, titanium Ti, aluminum Al, chromium Cr, silver Ag, and gold Au.
  • the second metal layer may be implemented by a single metal layer of the above metals, or any two Or a composite metal layer composed of a combination of two or more metals. Physical vapor deposition Vapor Deposition (PVD) method, or magnetron sputtering method to form a metal thin film.
  • PVD Physical vapor deposition Vapor Deposition
  • the second metal layer can be used to pattern the second metal layer to form the source electrode 60 and the drain electrode 70, and the second metal layer can be used to pattern the second metal layer to form a data line.
  • the drain 70 is electrically connected.
  • the second photomask includes an exposure area pattern corresponding to the data lines, so that when the source 60 and the drain 70 are formed by exposure, the data lines are simultaneously formed.
  • the data line outputs a data voltage to the source 60 or the drain 70 to control the pixel voltage of the pixel electrode 80.
  • the data lines, the source 60 and the drain 70 are formed in the same mask exposure, which can effectively reduce the manufacturing process of the array substrate 100 of the display panel, thereby reducing the manufacturing cost of the array substrate 100 and the liquid crystal display.
  • Both sides of the source electrode 60 and the drain electrode 70 have a metal burr from the microstructure point of view.
  • the passivation layer 90 By providing the passivation layer 90, the source electrode 60 and the drain electrode 70 can be better aligned. Metal burrs are covered, which effectively prevents metal burrs from being exposed outside the protective layer, so that the protective layer can be better Protect the source 60 and the drain 70, effectively avoiding the impact of subsequent processes on the source 60 and the drain 70, thereby improving the The yield rate of the display panel; and the color photoresist layer is provided between the two passivation layers 90, which can very well The protection is performed to effectively prevent the organic material of the color photoresist layer from releasing harmful impurities in subsequent processes, thereby achieving effective protection of the display panel and increasing its efficiency and life.
  • the above-mentioned photomask process refers to a patterning process using a mask mask.
  • processes including gluing, exposing, developing, etching, and peeling are respectively included, and during the etching process, dry etching or wet etching can be used to implement.
  • etching process dry etching or wet etching can be used to implement.
  • the manufacturing method of the array substrate 100 of the present application forms a gate electrode 20 by depositing a first metal layer and a first conductive layer on a provided substrate 10, and patterning the first metal layer and the first conductive layer with a first photomask. And a conductive isolation layer 30 covering the gate 20; and after depositing a gate insulating layer 40 on the gate 20, a semiconductor layer and a second metal layer are sequentially deposited on the gate insulating layer 40, The semiconductor layer is patterned to form an active layer 50; the second metal layer is patterned to form a source 60, a drain 70, and a pixel electrode 80 to complete the fabrication of the array substrate 100.
  • the conductive isolation layer 30 formed by patterning the first conductive layer is wrapped and covered on the gate 20 layer, so that the conductive isolation layer 30 can completely cover the gate 20 and thus prevent metal ions in subsequent high-temperature processes.
  • metal ions diffuse into the active layer 50 of the thin film transistor, which affects the switching characteristics of the thin film transistor, and affects other electrical properties of the thin film transistor, thereby ensuring the stability of the thin film transistor.
  • the present application also covers the gate 20 with a conductive isolation layer 30 so that when the sides of the gate 20 have metal burrs on a slope angle formed after photolithography, the metal burrs on the gate 20 can be covered. It is beneficial to prevent the metal burr from being exposed outside the gate 20, thereby generating a tip discharge.
  • the first metal layer and the first conductive layer are deposited on the substrate 10, and the first metal layer and the first conductive layer are patterned by using a first photomask.
  • the steps of forming the gate 20 and the conductive isolation layer 30 covering the gate 20 include:
  • a first metal layer and a first conductive layer are sequentially deposited on the substrate 10, and the first metal layer and the first conductive layer are patterned using a first photomask to form a gate electrode 20 and cover the gate electrode.
  • PVD Physical Vapor Deposition
  • PVD Physical Vapor Deposition
  • a sputtering deposition process to form a first metal layer on the substrate 10
  • PVD physical vapor deposition
  • a first photomask Process that is, patterning the first metal layer and the first conductive layer through processes such as gluing, exposing, developing, etching, and peeling to form a gate electrode 20 and a conductive isolation layer 30 covering the gate electrode 20 .
  • the first metal layer and the first conductive layer are deposited on the substrate 10, and the first metal layer and the first conductive layer are patterned by using a first photomask.
  • the steps of forming the gate 20 and the conductive isolation layer 30 covering the gate 20 include:
  • a first conductive layer is deposited on the gate 20, and the first metal layer is patterned using the first mask to form a conductive isolation layer 30.
  • PVD Physical Vapor Deposition
  • the first metal layer is formed on the substrate 10 by a sputtering deposition process, and the first photomask process is used, that is, through the processes of gluing, exposing, developing, etching, and peeling.
  • the first metal layer is patterned to form a gate electrode 20.
  • Physical vapor deposition is then used to cover the conductive isolation layer 30 on the gate 20, and then the first photomask process is used, that is, the first conductive layer is patterned through the processes of coating, exposure, development, etching, and peeling. To form a conductive isolation layer 30.
  • a process of patterning the semiconductor layer to form the active layer 50 includes:
  • a third photomask (not shown) is used to pattern the semiconductor layer to form the active layer 50.
  • indium gallium zinc oxide can be used (IGZO), aluminum-doped zinc oxide (AZO), indium zinc oxide (IZO), indium gallium zinc oxide (IGTO), zinc tin oxide (ZTO), etc.
  • a bright oxide semiconductor material is formed by a magnetron sputtering method, a semiconductor layer is deposited on the prepared gate insulating layer 40, and the semiconductor layer is patterned with a third mask to form an active layer 50.
  • the third mask includes An exposure area corresponding to a pattern corresponding to the active layer 50, Ultraviolet light or other light sources are irradiated from the side of the third mask away from the substrate 10 toward the substrate 10, and the semiconductor layer is exposed through the exposure area to form an active layer 50 with a specific pattern.
  • a second metal layer can be deposited on the active layer 50, and the second metal layer is patterned using a second photomask to form the source electrode 60, the drain electrode 70, and the pixel electrode 80.
  • the second photomask includes an exposure area corresponding to the patterns of the source 60, the drain 70, and the pixel electrode 80 to be formed.
  • Ultraviolet light or other light sources are irradiated from the side of the second photomask away from the substrate 10 toward the substrate 10, and After the second metal layer is exposed through the exposure area, a source electrode 60, a drain electrode 70, and a pixel electrode 80 having a specific pattern are formed.
  • the pixel electrode 80 and the source 60 and the drain 70 can be formed in the same mask exposure.
  • the photomask exposure step reduces one photomask exposure step, thereby reducing the manufacturing cost of the array substrate 100 and the display panel. It may also be manufactured by using two photomasks separately, and the process of forming the pixel electrode 80 and the process of the source 60 and the drain 70 may be performed separately.
  • the active layer 50, the source electrode 60, the drain electrode 70, and the pixel electrode 80 may also be formed during a photomask exposure process, which may be specifically implemented according to design requirements, and is not limited herein.
  • the present application also proposes an array substrate.
  • the array substrate 100 includes:
  • the gate insulating layer 40 is disposed on a side of the substrate 10 facing the gate 20 and the conductive isolation layer 30 and covers the conductive isolation layer 30;
  • the second metal layer includes a source electrode 60, a drain electrode 70, and a pixel electrode 80.
  • the source electrode 60 and the drain electrode The electrodes 70 are electrically connected through the active layer 50.
  • the gate 20 and the conductive isolation layer 30 may be formed by depositing a first metal layer and a first conductive layer on the substrate 10, and patterning the first metal layer and the first conductive layer by using a first photomask.
  • the first metal layer can be formed by physical vapor deposition (Physical Vapor Deposition (PVD) method is used to form a film on the substrate 10, or it is formed on the substrate 10 by a sputtering deposition process.
  • the first metal layer further includes a scan line, and the scan line is electrically connected to the gate 20, and the scan line outputs a voltage of the gate 20 to the gate 20, so as to control the on or off state of the thin film transistor.
  • the gate electrode 20 is made of copper or copper alloy material;
  • the conductive isolation layer 30 is indium tin oxide (ITO), indium zinc oxide (IZO), aluminum doped zinc oxide (AZO), indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO)
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • AZO aluminum doped zinc oxide
  • IGZO indium gallium zinc oxide
  • ZTO zinc tin oxide
  • the gate insulating layer 40 is configured to isolate the gate 20 from an active layer 50 that is subsequently formed on the gate insulating layer 40.
  • a gray photomask process is used to expose and develop the photoresist layer to obtain a photoresist mask and protect the photoresist mask.
  • a dry etching process is applied to etch the semiconductor layer to form a portion of the semiconductor layer that is not covered by the photoresist mask.
  • the source electrode 60, the drain electrode 70, and the pixel electrode 80 can be formed on the active layer 50 by a magnetron sputtering method to form a metal thin film. That is, after the first metal layer, the second metal layer is patterned by using a second mask to form the source electrode 60. And drain 70
  • the second metal layer further includes a data line.
  • the data line may be formed by patterning the second metal layer through a second photomask to form a data line.
  • the data line is electrically connected to the source 60 or the drain 70, and a gate 20 is output at the gate 20.
  • the voltage causes the source 60 and the drain 70 to communicate, so that the data line is controlled to output a data voltage to the source 60 or the drain 70, and the pixel voltage of the pixel electrode 80 is controlled.
  • the pixel electrode 80 further includes a passivation layer 90.
  • the passivation layer 90 is stacked on the second metal layer.
  • the passivation layer 90 is used to protect the source electrode 60, the drain electrode 70, and the pixel electrode 80, and prevent the source electrode 60, the drain electrode 70, and the pixel electrode 80 from being oxidized by a metal material.
  • the number of the pixel electrodes 80 is multiple, so that an electric field is formed between the adjacent pixel electrodes 80 and the upper CF substrate (color filter substrate 200) to control the rotation of the liquid crystal molecules.
  • the conductive isolation layer 30 formed by patterning the first conductive layer is wrapped and covered on the gate 20 layer, so that the conductive isolation layer 30 can completely cover the gate 20 and thus prevent metal ions in subsequent high-temperature processes.
  • metal ions diffuse into the active layer 50 of the thin film transistor, which affects the switching characteristics of the thin film transistor, and affects other electrical properties of the thin film transistor, thereby ensuring the stability of the thin film transistor.
  • the present application also covers the gate 20 with a conductive isolation layer 30 so that when the sides of the gate 20 have metal burrs on a slope angle formed after photolithography, the metal burrs on the gate 20 can be covered. It is beneficial to prevent the metal burr from being exposed outside the gate 20, thereby generating a tip discharge.
  • the present application also proposes a display panel.
  • the display panel includes a color filter substrate 200, a liquid crystal layer 300, and the array substrate 100 described above. It can be understood that the detailed structure of the array substrate 100 can be referred to The above embodiments are not repeated here; since the above-mentioned array substrate 100 is used in the display panel of the present application, the embodiments of the display panel of the present application include all the technical solutions of all the embodiments of the above-mentioned array substrate 100, and the achieved The technical effects are also completely the same, and will not be repeated here.
  • a pixel electrode 80 is formed on the array substrate 100, and a common electrode is formed on the color filter substrate 200;
  • the liquid crystal layer 300 is disposed between the color filter substrate 200 and the array substrate 100;
  • the display panel controls the liquid crystal molecules of the liquid crystal layer 300 to rotate through a voltage difference between the pixel electrode 80 and the common electrode (not shown), and displays an image through the color filter substrate 200.
  • the common electrode can also be disposed on the array substrate 100 and isolated from the gate electrode 20 by the gate insulating layer 40.
  • the gate 20 of each thin film transistor on the array substrate 100 is connected to the gate 20 driver of the display panel via a scan line on the array substrate 100; the source 60 (or the drain 70) on the thin film transistor
  • the pixel electrode 80 connected to the source 60 driver of the display panel is connected via the data line on the array substrate 100, and the drain 70 (or source 60) on the thin film transistor is electrically connected to the common electrode on the color filter substrate 200.
  • the display panel passes the pixel electrode 80 and the common electrode.
  • the difference in voltage controls the liquid crystal molecules of the liquid crystal layer 300 to rotate, and displays an image through the color filter substrate 200.

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本申请公开一种阵列基板及其制作方法，以及显示面板，该方法包括：利用第一道光罩图案化第一金属层及第一导电层，以形成栅极及覆盖于栅极上的导电隔离层。

Description

阵列基板及其制作方法，以及显示面板
技术领域
本申请涉及电子电路技术领域，特别涉及一种阵列基板及其制作方法，以及显示面板。
背景技术
在显示装置的阵列基板中，一般设置有一个或多个薄膜晶体管，在薄膜晶体管制程中，通常会采用金属层来制作栅极，然而金属离子在后续的高温制程中，容易扩散，影响薄膜晶体管的开关特性，导致显示异常，或者在栅极的容易出现不平整的现象，形成尖端放电，影响薄膜晶体管寿命。
申请内容
本申请的主要目的是提出阵列基板及其制作方法，以及显示面板，旨在保证阵列基板的薄膜晶体管的稳定性。
为实现上述目的，本申请提出一种阵列基板的制作方法，所述阵列基板的制作方法包括：
提供一基板；
在所述基板上沉积第一金属层及第一导电层，利用第一道光罩图案化所述第一金属层及第一导电层，以形成栅极及覆盖于所述栅极上的导电隔离层；
在所述栅极上沉积栅极绝缘层后，在所述栅极绝缘层上依次沉积半导体层和第二金属层，并图案化所述半导体层形成有源层，利用第二道光罩图案化所述第二金属层形成源极、漏极及像素电极。
可选地，所述在所述基板上沉积第一金属层及第一导电层，利用第一道光罩图案化所述第一金属层及第一导电层，以形成栅极及覆盖于所述栅极上的导电隔离层的步骤具体包括：
在所述基板上沉积第一金属层，利用第一道光罩图案化所述第一金属层以形成栅极；以及
在所述栅极上沉积第一导电层，利用所述第一道光罩图案化所述第一金属层以形成导电隔离层。
可选地，所述在所述基板上沉积第一金属层的步骤具体包括：
采用物理气相沉积方法成膜，或者采用溅射沉积工艺将所述第一金属层形成于所述基板上。
可选地，所述在所述栅极上沉积第一导电层的步骤具体包括：
采用物理气相沉积将导第一导电层覆盖于所述栅极上。
可选地，所述在所述基板上沉积第一金属层及第一导电层，利用第一道光罩图案化所述第一金属层及第一导电层，以形成栅极及覆盖于所述栅极上的导电隔离层的步骤具体包括：
所述第一金属层为铜或者铜质合金；以及
所述第一导电层为氧化铟锡、氧化铟锌、铝掺杂的氧化锌、铟镓锌氧化物、氧化锌锡等多元金属氧化物导电材料中的一种或多种多元金属氧化物导电材料的叠层结构。
可选地，所述在所述基板上沉积第一金属层及第一导电层，利用第一道光罩图案化所述第一金属层及第一导电层，以形成栅极及覆盖于所述栅极上的导电隔离层的步骤具体包括：
在所述基板上依次沉积第一金属层及第一导电层，利用第一道光罩图案化所述第一金属层及第一导电层，以形成栅极及覆盖于所述栅极上的导电隔离层。
可选地，所述在所述基板上依次沉积第一金属层及第一导电层的步骤具体包括：
采用物理气相沉积方法成膜，或者采用溅射沉积工艺将第一金属层形成于基板上，再采用物理气相沉积将第一导电层覆盖于所述第一金属层上。
可选地，所述在所述基板上沉积第一金属层及第一导电层，利用第一道光罩图案化所述第一金属层及第一导电层，以形成栅极及覆盖于所述栅极上的导电隔离层的步骤具体包括：
所述第一金属层为铜或者铜质合金；以及
所述第一导电层为氧化铟锡、氧化铟锌、铝掺杂的氧化锌、铟镓锌氧化物、氧化锌锡等多元金属氧化物导电材料中的一种或多种多元金属氧化物导电材料的叠层结构。
可选地，图案化所述半导体层形成所述有源层的过程包括：
利用第三道光罩图案化所述半导体层形成所述有源层。
可选地，在形成所述源极、所述漏极及所述像素电极后，所述阵列基板的制作方法还包括：
在所述源极、所述漏极及所述像素电极的表面沉积钝化层，并利用第四道光罩图案化所述钝化层。
本申请还提出一种阵列基板，所述阵列基板包括：
基板；
栅极及覆盖于所述栅极上的导电隔离层；
栅极绝缘层，设置于所述基板面对所述栅极和所述导电隔离层的一侧并覆盖所述导电隔离层；
有源层及第二金属层，依次层叠于所述栅极绝缘层上，所述第二金属层包括源极、漏极及像素电极，所述源极和所述漏极通过所述有源层电连接。
可选地，所述栅极由铜或者铜质合金材料制得；以及
所述导电隔离层为氧化铟锡、氧化铟锌、铝掺杂的氧化锌、铟镓锌氧化物、氧化锌锡 等多元金属氧化物导电材料中的一种或多种多元金属氧化物导电材料的叠层结构。
可选地，所述第二金属层还包括数据线，所述数据线可以是通过第二道光罩图案化第二金属层形成数据线。
可选地，所述像素电极还包括钝化层，钝化层层叠设置于所述第二金属层上。
本申请还提出一种显示面板，包括彩膜基板、液晶层及如上所述的阵列基板，
所述阵列基板上形成有像素电极，所述彩膜基板上形成有公共电极；
所述液晶层，设置于所述彩膜基板与所述阵列基板之间；
所述显示面板通过所述像素电极与所述公共电极之间的电压差控制所述液晶层的液晶分子转动，并通过所述彩膜基板显示图像。
可选地，所述栅极由铜或者铜质合金材料制得；以及
所述导电隔离层为氧化铟锡、氧化铟锌、铝掺杂的氧化锌、铟镓锌氧化物、氧化锌锡 等多元金属氧化物导电材料中的一种或多种多元金属氧化物导电材料的叠层结构。
可选地，所述第二金属层还包括数据线，所述数据线可以是通过第二道光罩图案化第二金属层形成数据线。
可选地，所述像素电极还包括钝化层，钝化层层叠设置于所述第二金属层上。
本申请阵列基板的制作方法通过在提供的一基板上沉积第一金属层及第一导电层，利用第一道光罩图案化第一金属层及第一导电层，以形成栅极及覆盖于所述栅极上的导电隔离层，并在在栅极上沉积形成栅极绝缘层后，在所述栅极绝缘层上依次沉积半导体层和第二金属层，并图案化所述半导体层形成有源层，利用第二道光罩图案化所述第二金属层形成源极、漏极及像素电极，以完成阵列基板的制作。本申请通过图案化第一导电层形成的导电隔离层包裹覆盖于栅极层上，以使导电隔离层可以对栅极形成完全覆盖于包裹，从而阻止后续高温制程中金属离子，例如铜离子扩散到薄膜晶体管的有源层，影响薄膜晶体管的开关特性，以及对薄膜晶体管的其他电性能造成影响，保证薄膜晶体管的稳定性。本申请还通过在栅极上覆盖导电隔离层，以在栅极的侧边在光刻后形成的坡度角上具有金属毛刺时，可以对栅极上的金属毛刺进行覆盖，有利于防止金属毛刺裸露在栅极外，从而产生尖端放电。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请阵列基板的制作方法一实施例的流程图；
图2为本申请阵列基板的制作方法中步骤S200所制作的阵列基板一实施例的示意图。
图3和图4为本申请阵列基板的制作方法的步骤S300所制作的阵列基板一实施例的示意图。
图5为本申请阵列基板一实施例的结构示意图；
图6为本申请显示面板一实施例的结构示意图。
附图标号说明：
标号 名称 标号 名称
10 基板 70 漏极
20 栅极 80 像素电极
30 导电隔离层 90 钝化层
40 栅极绝缘层 100 阵列基板
50 有源层 200 彩膜基板
60 源极 300 液晶层
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，若本申请实施例中有涉及方向性指示（诸如上、下、左、右、前、后……），则该方向性指示仅用于解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，若本申请实施例中有涉及“第一”、“第二”等的描述，则该“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
本申请提出一种阵列基板的制作方法。
用于制作显示装置的阵列基板，该显示装置可以是电视、手机、电脑等具有显示面板的显示装置。阵列基板一般设置有薄膜晶体管(Thin- film transistor，TFT)、像素电极、公共电极、公共信号线、数据线、扫描线等元件，其中，扫描线电连接至薄膜晶体管的栅极，数据线和像素电极分别电连接至薄膜晶体管的源极或漏极之一，扫描线提供扫描信号控制源极与漏极的连通或断开状态，当源极与漏极连通时，数据线传递数据信号控制像素电极的电压大小，公共信号线电连接公共电极并控制公共电极的电压大小，通过控制像素电极与公共电极的电压差控制液晶分子转动，以使显示面板显示图像的内容。
参照图1至图4，在本申请一实施例中，该阵列基板100的制作方法包括：
步骤S100、提供一基板10；
本实施例中，基板10为透明基板10，透明基板10可以是玻璃或塑料等透明材料制得的刚性基板10。
步骤S200、在所述基板10上沉积第一金属层及第一导电层，利用第一道光罩图案化所述第一金属层及第一导电层，以形成栅极20及覆盖于所述栅极20上的导电隔离层30；
第一金属层可通过物理气相沉积(Physical Vapor Deposition，PVD)方法成膜于基板10上，或者采用溅射沉积工艺制备形成于基板10上，并对金属层进行退火处理以对金属层进行活化，当然也可以是本领域技术人员所知的其它工艺来实现，此处不做限制。
第一金属层可为铜Cu、钼Mo、钛Ti、铝Al、铬Cr、银Ag、金Au等金属材料制得，例如可以采用上述金属的单层金属层来实现，或者采用任意两种或两种以上的金属组合构成的复合金属层来实现。本实施例可选为单层铜金属层制得。导电隔离层30可以为氧化铟锡(ITO)、氧化铟锌(IZO)、铝掺杂的氧化锌(AZO)、铟镓锌氧化物(IGZO)、氧化锌锡(ZTO) 等多元金属氧化物导电材料中的一种或多种多元金属氧化物导电材料的叠层结构。
第一道光罩包括与需要形成的栅极20和覆盖在栅极20上的导电隔离层30的图案对应的曝光区，紫外光、黄光或其他光源从第一道光罩背离基板10的一侧向基板10方向照射，并通过曝光区对第一金属层及第一导电层曝光后，再通过刻蚀工艺来形成特定图案的栅极20和导电隔离层30，其中刻蚀工艺可以采用干刻工艺或者湿刻工艺来实现。具体可在光刻胶掩膜版的保护下，应用湿刻工艺刻蚀金属 层及导电隔离层30，以刻蚀去除金属层和导电隔离层30中未被光刻胶掩膜版覆盖的部分。图案化第一金属层形成的栅极20用于后续形成薄膜晶体管。图案化第一导电层形成的导电隔离层30包裹覆盖于栅极20层上，由于栅极20刻蚀后的线宽损失小于导电隔离层30，因此导电隔离层30可以对栅极20形成完全覆盖于包裹，从而阻止后续高温制程中金属离子，例如铜离子扩散到薄膜晶体管的有源层50，影响薄膜晶体管的开关特性，以及对薄膜晶体管的其他电性能造成影响，保证薄膜晶体管的稳定性。栅极20的侧边在光刻后形成的坡度角上，从微结构来看可能具有金属毛刺的现象，通过设置导电隔离层30，能够更好的对栅极20上的金属毛刺进行覆盖，有利于防止金属毛刺裸露在栅极20外，从而产生尖端放电。
步骤S300、在栅极20上沉积栅极绝缘层40后，在所述栅极绝缘层40上依次沉积半导体层和第二金属层，并图案化所述半导体层形成有源层50，利用第二道光罩图案化所述第二金属层形成源极60、漏极70及像素电极80。
本实施例中，栅极绝缘层40的材料可以为SiOx、SiNx、HfO2、Al2O3等绝缘介电材料中的一种或多种绝缘介电材料的叠层结构，并通过化学气相沉积工艺或其他工艺来形成栅极绝缘层40，也可以是本领域技术人员所知的其它工艺。在沉积有涂布光刻胶于所述栅极绝缘层40上。通过一光罩进行曝光，其中，上述光罩将所述栅极绝缘层40区分为非曝光区和曝光区， 所述曝光区位于所述栅极20层上。对曝光后的基板10进行显影，保留非曝光区的光刻胶。对未被光刻胶覆盖的栅极绝缘层40进行不完全刻蚀，从而形成栅极绝缘层40，以将栅极20与后续形成于栅极绝缘层40上的有源层50相互隔绝。
半导体层可选为氧化物薄膜层，氧化物薄膜层可以采用铟镓锌氧化物 (IGZO)、铝掺杂的氧化锌(AZO)、氧化铟锌(IZO)、铟镓锌氧化物(IGTO)、氧化锌锡(ZTO)等多元金属氧化物导电材料中的一种或多种多元金属氧化物导电材料的叠层结构，并通过化学气相沉积工艺形成。当然也可以是本领域技术人员所知的其它工艺。在形成半导体层后，可以应用灰色调光罩工艺对光刻胶层进行曝光、显影，获得光刻胶掩膜版，在光刻胶掩膜版的保护下，应用干刻工艺，刻蚀半导体层，以刻蚀去除所述半导体层中未被所述光刻胶掩膜版覆盖的部分，从而形成薄膜晶体管20的有源层50。
第二金属层可为铜Cu、钼Mo、钛Ti、铝Al、铬Cr、银Ag、金Au等金属材料制得，例如可以采用上述金属的单层金属层来实现，或者采用任意两种或两种以上的金属组合构成的复合金属层来实现。并采用物理气相沉积(Physical Vapor Deposition，PVD)方法，或者磁控溅射方法形成金属薄膜。
在成膜后，可以利用第二道光罩图案化第二金属层形成源极60和漏极70的同时，通过第二道光罩图案化第二金属层形成数据线，数据线与源极60或漏极70电连接。具体的，第二道光罩包括与数据线对应的曝光区图案，从而在曝光形成源极60和漏极70的同时，数据线也同步形成。数据线向源极60或漏极70输出数据电压，从而控制像素电极80的像素电压大小。数据线、源极60和漏极70在同一次光罩曝光中形成，可以有效的减少显示面板的阵列基板100的制作过程，从而降低了阵列基板100及液晶显示器的制作成本。
源极60和漏极70的侧边从微结构来看都有金属毛刺的现象，通过设置钝化层90，能够更好的对源极60和漏极70上 的金属毛刺进行覆盖，非常有效的防止金属毛刺裸露在保护层外，使得保护层能够更好的 对源极60和漏极70进行保护，有效的避免后续的制程对源极60和漏极70的影响，从而非常好的提高 显示面板的良品率；而且将彩色光阻层设在两层钝化层90之间，能够非常好的对彩色光阻层 进行保护，有效的防止后续制程使彩色光阻层的有机材料释放出一些有害杂质气体，从而 实现对显示面板的有效保护，增加其效率及寿命。
可以理解的是，上述一次光罩工序，是指使用一张掩膜版Mask的构图工艺。在上述光罩工序中，分别包括有涂胶、曝光、显影、刻蚀和剥离等工艺，并且在刻蚀工艺时，可以采用干法刻蚀或湿法刻蚀来实现，本领域技术人员可以采用所知的阵列基板100制作工艺来实现上述阵列基板100的制成，此处不再赘述。
本申请阵列基板100的制作方法通过在提供的一基板10上沉积第一金属层及第一导电层，利用第一道光罩图案化第一金属层及第一导电层，以形成栅极20及覆盖于所述栅极20上的导电隔离层30；并在在栅极20上沉积形成栅极绝缘层40后，在所述栅极绝缘层40上依次沉积半导体层和第二金属层，并图案化所述半导体层形成有源层50；利用第二道光罩图案化所述第二金属层形成源极60、漏极70及像素电极80，以完成阵列基板100的制作。本申请通过图案化第一导电层形成的导电隔离层30包裹覆盖于栅极20层上，以使导电隔离层30可以对栅极20形成完全覆盖于包裹，从而阻止后续高温制程中金属离子，例如铜离子扩散到薄膜晶体管的有源层50，影响薄膜晶体管的开关特性，以及对薄膜晶体管的其他电性能造成影响，保证薄膜晶体管的稳定性。本申请还通过在栅极20上覆盖导电隔离层30，以在栅极20的侧边在光刻后形成的坡度角上具有金属毛刺时，可以对栅极20上的金属毛刺进行覆盖，有利于防止金属毛刺裸露在栅极20外，从而产生尖端放电。
参照图1，在一可选实施例中，所述在所述基板10上沉积第一金属层及第一导电层，利用第一道光罩图案化所述第一金属层及第一导电层，以形成栅极20及覆盖于所述栅极20上的导电隔离层30的步骤具体包括：
在所述基板10上依次沉积第一金属层及第一导电层，利用第一道光罩图案化所述第一金属层及第一导电层，以形成栅极20及覆盖于所述栅极20上的导电隔离层30。
本实施例中，可以采用物理气相沉积(Physical Vapor Deposition，PVD)方法成膜，或者采用溅射沉积工艺将制备第一金属层形成于基板10上，再采用物理气相沉积将导电隔离层30覆盖于第一金属层后，利用第一道光罩工序，也即通过涂胶、曝光、显影、刻蚀和剥离等工艺，图案化第一金属层及第一导电层，以形成栅极20及覆盖于所述栅极20上的导电隔离层30。
参照图1，在一可选实施例中，所述在所述基板10上沉积第一金属层及第一导电层，利用第一道光罩图案化所述第一金属层及第一导电层，以形成栅极20及覆盖于所述栅极20上的导电隔离层30的步骤具体包括：
在所述基板10上沉积第一金属层，利用第一道光罩图案化所述第一金属层以形成栅极20；
在所述栅极20上沉积第一导电层，利用所述第一道光罩图案化所述第一金属层以形成导电隔离层30。
本实施例中，可以采用物理气相沉积(Physical Vapor Deposition，PVD)方法成膜，或者采用溅射沉积工艺将第一金属层形成于基板10上，利用第一道光罩工序，也即通过涂胶、曝光、显影、刻蚀和剥离等工艺，图案化第一金属层，以形成栅极20。然后采用物理气相沉积将导电隔离层30覆盖于栅极20上，再利用第一道光罩工序，也即通过涂胶、曝光、显影、刻蚀和剥离等工艺，图案化第一导电层，以形成导电隔离层30。
参照图4，在一可选实施例中，图案化所述半导体层形成所述有源层50的过程包括：
利用第三道光罩（图未示出）图案化所述半导体层形成所述有源层50。
本实施例中，可以采用铟镓锌氧化物 (IGZO)、铝掺杂的氧化锌(AZO)、氧化铟锌(IZO)、铟镓锌氧化物(IGTO)、氧化锌锡(ZTO)等透 明氧化物半导体材料，利用磁控溅射方法成膜，在制得的栅极绝缘层40上沉积半导体层，利用第三道光罩图案化半导体层形成有源层50，其中第三道光罩包括与有源层50对应的图案对应的曝光区， 紫外光或其他光源从第三道光罩背离基板10的一侧向基板10方向照射，并通过曝光区对半导体层曝光后形成特定图案的有源层50。
在制得有源层50后，可以在有源层50上沉积第二金属层，利用第二道光罩图案化第二金属层形成源极60、漏极70及像素电极80。第二道光罩包括与需要形成的源极60、漏极70及像素电极80的图案对应的曝光区，紫外光或其他光源从第二道光罩背离基板10的一侧向基板10方向照射，并通过曝光区对第二金属层曝光后形成特定图案的源极60、漏极70及像素电极80。其中，像素电极80与源极60及漏极70可以在同一次光罩曝光中形成，即将形成像素电极80的制程与源极60及漏极70的制程结合，省略了单独形成像素电极80的光罩曝光步骤，从而减少了一次光罩曝光步骤，从而降低了阵列基板100及显示面板的制作成本。也可以分别采用两道光罩来制得，将形成像素电极80的制程与源极60及漏极70的制程分部进行。在一些实施例中，还可以将有源层50、源极60、漏极70及像素电极80在一次光罩曝光过程中形成，具体可根据设计需求来实现，此处不做限制。
本申请还提出一种阵列基板。
参照图5，在本申请一实施例中，该阵列基板100包括：
基板10；
栅极20及覆盖于所述栅极20上的导电隔离层30；
栅极绝缘层40，设置于所述基板10面对所述栅极20和所述导电隔离层30的一侧并覆盖所述导电隔离层30；
有源层50及第二金属层，依次层叠于所述栅极绝缘层40上，所述第二金属层包括源极60、漏极70及像素电极80，所述源极60和所述漏极70通过所述有源层50电连接。
本实施例中，栅极20和导电隔离层30可以是在基板10上沉积第一金属层及第一导电层，利用第一道光罩图案化所述第一金属层及第一导电层形成，第一金属层可通过物理气相沉积(Physical Vapor Deposition，PVD)方法成膜于基板10上，或者采用溅射沉积工艺制备形成于基板10上。第一金属层还包括扫描线，扫描线与栅极20电连接，扫描线向栅极20输出栅极20电压，从而控制薄膜晶体管的连通或断开状态。其中，所述栅极20由铜或者铜质合金材料制得；
所述导电隔离层30为氧化铟锡(ITO)、氧化铟锌(IZO)、铝掺杂的氧化锌(AZO)、铟镓锌氧化物(IGZO)、氧化锌锡(ZTO) 等多元金属氧化物导电材料中的一种或多种多元金属氧化物导电材料的叠层结构。
栅极绝缘层40设置为将栅极20与后续形成于栅极绝缘层40上的有源层50相互隔绝。
有源层50通过在栅极绝缘层40上形成半导体层后，应用灰色调光罩工艺对光刻胶层进行曝光、显影，获得光刻胶掩膜版，在光刻胶掩膜版的保护下，应用干刻工艺，刻蚀半导体层，以刻蚀去除半导体层中未被所述光刻胶掩膜版覆盖的部分而形成。
源极60、漏极70及像素电极80可以在有源层50上磁控溅射方法形成金属薄膜，也即第一金属层后，利用第二道光罩图案化第二金属层形成源极60和漏极70
第二金属层还包括数据线，数据线可以是通过第二道光罩图案化第二金属层形成数据线，数据线与源极60或漏极70电连接，在栅极20输出有栅极20电压而使源极60和漏极70连通，从而控制数据线向源极60或漏极70输出数据电压，进而控制像素电极80的像素电压大小。
像素电极80还包括钝化层90，钝化层90层叠设置于第二金属层上。 钝化层90用于保护源极60、漏极70及像素电极80，避免金属材料的源极60、漏极70及像素电极80氧化。
本实施例中，像素电极80的数量为多个，从而在相邻的像素电极80与上CF基板（彩膜基板200）之间形成电场控制液晶分子的转动。
本申请通过图案化第一导电层形成的导电隔离层30包裹覆盖于栅极20层上，以使导电隔离层30可以对栅极20形成完全覆盖于包裹，从而阻止后续高温制程中金属离子，例如铜离子扩散到薄膜晶体管的有源层50，影响薄膜晶体管的开关特性，以及对薄膜晶体管的其他电性能造成影响，保证薄膜晶体管的稳定性。本申请还通过在栅极20上覆盖导电隔离层30，以在栅极20的侧边在光刻后形成的坡度角上具有金属毛刺时，可以对栅极20上的金属毛刺进行覆盖，有利于防止金属毛刺裸露在栅极20外，从而产生尖端放电。
本申请还提出一种显示面板。
参照图1至图6，在本申请一实施例中，该显示面板包括彩膜基板200、液晶层300及如上所述的阵列基板100，可以理解的是，该阵列基板100的详细结构可参照上述实施例，此处不再赘述；由于在本申请显示面板中使用了上述阵列基板100，因此，本申请显示面板的实施例包括上述阵列基板100全部实施例的全部技术方案，且所达到的技术效果也完全相同，在此不再赘述。
其中，所述阵列基板100上形成有像素电极80，所述彩膜基板200上形成有公共电极；
所述液晶层300，设置于所述彩膜基板200与所述阵列基板100之间；
所述显示面板通过所述像素电极80与所述公共电极（图未示出）之间的电压差控制所述液晶层300的液晶分子转动，并通过所述彩膜基板200显示图像。
本实施例中，可以理解的是，公共电极还可以设置于阵列基板100上，并通过栅极绝缘层40与栅极20间进行隔离。在显示面板上电工作后，阵列基板100上的各薄膜晶体管的栅极20经阵列基板100上的扫描线与显示面板的栅极20驱动器连接；薄膜晶体管上的源极60（或者漏极70）经阵列基板100上的数据线与和显示面板的源极60驱动器连接的像素电极80连接，薄膜晶体管上的漏极70（或者源极60）与彩膜基板200上的公共电极电连接。在显示面板上对应扫描行的薄膜晶体管基于栅极20驱动器的控制而导通，并控制数据驱动器输出对应的数据信号经数据线输出至像素电极80时，显示面板通过像素电极80与公共电极之间的电压差控制所述液晶层300的液晶分子转动，并通过所述彩膜基板200显示图像。
以上所述仅为本申请的可选地实施例，并非因此限制本申请的专利范围，凡是在本申请的申请构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (18)

  1. 一种阵列基板的制作方法，其中，所述阵列基板的制作方法包括：
    提供一基板；
    在所述基板上沉积第一金属层及第一导电层，利用第一道光罩图案化所述第一金属层及第一导电层，以形成栅极及覆盖于所述栅极上的导电隔离层；以及
    在所述栅极上沉积栅极绝缘层后，在所述栅极绝缘层上依次沉积半导体层和第二金属层，并图案化所述半导体层形成有源层，利用第二道光罩图案化所述第二金属层形成源极、漏极及像素电极。
  2. 如权利要求1所述的阵列基板的制作方法，其中，所述在所述基板上沉积第一金属层及第一导电层，利用第一道光罩图案化所述第一金属层及第一导电层，以形成栅极及覆盖于所述栅极上的导电隔离层的步骤具体包括：
    在所述基板上沉积第一金属层，利用第一道光罩图案化所述第一金属层以形成栅极；以及
    在所述栅极上沉积第一导电层，利用所述第一道光罩图案化所述第一金属层以形成导电隔离层。
  3. 如权利要求2所述的阵列基板的制作方法，其中，所述在所述基板上沉积第一金属层的步骤具体包括：
    采用物理气相沉积方法成膜，或者采用溅射沉积工艺将所述第一金属层形成于所述基板上。
  4. 如权利要求2所述的阵列基板的制作方法，其中，所述在所述栅极上沉积第一导电层的步骤具体包括：
    采用物理气相沉积将导第一导电层覆盖于所述栅极上。
  5. 如权利要求2所述的阵列基板的制作方法，其中，所述在所述基板上沉积第一金属层及第一导电层，利用第一道光罩图案化所述第一金属层及第一导电层，以形成栅极及覆盖于所述栅极上的导电隔离层的步骤具体包括：
    所述第一金属层为铜或者铜质合金；以及
    所述第一导电层为氧化铟锡、氧化铟锌、铝掺杂的氧化锌、铟镓锌氧化物、氧化锌锡等多元金属氧化物导电材料中的一种或多种多元金属氧化物导电材料的叠层结构。
  6. 如权利要求1所述的阵列基板的制作方法，其中，所述在所述基板上沉积第一金属层及第一导电层，利用第一道光罩图案化所述第一金属层及第一导电层，以形成栅极及覆盖于所述栅极上的导电隔离层的步骤具体包括：
    在所述基板上依次沉积第一金属层及第一导电层，利用第一道光罩图案化所述第一金属层及第一导电层，以形成栅极及覆盖于所述栅极上的导电隔离层。
  7. 如权利要求6所述的阵列基板的制作方法，其中，所述在所述基板上依次沉积第一金属层及第一导电层的步骤具体包括：
    采用物理气相沉积方法成膜，或者采用溅射沉积工艺将第一金属层形成于基板上，再采用物理气相沉积将第一导电层覆盖于所述第一金属层上。
  8. 如权利要求6所述的阵列基板的制作方法，其中，所述在所述基板上沉积第一金属层及第一导电层，利用第一道光罩图案化所述第一金属层及第一导电层，以形成栅极及覆盖于所述栅极上的导电隔离层的步骤具体包括：
    所述第一金属层为铜或者铜质合金；以及
    所述第一导电层为氧化铟锡、氧化铟锌、铝掺杂的氧化锌、铟镓锌氧化物、氧化锌锡等多元金属氧化物导电材料中的一种或多种多元金属氧化物导电材料的叠层结构。
  9. 如权利要求1所述的阵列基板的制作方法，其中，图案化所述半导体层形成所述有源层的过程包括：
    利用第三道光罩图案化所述半导体层形成所述有源层。
  10. 如权利要求1所述的阵列基板的制作方法，其中，在形成所述源极、所述漏极及所述像素电极后，所述阵列基板的制作方法还包括：
    在所述源极、所述漏极及所述像素电极的表面沉积钝化层，并利用第四道光罩图案化所述钝化层。
  11. 一种阵列基板，其中，所述阵列基板包括：
    基板；
    栅极及覆盖于所述栅极上的导电隔离层；
    栅极绝缘层，设置于所述基板面对所述栅极和所述导电隔离层的一侧并覆盖所述导电隔离层；以及
    有源层及第二金属层，依次层叠于所述栅极绝缘层上，所述第二金属层包括源极、漏极及像素电极，所述源极和所述漏极通过所述有源层电连接。
  12. 如权利要求11所述的阵列基板，其中，
    所述栅极由铜或者铜质合金材料制得；以及
    所述导电隔离层为氧化铟锡、氧化铟锌、铝掺杂的氧化锌、铟镓锌氧化物、氧化锌锡 等多元金属氧化物导电材料中的一种或多种多元金属氧化物导电材料的叠层结构。
  13. 如权利要求11所述的阵列基板，其中，所述第二金属层还包括数据线，所述数据线可以是通过第二道光罩图案化第二金属层形成数据线。
  14. 如权利要求11所述的阵列基板，其中，所述像素电极还包括钝化层，钝化层层叠设置于所述第二金属层上。
  15. 一种显示面板，其中，包括彩膜基板、液晶层及如权利要求8所述的阵列基板，
    所述阵列基板上形成有像素电极，所述彩膜基板上形成有公共电极；
    所述液晶层，设置于所述彩膜基板与所述阵列基板之间；以及
    所述显示面板通过所述像素电极与所述公共电极之间的电压差控制所述液晶层的液晶分子转动，并通过所述彩膜基板显示图像；
    所述阵列基板包括：
    基板；
    栅极及覆盖于所述栅极上的导电隔离层；
    栅极绝缘层，设置于所述基板面对所述栅极和所述导电隔离层的一侧并覆盖所述导电隔离层；以及
    有源层及第二金属层，依次层叠于所述栅极绝缘层上，所述第二金属层包括源极、漏极及像素电极，所述源极和所述漏极通过所述有源层电连接。
  16. 如权利要求15所述的显示面板，其中，所述栅极由铜或者铜质合金材料制得；
    所述导电隔离层为氧化铟锡、氧化铟锌、铝掺杂的氧化锌、铟镓锌氧化物、氧化锌锡 等多元金属氧化物导电材料中的一种或多种多元金属氧化物导电材料的叠层结构。
  17. 如权利要求15所述的显示面板，其中，所述第二金属层还包括数据线，所述数据线可以是通过第二道光罩图案化第二金属层形成数据线。
  18. 如权利要求15所述的显示面板，其中，所述像素电极还包括钝化层，钝化层层叠设置于所述第二金属层上。
PCT/CN2018/116669 2018-09-21 2018-11-21 阵列基板及其制作方法，以及显示面板 Ceased WO2020056906A1 (zh)

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